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drivers/ata/pata_legacy.c
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// SPDX-License-Identifier: GPL-2.0-or-later |
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/* * pata-legacy.c - Legacy port PATA/SATA controller driver. |
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* Copyright 2005/2006 Red Hat, all rights reserved. |
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* |
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* An ATA driver for the legacy ATA ports. * * Data Sources: * Opti 82C465/82C611 support: Data sheets at opti-inc.com * HT6560 series: * Promise 20230/20620: * http://www.ryston.cz/petr/vlb/pdc20230b.html * http://www.ryston.cz/petr/vlb/pdc20230c.html * http://www.ryston.cz/petr/vlb/pdc20630.html |
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* QDI65x0: * http://www.ryston.cz/petr/vlb/qd6500.html * http://www.ryston.cz/petr/vlb/qd6580.html * * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by * Samuel Thibault <samuel.thibault@ens-lyon.org> |
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* * Unsupported but docs exist: * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 |
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* * This driver handles legacy (that is "ISA/VLB side") IDE ports found * on PC class systems. There are three hybrid devices that are exceptions * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and * the MPIIX where the tuning is PCI side but the IDE is "ISA side". * * Specific support is included for the ht6560a/ht6560b/opti82c611a/ |
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* opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A |
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* |
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* Support for the Winbond 83759A when operating in advanced mode. * Multichip mode is not currently supported. * |
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* Use the autospeed and pio_mask options with: * Appian ADI/2 aka CLPD7220 or AIC25VL01. * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, * Winbond W83759A, Promise PDC20230-B * * For now use autospeed and pio_mask as above with the W83759A. This may * change. |
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*/ |
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#include <linux/async.h> |
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#include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <scsi/scsi_host.h> #include <linux/ata.h> #include <linux/libata.h> #include <linux/platform_device.h> #define DRV_NAME "pata_legacy" |
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#define DRV_VERSION "0.6.5" |
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#define NR_HOST 6 |
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static int all; module_param(all, int, 0444); MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); |
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enum controller { BIOS = 0, SNOOP = 1, PDC20230 = 2, HT6560A = 3, HT6560B = 4, OPTI611A = 5, OPTI46X = 6, QDI6500 = 7, QDI6580 = 8, QDI6580DP = 9, /* Dual channel mode is different */ |
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W83759A = 10, |
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UNKNOWN = -1 }; |
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struct legacy_data { unsigned long timing; u8 clock[2]; u8 last; int fast; enum controller type; struct platform_device *platform_dev; }; |
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struct legacy_probe { unsigned char *name; unsigned long port; unsigned int irq; unsigned int slot; enum controller type; unsigned long private; }; struct legacy_controller { const char *name; struct ata_port_operations *ops; unsigned int pio_mask; unsigned int flags; |
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unsigned int pflags; |
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int (*setup)(struct platform_device *, struct legacy_probe *probe, struct legacy_data *data); |
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}; static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; static struct legacy_probe probe_list[NR_HOST]; |
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static struct legacy_data legacy_data[NR_HOST]; static struct ata_host *legacy_host[NR_HOST]; static int nr_legacy_host; |
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static int probe_all; /* Set to check all ISA port ranges */ static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ |
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static int autospeed; /* Chip present which snoops speed changes */ |
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static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */ |
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static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
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|
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/* Set to probe QDI controllers */ #ifdef CONFIG_PATA_QDI_MODULE static int qdi = 1; #else static int qdi; #endif |
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#ifdef CONFIG_PATA_WINBOND_VLB_MODULE |
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static int winbond = 1; /* Set to probe Winbond controllers, give I/O port if non standard */ #else static int winbond; /* Set to probe Winbond controllers, give I/O port if non standard */ #endif |
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/** |
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* legacy_probe_add - Add interface to probe list * @port: Controller port * @irq: IRQ number * @type: Controller type * @private: Controller specific info * * Add an entry into the probe list for ATA controllers. This is used * to add the default ISA slots and then to build up the table * further according to other ISA/VLB/Weird device scans * * An I/O port list is used to keep ordering stable and sane, as we * don't have any good way to talk about ordering otherwise */ static int legacy_probe_add(unsigned long port, unsigned int irq, enum controller type, unsigned long private) { struct legacy_probe *lp = &probe_list[0]; int i; struct legacy_probe *free = NULL; for (i = 0; i < NR_HOST; i++) { if (lp->port == 0 && free == NULL) free = lp; /* Matching port, or the correct slot for ordering */ if (lp->port == port || legacy_port[i] == port) { free = lp; break; } lp++; } if (free == NULL) { printk(KERN_ERR "pata_legacy: Too many interfaces. "); return -1; } /* Fill in the entry for later probing */ free->port = port; free->irq = irq; free->type = type; free->private = private; return 0; } /** |
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* legacy_set_mode - mode setting |
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* @link: IDE link |
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* @unused: Device that failed when error is returned |
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* * Use a non standard set_mode function. We don't want to be tuned. * * The BIOS configured everything. Our job is not to fiddle. Just use * whatever PIO the hardware is using and leave it at that. When we * get some kind of nice user driven API for control then we can * expand on this as per hdparm in the base kernel. */ |
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static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) |
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{ |
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struct ata_device *dev; |
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|
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ata_for_each_dev(dev, link, ENABLED) { |
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ata_dev_info(dev, "configured for PIO "); |
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dev->pio_mode = XFER_PIO_0; dev->xfer_mode = XFER_PIO_0; dev->xfer_shift = ATA_SHIFT_PIO; dev->flags |= ATA_DFLAG_PIO; |
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} |
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return 0; |
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} static struct scsi_host_template legacy_sht = { |
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ATA_PIO_SHT(DRV_NAME), |
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}; |
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static const struct ata_port_operations legacy_base_port_ops = { .inherits = &ata_sff_port_ops, .cable_detect = ata_cable_40wire, }; |
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/* * These ops are used if the user indicates the hardware * snoops the commands to decide on the mode and handles the * mode selection "magically" itself. Several legacy controllers * do this. The mode range can be set if it is not 0x1F by setting * pio_mask as well. */ static struct ata_port_operations simple_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.sff_data_xfer = ata_sff_data_xfer32, |
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}; static struct ata_port_operations legacy_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.sff_data_xfer = ata_sff_data_xfer32, |
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.set_mode = legacy_set_mode, |
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}; /* * Promise 20230C and 20620 support * |
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* This controller supports PIO0 to PIO2. We set PIO timings * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA * support is weird being DMA to controller and PIO'd to the host * and not supported. |
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*/ static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) { int tries = 5; int pio = adev->pio_mode - XFER_PIO_0; u8 rt; unsigned long flags; |
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|
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/* Safe as UP only. Force I/Os to occur together */ |
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|
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local_irq_save(flags); |
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|
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/* Unlock the control interface */ |
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do { |
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inb(0x1F5); outb(inb(0x1F2) | 0x80, 0x1F2); inb(0x1F2); inb(0x3F6); inb(0x3F6); inb(0x1F2); inb(0x1F2); } |
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while ((inb(0x1F2) & 0x80) && --tries); |
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local_irq_restore(flags); |
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|
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outb(inb(0x1F4) & 0x07, 0x1F4); rt = inb(0x1F3); rt &= 0x07 << (3 * adev->devno); if (pio) rt |= (1 + 3 * pio) << (3 * adev->devno); udelay(100); outb(inb(0x1F2) | 0x01, 0x1F2); udelay(100); inb(0x1F5); } |
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static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, |
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unsigned char *buf, unsigned int buflen, int rw) |
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{ |
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struct ata_device *dev = qc->dev; |
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struct ata_port *ap = dev->link->ap; |
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int slop = buflen & 3; |
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|
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/* 32bit I/O capable *and* we need to write a whole number of dwords */ |
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if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) && (ap->pflags & ATA_PFLAG_PIO32)) { |
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unsigned long flags; |
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local_irq_save(flags); /* Perform the 32bit I/O synchronization sequence */ |
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ioread8(ap->ioaddr.nsect_addr); ioread8(ap->ioaddr.nsect_addr); ioread8(ap->ioaddr.nsect_addr); |
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/* Now the data */ |
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if (rw == READ) |
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ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
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else iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
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if (unlikely(slop)) { |
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__le32 pad; |
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if (rw == READ) { |
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pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
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memcpy(buf + buflen - slop, &pad, slop); |
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} else { memcpy(&pad, buf + buflen - slop, slop); iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
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} |
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buflen += 4 - slop; |
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} local_irq_restore(flags); |
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} else |
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buflen = ata_sff_data_xfer32(qc, buf, buflen, rw); |
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return buflen; |
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} static struct ata_port_operations pdc20230_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.set_piomode = pdc20230_set_piomode, |
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.sff_data_xfer = pdc_data_xfer_vlb, |
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}; /* * Holtek 6560A support * |
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* This controller supports PIO0 to PIO2 (no IORDY even though higher * timings can be loaded). |
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*/ static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) { u8 active, recover; struct ata_timing t; /* Get the timing data in cycles. For now play safe at 50Mhz */ ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
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active = clamp_val(t.active, 2, 15); recover = clamp_val(t.recover, 4, 15); |
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inb(0x3E6); inb(0x3E6); inb(0x3E6); inb(0x3E6); |
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iowrite8(recover << 4 | active, ap->ioaddr.device_addr); ioread8(ap->ioaddr.status_addr); |
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} static struct ata_port_operations ht6560a_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.set_piomode = ht6560a_set_piomode, |
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}; /* * Holtek 6560B support * |
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* This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO * setting unless we see an ATAPI device in which case we force it off. |
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* * FIXME: need to implement 2nd channel support. */ static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) { u8 active, recover; struct ata_timing t; /* Get the timing data in cycles. For now play safe at 50Mhz */ ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); |
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active = clamp_val(t.active, 2, 15); |
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recover = clamp_val(t.recover, 2, 16) & 0x0F; |
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inb(0x3E6); inb(0x3E6); inb(0x3E6); inb(0x3E6); |
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iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
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if (adev->class != ATA_DEV_ATA) { u8 rconf = inb(0x3E6); if (rconf & 0x24) { |
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rconf &= ~0x24; |
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outb(rconf, 0x3E6); } } |
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ioread8(ap->ioaddr.status_addr); |
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} static struct ata_port_operations ht6560b_port_ops = { |
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.inherits = &legacy_base_port_ops, |
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.set_piomode = ht6560b_set_piomode, |
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}; /* * Opti core chipset helpers */ |
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|
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/** * opti_syscfg - read OPTI chipset configuration * @reg: Configuration register to read * * Returns the value of an OPTI system board configuration register. */ static u8 opti_syscfg(u8 reg) { unsigned long flags; u8 r; |
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|
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/* Uniprocessor chipset and must force cycles adjancent */ local_irq_save(flags); outb(reg, 0x22); r = inb(0x24); local_irq_restore(flags); return r; } /* * Opti 82C611A * * This controller supports PIO0 to PIO3. */ |
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static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ u8 active, recover, setup; struct ata_timing t; struct ata_device *pair = ata_dev_pair(adev); int clock; int khz[4] = { 50000, 40000, 33000, 25000 }; u8 rc; /* Enter configuration mode */ |
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ioread16(ap->ioaddr.error_addr); ioread16(ap->ioaddr.error_addr); iowrite8(3, ap->ioaddr.nsect_addr); |
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/* Read VLB clock strapping */ |
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clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
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/* Get the timing data in cycles */ ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); /* Setup timing is shared */ if (pair) { struct ata_timing tp; ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); } |
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active = clamp_val(t.active, 2, 17) - 2; recover = clamp_val(t.recover, 1, 16) - 1; setup = clamp_val(t.setup, 1, 4) - 1; |
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/* Select the right timing bank for write timing */ |
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rc = ioread8(ap->ioaddr.lbal_addr); |
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rc &= 0x7F; rc |= (adev->devno << 7); |
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iowrite8(rc, ap->ioaddr.lbal_addr); |
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/* Write the timings */ |
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iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
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/* Select the right bank for read timings, also load the shared timings for address */ |
0d5ff5667 libata: convert t... |
473 |
rc = ioread8(ap->ioaddr.device_addr); |
669a5db41 [libata] Add a bu... |
474 475 476 |
rc &= 0xC0; rc |= adev->devno; /* Index select */ rc |= (setup << 4) | 0x04; |
0d5ff5667 libata: convert t... |
477 |
iowrite8(rc, ap->ioaddr.device_addr); |
669a5db41 [libata] Add a bu... |
478 479 |
/* Load the read timings */ |
0d5ff5667 libata: convert t... |
480 |
iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db41 [libata] Add a bu... |
481 482 |
/* Ensure the timing register mode is right */ |
0d5ff5667 libata: convert t... |
483 |
rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db41 [libata] Add a bu... |
484 485 |
rc &= 0x73; rc |= 0x84; |
0d5ff5667 libata: convert t... |
486 |
iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db41 [libata] Add a bu... |
487 488 |
/* Exit command mode */ |
0d5ff5667 libata: convert t... |
489 |
iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db41 [libata] Add a bu... |
490 491 492 493 |
} static struct ata_port_operations opti82c611a_port_ops = { |
029cfd6b7 libata: implement... |
494 |
.inherits = &legacy_base_port_ops, |
669a5db41 [libata] Add a bu... |
495 |
.set_piomode = opti82c611a_set_piomode, |
669a5db41 [libata] Add a bu... |
496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 |
}; /* * Opti 82C465MV * * This controller supports PIO0 to PIO3. Unlike the 611A the MVB * version is dual channel but doesn't have a lot of unique registers. */ static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) { u8 active, recover, setup; struct ata_timing t; struct ata_device *pair = ata_dev_pair(adev); int clock; int khz[4] = { 50000, 40000, 33000, 25000 }; u8 rc; u8 sysclk; /* Get the clock */ |
e0044c982 pata_legacy: bogu... |
516 |
sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */ |
669a5db41 [libata] Add a bu... |
517 518 |
/* Enter configuration mode */ |
0d5ff5667 libata: convert t... |
519 520 521 |
ioread16(ap->ioaddr.error_addr); ioread16(ap->ioaddr.error_addr); iowrite8(3, ap->ioaddr.nsect_addr); |
669a5db41 [libata] Add a bu... |
522 523 524 525 526 527 528 529 530 531 532 533 534 535 |
/* Read VLB clock strapping */ clock = 1000000000 / khz[sysclk]; /* Get the timing data in cycles */ ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); /* Setup timing is shared */ if (pair) { struct ata_timing tp; ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); } |
07633b5d0 ata: remove FIT()... |
536 537 538 |
active = clamp_val(t.active, 2, 17) - 2; recover = clamp_val(t.recover, 1, 16) - 1; setup = clamp_val(t.setup, 1, 4) - 1; |
669a5db41 [libata] Add a bu... |
539 540 |
/* Select the right timing bank for write timing */ |
0d5ff5667 libata: convert t... |
541 |
rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db41 [libata] Add a bu... |
542 543 |
rc &= 0x7F; rc |= (adev->devno << 7); |
0d5ff5667 libata: convert t... |
544 |
iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db41 [libata] Add a bu... |
545 546 |
/* Write the timings */ |
0d5ff5667 libata: convert t... |
547 |
iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db41 [libata] Add a bu... |
548 549 550 |
/* Select the right bank for read timings, also load the shared timings for address */ |
0d5ff5667 libata: convert t... |
551 |
rc = ioread8(ap->ioaddr.device_addr); |
669a5db41 [libata] Add a bu... |
552 553 554 |
rc &= 0xC0; rc |= adev->devno; /* Index select */ rc |= (setup << 4) | 0x04; |
0d5ff5667 libata: convert t... |
555 |
iowrite8(rc, ap->ioaddr.device_addr); |
669a5db41 [libata] Add a bu... |
556 557 |
/* Load the read timings */ |
0d5ff5667 libata: convert t... |
558 |
iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db41 [libata] Add a bu... |
559 560 |
/* Ensure the timing register mode is right */ |
0d5ff5667 libata: convert t... |
561 |
rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db41 [libata] Add a bu... |
562 563 |
rc &= 0x73; rc |= 0x84; |
0d5ff5667 libata: convert t... |
564 |
iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db41 [libata] Add a bu... |
565 566 |
/* Exit command mode */ |
0d5ff5667 libata: convert t... |
567 |
iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db41 [libata] Add a bu... |
568 569 570 571 572 573 |
/* We need to know this for quad device on the MVB */ ap->host->private_data = ap; } /** |
9363c3825 libata: rename SF... |
574 |
* opt82c465mv_qc_issue - command issue |
669a5db41 [libata] Add a bu... |
575 576 577 578 579 580 581 582 583 584 585 586 |
* @qc: command pending * * Called when the libata layer is about to issue a command. We wrap * this interface so that we can load the correct ATA timings. The * MVB has a single set of timing registers and these are shared * across channels. As there are two registers we really ought to * track the last two used values as a sort of register window. For * now we just reload on a channel switch. On the single channel * setup this condition never fires so we do nothing extra. * * FIXME: dual channel needs ->serialize support */ |
9363c3825 libata: rename SF... |
587 |
static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) |
669a5db41 [libata] Add a bu... |
588 589 590 591 592 593 594 595 596 |
{ struct ata_port *ap = qc->ap; struct ata_device *adev = qc->dev; /* If timings are set and for the wrong channel (2nd test is due to a libata shortcoming and will eventually go I hope) */ if (ap->host->private_data != ap->host && ap->host->private_data != NULL) opti82c46x_set_piomode(ap, adev); |
9363c3825 libata: rename SF... |
597 |
return ata_sff_qc_issue(qc); |
669a5db41 [libata] Add a bu... |
598 599 600 |
} static struct ata_port_operations opti82c46x_port_ops = { |
029cfd6b7 libata: implement... |
601 |
.inherits = &legacy_base_port_ops, |
669a5db41 [libata] Add a bu... |
602 |
.set_piomode = opti82c46x_set_piomode, |
9363c3825 libata: rename SF... |
603 |
.qc_issue = opti82c46x_qc_issue, |
669a5db41 [libata] Add a bu... |
604 |
}; |
669a5db41 [libata] Add a bu... |
605 |
/** |
8c7e8f947 pata_legacy: unif... |
606 |
* qdi65x0_set_piomode - PIO setup for QDI65x0 |
defc9cd82 pata_legacy: resy... |
607 608 |
* @ap: Port * @adev: Device |
669a5db41 [libata] Add a bu... |
609 |
* |
8c7e8f947 pata_legacy: unif... |
610 611 612 613 |
* In single channel mode the 6580 has one clock per device and we can * avoid the requirement to clock switch. We also have to load the timing * into the right clock according to whether we are master or slave. * |
defc9cd82 pata_legacy: resy... |
614 |
* In dual channel mode the 6580 has one clock per channel and we have |
9363c3825 libata: rename SF... |
615 |
* to software clockswitch in qc_issue. |
669a5db41 [libata] Add a bu... |
616 |
*/ |
8c7e8f947 pata_legacy: unif... |
617 |
static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) |
669a5db41 [libata] Add a bu... |
618 |
{ |
defc9cd82 pata_legacy: resy... |
619 |
struct ata_timing t; |
cb616dd5b ata: fix sparse w... |
620 |
struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd82 pata_legacy: resy... |
621 622 |
int active, recovery; u8 timing; |
669a5db41 [libata] Add a bu... |
623 |
|
defc9cd82 pata_legacy: resy... |
624 625 |
/* Get the timing data in cycles */ ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); |
cb616dd5b ata: fix sparse w... |
626 |
if (ld_qdi->fast) { |
07633b5d0 ata: remove FIT()... |
627 628 |
active = 8 - clamp_val(t.active, 1, 8); recovery = 18 - clamp_val(t.recover, 3, 18); |
defc9cd82 pata_legacy: resy... |
629 |
} else { |
07633b5d0 ata: remove FIT()... |
630 631 |
active = 9 - clamp_val(t.active, 2, 9); recovery = 15 - clamp_val(t.recover, 0, 15); |
defc9cd82 pata_legacy: resy... |
632 633 |
} timing = (recovery << 4) | active | 0x08; |
cb616dd5b ata: fix sparse w... |
634 |
ld_qdi->clock[adev->devno] = timing; |
669a5db41 [libata] Add a bu... |
635 |
|
8c7e8f947 pata_legacy: unif... |
636 637 638 639 |
if (ld_qdi->type == QDI6580) outb(timing, ld_qdi->timing + 2 * adev->devno); else outb(timing, ld_qdi->timing + 2 * ap->port_no); |
defc9cd82 pata_legacy: resy... |
640 |
|
defc9cd82 pata_legacy: resy... |
641 |
/* Clear the FIFO */ |
8c7e8f947 pata_legacy: unif... |
642 |
if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) |
6809e7301 pata_legacy: fix ... |
643 |
outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); |
defc9cd82 pata_legacy: resy... |
644 645 646 |
} /** |
9363c3825 libata: rename SF... |
647 |
* qdi_qc_issue - command issue |
defc9cd82 pata_legacy: resy... |
648 649 650 651 652 |
* @qc: command pending * * Called when the libata layer is about to issue a command. We wrap * this interface so that we can load the correct ATA timings. */ |
9363c3825 libata: rename SF... |
653 |
static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) |
defc9cd82 pata_legacy: resy... |
654 655 656 |
{ struct ata_port *ap = qc->ap; struct ata_device *adev = qc->dev; |
cb616dd5b ata: fix sparse w... |
657 |
struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd82 pata_legacy: resy... |
658 |
|
cb616dd5b ata: fix sparse w... |
659 |
if (ld_qdi->clock[adev->devno] != ld_qdi->last) { |
defc9cd82 pata_legacy: resy... |
660 |
if (adev->pio_mode) { |
cb616dd5b ata: fix sparse w... |
661 662 |
ld_qdi->last = ld_qdi->clock[adev->devno]; outb(ld_qdi->clock[adev->devno], ld_qdi->timing + |
defc9cd82 pata_legacy: resy... |
663 664 |
2 * ap->port_no); } |
669a5db41 [libata] Add a bu... |
665 |
} |
9363c3825 libata: rename SF... |
666 |
return ata_sff_qc_issue(qc); |
defc9cd82 pata_legacy: resy... |
667 |
} |
669a5db41 [libata] Add a bu... |
668 |
|
989e0aac1 ata: pass queued ... |
669 670 671 |
static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf, unsigned int buflen, int rw) |
defc9cd82 pata_legacy: resy... |
672 |
{ |
989e0aac1 ata: pass queued ... |
673 |
struct ata_device *adev = qc->dev; |
defc9cd82 pata_legacy: resy... |
674 675 |
struct ata_port *ap = adev->link->ap; int slop = buflen & 3; |
669a5db41 [libata] Add a bu... |
676 |
|
e3cf95dd6 ata: Report 16/32... |
677 678 |
if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) && (ap->pflags & ATA_PFLAG_PIO32)) { |
defc9cd82 pata_legacy: resy... |
679 680 681 682 |
if (rw == WRITE) iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); else ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
669a5db41 [libata] Add a bu... |
683 |
|
defc9cd82 pata_legacy: resy... |
684 |
if (unlikely(slop)) { |
6ad67403d ata: endianness a... |
685 |
__le32 pad; |
defc9cd82 pata_legacy: resy... |
686 687 |
if (rw == WRITE) { memcpy(&pad, buf + buflen - slop, slop); |
6ad67403d ata: endianness a... |
688 |
iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
defc9cd82 pata_legacy: resy... |
689 |
} else { |
6ad67403d ata: endianness a... |
690 |
pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
defc9cd82 pata_legacy: resy... |
691 692 693 694 695 |
memcpy(buf + buflen - slop, &pad, slop); } } return (buflen + 3) & ~3; } else |
989e0aac1 ata: pass queued ... |
696 |
return ata_sff_data_xfer(qc, buf, buflen, rw); |
defc9cd82 pata_legacy: resy... |
697 |
} |
b83254877 pata_legacy: Merg... |
698 699 700 701 702 703 704 705 |
static int qdi_port(struct platform_device *dev, struct legacy_probe *lp, struct legacy_data *ld) { if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) return -EBUSY; ld->timing = lp->private; return 0; } |
defc9cd82 pata_legacy: resy... |
706 |
static struct ata_port_operations qdi6500_port_ops = { |
029cfd6b7 libata: implement... |
707 |
.inherits = &legacy_base_port_ops, |
8c7e8f947 pata_legacy: unif... |
708 |
.set_piomode = qdi65x0_set_piomode, |
9363c3825 libata: rename SF... |
709 |
.qc_issue = qdi_qc_issue, |
5682ed33a libata: rename SF... |
710 |
.sff_data_xfer = vlb32_data_xfer, |
defc9cd82 pata_legacy: resy... |
711 712 713 |
}; static struct ata_port_operations qdi6580_port_ops = { |
029cfd6b7 libata: implement... |
714 |
.inherits = &legacy_base_port_ops, |
8c7e8f947 pata_legacy: unif... |
715 |
.set_piomode = qdi65x0_set_piomode, |
5682ed33a libata: rename SF... |
716 |
.sff_data_xfer = vlb32_data_xfer, |
defc9cd82 pata_legacy: resy... |
717 718 719 |
}; static struct ata_port_operations qdi6580dp_port_ops = { |
029cfd6b7 libata: implement... |
720 |
.inherits = &legacy_base_port_ops, |
8c7e8f947 pata_legacy: unif... |
721 |
.set_piomode = qdi65x0_set_piomode, |
43c7d17ee pata_legacy: fix ... |
722 |
.qc_issue = qdi_qc_issue, |
5682ed33a libata: rename SF... |
723 |
.sff_data_xfer = vlb32_data_xfer, |
defc9cd82 pata_legacy: resy... |
724 |
}; |
b83254877 pata_legacy: Merg... |
725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 |
static DEFINE_SPINLOCK(winbond_lock); static void winbond_writecfg(unsigned long port, u8 reg, u8 val) { unsigned long flags; spin_lock_irqsave(&winbond_lock, flags); outb(reg, port + 0x01); outb(val, port + 0x02); spin_unlock_irqrestore(&winbond_lock, flags); } static u8 winbond_readcfg(unsigned long port, u8 reg) { u8 val; unsigned long flags; spin_lock_irqsave(&winbond_lock, flags); outb(reg, port + 0x01); val = inb(port + 0x02); spin_unlock_irqrestore(&winbond_lock, flags); return val; } static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) { struct ata_timing t; |
cb616dd5b ata: fix sparse w... |
752 |
struct legacy_data *ld_winbond = ap->host->private_data; |
b83254877 pata_legacy: Merg... |
753 754 755 |
int active, recovery; u8 reg; int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); |
cb616dd5b ata: fix sparse w... |
756 |
reg = winbond_readcfg(ld_winbond->timing, 0x81); |
b83254877 pata_legacy: Merg... |
757 758 759 760 761 762 |
/* Get the timing data in cycles */ if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); else ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); |
07633b5d0 ata: remove FIT()... |
763 764 |
active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; |
b83254877 pata_legacy: Merg... |
765 |
timing = (active << 4) | recovery; |
cb616dd5b ata: fix sparse w... |
766 |
winbond_writecfg(ld_winbond->timing, timing, reg); |
b83254877 pata_legacy: Merg... |
767 768 769 770 771 772 773 774 |
/* Load the setup timing */ reg = 0x35; if (adev->class != ATA_DEV_ATA) reg |= 0x08; /* FIFO off */ if (!ata_pio_need_iordy(adev)) reg |= 0x02; /* IORDY off */ |
07633b5d0 ata: remove FIT()... |
775 |
reg |= (clamp_val(t.setup, 0, 3) << 6); |
cb616dd5b ata: fix sparse w... |
776 |
winbond_writecfg(ld_winbond->timing, timing + 1, reg); |
b83254877 pata_legacy: Merg... |
777 778 779 780 781 782 783 784 785 786 787 788 |
} static int winbond_port(struct platform_device *dev, struct legacy_probe *lp, struct legacy_data *ld) { if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) return -EBUSY; ld->timing = lp->private; return 0; } static struct ata_port_operations winbond_port_ops = { |
029cfd6b7 libata: implement... |
789 |
.inherits = &legacy_base_port_ops, |
b83254877 pata_legacy: Merg... |
790 |
.set_piomode = winbond_set_piomode, |
5682ed33a libata: rename SF... |
791 |
.sff_data_xfer = vlb32_data_xfer, |
b83254877 pata_legacy: Merg... |
792 |
}; |
defc9cd82 pata_legacy: resy... |
793 |
static struct legacy_controller controllers[] = { |
b2f104bba pata_legacy: use ... |
794 |
{"BIOS", &legacy_port_ops, ATA_PIO4, |
e3cf95dd6 ata: Report 16/32... |
795 |
ATA_FLAG_NO_IORDY, 0, NULL }, |
b2f104bba pata_legacy: use ... |
796 |
{"Snooping", &simple_port_ops, ATA_PIO4, |
e3cf95dd6 ata: Report 16/32... |
797 |
0, 0, NULL }, |
b2f104bba pata_legacy: use ... |
798 |
{"PDC20230", &pdc20230_port_ops, ATA_PIO2, |
e3cf95dd6 ata: Report 16/32... |
799 |
ATA_FLAG_NO_IORDY, |
16e6aeca9 [libata] fix buil... |
800 |
ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, |
b2f104bba pata_legacy: use ... |
801 |
{"HT6560A", &ht6560a_port_ops, ATA_PIO2, |
e3cf95dd6 ata: Report 16/32... |
802 |
ATA_FLAG_NO_IORDY, 0, NULL }, |
b2f104bba pata_legacy: use ... |
803 |
{"HT6560B", &ht6560b_port_ops, ATA_PIO4, |
e3cf95dd6 ata: Report 16/32... |
804 |
ATA_FLAG_NO_IORDY, 0, NULL }, |
b2f104bba pata_legacy: use ... |
805 |
{"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3, |
e3cf95dd6 ata: Report 16/32... |
806 |
0, 0, NULL }, |
b2f104bba pata_legacy: use ... |
807 |
{"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3, |
e3cf95dd6 ata: Report 16/32... |
808 |
0, 0, NULL }, |
b2f104bba pata_legacy: use ... |
809 |
{"QDI6500", &qdi6500_port_ops, ATA_PIO2, |
e3cf95dd6 ata: Report 16/32... |
810 |
ATA_FLAG_NO_IORDY, |
16e6aeca9 [libata] fix buil... |
811 |
ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
b2f104bba pata_legacy: use ... |
812 |
{"QDI6580", &qdi6580_port_ops, ATA_PIO4, |
16e6aeca9 [libata] fix buil... |
813 |
0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
b2f104bba pata_legacy: use ... |
814 |
{"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4, |
16e6aeca9 [libata] fix buil... |
815 |
0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
b2f104bba pata_legacy: use ... |
816 |
{"W83759A", &winbond_port_ops, ATA_PIO4, |
16e6aeca9 [libata] fix buil... |
817 |
0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, |
e3cf95dd6 ata: Report 16/32... |
818 |
winbond_port } |
defc9cd82 pata_legacy: resy... |
819 820 821 822 823 824 825 826 827 |
}; /** * probe_chip_type - Discover controller * @probe: Probe entry to check * * Probe an ATA port and identify the type of controller. We don't * check if the controller appears to be driveless at this point. */ |
b83254877 pata_legacy: Merg... |
828 |
static __init int probe_chip_type(struct legacy_probe *probe) |
defc9cd82 pata_legacy: resy... |
829 830 |
{ int mask = 1 << probe->slot; |
b83254877 pata_legacy: Merg... |
831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 |
if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { u8 reg = winbond_readcfg(winbond, 0x81); reg |= 0x80; /* jumpered mode off */ winbond_writecfg(winbond, 0x81, reg); reg = winbond_readcfg(winbond, 0x83); reg |= 0xF0; /* local control */ winbond_writecfg(winbond, 0x83, reg); reg = winbond_readcfg(winbond, 0x85); reg |= 0xF0; /* programmable timing */ winbond_writecfg(winbond, 0x85, reg); reg = winbond_readcfg(winbond, 0x81); if (reg & mask) return W83759A; } |
defc9cd82 pata_legacy: resy... |
847 848 849 |
if (probe->port == 0x1F0) { unsigned long flags; local_irq_save(flags); |
669a5db41 [libata] Add a bu... |
850 |
/* Probes */ |
669a5db41 [libata] Add a bu... |
851 |
outb(inb(0x1F2) | 0x80, 0x1F2); |
defc9cd82 pata_legacy: resy... |
852 |
inb(0x1F5); |
669a5db41 [libata] Add a bu... |
853 854 855 856 857 858 859 860 |
inb(0x1F2); inb(0x3F6); inb(0x3F6); inb(0x1F2); inb(0x1F2); if ((inb(0x1F2) & 0x80) == 0) { /* PDC20230c or 20630 ? */ |
defc9cd82 pata_legacy: resy... |
861 862 863 |
printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" " detected. "); |
669a5db41 [libata] Add a bu... |
864 865 |
udelay(100); inb(0x1F5); |
defc9cd82 pata_legacy: resy... |
866 867 |
local_irq_restore(flags); return PDC20230; |
669a5db41 [libata] Add a bu... |
868 869 870 871 |
} else { outb(0x55, 0x1F2); inb(0x1F2); inb(0x1F2); |
defc9cd82 pata_legacy: resy... |
872 873 874 875 876 877 |
if (inb(0x1F2) == 0x00) printk(KERN_INFO "PDC20230-B VLB ATA " "controller detected. "); local_irq_restore(flags); return BIOS; |
669a5db41 [libata] Add a bu... |
878 |
} |
669a5db41 [libata] Add a bu... |
879 |
} |
defc9cd82 pata_legacy: resy... |
880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 |
if (ht6560a & mask) return HT6560A; if (ht6560b & mask) return HT6560B; if (opti82c611a & mask) return OPTI611A; if (opti82c46x & mask) return OPTI46X; if (autospeed & mask) return SNOOP; return BIOS; } /** * legacy_init_one - attach a legacy interface * @pl: probe record * * Register an ISA bus IDE interface. Such interfaces are PIO and we * assume do not support IRQ sharing. */ static __init int legacy_init_one(struct legacy_probe *probe) { struct legacy_controller *controller = &controllers[probe->type]; int pio_modes = controller->pio_mask; unsigned long io = probe->port; u32 mask = (1 << probe->slot); struct ata_port_operations *ops = controller->ops; struct legacy_data *ld = &legacy_data[probe->slot]; struct ata_host *host = NULL; struct ata_port *ap; struct platform_device *pdev; struct ata_device *dev; void __iomem *io_addr, *ctrl_addr; u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; int ret; iordy |= controller->flags; pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); if (IS_ERR(pdev)) return PTR_ERR(pdev); |
669a5db41 [libata] Add a bu... |
923 |
|
defc9cd82 pata_legacy: resy... |
924 925 926 927 928 |
ret = -EBUSY; if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || devm_request_region(&pdev->dev, io + 0x0206, 1, "pata_legacy") == NULL) goto fail; |
f834e49f1 libata: Add a hos... |
929 |
|
5d728824e libata: convert t... |
930 |
ret = -ENOMEM; |
defc9cd82 pata_legacy: resy... |
931 932 933 934 |
io_addr = devm_ioport_map(&pdev->dev, io, 8); ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); if (!io_addr || !ctrl_addr) goto fail; |
8c7e8f947 pata_legacy: unif... |
935 |
ld->type = probe->type; |
defc9cd82 pata_legacy: resy... |
936 |
if (controller->setup) |
b83254877 pata_legacy: Merg... |
937 |
if (controller->setup(pdev, probe, ld) < 0) |
defc9cd82 pata_legacy: resy... |
938 |
goto fail; |
5d728824e libata: convert t... |
939 940 941 942 943 944 945 946 |
host = ata_host_alloc(&pdev->dev, 1); if (!host) goto fail; ap = host->ports[0]; ap->ops = ops; ap->pio_mask = pio_modes; ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; |
e3cf95dd6 ata: Report 16/32... |
947 |
ap->pflags |= controller->pflags; |
5d728824e libata: convert t... |
948 949 950 |
ap->ioaddr.cmd_addr = io_addr; ap->ioaddr.altstatus_addr = ctrl_addr; ap->ioaddr.ctl_addr = ctrl_addr; |
9363c3825 libata: rename SF... |
951 |
ata_sff_std_ports(&ap->ioaddr); |
b83254877 pata_legacy: Merg... |
952 |
ap->host->private_data = ld; |
5d728824e libata: convert t... |
953 |
|
defc9cd82 pata_legacy: resy... |
954 |
ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); |
cbcdd8759 libata: implement... |
955 |
|
9363c3825 libata: rename SF... |
956 957 |
ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, &legacy_sht); |
5d728824e libata: convert t... |
958 |
if (ret) |
669a5db41 [libata] Add a bu... |
959 |
goto fail; |
45bc955bb pata_legacy: wait... |
960 |
async_synchronize_full(); |
669a5db41 [libata] Add a bu... |
961 |
ld->platform_dev = pdev; |
669a5db41 [libata] Add a bu... |
962 |
|
defc9cd82 pata_legacy: resy... |
963 964 965 |
/* Nothing found means we drop the port as its probably not there */ ret = -ENODEV; |
1eca4365b libata: beef up i... |
966 |
ata_for_each_dev(dev, &ap->link, ALL) { |
defc9cd82 pata_legacy: resy... |
967 968 969 970 971 972 |
if (!ata_dev_absent(dev)) { legacy_host[probe->slot] = host; ld->platform_dev = pdev; return 0; } } |
20cbf5f8c pata_legacy: fix ... |
973 |
ata_host_detach(host); |
669a5db41 [libata] Add a bu... |
974 975 |
fail: platform_device_unregister(pdev); |
669a5db41 [libata] Add a bu... |
976 977 978 979 980 981 982 983 984 |
return ret; } /** * legacy_check_special_cases - ATA special cases * @p: PCI device to check * @master: set this if we find an ATA master * @master: set this if we find an ATA secondary * |
defc9cd82 pata_legacy: resy... |
985 986 987 988 989 |
* A small number of vendors implemented early PCI ATA interfaces * on bridge logic without the ATA interface being PCI visible. * Where we have a matching PCI driver we must skip the relevant * device here. If we don't know about it then the legacy driver * is the right driver anyway. |
669a5db41 [libata] Add a bu... |
990 |
*/ |
b83254877 pata_legacy: Merg... |
991 |
static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, |
defc9cd82 pata_legacy: resy... |
992 |
int *secondary) |
669a5db41 [libata] Add a bu... |
993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 |
{ /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ if (p->vendor == 0x1078 && p->device == 0x0000) { *primary = *secondary = 1; return; } /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ if (p->vendor == 0x1078 && p->device == 0x0002) { *primary = *secondary = 1; return; } /* Intel MPIIX - PIO ATA on non PCI side of bridge */ if (p->vendor == 0x8086 && p->device == 0x1234) { u16 r; pci_read_config_word(p, 0x6C, &r); |
defc9cd82 pata_legacy: resy... |
1008 1009 |
if (r & 0x8000) { /* ATA port enabled */ |
669a5db41 [libata] Add a bu... |
1010 1011 1012 1013 1014 1015 1016 1017 |
if (r & 0x4000) *secondary = 1; else *primary = 1; } return; } } |
defc9cd82 pata_legacy: resy... |
1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 |
static __init void probe_opti_vlb(void) { /* If an OPTI 82C46X is present find out where the channels are */ static const char *optis[4] = { "3/463MV", "5MV", "5MVA", "5MVB" }; u8 chans = 1; u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; opti82c46x = 3; /* Assume master and slave first */ printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support. ", optis[ctrl]); if (ctrl == 3) chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; ctrl = opti_syscfg(0xAC); /* Check enabled and this port is the 465MV port. On the MVB we may have two channels */ if (ctrl & 8) { if (chans == 2) { legacy_probe_add(0x1F0, 14, OPTI46X, 0); legacy_probe_add(0x170, 15, OPTI46X, 0); } if (ctrl & 4) legacy_probe_add(0x170, 15, OPTI46X, 0); else legacy_probe_add(0x1F0, 14, OPTI46X, 0); } else legacy_probe_add(0x1F0, 14, OPTI46X, 0); } static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) { static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; /* Check card type */ if ((r & 0xF0) == 0xC0) { /* QD6500: single channel */ |
b83254877 pata_legacy: Merg... |
1056 |
if (r & 8) |
defc9cd82 pata_legacy: resy... |
1057 |
/* Disabled ? */ |
defc9cd82 pata_legacy: resy... |
1058 |
return; |
defc9cd82 pata_legacy: resy... |
1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 |
legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), QDI6500, port); } if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { /* QD6580: dual channel */ if (!request_region(port + 2 , 2, "pata_qdi")) { release_region(port, 2); return; } res = inb(port + 3); /* Single channel mode ? */ if (res & 1) legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), QDI6580, port); else { /* Dual channel mode */ legacy_probe_add(0x1F0, 14, QDI6580DP, port); /* port + 0x02, r & 0x04 */ legacy_probe_add(0x170, 15, QDI6580DP, port + 2); } |
b83254877 pata_legacy: Merg... |
1078 |
release_region(port + 2, 2); |
defc9cd82 pata_legacy: resy... |
1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 |
} } static __init void probe_qdi_vlb(void) { unsigned long flags; static const unsigned long qd_port[2] = { 0x30, 0xB0 }; int i; /* * Check each possible QD65xx base address */ for (i = 0; i < 2; i++) { unsigned long port = qd_port[i]; u8 r, res; if (request_region(port, 2, "pata_qdi")) { /* Check for a card */ local_irq_save(flags); /* I have no h/w that needs this delay but it is present in the historic code */ r = inb(port); udelay(1); outb(0x19, port); udelay(1); res = inb(port); udelay(1); outb(r, port); udelay(1); local_irq_restore(flags); /* Fail */ if (res == 0x19) { release_region(port, 2); continue; } /* Passes the presence test */ r = inb(port + 1); udelay(1); /* Check port agrees with port set */ |
b83254877 pata_legacy: Merg... |
1121 1122 1123 |
if ((r & 2) >> 1 == i) qdi65_identify_port(r, res, port); release_region(port, 2); |
defc9cd82 pata_legacy: resy... |
1124 1125 1126 |
} } } |
669a5db41 [libata] Add a bu... |
1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 |
/** * legacy_init - attach legacy interfaces * * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. * Right now we do not scan the ide0 and ide1 address but should do so * for non PCI systems or systems with no PCI IDE legacy mode devices. * If you fix that note there are special cases to consider like VLB * drivers and CS5510/20. */ static __init int legacy_init(void) { int i; int ct = 0; int primary = 0; int secondary = 0; |
defc9cd82 pata_legacy: resy... |
1144 1145 1146 |
int pci_present = 0; struct legacy_probe *pl = &probe_list[0]; int slot = 0; |
669a5db41 [libata] Add a bu... |
1147 1148 1149 1150 1151 |
struct pci_dev *p = NULL; for_each_pci_dev(p) { int r; |
defc9cd82 pata_legacy: resy... |
1152 1153 1154 |
/* Check for any overlap of the system ATA mappings. Native mode controllers stuck on these addresses or some devices in 'raid' mode won't be found by the storage class test */ |
669a5db41 [libata] Add a bu... |
1155 1156 1157 1158 1159 1160 1161 1162 |
for (r = 0; r < 6; r++) { if (pci_resource_start(p, r) == 0x1f0) primary = 1; if (pci_resource_start(p, r) == 0x170) secondary = 1; } /* Check for special cases */ legacy_check_special_cases(p, &primary, &secondary); |
defc9cd82 pata_legacy: resy... |
1163 1164 1165 |
/* If PCI bus is present then don't probe for tertiary legacy ports */ pci_present = 1; |
669a5db41 [libata] Add a bu... |
1166 |
} |
b83254877 pata_legacy: Merg... |
1167 1168 |
if (winbond == 1) winbond = 0x130; /* Default port, alt is 1B0 */ |
defc9cd82 pata_legacy: resy... |
1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 |
if (primary == 0 || all) legacy_probe_add(0x1F0, 14, UNKNOWN, 0); if (secondary == 0 || all) legacy_probe_add(0x170, 15, UNKNOWN, 0); if (probe_all || !pci_present) { /* ISA/VLB extra ports */ legacy_probe_add(0x1E8, 11, UNKNOWN, 0); legacy_probe_add(0x168, 10, UNKNOWN, 0); legacy_probe_add(0x1E0, 8, UNKNOWN, 0); legacy_probe_add(0x160, 12, UNKNOWN, 0); |
669a5db41 [libata] Add a bu... |
1180 |
} |
defc9cd82 pata_legacy: resy... |
1181 1182 1183 1184 |
if (opti82c46x) probe_opti_vlb(); if (qdi) probe_qdi_vlb(); |
defc9cd82 pata_legacy: resy... |
1185 1186 |
for (i = 0; i < NR_HOST; i++, pl++) { if (pl->port == 0) |
669a5db41 [libata] Add a bu... |
1187 |
continue; |
defc9cd82 pata_legacy: resy... |
1188 1189 1190 1191 |
if (pl->type == UNKNOWN) pl->type = probe_chip_type(pl); pl->slot = slot++; if (legacy_init_one(pl) == 0) |
669a5db41 [libata] Add a bu... |
1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 |
ct++; } if (ct != 0) return 0; return -ENODEV; } static __exit void legacy_exit(void) { int i; for (i = 0; i < nr_legacy_host; i++) { struct legacy_data *ld = &legacy_data[i]; |
24dc5f33e libata: update li... |
1205 |
ata_host_detach(legacy_host[i]); |
669a5db41 [libata] Add a bu... |
1206 |
platform_device_unregister(ld->platform_dev); |
669a5db41 [libata] Add a bu... |
1207 1208 1209 1210 1211 1212 1213 |
} } MODULE_AUTHOR("Alan Cox"); MODULE_DESCRIPTION("low-level driver for legacy ATA"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_VERSION); |
0dcd0a763 libata: remove no... |
1214 |
MODULE_ALIAS("pata_qdi"); |
6d981b9a9 libata: remove no... |
1215 |
MODULE_ALIAS("pata_winbond"); |
669a5db41 [libata] Add a bu... |
1216 1217 1218 1219 1220 1221 1222 |
module_param(probe_all, int, 0); module_param(autospeed, int, 0); module_param(ht6560a, int, 0); module_param(ht6560b, int, 0); module_param(opti82c611a, int, 0); module_param(opti82c46x, int, 0); |
defc9cd82 pata_legacy: resy... |
1223 |
module_param(qdi, int, 0); |
6d981b9a9 libata: remove no... |
1224 |
module_param(winbond, int, 0); |
669a5db41 [libata] Add a bu... |
1225 |
module_param(pio_mask, int, 0); |
f834e49f1 libata: Add a hos... |
1226 |
module_param(iordy_mask, int, 0); |
669a5db41 [libata] Add a bu... |
1227 1228 1229 |
module_init(legacy_init); module_exit(legacy_exit); |