Blame view
drivers/rtc/rtc-mt6397.c
9.1 KB
1802d0bee
|
1 |
// SPDX-License-Identifier: GPL-2.0-only |
fc2979118
|
2 3 4 |
/* * Copyright (c) 2014-2015 MediaTek Inc. * Author: Tianping.Fang <tianping.fang@mediatek.com> |
fc2979118
|
5 |
*/ |
851b87148
|
6 7 8 |
#include <linux/err.h> #include <linux/interrupt.h> #include <linux/mfd/mt6397/core.h> |
fc2979118
|
9 |
#include <linux/module.h> |
851b87148
|
10 |
#include <linux/mutex.h> |
29ee40091
|
11 |
#include <linux/of_device.h> |
851b87148
|
12 |
#include <linux/platform_device.h> |
fc2979118
|
13 14 |
#include <linux/regmap.h> #include <linux/rtc.h> |
c512995ce
|
15 |
#include <linux/mfd/mt6397/rtc.h> |
851b87148
|
16 |
#include <linux/mod_devicetable.h> |
fc2979118
|
17 18 19 |
static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) { |
fc2979118
|
20 21 |
int ret; u32 data; |
29ee40091
|
22 |
ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1); |
fc2979118
|
23 24 |
if (ret < 0) return ret; |
851b87148
|
25 26 27 28 29 30 |
ret = regmap_read_poll_timeout(rtc->regmap, rtc->addr_base + RTC_BBPU, data, !(data & RTC_BBPU_CBUSY), MTK_RTC_POLL_DELAY_US, MTK_RTC_POLL_TIMEOUT); if (ret < 0) |
770c03e6d
|
31 32 33 |
dev_err(rtc->rtc_dev->dev.parent, "failed to write WRTGR: %d ", ret); |
fc2979118
|
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 |
return ret; } static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data) { struct mt6397_rtc *rtc = data; u32 irqsta, irqen; int ret; ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta); if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) { rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); irqen = irqsta & ~RTC_IRQ_EN_AL; mutex_lock(&rtc->lock); if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, |
653997eee
|
50 |
irqen) == 0) |
fc2979118
|
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 |
mtk_rtc_write_trigger(rtc); mutex_unlock(&rtc->lock); return IRQ_HANDLED; } return IRQ_NONE; } static int __mtk_rtc_read_time(struct mt6397_rtc *rtc, struct rtc_time *tm, int *sec) { int ret; u16 data[RTC_OFFSET_COUNT]; mutex_lock(&rtc->lock); ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, data, RTC_OFFSET_COUNT); if (ret < 0) goto exit; tm->tm_sec = data[RTC_OFFSET_SEC]; tm->tm_min = data[RTC_OFFSET_MIN]; tm->tm_hour = data[RTC_OFFSET_HOUR]; tm->tm_mday = data[RTC_OFFSET_DOM]; tm->tm_mon = data[RTC_OFFSET_MTH]; tm->tm_year = data[RTC_OFFSET_YEAR]; ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec); exit: mutex_unlock(&rtc->lock); return ret; } static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm) { time64_t time; struct mt6397_rtc *rtc = dev_get_drvdata(dev); |
939399676
|
89 |
int days, sec, ret; |
fc2979118
|
90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 |
do { ret = __mtk_rtc_read_time(rtc, tm, &sec); if (ret < 0) goto exit; } while (sec < tm->tm_sec); /* HW register use 7 bits to store year data, minus * RTC_MIN_YEAR_OFFSET before write year data to register, and plus * RTC_MIN_YEAR_OFFSET back after read year from register */ tm->tm_year += RTC_MIN_YEAR_OFFSET; /* HW register start mon from one, but tm_mon start from zero. */ tm->tm_mon--; time = rtc_tm_to_time64(tm); /* rtc_tm_to_time64 covert Gregorian date to seconds since * 01-01-1970 00:00:00, and this date is Thursday. */ |
939399676
|
110 111 |
days = div_s64(time, 86400); tm->tm_wday = (days + 4) % 7; |
fc2979118
|
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 |
exit: return ret; } static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm) { struct mt6397_rtc *rtc = dev_get_drvdata(dev); int ret; u16 data[RTC_OFFSET_COUNT]; tm->tm_year -= RTC_MIN_YEAR_OFFSET; tm->tm_mon++; data[RTC_OFFSET_SEC] = tm->tm_sec; data[RTC_OFFSET_MIN] = tm->tm_min; data[RTC_OFFSET_HOUR] = tm->tm_hour; data[RTC_OFFSET_DOM] = tm->tm_mday; data[RTC_OFFSET_MTH] = tm->tm_mon; data[RTC_OFFSET_YEAR] = tm->tm_year; mutex_lock(&rtc->lock); ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC, data, RTC_OFFSET_COUNT); if (ret < 0) goto exit; /* Time register write to hardware after call trigger function */ ret = mtk_rtc_write_trigger(rtc); exit: mutex_unlock(&rtc->lock); return ret; } static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) { struct rtc_time *tm = &alm->time; struct mt6397_rtc *rtc = dev_get_drvdata(dev); u32 irqen, pdn2; int ret; u16 data[RTC_OFFSET_COUNT]; mutex_lock(&rtc->lock); ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen); if (ret < 0) goto err_exit; ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2); if (ret < 0) goto err_exit; ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC, data, RTC_OFFSET_COUNT); if (ret < 0) goto err_exit; alm->enabled = !!(irqen & RTC_IRQ_EN_AL); alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM); mutex_unlock(&rtc->lock); |
653997eee
|
171 172 173 174 175 176 |
tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK; tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK; tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK; tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK; tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK; tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK; |
fc2979118
|
177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 |
tm->tm_year += RTC_MIN_YEAR_OFFSET; tm->tm_mon--; return 0; err_exit: mutex_unlock(&rtc->lock); return ret; } static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) { struct rtc_time *tm = &alm->time; struct mt6397_rtc *rtc = dev_get_drvdata(dev); int ret; u16 data[RTC_OFFSET_COUNT]; tm->tm_year -= RTC_MIN_YEAR_OFFSET; tm->tm_mon++; |
fc2979118
|
196 |
mutex_lock(&rtc->lock); |
653997eee
|
197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 |
ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC, data, RTC_OFFSET_COUNT); if (ret < 0) goto exit; data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) | (tm->tm_sec & RTC_AL_SEC_MASK)); data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) | (tm->tm_min & RTC_AL_MIN_MASK)); data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) | (tm->tm_hour & RTC_AL_HOU_MASK)); data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) | (tm->tm_mday & RTC_AL_DOM_MASK)); data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) | (tm->tm_mon & RTC_AL_MTH_MASK)); data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) | (tm->tm_year & RTC_AL_YEA_MASK)); |
fc2979118
|
214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 |
if (alm->enabled) { ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_AL_SEC, data, RTC_OFFSET_COUNT); if (ret < 0) goto exit; ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK, RTC_AL_MASK_DOW); if (ret < 0) goto exit; ret = regmap_update_bits(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, RTC_IRQ_EN_ONESHOT_AL, RTC_IRQ_EN_ONESHOT_AL); if (ret < 0) goto exit; } else { ret = regmap_update_bits(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, RTC_IRQ_EN_ONESHOT_AL, 0); if (ret < 0) goto exit; } /* All alarm time register write to hardware after calling * mtk_rtc_write_trigger. This can avoid race condition if alarm * occur happen during writing alarm time register. */ ret = mtk_rtc_write_trigger(rtc); exit: mutex_unlock(&rtc->lock); return ret; } |
34c7b3ac4
|
247 |
static const struct rtc_class_ops mtk_rtc_ops = { |
fc2979118
|
248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 |
.read_time = mtk_rtc_read_time, .set_time = mtk_rtc_set_time, .read_alarm = mtk_rtc_read_alarm, .set_alarm = mtk_rtc_set_alarm, }; static int mtk_rtc_probe(struct platform_device *pdev) { struct resource *res; struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent); struct mt6397_rtc *rtc; int ret; rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL); if (!rtc) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); rtc->addr_base = res->start; |
29ee40091
|
267 |
rtc->data = of_device_get_match_data(&pdev->dev); |
e695d3a0b
|
268 269 270 |
rtc->irq = platform_get_irq(pdev, 0); if (rtc->irq < 0) return rtc->irq; |
fc2979118
|
271 272 |
rtc->regmap = mt6397_chip->regmap; |
fc2979118
|
273 274 275 |
mutex_init(&rtc->lock); platform_set_drvdata(pdev, rtc); |
851b87148
|
276 |
rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); |
babab2f86
|
277 278 |
if (IS_ERR(rtc->rtc_dev)) return PTR_ERR(rtc->rtc_dev); |
851b87148
|
279 280 281 282 |
ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL, mtk_rtc_irq_handler_thread, IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mt6397-rtc", rtc); |
fc2979118
|
283 284 285 286 |
if (ret) { dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d ", rtc->irq, ret); |
24db953e9
|
287 |
return ret; |
fc2979118
|
288 |
} |
baeca4495
|
289 |
device_init_wakeup(&pdev->dev, 1); |
babab2f86
|
290 |
rtc->rtc_dev->ops = &mtk_rtc_ops; |
751438bc0
|
291 |
return rtc_register_device(rtc->rtc_dev); |
fc2979118
|
292 |
} |
d7f9777de
|
293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 |
#ifdef CONFIG_PM_SLEEP static int mt6397_rtc_suspend(struct device *dev) { struct mt6397_rtc *rtc = dev_get_drvdata(dev); if (device_may_wakeup(dev)) enable_irq_wake(rtc->irq); return 0; } static int mt6397_rtc_resume(struct device *dev) { struct mt6397_rtc *rtc = dev_get_drvdata(dev); if (device_may_wakeup(dev)) disable_irq_wake(rtc->irq); return 0; } #endif static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend, mt6397_rtc_resume); |
29ee40091
|
317 318 319 320 321 322 323 |
static const struct mtk_rtc_data mt6358_rtc_data = { .wrtgr = RTC_WRTGR_MT6358, }; static const struct mtk_rtc_data mt6397_rtc_data = { .wrtgr = RTC_WRTGR_MT6397, }; |
fc2979118
|
324 |
static const struct of_device_id mt6397_rtc_of_match[] = { |
29ee40091
|
325 326 327 |
{ .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data }, { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data }, { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data }, |
fc2979118
|
328 329 |
{ } }; |
73798d5c4
|
330 |
MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match); |
fc2979118
|
331 332 333 334 335 |
static struct platform_driver mtk_rtc_driver = { .driver = { .name = "mt6397-rtc", .of_match_table = mt6397_rtc_of_match, |
d7f9777de
|
336 |
.pm = &mt6397_pm_ops, |
fc2979118
|
337 338 |
}, .probe = mtk_rtc_probe, |
fc2979118
|
339 340 341 342 343 344 345 |
}; module_platform_driver(mtk_rtc_driver); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>"); MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC"); |