Blame view
drivers/pwm/pwm-lpss-pci.c
3.02 KB
d2912cb15
|
1 |
// SPDX-License-Identifier: GPL-2.0-only |
c558e39e1
|
2 3 4 5 6 7 |
/* * Intel Low Power Subsystem PWM controller PCI driver * * Copyright (C) 2014, Intel Corporation * * Derived from the original pwm-lpss.c |
c558e39e1
|
8 9 10 11 12 |
*/ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> |
f080be27d
|
13 |
#include <linux/pm_runtime.h> |
c558e39e1
|
14 15 |
#include "pwm-lpss.h" |
9900073cf
|
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 |
/* BayTrail */ static const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { .clk_rate = 25000000, .npwm = 1, .base_unit_bits = 16, }; /* Braswell */ static const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = { .clk_rate = 19200000, .npwm = 1, .base_unit_bits = 16, }; /* Broxton */ static const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = { .clk_rate = 19200000, .npwm = 4, .base_unit_bits = 22, |
b997e3edc
|
35 |
.bypass = true, |
9900073cf
|
36 |
}; |
3c1460e93
|
37 38 39 40 41 42 |
/* Tangier */ static const struct pwm_lpss_boardinfo pwm_lpss_tng_info = { .clk_rate = 19200000, .npwm = 4, .base_unit_bits = 22, }; |
c558e39e1
|
43 44 45 46 47 48 |
static int pwm_lpss_probe_pci(struct pci_dev *pdev, const struct pci_device_id *id) { const struct pwm_lpss_boardinfo *info; struct pwm_lpss_chip *lpwm; int err; |
90927fe9a
|
49 |
err = pcim_enable_device(pdev); |
c558e39e1
|
50 51 52 53 54 55 56 57 58 |
if (err < 0) return err; info = (struct pwm_lpss_boardinfo *)id->driver_data; lpwm = pwm_lpss_probe(&pdev->dev, &pdev->resource[0], info); if (IS_ERR(lpwm)) return PTR_ERR(lpwm); pci_set_drvdata(pdev, lpwm); |
f080be27d
|
59 60 61 |
pm_runtime_put(&pdev->dev); pm_runtime_allow(&pdev->dev); |
c558e39e1
|
62 63 64 65 66 67 |
return 0; } static void pwm_lpss_remove_pci(struct pci_dev *pdev) { struct pwm_lpss_chip *lpwm = pci_get_drvdata(pdev); |
f080be27d
|
68 69 |
pm_runtime_forbid(&pdev->dev); pm_runtime_get_sync(&pdev->dev); |
c558e39e1
|
70 |
pwm_lpss_remove(lpwm); |
c558e39e1
|
71 |
} |
f080be27d
|
72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 |
#ifdef CONFIG_PM static int pwm_lpss_runtime_suspend_pci(struct device *dev) { /* * The PCI core will handle transition to D3 automatically. We only * need to provide runtime PM hooks for that to happen. */ return 0; } static int pwm_lpss_runtime_resume_pci(struct device *dev) { return 0; } #endif static const struct dev_pm_ops pwm_lpss_pci_pm = { SET_RUNTIME_PM_OPS(pwm_lpss_runtime_suspend_pci, pwm_lpss_runtime_resume_pci, NULL) }; |
c558e39e1
|
92 |
static const struct pci_device_id pwm_lpss_pci_ids[] = { |
87219cb47
|
93 |
{ PCI_VDEVICE(INTEL, 0x0ac8), (unsigned long)&pwm_lpss_bxt_info}, |
c558e39e1
|
94 95 |
{ PCI_VDEVICE(INTEL, 0x0f08), (unsigned long)&pwm_lpss_byt_info}, { PCI_VDEVICE(INTEL, 0x0f09), (unsigned long)&pwm_lpss_byt_info}, |
3c1460e93
|
96 |
{ PCI_VDEVICE(INTEL, 0x11a5), (unsigned long)&pwm_lpss_tng_info}, |
87219cb47
|
97 |
{ PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)&pwm_lpss_bxt_info}, |
c558e39e1
|
98 99 |
{ PCI_VDEVICE(INTEL, 0x2288), (unsigned long)&pwm_lpss_bsw_info}, { PCI_VDEVICE(INTEL, 0x2289), (unsigned long)&pwm_lpss_bsw_info}, |
ae2520540
|
100 |
{ PCI_VDEVICE(INTEL, 0x31c8), (unsigned long)&pwm_lpss_bxt_info}, |
03f00e531
|
101 |
{ PCI_VDEVICE(INTEL, 0x5ac8), (unsigned long)&pwm_lpss_bxt_info}, |
c558e39e1
|
102 103 104 105 106 107 108 109 110 |
{ }, }; MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids); static struct pci_driver pwm_lpss_driver_pci = { .name = "pwm-lpss", .id_table = pwm_lpss_pci_ids, .probe = pwm_lpss_probe_pci, .remove = pwm_lpss_remove_pci, |
f080be27d
|
111 112 113 |
.driver = { .pm = &pwm_lpss_pci_pm, }, |
c558e39e1
|
114 115 116 117 118 |
}; module_pci_driver(pwm_lpss_driver_pci); MODULE_DESCRIPTION("PWM PCI driver for Intel LPSS"); MODULE_LICENSE("GPL v2"); |