Blame view
include/asm-x86_64/apic.h
2.73 KB
1da177e4c
|
1 2 |
#ifndef __ASM_APIC_H #define __ASM_APIC_H |
1da177e4c
|
3 |
#include <linux/pm.h> |
8339e9fba
|
4 |
#include <linux/delay.h> |
1da177e4c
|
5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
#include <asm/fixmap.h> #include <asm/apicdef.h> #include <asm/system.h> #define Dprintk(x...) /* * Debugging macros */ #define APIC_QUIET 0 #define APIC_VERBOSE 1 #define APIC_DEBUG 2 extern int apic_verbosity; |
73dea47fa
|
19 |
extern int apic_runs_main_timer; |
2c8c0e6b8
|
20 |
extern int ioapic_force; |
b7f5e3c77
|
21 |
extern int apic_mapped; |
1da177e4c
|
22 23 24 25 26 27 28 29 30 31 32 |
/* * Define the default level of output to be very little * This can be turned up by using apic=verbose for more * information and apic=debug for _lots_ of information. * apic_verbosity is defined in apic.c */ #define apic_printk(v, s, a...) do { \ if ((v) <= apic_verbosity) \ printk(s, ##a); \ } while (0) |
1da177e4c
|
33 34 35 36 37 38 39 40 41 42 |
struct pt_regs; /* * Basic functions accessing APICs. */ static __inline void apic_write(unsigned long reg, unsigned int v) { *((volatile unsigned int *)(APIC_BASE+reg)) = v; } |
1da177e4c
|
43 44 45 46 |
static __inline unsigned int apic_read(unsigned long reg) { return *((volatile unsigned int *)(APIC_BASE+reg)); } |
8339e9fba
|
47 48 |
extern void apic_wait_icr_idle(void); extern unsigned int safe_apic_wait_icr_idle(void); |
1da177e4c
|
49 |
|
1da177e4c
|
50 51 52 53 54 55 56 57 58 59 |
static inline void ack_APIC_irq(void) { /* * ack_APIC_irq() actually gets compiled as a single instruction: * - a single rmw on Pentium/82489DX * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC) * ... yummie. */ /* Docs say use 0 for future compatibility */ |
11a8e778c
|
60 |
apic_write(APIC_EOI, 0); |
1da177e4c
|
61 62 63 64 65 |
} extern int get_maxlvt (void); extern void clear_local_APIC (void); extern void connect_bsp_APIC (void); |
208fb9316
|
66 |
extern void disconnect_bsp_APIC (int virt_wire_setup); |
1da177e4c
|
67 68 69 70 71 72 73 |
extern void disable_local_APIC (void); extern int verify_local_APIC (void); extern void cache_APIC_registers (void); extern void sync_Arb_IDs (void); extern void init_bsp_APIC (void); extern void setup_local_APIC (void); extern void init_apic_mappings (void); |
7d12e780e
|
74 |
extern void smp_local_timer_interrupt (void); |
1da177e4c
|
75 76 |
extern void setup_boot_APIC_clock (void); extern void setup_secondary_APIC_clock (void); |
1da177e4c
|
77 78 79 |
extern int APIC_init_uniprocessor (void); extern void disable_APIC_timer(void); extern void enable_APIC_timer(void); |
3c43f0390
|
80 |
extern void setup_apic_routing(void); |
1da177e4c
|
81 |
|
f40f31bfe
|
82 83 |
extern void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector, unsigned char msg_type, unsigned char mask); |
17fc14ff1
|
84 |
|
55f93afd8
|
85 |
extern int apic_is_clustered_box(void); |
17fc14ff1
|
86 87 88 89 90 91 |
#define K8_APIC_EXT_LVT_BASE 0x500 #define K8_APIC_EXT_INT_MSG_FIX 0x0 #define K8_APIC_EXT_INT_MSG_SMI 0x2 #define K8_APIC_EXT_INT_MSG_NMI 0x4 #define K8_APIC_EXT_INT_MSG_EXT 0x7 #define K8_APIC_EXT_LVT_ENTRY_THRESHOLD 0 |
d25bf7e5f
|
92 93 94 95 96 |
void smp_send_timer_broadcast_ipi(void); void switch_APIC_timer_to_ipi(void *cpumask); void switch_ipi_to_APIC_timer(void *cpumask); #define ARCH_APICTIMER_STOPS_ON_C3 1 |
1da177e4c
|
97 |
extern unsigned boot_cpu_id; |
2e7c28382
|
98 |
extern int local_apic_timer_c2_ok; |
1da177e4c
|
99 100 |
#endif /* __ASM_APIC_H */ |