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drivers/edac/i7300_edac.c
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/* * Intel 7300 class Memory Controllers kernel module (Clarksboro) * * This file may be distributed under the terms of the * GNU General Public License version 2 only. * * Copyright (c) 2010 by: * Mauro Carvalho Chehab <mchehab@redhat.com> * * Red Hat Inc. http://www.redhat.com * * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet * http://www.intel.com/Assets/PDF/datasheet/318082.pdf * * TODO: The chipset allow checking for PCI Express errors also. Currently, * the driver covers only memory error errors * * This driver uses "csrows" EDAC attribute to represent DIMM slot# */ #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> #include <linux/edac.h> #include <linux/mmzone.h> #include "edac_core.h" /* * Alter this version for the I7300 module when modifications are made */ |
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#define I7300_REVISION " Ver: 1.0.0" |
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#define EDAC_MOD_STR "i7300_edac" #define i7300_printk(level, fmt, arg...) \ edac_printk(level, "i7300", fmt, ##arg) #define i7300_mc_printk(mci, level, fmt, arg...) \ edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg) |
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/*********************************************** * i7300 Limit constants Structs and static vars ***********************************************/ |
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/* * Memory topology is organized as: * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0) * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0) * Each channel can have to 8 DIMM sets (called as SLOTS) * Slots should generally be filled in pairs * Except on Single Channel mode of operation * just slot 0/channel0 filled on this mode * On normal operation mode, the two channels on a branch should be |
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* filled together for the same SLOT# |
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* When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four * channels on both branches should be filled */ /* Limits for i7300 */ #define MAX_SLOTS 8 #define MAX_BRANCHES 2 #define MAX_CH_PER_BRANCH 2 #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES) #define MAX_MIR 3 #define to_channel(ch, branch) ((((branch)) << 1) | (ch)) #define to_csrow(slot, ch, branch) \ (to_channel(ch, branch) | ((slot) << 2)) |
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/* Device name and register DID (Device ID) */ struct i7300_dev_info { const char *ctl_name; /* name for this device */ u16 fsb_mapping_errors; /* DID for the branchmap,control */ }; /* Table of devices attributes supported by this driver */ static const struct i7300_dev_info i7300_devs[] = { { .ctl_name = "I7300", .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, }, }; struct i7300_dimm_info { int megabytes; /* size, 0 means not present */ }; /* driver private data structure */ struct i7300_pvt { struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */ struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */ struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */ struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */ u16 tolm; /* top of low memory */ u64 ambase; /* AMB BAR */ u32 mc_settings; /* Report several settings */ u32 mc_settings_a; u16 mir[MAX_MIR]; /* Memory Interleave Reg*/ |
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u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ |
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u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */ /* DIMM information matrix, allocating architecture maximums */ struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS]; /* Temporary buffer for use when preparing error messages */ char *tmp_prt_buffer; }; /* FIXME: Why do we need to have this static? */ static struct edac_pci_ctl_info *i7300_pci; /*************************************************** * i7300 Register definitions for memory enumeration ***************************************************/ |
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/* |
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* Device 16, * Function 0: System Address (not documented) * Function 1: Memory Branch Map, Control, Errors Register */ |
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/* OFFSETS for Function 0 */ |
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#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ #define MAXCH 0x56 /* Max Channel Number */ #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ |
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/* OFFSETS for Function 1 */ |
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#define MC_SETTINGS 0x40 |
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#define IS_MIRRORED(mc) ((mc) & (1 << 16)) #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5)) #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31)) #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8)) |
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|
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#define MC_SETTINGS_A 0x58 #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14)) |
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|
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#define TOLM 0x6C |
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#define MIR0 0x80 #define MIR1 0x84 #define MIR2 0x88 |
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|
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/* * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it * seems that we cannot use this information directly for the same usage. * Each memory slot may have up to 2 AMB interfaces, one for income and another * for outcome interface to the next slot. * For now, the driver just stores the AMB present registers, but rely only at * the MTR info to detect memory. * Datasheet is also not clear about how to map each AMBPRESENT registers to * one of the 4 available channels. */ #define AMBPRESENT_0 0x64 #define AMBPRESENT_1 0x66 |
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static const u16 mtr_regs[MAX_SLOTS] = { |
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0x80, 0x84, 0x88, 0x8c, 0x82, 0x86, 0x8a, 0x8e }; |
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/* * Defines to extract the vaious fields from the |
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* MTRx - Memory Technology Registers */ #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) #define MTR_DRAM_BANKS_ADDR_BITS 2 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) |
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#ifdef CONFIG_EDAC_DEBUG /* MTR NUMROW */ static const char *numrow_toString[] = { "8,192 - 13 rows", "16,384 - 14 rows", "32,768 - 15 rows", "65,536 - 16 rows" }; /* MTR NUMCOL */ static const char *numcol_toString[] = { "1,024 - 10 columns", "2,048 - 11 columns", "4,096 - 12 columns", "reserved" }; #endif |
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/************************************************ * i7300 Register definitions for error detection ************************************************/ |
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/* * Device 16.1: FBD Error Registers */ #define FERR_FAT_FBD 0x98 static const char *ferr_fat_fbd_name[] = { [22] = "Non-Redundant Fast Reset Timeout", [2] = ">Tmid Thermal event with intelligent throttling disabled", [1] = "Memory or FBD configuration CRC read error", [0] = "Memory Write error on non-redundant retry or " "FBD configuration Write error on retry", }; #define GET_FBD_FAT_IDX(fbderr) (fbderr & (3 << 28)) #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) #define FERR_NF_FBD 0xa0 static const char *ferr_nf_fbd_name[] = { [24] = "DIMM-Spare Copy Completed", [23] = "DIMM-Spare Copy Initiated", [22] = "Redundant Fast Reset Timeout", [21] = "Memory Write error on redundant retry", [18] = "SPD protocol Error", [17] = "FBD Northbound parity error on FBD Sync Status", [16] = "Correctable Patrol Data ECC", [15] = "Correctable Resilver- or Spare-Copy Data ECC", [14] = "Correctable Mirrored Demand Data ECC", [13] = "Correctable Non-Mirrored Demand Data ECC", [11] = "Memory or FBD configuration CRC read error", [10] = "FBD Configuration Write error on first attempt", [9] = "Memory Write error on first attempt", [8] = "Non-Aliased Uncorrectable Patrol Data ECC", [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC", [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", [4] = "Aliased Uncorrectable Patrol Data ECC", [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", [2] = "Aliased Uncorrectable Mirrored Demand Data ECC", [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", [0] = "Uncorrectable Data ECC on Replay", }; #define GET_FBD_NF_IDX(fbderr) (fbderr & (3 << 28)) #define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\ (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\ (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\ (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ (1 << 1) | (1 << 0)) #define EMASK_FBD 0xa8 #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\ (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\ (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\ (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\ (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ (1 << 1) | (1 << 0)) |
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/* * Device 16.2: Global Error Registers */ |
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#define FERR_GLOBAL_HI 0x48 static const char *ferr_global_hi_name[] = { [3] = "FSB 3 Fatal Error", [2] = "FSB 2 Fatal Error", [1] = "FSB 1 Fatal Error", [0] = "FSB 0 Fatal Error", }; #define ferr_global_hi_is_fatal(errno) 1 |
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#define FERR_GLOBAL_LO 0x40 |
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static const char *ferr_global_lo_name[] = { |
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[31] = "Internal MCH Fatal Error", [30] = "Intel QuickData Technology Device Fatal Error", [29] = "FSB1 Fatal Error", [28] = "FSB0 Fatal Error", [27] = "FBD Channel 3 Fatal Error", [26] = "FBD Channel 2 Fatal Error", [25] = "FBD Channel 1 Fatal Error", [24] = "FBD Channel 0 Fatal Error", [23] = "PCI Express Device 7Fatal Error", [22] = "PCI Express Device 6 Fatal Error", [21] = "PCI Express Device 5 Fatal Error", [20] = "PCI Express Device 4 Fatal Error", [19] = "PCI Express Device 3 Fatal Error", [18] = "PCI Express Device 2 Fatal Error", [17] = "PCI Express Device 1 Fatal Error", [16] = "ESI Fatal Error", [15] = "Internal MCH Non-Fatal Error", [14] = "Intel QuickData Technology Device Non Fatal Error", [13] = "FSB1 Non-Fatal Error", [12] = "FSB 0 Non-Fatal Error", [11] = "FBD Channel 3 Non-Fatal Error", [10] = "FBD Channel 2 Non-Fatal Error", [9] = "FBD Channel 1 Non-Fatal Error", [8] = "FBD Channel 0 Non-Fatal Error", [7] = "PCI Express Device 7 Non-Fatal Error", [6] = "PCI Express Device 6 Non-Fatal Error", [5] = "PCI Express Device 5 Non-Fatal Error", [4] = "PCI Express Device 4 Non-Fatal Error", [3] = "PCI Express Device 3 Non-Fatal Error", [2] = "PCI Express Device 2 Non-Fatal Error", [1] = "PCI Express Device 1 Non-Fatal Error", [0] = "ESI Non-Fatal Error", }; |
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#define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1) |
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|
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#define NRECMEMA 0xbe #define NRECMEMA_BANK(v) (((v) >> 12) & 7) #define NRECMEMA_RANK(v) (((v) >> 8) & 15) #define NRECMEMB 0xc0 #define NRECMEMB_IS_WR(v) ((v) & (1 << 31)) #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff) #define NRECMEMB_RAS(v) ((v) & 0xffff) |
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#define REDMEMA 0xdc |
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#define REDMEMB 0x7c #define IS_SECOND_CH(v) ((v) * (1 << 17)) |
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#define RECMEMA 0xe0 #define RECMEMA_BANK(v) (((v) >> 12) & 7) #define RECMEMA_RANK(v) (((v) >> 8) & 15) #define RECMEMB 0xe4 #define RECMEMB_IS_WR(v) ((v) & (1 << 31)) #define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff) #define RECMEMB_RAS(v) ((v) & 0xffff) |
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/******************************************** * i7300 Functions related to error detection ********************************************/ |
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/** * get_err_from_table() - Gets the error message from a table * @table: table name (array of char *) * @size: number of elements at the table * @pos: position of the element to be returned * * This is a small routine that gets the pos-th element of a table. If the * element doesn't exist (or it is empty), it returns "reserved". * Instead of calling it directly, the better is to call via the macro * GET_ERR_FROM_TABLE(), that automatically checks the table size via * ARRAY_SIZE() macro */ static const char *get_err_from_table(const char *table[], int size, int pos) |
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{ |
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if (unlikely(pos >= size)) return "Reserved"; if (unlikely(!table[pos])) |
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return "Reserved"; return table[pos]; |
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} |
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#define GET_ERR_FROM_TABLE(table, pos) \ get_err_from_table(table, ARRAY_SIZE(table), pos) |
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/** * i7300_process_error_global() - Retrieve the hardware error information from * the hardware global error registers and * sends it to dmesg * @mci: struct mem_ctl_info pointer |
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*/ |
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static void i7300_process_error_global(struct mem_ctl_info *mci) |
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{ |
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struct i7300_pvt *pvt; |
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u32 errnum, error_reg; |
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unsigned long errors; const char *specific; bool is_fatal; |
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pvt = mci->pvt_info; |
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|
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/* read in the 1st FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
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FERR_GLOBAL_HI, &error_reg); if (unlikely(error_reg)) { errors = error_reg; |
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errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_global_hi_name)); specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum); is_fatal = ferr_global_hi_is_fatal(errnum); |
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/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
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FERR_GLOBAL_HI, error_reg); |
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|
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goto error_global; |
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} |
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pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
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FERR_GLOBAL_LO, &error_reg); if (unlikely(error_reg)) { errors = error_reg; |
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errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_global_lo_name)); specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum); is_fatal = ferr_global_lo_is_fatal(errnum); |
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/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
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FERR_GLOBAL_LO, error_reg); |
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|
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goto error_global; } return; |
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error_global: i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s ", is_fatal ? "Fatal" : "NOT fatal", specific); |
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} |
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/** * i7300_process_fbd_error() - Retrieve the hardware error information from * the FBD error registers and sends it via * EDAC error API calls * @mci: struct mem_ctl_info pointer |
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*/ |
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static void i7300_process_fbd_error(struct mem_ctl_info *mci) |
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{ struct i7300_pvt *pvt; |
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u32 errnum, value, error_reg; |
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u16 val16; |
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unsigned branch, channel, bank, rank, cas, ras; |
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u32 syndrome; |
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unsigned long errors; const char *specific; |
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bool is_wr; |
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pvt = mci->pvt_info; /* read in the 1st FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, |
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FERR_FAT_FBD, &error_reg); if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) { errors = error_reg & FERR_FAT_FBD_ERR_MASK ; |
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errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_fat_fbd_name)); specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum); |
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branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0; |
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|
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pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, NRECMEMA, &val16); bank = NRECMEMA_BANK(val16); rank = NRECMEMA_RANK(val16); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, NRECMEMB, &value); |
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is_wr = NRECMEMB_IS_WR(value); cas = NRECMEMB_CAS(value); ras = NRECMEMB_RAS(value); |
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/* Clean the error register */ pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, error_reg); |
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snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, "FATAL (Branch=%d DRAM-Bank=%d %s " "RAS=%d CAS=%d Err=0x%lx (%s))", |
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branch, bank, |
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is_wr ? "RDWR" : "RD", ras, cas, errors, specific); /* Call the helper to output message */ edac_mc_handle_fbd_ue(mci, rank, branch << 1, (branch << 1) + 1, pvt->tmp_prt_buffer); |
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} /* read in the 1st NON-FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, |
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FERR_NF_FBD, &error_reg); if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) { errors = error_reg & FERR_NF_FBD_ERR_MASK; |
57021918a i7300_edac: Add s... |
462 463 464 |
errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_nf_fbd_name)); specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum); |
5f032119d i7300_edac: Fix e... |
465 |
branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0; |
57021918a i7300_edac: Add s... |
466 |
|
32f947261 i7300_edac: enric... |
467 468 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, REDMEMA, &syndrome); |
32f947261 i7300_edac: enric... |
469 470 471 472 473 474 475 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, RECMEMA, &val16); bank = RECMEMA_BANK(val16); rank = RECMEMA_RANK(val16); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, RECMEMB, &value); |
32f947261 i7300_edac: enric... |
476 477 478 |
is_wr = RECMEMB_IS_WR(value); cas = RECMEMB_CAS(value); ras = RECMEMB_RAS(value); |
8199d8cc6 i7300_edac: enric... |
479 |
|
37b69cf91 i7300_edac: Prope... |
480 481 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, REDMEMB, &value); |
37b69cf91 i7300_edac: Prope... |
482 483 484 |
channel = (branch << 1); if (IS_SECOND_CH(value)) channel++; |
5f032119d i7300_edac: Fix e... |
485 486 487 |
/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, error_reg); |
32f947261 i7300_edac: enric... |
488 489 |
/* Form out message */ snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, |
37b69cf91 i7300_edac: Prope... |
490 |
"Corrected error (Branch=%d, Channel %d), " |
32f947261 i7300_edac: enric... |
491 492 |
" DRAM-Bank=%d %s " "RAS=%d CAS=%d, CE Err=0x%lx, Syndrome=0x%08x(%s))", |
37b69cf91 i7300_edac: Prope... |
493 |
branch, channel, |
32f947261 i7300_edac: enric... |
494 495 496 497 498 499 500 501 502 503 504 |
bank, is_wr ? "RDWR" : "RD", ras, cas, errors, syndrome, specific); /* * Call the helper to output message * NOTE: Errors are reported per-branch, and not per-channel * Currently, we don't know how to identify the right * channel. */ |
37b69cf91 i7300_edac: Prope... |
505 |
edac_mc_handle_fbd_ce(mci, rank, channel, |
32f947261 i7300_edac: enric... |
506 507 508 |
pvt->tmp_prt_buffer); } return; |
57021918a i7300_edac: Add s... |
509 |
} |
d091a6eb1 i7300_edac: Impro... |
510 511 512 |
/** * i7300_check_error() - Calls the error checking subroutines * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
513 |
*/ |
f42774224 i7300_edac: Clean... |
514 |
static void i7300_check_error(struct mem_ctl_info *mci) |
5de6e07ed i7300_edac: Add e... |
515 |
{ |
f42774224 i7300_edac: Clean... |
516 517 |
i7300_process_error_global(mci); i7300_process_fbd_error(mci); |
5de6e07ed i7300_edac: Add e... |
518 |
}; |
fcaf780b2 i7300_edac: start... |
519 |
|
d091a6eb1 i7300_edac: Impro... |
520 521 522 |
/** * i7300_clear_error() - Clears the error registers * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
523 524 525 |
*/ static void i7300_clear_error(struct mem_ctl_info *mci) { |
e43276050 i7300_edac: Add a... |
526 527 528 529 530 531 |
struct i7300_pvt *pvt = mci->pvt_info; u32 value; /* * All error values are RWC - we need to read and write 1 to the * bit that we want to cleanup */ |
fcaf780b2 i7300_edac: start... |
532 |
|
e43276050 i7300_edac: Add a... |
533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 |
/* Clear global error registers */ pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_HI, &value); pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_HI, value); pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_LO, &value); pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_LO, value); /* Clear FBD error registers */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, &value); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, value); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, &value); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, value); |
fcaf780b2 i7300_edac: start... |
554 |
} |
d091a6eb1 i7300_edac: Impro... |
555 556 557 558 |
/** * i7300_enable_error_reporting() - Enable the memory reporting logic at the * hardware * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
559 560 561 |
*/ static void i7300_enable_error_reporting(struct mem_ctl_info *mci) { |
57021918a i7300_edac: Add s... |
562 563 564 565 566 567 568 569 570 571 572 573 |
struct i7300_pvt *pvt = mci->pvt_info; u32 fbd_error_mask; /* Read the FBD Error Mask Register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, EMASK_FBD, &fbd_error_mask); /* Enable with a '0' */ fbd_error_mask &= ~(EMASK_FBD_ERR_MASK); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, EMASK_FBD, fbd_error_mask); |
fcaf780b2 i7300_edac: start... |
574 |
} |
5de6e07ed i7300_edac: Add e... |
575 576 577 578 |
/************************************************ * i7300 Functions related to memory enumberation ************************************************/ |
fcaf780b2 i7300_edac: start... |
579 |
|
d091a6eb1 i7300_edac: Impro... |
580 581 582 583 584 585 586 587 |
/** * decode_mtr() - Decodes the MTR descriptor, filling the edac structs * @pvt: pointer to the private data struct used by i7300 driver * @slot: DIMM slot (0 to 7) * @ch: Channel number within the branch (0 or 1) * @branch: Branch number (0 or 1) * @dinfo: Pointer to DIMM info where dimm size is stored * @p_csrow: Pointer to the struct csrow_info that corresponds to that element |
fcaf780b2 i7300_edac: start... |
588 589 590 591 |
*/ static int decode_mtr(struct i7300_pvt *pvt, int slot, int ch, int branch, struct i7300_dimm_info *dinfo, |
1aa4a7b6b V4L/DVB: i7300_ed... |
592 |
struct csrow_info *p_csrow, |
e6649cc62 i7300_edac: Prope... |
593 |
u32 *nr_pages) |
fcaf780b2 i7300_edac: start... |
594 595 596 597 598 599 600 601 602 603 604 605 606 607 |
{ int mtr, ans, addrBits, channel; channel = to_channel(ch, branch); mtr = pvt->mtr[slot][branch]; ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; debugf2("\tMTR%d CH%d: DIMMs are %s (mtr) ", slot, channel, ans ? "Present" : "NOT Present"); /* Determine if there is a DIMM present in this DIMM slot */ |
fcaf780b2 i7300_edac: start... |
608 609 |
if (!ans) return 0; |
fcaf780b2 i7300_edac: start... |
610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 |
/* Start with the number of bits for a Bank * on the DRAM */ addrBits = MTR_DRAM_BANKS_ADDR_BITS; /* Add thenumber of ROW bits */ addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); /* add the number of COLUMN bits */ addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); /* add the number of RANK bits */ addrBits += MTR_DIMM_RANKS(mtr); addrBits += 6; /* add 64 bits per DIMM */ addrBits -= 20; /* divide by 2^^20 */ addrBits -= 3; /* 8 bits per bytes */ dinfo->megabytes = 1 << addrBits; |
e6649cc62 i7300_edac: Prope... |
626 |
*nr_pages = dinfo->megabytes << 8; |
fcaf780b2 i7300_edac: start... |
627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 |
debugf2("\t\tWIDTH: x%d ", MTR_DRAM_WIDTH(mtr)); debugf2("\t\tELECTRICAL THROTTLING is %s ", MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); debugf2("\t\tNUMBANK: %d bank(s) ", MTR_DRAM_BANKS(mtr)); debugf2("\t\tNUMRANK: %s ", MTR_DIMM_RANKS(mtr) ? "double" : "single"); debugf2("\t\tNUMROW: %s ", numrow_toString[MTR_DIMM_ROWS(mtr)]); debugf2("\t\tNUMCOL: %s ", numcol_toString[MTR_DIMM_COLS(mtr)]); debugf2("\t\tSIZE: %d MB ", dinfo->megabytes); p_csrow->grain = 8; |
fcaf780b2 i7300_edac: start... |
647 |
p_csrow->mtype = MEM_FB_DDR2; |
1aa4a7b6b V4L/DVB: i7300_ed... |
648 |
p_csrow->csrow_idx = slot; |
1aa4a7b6b V4L/DVB: i7300_ed... |
649 |
p_csrow->page_mask = 0; |
116389ed2 i7300_edac: Add a... |
650 651 |
/* |
15154c57c i7300_edac: Prope... |
652 |
* The type of error detection actually depends of the |
116389ed2 i7300_edac: Add a... |
653 |
* mode of operation. When it is just one single memory chip, at |
15154c57c i7300_edac: Prope... |
654 655 |
* socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. * In normal or mirrored mode, it uses Lockstep mode, |
116389ed2 i7300_edac: Add a... |
656 657 658 |
* with the possibility of using an extended algorithm for x8 memories * See datasheet Sections 7.3.6 to 7.3.8 */ |
15154c57c i7300_edac: Prope... |
659 660 661 |
if (IS_SINGLE_MODE(pvt->mc_settings_a)) { p_csrow->edac_mode = EDAC_SECDED; |
3b330f675 i7300_edac: Make ... |
662 663 |
debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code "); |
15154c57c i7300_edac: Prope... |
664 |
} else { |
3b330f675 i7300_edac: Make ... |
665 666 |
debugf2("\t\tECC code is on Lockstep mode "); |
28c2ce7c8 i7300_edac: Fix M... |
667 |
if (MTR_DRAM_WIDTH(mtr) == 8) |
15154c57c i7300_edac: Prope... |
668 669 670 671 |
p_csrow->edac_mode = EDAC_S8ECD8ED; else p_csrow->edac_mode = EDAC_S4ECD4ED; } |
fcaf780b2 i7300_edac: start... |
672 673 |
/* ask what device type on this row */ |
28c2ce7c8 i7300_edac: Fix M... |
674 |
if (MTR_DRAM_WIDTH(mtr) == 8) { |
3b330f675 i7300_edac: Make ... |
675 676 |
debugf2("\t\tScrub algorithm for x8 is on %s mode ", |
d7de2bdb0 i7300_edac: Adds ... |
677 678 |
IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? "enhanced" : "normal"); |
fcaf780b2 i7300_edac: start... |
679 |
p_csrow->dtype = DEV_X8; |
d7de2bdb0 i7300_edac: Adds ... |
680 |
} else |
fcaf780b2 i7300_edac: start... |
681 682 683 684 |
p_csrow->dtype = DEV_X4; return mtr; } |
d091a6eb1 i7300_edac: Impro... |
685 686 687 |
/** * print_dimm_size() - Prints dump of the memory organization * @pvt: pointer to the private data struct used by i7300 driver |
fcaf780b2 i7300_edac: start... |
688 |
* |
d091a6eb1 i7300_edac: Impro... |
689 |
* Useful for debug. If debug is disabled, this routine do nothing |
fcaf780b2 i7300_edac: start... |
690 691 692 |
*/ static void print_dimm_size(struct i7300_pvt *pvt) { |
d091a6eb1 i7300_edac: Impro... |
693 |
#ifdef CONFIG_EDAC_DEBUG |
fcaf780b2 i7300_edac: start... |
694 |
struct i7300_dimm_info *dinfo; |
85580ea4f i7300_edac: pre-a... |
695 |
char *p; |
fcaf780b2 i7300_edac: start... |
696 697 698 699 |
int space, n; int channel, slot; space = PAGE_SIZE; |
85580ea4f i7300_edac: pre-a... |
700 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
701 702 703 704 705 706 707 708 709 |
n = snprintf(p, space, " "); p += n; space -= n; for (channel = 0; channel < MAX_CHANNELS; channel++) { n = snprintf(p, space, "channel %d | ", channel); p += n; space -= n; } |
85580ea4f i7300_edac: pre-a... |
710 711 712 |
debugf2("%s ", pvt->tmp_prt_buffer); p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
713 714 |
space = PAGE_SIZE; n = snprintf(p, space, "-------------------------------" |
9c6f6b65d i7300-edac: Codin... |
715 |
"------------------------------"); |
fcaf780b2 i7300_edac: start... |
716 717 |
p += n; space -= n; |
85580ea4f i7300_edac: pre-a... |
718 719 720 |
debugf2("%s ", pvt->tmp_prt_buffer); p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
721 722 723 724 725 726 727 728 729 730 731 732 733 |
space = PAGE_SIZE; for (slot = 0; slot < MAX_SLOTS; slot++) { n = snprintf(p, space, "csrow/SLOT %d ", slot); p += n; space -= n; for (channel = 0; channel < MAX_CHANNELS; channel++) { dinfo = &pvt->dimm_info[slot][channel]; n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); p += n; space -= n; } |
85580ea4f i7300_edac: pre-a... |
734 735 736 |
debugf2("%s ", pvt->tmp_prt_buffer); p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
737 738 739 740 |
space = PAGE_SIZE; } n = snprintf(p, space, "-------------------------------" |
9c6f6b65d i7300-edac: Codin... |
741 |
"------------------------------"); |
fcaf780b2 i7300_edac: start... |
742 743 |
p += n; space -= n; |
85580ea4f i7300_edac: pre-a... |
744 745 746 |
debugf2("%s ", pvt->tmp_prt_buffer); p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
747 |
space = PAGE_SIZE; |
d091a6eb1 i7300_edac: Impro... |
748 |
#endif |
fcaf780b2 i7300_edac: start... |
749 |
} |
d091a6eb1 i7300_edac: Impro... |
750 751 752 753 754 |
/** * i7300_init_csrows() - Initialize the 'csrows' table within * the mci control structure with the * addressing of memory. * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
755 756 757 758 759 760 |
*/ static int i7300_init_csrows(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; struct i7300_dimm_info *dinfo; struct csrow_info *p_csrow; |
d091a6eb1 i7300_edac: Impro... |
761 |
int rc = -ENODEV; |
fcaf780b2 i7300_edac: start... |
762 763 |
int mtr; int ch, branch, slot, channel; |
e6649cc62 i7300_edac: Prope... |
764 |
u32 last_page = 0, nr_pages; |
fcaf780b2 i7300_edac: start... |
765 766 |
pvt = mci->pvt_info; |
fcaf780b2 i7300_edac: start... |
767 768 769 770 771 772 773 |
debugf2("Memory Technology Registers: "); /* Get the AMB present registers for the four channels */ for (branch = 0; branch < MAX_BRANCHES; branch++) { /* Read and dump branch 0's MTRs */ channel = to_channel(0, branch); |
9c6f6b65d i7300-edac: Codin... |
774 775 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_0, |
fcaf780b2 i7300_edac: start... |
776 777 778 779 780 781 |
&pvt->ambpresent[channel]); debugf2("\t\tAMB-present CH%d = 0x%x: ", channel, pvt->ambpresent[channel]); channel = to_channel(1, branch); |
9c6f6b65d i7300-edac: Codin... |
782 783 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_1, |
fcaf780b2 i7300_edac: start... |
784 785 786 787 788 789 790 791 792 793 |
&pvt->ambpresent[channel]); debugf2("\t\tAMB-present CH%d = 0x%x: ", channel, pvt->ambpresent[channel]); } /* Get the set of MTR[0-7] regs by each branch */ for (slot = 0; slot < MAX_SLOTS; slot++) { int where = mtr_regs[slot]; for (branch = 0; branch < MAX_BRANCHES; branch++) { |
3e57eef64 i7300_edac: Bette... |
794 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], |
fcaf780b2 i7300_edac: start... |
795 796 797 798 799 800 801 802 803 |
where, &pvt->mtr[slot][branch]); for (ch = 0; ch < MAX_BRANCHES; ch++) { int channel = to_channel(ch, branch); dinfo = &pvt->dimm_info[slot][channel]; p_csrow = &mci->csrows[slot]; mtr = decode_mtr(pvt, slot, ch, branch, |
e6649cc62 i7300_edac: Prope... |
804 |
dinfo, p_csrow, &nr_pages); |
fcaf780b2 i7300_edac: start... |
805 806 807 |
/* if no DIMMS on this row, continue */ if (!MTR_DIMMS_PRESENT(mtr)) continue; |
e6649cc62 i7300_edac: Prope... |
808 809 810 811 812 |
/* Update per_csrow memory count */ p_csrow->nr_pages += nr_pages; p_csrow->first_page = last_page; last_page += nr_pages; p_csrow->last_page = last_page; |
d091a6eb1 i7300_edac: Impro... |
813 |
rc = 0; |
fcaf780b2 i7300_edac: start... |
814 815 816 |
} } } |
d091a6eb1 i7300_edac: Impro... |
817 |
return rc; |
fcaf780b2 i7300_edac: start... |
818 |
} |
d091a6eb1 i7300_edac: Impro... |
819 820 821 822 823 |
/** * decode_mir() - Decodes Memory Interleave Register (MIR) info * @int mir_no: number of the MIR register to decode * @mir: array with the MIR data cached on the driver */ |
fcaf780b2 i7300_edac: start... |
824 825 826 |
static void decode_mir(int mir_no, u16 mir[MAX_MIR]) { if (mir[mir_no] & 3) |
9c6f6b65d i7300-edac: Codin... |
827 828 829 |
debugf2("MIR%d: limit= 0x%x Branch(es) that participate:" " %s %s ", |
fcaf780b2 i7300_edac: start... |
830 831 832 |
mir_no, (mir[mir_no] >> 4) & 0xfff, (mir[mir_no] & 1) ? "B0" : "", |
9c6f6b65d i7300-edac: Codin... |
833 |
(mir[mir_no] & 2) ? "B1" : ""); |
fcaf780b2 i7300_edac: start... |
834 |
} |
d091a6eb1 i7300_edac: Impro... |
835 836 837 |
/** * i7300_get_mc_regs() - Get the contents of the MC enumeration registers * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
838 |
* |
d091a6eb1 i7300_edac: Impro... |
839 |
* Data read is cached internally for its usage when needed |
fcaf780b2 i7300_edac: start... |
840 841 842 843 844 845 846 847 |
*/ static int i7300_get_mc_regs(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; u32 actual_tolm; int i, rc; pvt = mci->pvt_info; |
3e57eef64 i7300_edac: Bette... |
848 |
pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, |
fcaf780b2 i7300_edac: start... |
849 850 851 852 853 854 |
(u32 *) &pvt->ambase); debugf2("AMBASE= 0x%lx ", (long unsigned int)pvt->ambase); /* Get the Branch Map regs */ |
3e57eef64 i7300_edac: Bette... |
855 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); |
fcaf780b2 i7300_edac: start... |
856 857 858 859 860 861 862 863 864 |
pvt->tolm >>= 12; debugf2("TOLM (number of 256M regions) =%u (0x%x) ", pvt->tolm, pvt->tolm); actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x) ", actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); |
af3d8831e i7300_edac: displ... |
865 |
/* Get memory controller settings */ |
3e57eef64 i7300_edac: Bette... |
866 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, |
af3d8831e i7300_edac: displ... |
867 |
&pvt->mc_settings); |
bb81a2163 i7300_edac: Detec... |
868 869 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A, &pvt->mc_settings_a); |
d7de2bdb0 i7300_edac: Adds ... |
870 |
|
bb81a2163 i7300_edac: Detec... |
871 872 873 874 875 876 |
if (IS_SINGLE_MODE(pvt->mc_settings_a)) debugf0("Memory controller operating on single mode "); else debugf0("Memory controller operating on %s mode ", |
d7de2bdb0 i7300_edac: Adds ... |
877 |
IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored"); |
bb81a2163 i7300_edac: Detec... |
878 |
|
af3d8831e i7300_edac: displ... |
879 880 |
debugf0("Error detection is %s ", |
d7de2bdb0 i7300_edac: Adds ... |
881 882 883 884 |
IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); debugf0("Retry is %s ", IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); |
af3d8831e i7300_edac: displ... |
885 886 |
/* Get Memory Interleave Range registers */ |
9c6f6b65d i7300-edac: Codin... |
887 888 889 890 891 892 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, &pvt->mir[0]); pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, &pvt->mir[1]); pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, &pvt->mir[2]); |
fcaf780b2 i7300_edac: start... |
893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 |
/* Decode the MIR regs */ for (i = 0; i < MAX_MIR; i++) decode_mir(i, pvt->mir); rc = i7300_init_csrows(mci); if (rc < 0) return rc; /* Go and determine the size of each DIMM and place in an * orderly matrix */ print_dimm_size(pvt); return 0; } |
5de6e07ed i7300_edac: Add e... |
908 909 910 |
/************************************************* * i7300 Functions related to device probe/release *************************************************/ |
d091a6eb1 i7300_edac: Impro... |
911 912 913 |
/** * i7300_put_devices() - Release the PCI devices * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
914 915 916 917 918 919 920 921 922 923 |
*/ static void i7300_put_devices(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; int branch; pvt = mci->pvt_info; /* Decrement usage count for devices */ for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++) |
3e57eef64 i7300_edac: Bette... |
924 925 926 |
pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]); pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs); pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map); |
fcaf780b2 i7300_edac: start... |
927 |
} |
d091a6eb1 i7300_edac: Impro... |
928 929 930 931 |
/** * i7300_get_devices() - Find and perform 'get' operation on the MCH's * device/functions we want to reference for this driver * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
932 |
* |
d091a6eb1 i7300_edac: Impro... |
933 934 935 936 937 |
* Access and prepare the several devices for usage: * I7300 devices used by this driver: * Device 16, functions 0,1 and 2: PCI_DEVICE_ID_INTEL_I7300_MCH_ERR * Device 21 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 * Device 22 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 |
fcaf780b2 i7300_edac: start... |
938 |
*/ |
d091a6eb1 i7300_edac: Impro... |
939 |
static int __devinit i7300_get_devices(struct mem_ctl_info *mci) |
fcaf780b2 i7300_edac: start... |
940 941 942 943 944 945 946 947 |
{ struct i7300_pvt *pvt; struct pci_dev *pdev; pvt = mci->pvt_info; /* Attempt to 'get' the MCH register we want */ pdev = NULL; |
9c6f6b65d i7300-edac: Codin... |
948 949 |
while (!pvt->pci_dev_16_1_fsb_addr_map || !pvt->pci_dev_16_2_fsb_err_regs) { |
fcaf780b2 i7300_edac: start... |
950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 |
pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev); if (!pdev) { /* End of list, leave */ i7300_printk(KERN_ERR, "'system address,Process Bus' " "device not found:" "vendor 0x%x device 0x%x ERR funcs " "(broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR); goto error; } /* Store device 16 funcs 1 and 2 */ switch (PCI_FUNC(pdev->devfn)) { case 1: |
3e57eef64 i7300_edac: Bette... |
968 |
pvt->pci_dev_16_1_fsb_addr_map = pdev; |
fcaf780b2 i7300_edac: start... |
969 970 |
break; case 2: |
3e57eef64 i7300_edac: Bette... |
971 |
pvt->pci_dev_16_2_fsb_err_regs = pdev; |
fcaf780b2 i7300_edac: start... |
972 973 974 975 976 977 |
break; } } debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x ", |
3e57eef64 i7300_edac: Bette... |
978 |
pci_name(pvt->pci_dev_16_0_fsb_ctlr), |
9c6f6b65d i7300-edac: Codin... |
979 980 |
pvt->pci_dev_16_0_fsb_ctlr->vendor, pvt->pci_dev_16_0_fsb_ctlr->device); |
fcaf780b2 i7300_edac: start... |
981 982 |
debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x ", |
3e57eef64 i7300_edac: Bette... |
983 |
pci_name(pvt->pci_dev_16_1_fsb_addr_map), |
9c6f6b65d i7300-edac: Codin... |
984 985 |
pvt->pci_dev_16_1_fsb_addr_map->vendor, pvt->pci_dev_16_1_fsb_addr_map->device); |
fcaf780b2 i7300_edac: start... |
986 987 |
debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x ", |
3e57eef64 i7300_edac: Bette... |
988 |
pci_name(pvt->pci_dev_16_2_fsb_err_regs), |
9c6f6b65d i7300-edac: Codin... |
989 990 |
pvt->pci_dev_16_2_fsb_err_regs->vendor, pvt->pci_dev_16_2_fsb_err_regs->device); |
fcaf780b2 i7300_edac: start... |
991 |
|
3e57eef64 i7300_edac: Bette... |
992 |
pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, |
9c6f6b65d i7300-edac: Codin... |
993 |
PCI_DEVICE_ID_INTEL_I7300_MCH_FB0, |
fcaf780b2 i7300_edac: start... |
994 |
NULL); |
3e57eef64 i7300_edac: Bette... |
995 |
if (!pvt->pci_dev_2x_0_fbd_branch[0]) { |
fcaf780b2 i7300_edac: start... |
996 997 998 999 1000 1001 1002 |
i7300_printk(KERN_ERR, "MC: 'BRANCH 0' device not found:" "vendor 0x%x device 0x%x Func 0 (broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0); goto error; } |
3e57eef64 i7300_edac: Bette... |
1003 |
pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL, |
fcaf780b2 i7300_edac: start... |
1004 1005 |
PCI_DEVICE_ID_INTEL_I7300_MCH_FB1, NULL); |
3e57eef64 i7300_edac: Bette... |
1006 |
if (!pvt->pci_dev_2x_0_fbd_branch[1]) { |
fcaf780b2 i7300_edac: start... |
1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 |
i7300_printk(KERN_ERR, "MC: 'BRANCH 1' device not found:" "vendor 0x%x device 0x%x Func 0 " "(broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB1); goto error; } return 0; error: i7300_put_devices(mci); return -ENODEV; } |
d091a6eb1 i7300_edac: Impro... |
1023 1024 1025 1026 |
/** * i7300_init_one() - Probe for one instance of the device * @pdev: struct pci_dev pointer * @id: struct pci_device_id pointer - currently unused |
fcaf780b2 i7300_edac: start... |
1027 |
*/ |
d091a6eb1 i7300_edac: Impro... |
1028 1029 |
static int __devinit i7300_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
fcaf780b2 i7300_edac: start... |
1030 1031 1032 1033 1034 1035 |
{ struct mem_ctl_info *mci; struct i7300_pvt *pvt; int num_channels; int num_dimms_per_channel; int num_csrows; |
d091a6eb1 i7300_edac: Impro... |
1036 |
int rc; |
fcaf780b2 i7300_edac: start... |
1037 |
|
d091a6eb1 i7300_edac: Impro... |
1038 1039 1040 1041 |
/* wake up device */ rc = pci_enable_device(pdev); if (rc == -EIO) return rc; |
fcaf780b2 i7300_edac: start... |
1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 |
debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x ", __func__, pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); /* We only are looking for func 0 of the set */ if (PCI_FUNC(pdev->devfn) != 0) return -ENODEV; /* As we don't have a motherboard identification routine to determine * actual number of slots/dimms per channel, we thus utilize the * resource as specified by the chipset. Thus, we might have * have more DIMMs per channel than actually on the mobo, but this |
25985edce Fix common misspe... |
1057 |
* allows the driver to support up to the chipset max, without |
fcaf780b2 i7300_edac: start... |
1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 |
* some fancy mobo determination. */ num_dimms_per_channel = MAX_SLOTS; num_channels = MAX_CHANNELS; num_csrows = MAX_SLOTS * MAX_CHANNELS; debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d ", __func__, num_channels, num_dimms_per_channel, num_csrows); /* allocate a new MC control structure */ mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0); if (mci == NULL) return -ENOMEM; debugf0("MC: " __FILE__ ": %s(): mci = %p ", __func__, mci); mci->dev = &pdev->dev; /* record ptr to the generic device */ pvt = mci->pvt_info; |
3e57eef64 i7300_edac: Bette... |
1080 |
pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */ |
fcaf780b2 i7300_edac: start... |
1081 |
|
85580ea4f i7300_edac: pre-a... |
1082 1083 1084 1085 1086 |
pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL); if (!pvt->tmp_prt_buffer) { edac_mc_free(mci); return -ENOMEM; } |
fcaf780b2 i7300_edac: start... |
1087 |
/* 'get' the pci devices we want to reserve for our use */ |
d091a6eb1 i7300_edac: Impro... |
1088 |
if (i7300_get_devices(mci)) |
fcaf780b2 i7300_edac: start... |
1089 1090 1091 1092 1093 1094 1095 1096 |
goto fail0; mci->mc_idx = 0; mci->mtype_cap = MEM_FLAG_FB_DDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE; mci->edac_cap = EDAC_FLAG_NONE; mci->mod_name = "i7300_edac.c"; mci->mod_ver = I7300_REVISION; |
d091a6eb1 i7300_edac: Impro... |
1097 |
mci->ctl_name = i7300_devs[0].ctl_name; |
fcaf780b2 i7300_edac: start... |
1098 1099 |
mci->dev_name = pci_name(pdev); mci->ctl_page_to_phys = NULL; |
fcaf780b2 i7300_edac: start... |
1100 1101 |
/* Set the function pointer to an actual operation function */ mci->edac_check = i7300_check_error; |
fcaf780b2 i7300_edac: start... |
1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 |
/* initialize the MC control structure 'csrows' table * with the mapping and control information */ if (i7300_get_mc_regs(mci)) { debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE " " because i7300_init_csrows() returned nonzero " "value "); mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ } else { |
fcaf780b2 i7300_edac: start... |
1113 1114 1115 |
debugf1("MC: Enable error reporting now "); i7300_enable_error_reporting(mci); |
fcaf780b2 i7300_edac: start... |
1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 |
} /* add this new MC control structure to EDAC's list of MCs */ if (edac_mc_add_mc(mci)) { debugf0("MC: " __FILE__ ": %s(): failed edac_mc_add_mc() ", __func__); /* FIXME: perhaps some code should go here that disables error * reporting if we just enabled it */ goto fail1; } |
fcaf780b2 i7300_edac: start... |
1128 |
i7300_clear_error(mci); |
fcaf780b2 i7300_edac: start... |
1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 |
/* allocating generic PCI control info */ i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); if (!i7300_pci) { printk(KERN_WARNING "%s(): Unable to create PCI control ", __func__); printk(KERN_WARNING "%s(): PCI error report via EDAC not setup ", __func__); } return 0; /* Error exit unwinding stack */ fail1: i7300_put_devices(mci); fail0: |
85580ea4f i7300_edac: pre-a... |
1151 |
kfree(pvt->tmp_prt_buffer); |
fcaf780b2 i7300_edac: start... |
1152 1153 1154 |
edac_mc_free(mci); return -ENODEV; } |
d091a6eb1 i7300_edac: Impro... |
1155 1156 1157 |
/** * i7300_remove_one() - Remove the driver * @pdev: struct pci_dev pointer |
fcaf780b2 i7300_edac: start... |
1158 1159 1160 1161 |
*/ static void __devexit i7300_remove_one(struct pci_dev *pdev) { struct mem_ctl_info *mci; |
85580ea4f i7300_edac: pre-a... |
1162 |
char *tmp; |
fcaf780b2 i7300_edac: start... |
1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 |
debugf0(__FILE__ ": %s() ", __func__); if (i7300_pci) edac_pci_release_generic_ctl(i7300_pci); mci = edac_mc_del_mc(&pdev->dev); if (!mci) return; |
85580ea4f i7300_edac: pre-a... |
1173 |
tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
1174 1175 |
/* retrieve references to resources, and free those resources */ i7300_put_devices(mci); |
85580ea4f i7300_edac: pre-a... |
1176 |
kfree(tmp); |
fcaf780b2 i7300_edac: start... |
1177 1178 1179 1180 |
edac_mc_free(mci); } /* |
d091a6eb1 i7300_edac: Impro... |
1181 |
* pci_device_id: table for which devices we are looking for |
fcaf780b2 i7300_edac: start... |
1182 |
* |
d091a6eb1 i7300_edac: Impro... |
1183 |
* Has only 8086:360c PCI ID |
fcaf780b2 i7300_edac: start... |
1184 1185 1186 1187 1188 1189 1190 1191 1192 |
*/ static const struct pci_device_id i7300_pci_tbl[] __devinitdata = { {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)}, {0,} /* 0 terminated list. */ }; MODULE_DEVICE_TABLE(pci, i7300_pci_tbl); /* |
d091a6eb1 i7300_edac: Impro... |
1193 |
* i7300_driver: pci_driver structure for this module |
fcaf780b2 i7300_edac: start... |
1194 1195 1196 1197 1198 1199 1200 |
*/ static struct pci_driver i7300_driver = { .name = "i7300_edac", .probe = i7300_init_one, .remove = __devexit_p(i7300_remove_one), .id_table = i7300_pci_tbl, }; |
d091a6eb1 i7300_edac: Impro... |
1201 1202 |
/** * i7300_init() - Registers the driver |
fcaf780b2 i7300_edac: start... |
1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 |
*/ static int __init i7300_init(void) { int pci_rc; debugf2("MC: " __FILE__ ": %s() ", __func__); /* Ensure that the OPSTATE is set correctly for POLL or NMI */ opstate_init(); pci_rc = pci_register_driver(&i7300_driver); return (pci_rc < 0) ? pci_rc : 0; } |
d091a6eb1 i7300_edac: Impro... |
1218 1219 |
/** * i7300_init() - Unregisters the driver |
fcaf780b2 i7300_edac: start... |
1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 |
*/ static void __exit i7300_exit(void) { debugf2("MC: " __FILE__ ": %s() ", __func__); pci_unregister_driver(&i7300_driver); } module_init(i7300_init); module_exit(i7300_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - " I7300_REVISION); module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |