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drivers/mfd/twl4030-irq.c
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/* * twl4030-irq.c - TWL4030/TPS659x0 irq support * * Copyright (C) 2005-2006 Texas Instruments, Inc. * * Modifications to defer interrupt handling to a kernel thread: * Copyright (C) 2006 MontaVista Software, Inc. * * Based on tlv320aic23.c: * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> * * Code cleanup and modifications to IRQ handler. * by syed khasim <x0khasim@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> |
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#include <linux/slab.h> |
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#include <linux/i2c/twl.h> |
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#include "twl-core.h" |
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/* * TWL4030 IRQ handling has two stages in hardware, and thus in software. * The Primary Interrupt Handler (PIH) stage exposes status bits saying * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. * SIH modules are more traditional IRQ components, which support per-IRQ * enable/disable and trigger controls; they do most of the work. * * These chips are designed to support IRQ handling from two different * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status * and mask registers in the PIH and SIH modules. * * We set up IRQs starting at a platform-specified base, always starting * with PIH and the SIH for PWR_INT and then usually adding GPIO: * base + 0 .. base + 7 PIH * base + 8 .. base + 15 SIH for PWR_INT * base + 16 .. base + 33 SIH for GPIO */ /* PIH register offsets */ #define REG_PIH_ISR_P1 0x01 #define REG_PIH_ISR_P2 0x02 #define REG_PIH_SIR 0x03 /* for testing */ /* Linux could (eventually) use either IRQ line */ static int irq_line; struct sih { char name[8]; u8 module; /* module id */ u8 control_offset; /* for SIH_CTRL */ bool set_cor; u8 bits; /* valid in isr/imr */ u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ u8 edr_offset; u8 bytes_edr; /* bytelen of EDR */ |
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u8 irq_lines; /* number of supported irq lines */ |
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/* SIR ignored -- set interrupt, for testing only */ |
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struct sih_irq_data { |
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u8 isr_offset; u8 imr_offset; } mask[2]; /* + 2 bytes padding */ }; |
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static const struct sih *sih_modules; static int nr_sih_modules; |
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#define SIH_INITIALIZER(modname, nbits) \ .module = TWL4030_MODULE_ ## modname, \ .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ .bits = nbits, \ .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ .edr_offset = TWL4030_ ## modname ## _EDR, \ .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ |
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.irq_lines = 2, \ |
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.mask = { { \ .isr_offset = TWL4030_ ## modname ## _ISR1, \ .imr_offset = TWL4030_ ## modname ## _IMR1, \ }, \ { \ .isr_offset = TWL4030_ ## modname ## _ISR2, \ .imr_offset = TWL4030_ ## modname ## _IMR2, \ }, }, /* register naming policies are inconsistent ... */ #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT /* Order in this table matches order in PIH_ISR. That is, * BIT(n) in PIH_ISR is sih_modules[n]. */ |
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/* sih_modules_twl4030 is used both in twl4030 and twl5030 */ static const struct sih sih_modules_twl4030[6] = { |
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[0] = { .name = "gpio", .module = TWL4030_MODULE_GPIO, .control_offset = REG_GPIO_SIH_CTRL, .set_cor = true, .bits = TWL4030_GPIO_MAX, .bytes_ixr = 3, /* Note: *all* of these IRQs default to no-trigger */ .edr_offset = REG_GPIO_EDR1, .bytes_edr = 5, |
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.irq_lines = 2, |
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.mask = { { .isr_offset = REG_GPIO_ISR1A, .imr_offset = REG_GPIO_IMR1A, }, { .isr_offset = REG_GPIO_ISR1B, .imr_offset = REG_GPIO_IMR1B, }, }, }, [1] = { .name = "keypad", .set_cor = true, SIH_INITIALIZER(KEYPAD_KEYP, 4) }, [2] = { .name = "bci", .module = TWL4030_MODULE_INTERRUPTS, .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, |
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.set_cor = true, |
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.bits = 12, .bytes_ixr = 2, .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, /* Note: most of these IRQs default to no-trigger */ .bytes_edr = 3, |
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.irq_lines = 2, |
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.mask = { { .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, }, { .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, }, }, }, [3] = { .name = "madc", SIH_INITIALIZER(MADC, 4) }, [4] = { /* USB doesn't use the same SIH organization */ .name = "usb", }, [5] = { .name = "power", .set_cor = true, SIH_INITIALIZER(INT_PWR, 8) }, /* there are no SIH modules #6 or #7 ... */ }; |
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static const struct sih sih_modules_twl5031[8] = { [0] = { .name = "gpio", .module = TWL4030_MODULE_GPIO, .control_offset = REG_GPIO_SIH_CTRL, .set_cor = true, .bits = TWL4030_GPIO_MAX, .bytes_ixr = 3, /* Note: *all* of these IRQs default to no-trigger */ .edr_offset = REG_GPIO_EDR1, .bytes_edr = 5, .irq_lines = 2, .mask = { { .isr_offset = REG_GPIO_ISR1A, .imr_offset = REG_GPIO_IMR1A, }, { .isr_offset = REG_GPIO_ISR1B, .imr_offset = REG_GPIO_IMR1B, }, }, }, [1] = { .name = "keypad", .set_cor = true, SIH_INITIALIZER(KEYPAD_KEYP, 4) }, [2] = { .name = "bci", .module = TWL5031_MODULE_INTERRUPTS, .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, .bits = 7, .bytes_ixr = 1, .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, /* Note: most of these IRQs default to no-trigger */ .bytes_edr = 2, .irq_lines = 2, .mask = { { .isr_offset = TWL5031_INTERRUPTS_BCIISR1, .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, }, { .isr_offset = TWL5031_INTERRUPTS_BCIISR2, .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, }, }, }, [3] = { .name = "madc", SIH_INITIALIZER(MADC, 4) }, [4] = { /* USB doesn't use the same SIH organization */ .name = "usb", }, [5] = { .name = "power", .set_cor = true, SIH_INITIALIZER(INT_PWR, 8) }, [6] = { /* |
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* ECI/DBI doesn't use the same SIH organization. * For example, it supports only one interrupt output line. * That is, the interrupts are seen on both INT1 and INT2 lines. |
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*/ |
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.name = "eci_dbi", |
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.module = TWL5031_MODULE_ACCESSORY, .bits = 9, .bytes_ixr = 2, .irq_lines = 1, .mask = { { .isr_offset = TWL5031_ACIIDR_LSB, .imr_offset = TWL5031_ACIIMR_LSB, }, }, }, [7] = { |
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/* Audio accessory */ .name = "audio", |
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.module = TWL5031_MODULE_ACCESSORY, .control_offset = TWL5031_ACCSIHCTRL, .bits = 2, .bytes_ixr = 1, .edr_offset = TWL5031_ACCEDR1, /* Note: most of these IRQs default to no-trigger */ .bytes_edr = 1, .irq_lines = 2, .mask = { { .isr_offset = TWL5031_ACCISR1, .imr_offset = TWL5031_ACCIMR1, }, { .isr_offset = TWL5031_ACCISR2, .imr_offset = TWL5031_ACCIMR2, }, }, }, }; |
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#undef TWL4030_MODULE_KEYPAD_KEYP #undef TWL4030_MODULE_INT_PWR #undef TWL4030_INT_PWR_EDR /*----------------------------------------------------------------------*/ static unsigned twl4030_irq_base; |
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/* * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. * This is a chained interrupt, so there is no desc->action method for it. * Now we need to query the interrupt controller in the twl4030 to determine * which module is generating the interrupt request. However, we can't do i2c * transactions in interrupt context, so we must defer that work to a kernel * thread. All we do here is acknowledge and mask the interrupt and wakeup * the kernel thread. */ |
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static irqreturn_t handle_twl4030_pih(int irq, void *devid) |
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{ |
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int module_irq; irqreturn_t ret; u8 pih_isr; ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, REG_PIH_ISR_P1); if (ret) { pr_warning("twl4030: I2C error %d reading PIH ISR ", ret); return IRQ_NONE; } /* these handlers deal with the relevant SIH irq status */ for (module_irq = twl4030_irq_base; pih_isr; pih_isr >>= 1, module_irq++) { if (pih_isr & 0x1) |
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handle_nested_irq(module_irq); |
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} |
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return IRQ_HANDLED; |
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} |
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/*----------------------------------------------------------------------*/ /* * twl4030_init_sih_modules() ... start from a known state where no * IRQs will be coming in, and where we can quickly enable them then * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. * * NOTE: we don't touch EDR registers here; they stay with hardware * defaults or whatever the last value was. Note that when both EDR * bits for an IRQ are clear, that's as if its IMR bit is set... */ static int twl4030_init_sih_modules(unsigned line) { const struct sih *sih; u8 buf[4]; int i; int status; /* line 0 == int1_n signal; line 1 == int2_n signal */ if (line > 1) return -EINVAL; irq_line = line; /* disable all interrupts on our line */ memset(buf, 0xff, sizeof buf); sih = sih_modules; |
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for (i = 0; i < nr_sih_modules; i++, sih++) { |
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/* skip USB -- it's funky */ if (!sih->bytes_ixr) continue; |
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/* Not all the SIH modules support multiple interrupt lines */ if (sih->irq_lines <= line) continue; |
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status = twl_i2c_write(sih->module, buf, |
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sih->mask[line].imr_offset, sih->bytes_ixr); if (status < 0) pr_err("twl4030: err %d initializing %s %s ", status, sih->name, "IMR"); /* Maybe disable "exclusive" mode; buffer second pending irq; * set Clear-On-Read (COR) bit. * * NOTE that sometimes COR polarity is documented as being |
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* inverted: for MADC, COR=1 means "clear on write". |
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* And for PWR_INT it's not documented... */ if (sih->set_cor) { |
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status = twl_i2c_write_u8(sih->module, |
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TWL4030_SIH_CTRL_COR_MASK, sih->control_offset); if (status < 0) pr_err("twl4030: err %d initializing %s %s ", status, sih->name, "SIH_CTRL"); } } sih = sih_modules; |
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for (i = 0; i < nr_sih_modules; i++, sih++) { |
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u8 rxbuf[4]; int j; /* skip USB */ if (!sih->bytes_ixr) continue; |
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/* Not all the SIH modules support multiple interrupt lines */ if (sih->irq_lines <= line) continue; |
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/* Clear pending interrupt status. Either the read was * enough, or we need to write those bits. Repeat, in * case an IRQ is pending (PENDDIS=0) ... that's not * uncommon with PWR_INT.PWRON. */ for (j = 0; j < 2; j++) { |
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status = twl_i2c_read(sih->module, rxbuf, |
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sih->mask[line].isr_offset, sih->bytes_ixr); if (status < 0) pr_err("twl4030: err %d initializing %s %s ", status, sih->name, "ISR"); if (!sih->set_cor) |
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status = twl_i2c_write(sih->module, buf, |
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sih->mask[line].isr_offset, sih->bytes_ixr); /* else COR=1 means read sufficed. * (for most SIH modules...) */ } } return 0; } static inline void activate_irq(int irq) { #ifdef CONFIG_ARM /* ARM requires an extra step to clear IRQ_NOREQUEST, which it * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. */ set_irq_flags(irq, IRQF_VALID); #else /* same effect on other architectures */ |
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irq_set_noprobe(irq); |
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#endif } /*----------------------------------------------------------------------*/ |
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struct sih_agent { int irq_base; const struct sih *sih; u32 imr; bool imr_change_pending; |
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u32 edge_change; |
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struct mutex irq_lock; |
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char *irq_name; |
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}; |
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/*----------------------------------------------------------------------*/ /* * All irq_chip methods get issued from code holding irq_desc[irq].lock, * which can't perform the underlying I2C operations (because they sleep). * So we must hand them off to a thread (workqueue) and cope with asynch * completion, potentially including some re-ordering, of these requests. */ |
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static void twl4030_sih_mask(struct irq_data *data) |
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{ |
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struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
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agent->imr |= BIT(data->irq - agent->irq_base); agent->imr_change_pending = true; |
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} |
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static void twl4030_sih_unmask(struct irq_data *data) |
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{ |
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struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
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|
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agent->imr &= ~BIT(data->irq - agent->irq_base); agent->imr_change_pending = true; |
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} |
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static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger) |
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{ |
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struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; |
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if (irqd_get_trigger_type(data) != trigger) |
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agent->edge_change |= BIT(data->irq - agent->irq_base); |
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|
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return 0; } |
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static void twl4030_sih_bus_lock(struct irq_data *data) { |
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struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
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|
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mutex_lock(&agent->irq_lock); |
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} static void twl4030_sih_bus_sync_unlock(struct irq_data *data) { |
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struct sih_agent *agent = irq_data_get_irq_chip_data(data); const struct sih *sih = agent->sih; int status; if (agent->imr_change_pending) { union { u32 word; u8 bytes[4]; } imr; |
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/* byte[0] gets overwritten as we write ... */ |
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imr.word = cpu_to_le32(agent->imr << 8); agent->imr_change_pending = false; /* write the whole mask ... simpler than subsetting it */ status = twl_i2c_write(sih->module, imr.bytes, sih->mask[irq_line].imr_offset, sih->bytes_ixr); if (status) pr_err("twl4030: %s, %s --> %d ", __func__, "write", status); } |
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|
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if (agent->edge_change) { u32 edge_change; u8 bytes[6]; edge_change = agent->edge_change; agent->edge_change = 0; /* * Read, reserving first byte for write scratch. Yes, this * could be cached for some speedup ... but be careful about * any processor on the other IRQ line, EDR registers are * shared. */ status = twl_i2c_read(sih->module, bytes + 1, sih->edr_offset, sih->bytes_edr); if (status) { pr_err("twl4030: %s, %s --> %d ", __func__, "read", status); return; } /* Modify only the bits we know must change */ while (edge_change) { int i = fls(edge_change) - 1; struct irq_data *idata; int byte = 1 + (i >> 2); int off = (i & 0x3) * 2; unsigned int type; idata = irq_get_irq_data(i + agent->irq_base); bytes[byte] &= ~(0x03 << off); type = irqd_get_trigger_type(idata); if (type & IRQ_TYPE_EDGE_RISING) bytes[byte] |= BIT(off + 1); if (type & IRQ_TYPE_EDGE_FALLING) bytes[byte] |= BIT(off + 0); edge_change &= ~BIT(i); } /* Write */ status = twl_i2c_write(sih->module, bytes, sih->edr_offset, sih->bytes_edr); if (status) pr_err("twl4030: %s, %s --> %d ", __func__, "write", status); } |
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mutex_unlock(&agent->irq_lock); |
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} |
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static struct irq_chip twl4030_sih_irq_chip = { .name = "twl4030", |
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.irq_mask = twl4030_sih_mask, |
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.irq_unmask = twl4030_sih_unmask, .irq_set_type = twl4030_sih_set_type, |
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.irq_bus_lock = twl4030_sih_bus_lock, .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock, |
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}; /*----------------------------------------------------------------------*/ static inline int sih_read_isr(const struct sih *sih) { int status; union { u8 bytes[4]; u32 word; } isr; /* FIXME need retry-on-error ... */ isr.word = 0; |
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status = twl_i2c_read(sih->module, isr.bytes, |
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sih->mask[irq_line].isr_offset, sih->bytes_ixr); return (status < 0) ? status : le32_to_cpu(isr.word); } /* * Generic handler for SIH interrupts ... we "know" this is called * in task context, with IRQs enabled. */ |
c1e61bcf8 mfd: Use request_... |
578 |
static irqreturn_t handle_twl4030_sih(int irq, void *data) |
a30d46c04 mfd: twl4030 IRQ ... |
579 |
{ |
d5bb12216 mfd: Cleanup irq ... |
580 |
struct sih_agent *agent = irq_get_handler_data(irq); |
a30d46c04 mfd: twl4030 IRQ ... |
581 582 583 584 |
const struct sih *sih = agent->sih; int isr; /* reading ISR acks the IRQs, using clear-on-read mode */ |
a30d46c04 mfd: twl4030 IRQ ... |
585 |
isr = sih_read_isr(sih); |
a30d46c04 mfd: twl4030 IRQ ... |
586 587 588 589 590 591 |
if (isr < 0) { pr_err("twl4030: %s SIH, read ISR error %d ", sih->name, isr); /* REVISIT: recover; eventually mask it all, etc */ |
c1e61bcf8 mfd: Use request_... |
592 |
return IRQ_HANDLED; |
a30d46c04 mfd: twl4030 IRQ ... |
593 594 595 596 597 598 599 600 |
} while (isr) { irq = fls(isr); irq--; isr &= ~BIT(irq); if (irq < sih->bits) |
925e853c2 mfd: Set twl4030-... |
601 |
handle_nested_irq(agent->irq_base + irq); |
a30d46c04 mfd: twl4030 IRQ ... |
602 603 604 605 606 |
else pr_err("twl4030: %s SIH, invalid ISR bit %d ", sih->name, irq); } |
c1e61bcf8 mfd: Use request_... |
607 |
return IRQ_HANDLED; |
a30d46c04 mfd: twl4030 IRQ ... |
608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 |
} static unsigned twl4030_irq_next; /* returns the first IRQ used by this SIH bank, * or negative errno */ int twl4030_sih_setup(int module) { int sih_mod; const struct sih *sih = NULL; struct sih_agent *agent; int i, irq; int status = -EINVAL; unsigned irq_base = twl4030_irq_next; /* only support modules with standard clear-on-read for now */ for (sih_mod = 0, sih = sih_modules; |
1920a61e2 mfd: Initial supp... |
626 |
sih_mod < nr_sih_modules; |
a30d46c04 mfd: twl4030 IRQ ... |
627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 |
sih_mod++, sih++) { if (sih->module == module && sih->set_cor) { if (!WARN((irq_base + sih->bits) > NR_IRQS, "irq %d for %s too big ", irq_base + sih->bits, sih->name)) status = 0; break; } } if (status < 0) return status; agent = kzalloc(sizeof *agent, GFP_KERNEL); if (!agent) return -ENOMEM; status = 0; agent->irq_base = irq_base; agent->sih = sih; agent->imr = ~0; |
91e3569ff mfd: Implement bu... |
650 |
mutex_init(&agent->irq_lock); |
a30d46c04 mfd: twl4030 IRQ ... |
651 652 653 |
for (i = 0; i < sih->bits; i++) { irq = irq_base + i; |
91e3569ff mfd: Implement bu... |
654 |
irq_set_chip_data(irq, agent); |
d5bb12216 mfd: Cleanup irq ... |
655 656 |
irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip, handle_edge_irq); |
b18d1f0f4 mfd: Set twl4030-... |
657 |
irq_set_nested_thread(irq, 1); |
a30d46c04 mfd: twl4030 IRQ ... |
658 659 |
activate_irq(irq); } |
a30d46c04 mfd: twl4030 IRQ ... |
660 661 662 663 |
twl4030_irq_next += i; /* replace generic PIH handler (handle_simple_irq) */ irq = sih_mod + twl4030_irq_base; |
d5bb12216 mfd: Cleanup irq ... |
664 |
irq_set_handler_data(irq, agent); |
c1e61bcf8 mfd: Use request_... |
665 666 667 |
agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name); status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0, agent->irq_name ?: sih->name, NULL); |
a30d46c04 mfd: twl4030 IRQ ... |
668 669 670 671 |
pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d ", sih->name, irq, irq_base, twl4030_irq_next - 1); |
c1e61bcf8 mfd: Use request_... |
672 |
return status < 0 ? status : irq_base; |
a30d46c04 mfd: twl4030 IRQ ... |
673 674 675 676 677 678 679 680 681 |
} /* FIXME need a call to reverse twl4030_sih_setup() ... */ /*----------------------------------------------------------------------*/ /* FIXME pass in which interrupt line we'll use ... */ #define twl_irq_line 0 |
e8deb28ca mfd: Add support ... |
682 |
int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) |
a30d46c04 mfd: twl4030 IRQ ... |
683 684 685 686 687 |
{ static struct irq_chip twl4030_irq_chip; int status; int i; |
a30d46c04 mfd: twl4030 IRQ ... |
688 689 690 691 692 693 694 695 |
/* * Mask and clear all TWL4030 interrupts since initially we do * not have any TWL4030 module interrupt handlers present */ status = twl4030_init_sih_modules(twl_irq_line); if (status < 0) return status; |
a30d46c04 mfd: twl4030 IRQ ... |
696 697 698 699 700 701 702 |
twl4030_irq_base = irq_base; /* install an irq handler for each of the SIH modules; * clone dummy irq_chip since PIH can't *do* anything */ twl4030_irq_chip = dummy_irq_chip; twl4030_irq_chip.name = "twl4030"; |
fe2122138 mfd: twl4030: Fix... |
703 |
twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack; |
a30d46c04 mfd: twl4030 IRQ ... |
704 705 |
for (i = irq_base; i < irq_end; i++) { |
d5bb12216 mfd: Cleanup irq ... |
706 707 |
irq_set_chip_and_handler(i, &twl4030_irq_chip, handle_simple_irq); |
925e853c2 mfd: Set twl4030-... |
708 |
irq_set_nested_thread(i, 1); |
a30d46c04 mfd: twl4030 IRQ ... |
709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 |
activate_irq(i); } twl4030_irq_next = i; pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d ", "PIH", irq_num, irq_base, twl4030_irq_next - 1); /* ... and the PWR_INT module ... */ status = twl4030_sih_setup(TWL4030_MODULE_INT); if (status < 0) { pr_err("twl4030: sih_setup PWR INT --> %d ", status); goto fail; } /* install an irq handler to demultiplex the TWL4030 interrupt */ |
286f8f3cd mfd: Base interru... |
725 726 727 |
status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih, IRQF_ONESHOT, "TWL4030-PIH", NULL); |
1cef8e410 mfd: twl4030 irq ... |
728 729 730 731 732 |
if (status < 0) { pr_err("twl4030: could not claim irq%d: %d ", irq_num, status); goto fail_rqirq; } |
1cef8e410 mfd: twl4030 irq ... |
733 |
return status; |
1cef8e410 mfd: twl4030 irq ... |
734 735 |
fail_rqirq: /* clean up twl4030_sih_setup */ |
a30d46c04 mfd: twl4030 IRQ ... |
736 |
fail: |
925e853c2 mfd: Set twl4030-... |
737 738 |
for (i = irq_base; i < irq_end; i++) { irq_set_nested_thread(i, 0); |
d5bb12216 mfd: Cleanup irq ... |
739 |
irq_set_chip_and_handler(i, NULL, NULL); |
925e853c2 mfd: Set twl4030-... |
740 |
} |
2f2a7d5ef mfd: Drop twl4030... |
741 |
|
a30d46c04 mfd: twl4030 IRQ ... |
742 743 |
return status; } |
e8deb28ca mfd: Add support ... |
744 |
int twl4030_exit_irq(void) |
a30d46c04 mfd: twl4030 IRQ ... |
745 746 747 748 749 750 751 752 753 |
{ /* FIXME undo twl_init_irq() */ if (twl4030_irq_base) { pr_err("twl4030: can't yet clean up IRQs? "); return -ENOSYS; } return 0; } |
1920a61e2 mfd: Initial supp... |
754 |
|
e8deb28ca mfd: Add support ... |
755 |
int twl4030_init_chip_irq(const char *chip) |
1920a61e2 mfd: Initial supp... |
756 757 758 759 760 761 762 763 764 765 766 |
{ if (!strcmp(chip, "twl5031")) { sih_modules = sih_modules_twl5031; nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); } else { sih_modules = sih_modules_twl4030; nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); } return 0; } |