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drivers/edac/amd64_edac.h
14.9 KB
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/* * AMD64 class Memory Controller kernel module * * Copyright (c) 2009 SoftwareBitMaker. |
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* Copyright (c) 2009-15 Advanced Micro Devices, Inc. |
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* * This file may be distributed under the terms of the * GNU General Public License. |
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*/ #include <linux/module.h> #include <linux/ctype.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> #include <linux/mmzone.h> #include <linux/edac.h> |
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#include <asm/cpu_device_id.h> |
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#include <asm/msr.h> |
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#include "edac_module.h" |
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#include "mce_amd.h" |
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#define amd64_info(fmt, arg...) \ edac_printk(KERN_INFO, "amd64", fmt, ##arg) |
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#define amd64_warn(fmt, arg...) \ |
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edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg) |
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#define amd64_err(fmt, arg...) \ |
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edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg) |
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#define amd64_mc_warn(mci, fmt, arg...) \ edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) #define amd64_mc_err(mci, fmt, arg...) \ edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) |
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/* * Throughout the comments in this code, the following terms are used: * * SysAddr, DramAddr, and InputAddr * * These terms come directly from the amd64 documentation * (AMD publication #26094). They are defined as follows: * * SysAddr: * This is a physical address generated by a CPU core or a device * doing DMA. If generated by a CPU core, a SysAddr is the result of * a virtual to physical address translation by the CPU core's address * translation mechanism (MMU). * * DramAddr: * A DramAddr is derived from a SysAddr by subtracting an offset that * depends on which node the SysAddr maps to and whether the SysAddr * is within a range affected by memory hoisting. The DRAM Base * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers * determine which node a SysAddr maps to. * * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr * is within the range of addresses specified by this register, then * a value x from the DHAR is subtracted from the SysAddr to produce a * DramAddr. Here, x represents the base address for the node that * the SysAddr maps to plus an offset due to memory hoisting. See * section 3.4.8 and the comments in amd64_get_dram_hole_info() and * sys_addr_to_dram_addr() below for more information. * * If the SysAddr is not affected by the DHAR then a value y is * subtracted from the SysAddr to produce a DramAddr. Here, y is the * base address for the node that the SysAddr maps to. See section * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more * information. * * InputAddr: * A DramAddr is translated to an InputAddr before being passed to the * memory controller for the node that the DramAddr is associated * with. The memory controller then maps the InputAddr to a csrow. * If node interleaving is not in use, then the InputAddr has the same * value as the DramAddr. Otherwise, the InputAddr is produced by * discarding the bits used for node interleaving from the DramAddr. * See section 3.4.4 for more information. * * The memory controller for a given node uses its DRAM CS Base and * DRAM CS Mask registers to map an InputAddr to a csrow. See * sections 3.5.4 and 3.5.5 for more information. */ |
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#define EDAC_AMD64_VERSION "3.5.0" |
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#define EDAC_MOD_STR "amd64_edac" /* Extended Model from CPUID, for CPU Revision numbers */ |
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#define K8_REV_D 1 #define K8_REV_E 2 #define K8_REV_F 4 |
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/* Hardware limit on ChipSelect rows per MC and processors per system */ |
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#define NUM_CHIPSELECTS 8 #define DRAM_RANGES 8 |
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#define NUM_CONTROLLERS 8 |
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#define ON true #define OFF false |
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/* * PCI-defined configuration space registers */ |
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#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 |
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#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572 |
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#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 |
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 |
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#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 |
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee |
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#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496 |
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#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e |
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#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446 |
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#define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650 #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656 |
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/* * Function 1 - Address Map */ |
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#define DRAM_BASE_LO 0x40 #define DRAM_LIMIT_LO 0x44 |
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/* * F15 M30h D18F1x2[1C:00] */ #define DRAM_CONT_BASE 0x200 #define DRAM_CONT_LIMIT 0x204 /* * F15 M30h D18F1x2[4C:40] */ #define DRAM_CONT_HIGH_OFF 0x240 |
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#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) |
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#define DHAR 0xf0 |
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#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) |
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/* NOTE: Extra mask bit vs K8 */ |
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#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) |
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#define DCT_CFG_SEL 0x10C |
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#define DRAM_LOCAL_NODE_BASE 0x120 |
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#define DRAM_LOCAL_NODE_LIM 0x124 |
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#define DRAM_BASE_HI 0x140 #define DRAM_LIMIT_HI 0x144 |
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/* * Function 2 - DRAM controller */ |
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#define DCSB0 0x40 #define DCSB1 0x140 #define DCSB_CS_ENABLE BIT(0) |
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#define DCSM0 0x60 #define DCSM1 0x160 |
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#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE) |
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#define DRAM_CONTROL 0x78 |
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#define DBAM0 0x80 #define DBAM1 0x180 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ |
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#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) |
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#define DBAM_MAX_VALUE 11 |
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#define DCLR0 0x90 #define DCLR1 0x190 |
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#define REVE_WIDTH_128 BIT(16) |
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#define WIDTH_128 BIT(11) |
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#define DCHR0 0x94 #define DCHR1 0x194 |
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#define DDR3_MODE BIT(8) |
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#define DCT_SEL_LO 0x110 |
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#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) |
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#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) |
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#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) |
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#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) |
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#define SWAP_INTLV_REG 0x10c |
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#define DCT_SEL_HI 0x114 |
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#define F15H_M60H_SCRCTRL 0x1C8 |
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#define F17H_SCR_BASE_ADDR 0x48 #define F17H_SCR_LIMIT_ADDR 0x4C |
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/* * Function 3 - Misc Control */ |
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#define NBCTL 0x40 |
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#define NBCFG 0x44 #define NBCFG_CHIPKILL BIT(23) #define NBCFG_ECC_ENABLE BIT(22) |
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/* F3x48: NBSL */ |
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#define F10_NBSL_EXT_ERR_ECC 0x8 |
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#define NBSL_PP_OBS 0x2 |
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#define SCRCTRL 0x58 |
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#define F10_ONLINE_SPARE 0xB0 |
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#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) |
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#define F10_NB_ARRAY_ADDR 0xB8 |
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#define F10_NB_ARRAY_DRAM BIT(31) |
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/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ |
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#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1) |
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#define F10_NB_ARRAY_DATA 0xBC |
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#define F10_NB_ARR_ECC_WR_REQ BIT(17) |
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#define SET_NB_DRAM_INJECTION_WRITE(inj) \ (BIT(((inj.word) & 0xF) + 20) | \ |
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F10_NB_ARR_ECC_WR_REQ | inj.bit_map) |
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#define SET_NB_DRAM_INJECTION_READ(inj) \ (BIT(((inj.word) & 0xF) + 20) | \ BIT(16) | inj.bit_map) |
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#define NBCAP 0xE8 #define NBCAP_CHIPKILL BIT(4) #define NBCAP_SECDED BIT(3) #define NBCAP_DCT_DUAL BIT(0) |
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#define EXT_NB_MCA_CFG 0x180 |
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/* MSRs */ |
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#define MSR_MCGCTL_NBE BIT(4) |
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/* F17h */ /* F0: */ #define DF_DHAR 0x104 |
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/* UMC CH register offsets */ |
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#define UMCCH_BASE_ADDR 0x0 |
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#define UMCCH_BASE_ADDR_SEC 0x10 |
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#define UMCCH_ADDR_MASK 0x20 |
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#define UMCCH_ADDR_MASK_SEC 0x28 |
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#define UMCCH_ADDR_CFG 0x30 |
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#define UMCCH_DIMM_CFG 0x80 |
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#define UMCCH_UMC_CFG 0x100 |
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#define UMCCH_SDP_CTRL 0x104 |
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#define UMCCH_ECC_CTRL 0x14C |
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#define UMCCH_ECC_BAD_SYMBOL 0xD90 #define UMCCH_UMC_CAP 0xDF0 |
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#define UMCCH_UMC_CAP_HI 0xDF4 /* UMC CH bitfields */ |
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#define UMC_ECC_CHIPKILL_CAP BIT(31) |
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#define UMC_ECC_ENABLED BIT(30) |
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#define UMC_SDP_INIT BIT(31) |
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enum amd_families { |
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K8_CPUS = 0, F10_CPUS, |
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F15_CPUS, |
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F15_M30H_CPUS, |
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F15_M60H_CPUS, |
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F16_CPUS, |
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F16_M30H_CPUS, |
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F17_CPUS, |
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F17_M10H_CPUS, |
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F17_M30H_CPUS, |
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F17_M60H_CPUS, |
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F17_M70H_CPUS, |
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F19_CPUS, |
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NUM_FAMILIES, |
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}; |
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/* Error injection control structure */ struct error_injection { |
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u32 section; u32 word; u32 bit_map; |
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}; |
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/* low and high part of PCI config space regs */ struct reg_pair { u32 lo, hi; }; /* * See F1x[1, 0][7C:40] DRAM Base/Limit Registers */ struct dram_range { struct reg_pair base; struct reg_pair lim; }; |
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/* A DCT chip selects collection */ struct chip_select { u32 csbases[NUM_CHIPSELECTS]; |
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u32 csbases_sec[NUM_CHIPSELECTS]; |
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u8 b_cnt; u32 csmasks[NUM_CHIPSELECTS]; |
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u32 csmasks_sec[NUM_CHIPSELECTS]; |
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u8 m_cnt; }; |
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struct amd64_umc { |
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u32 dimm_cfg; /* DIMM Configuration reg */ |
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u32 umc_cfg; /* Configuration reg */ |
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u32 sdp_ctrl; /* SDP Control reg */ |
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u32 ecc_ctrl; /* DRAM ECC Control reg */ |
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u32 umc_cap_hi; /* Capabilities High reg */ |
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}; |
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struct amd64_pvt { |
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struct low_ops *ops; |
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/* pci_device handles which we utilize */ |
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struct pci_dev *F0, *F1, *F2, *F3, *F6; |
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u16 mc_node_id; /* MC index of this MC node */ |
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u8 fam; /* CPU family */ |
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u8 model; /* ... model */ u8 stepping; /* ... stepping */ |
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int ext_model; /* extended model value of this node */ |
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int channel_count; /* Raw registers */ u32 dclr0; /* DRAM Configuration Low DCT0 reg */ u32 dclr1; /* DRAM Configuration Low DCT1 reg */ u32 dchr0; /* DRAM Configuration High DCT0 reg */ u32 dchr1; /* DRAM Configuration High DCT1 reg */ u32 nbcap; /* North Bridge Capabilities */ u32 nbcfg; /* F10 North Bridge Configuration */ u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ u32 dhar; /* DRAM Hoist reg */ u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ |
d971e28e2 EDAC/amd64: Suppo... |
349 350 |
/* one for each DCT/UMC */ struct chip_select csels[NUM_CONTROLLERS]; |
cfe40fdb4 amd64_edac: add d... |
351 |
|
7f19bf755 amd64_edac: Remov... |
352 353 |
/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ struct dram_range ranges[DRAM_RANGES]; |
cfe40fdb4 amd64_edac: add d... |
354 |
|
cfe40fdb4 amd64_edac: add d... |
355 356 |
u64 top_mem; /* top of memory below 4GB */ u64 top_mem2; /* top of memory above 4GB */ |
78da121e1 amd64_edac: Clean... |
357 358 |
u32 dct_sel_lo; /* DRAM Controller Select Low */ u32 dct_sel_hi; /* DRAM Controller Select High */ |
b2b0c6054 amd64_edac: Add s... |
359 |
u32 online_spare; /* On-Line spare Reg */ |
cfe40fdb4 amd64_edac: add d... |
360 |
|
7835961d3 EDAC/amd64: Recog... |
361 |
/* x4, x8, or x16 syndromes in use */ |
a3b7db09a amd64_edac: Adjus... |
362 |
u8 ecc_sym_sz; |
ad6a32e96 amd64_edac: Sanit... |
363 |
|
cfe40fdb4 amd64_edac: add d... |
364 365 |
/* place to store error injection parameters prior to issue */ struct error_injection injection; |
a597d2a5d amd64_edac: Add F... |
366 367 368 |
/* cache the dram_type */ enum mem_type dram_type; |
f1cbbec9f EDAC, amd64: Add ... |
369 370 |
struct amd64_umc *umc; /* UMC registers */ |
ae7bb7c67 amd64_edac: Carve... |
371 |
}; |
33ca0643c amd64_edac: Reorg... |
372 373 374 375 376 |
enum err_codes { DECODE_OK = 0, ERR_NODE = -1, ERR_CSROW = -2, ERR_CHANNEL = -3, |
713ad5467 EDAC, amd64: Defi... |
377 378 |
ERR_SYND = -4, ERR_NORM_ADDR = -5, |
33ca0643c amd64_edac: Reorg... |
379 380 381 382 383 384 385 386 387 388 389 |
}; struct err_info { int err_code; struct mem_ctl_info *src_mci; int csrow; int channel; u16 syndrome; u32 page; u32 offset; }; |
196b79fcc EDAC, amd64: Exte... |
390 391 |
static inline u32 get_umc_base(u8 channel) { |
bdcee7747 EDAC/amd64: Suppo... |
392 393 |
/* chY: 0xY50000 */ return 0x50000 + (channel << 20); |
196b79fcc EDAC, amd64: Exte... |
394 |
} |
c7e5301a1 amd64_edac: Fix t... |
395 |
static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) |
7f19bf755 amd64_edac: Remov... |
396 397 398 399 400 401 402 403 |
{ u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; if (boot_cpu_data.x86 == 0xf) return addr; return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; } |
c7e5301a1 amd64_edac: Fix t... |
404 |
static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) |
7f19bf755 amd64_edac: Remov... |
405 406 407 408 409 410 411 412 |
{ u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; if (boot_cpu_data.x86 == 0xf) return lim; return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; } |
f192c7b16 amd64_edac: Simpl... |
413 414 415 416 |
static inline u16 extract_syndrome(u64 status) { return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); } |
18b94f66f amd64_edac: Add E... |
417 418 419 420 421 422 423 424 |
static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) { if (pvt->fam == 0x15 && pvt->model >= 0x30) return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | ((pvt->dct_sel_lo >> 6) & 0x3); return ((pvt)->dct_sel_lo >> 6) & 0x3; } |
ae7bb7c67 amd64_edac: Carve... |
425 426 427 428 429 430 |
/* * per-node ECC settings descriptor */ struct ecc_settings { u32 old_nbctl; bool nbctl_valid; |
cfe40fdb4 amd64_edac: add d... |
431 |
struct flags { |
d95cf4de6 amd64_edac: Simpl... |
432 433 |
unsigned long nb_mce_enable:1; unsigned long nb_ecc_prev:1; |
cfe40fdb4 amd64_edac: add d... |
434 435 |
} flags; }; |
7d6034d32 amd64_edac: add m... |
436 |
#ifdef CONFIG_EDAC_DEBUG |
e339f1ec9 EDAC: amd64: Use ... |
437 |
extern const struct attribute_group amd64_edac_dbg_group; |
7d6034d32 amd64_edac: add m... |
438 439 440 |
#endif #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION |
e339f1ec9 EDAC: amd64: Use ... |
441 |
extern const struct attribute_group amd64_edac_inj_group; |
7d6034d32 amd64_edac: add m... |
442 |
#endif |
cfe40fdb4 amd64_edac: add d... |
443 444 445 446 447 |
/* * Each of the PCI Device IDs types have their own set of hardware accessor * functions and per device encoding/decoding logic. */ struct low_ops { |
1433eb990 amd64_edac: enhan... |
448 |
int (*early_channel_count) (struct amd64_pvt *pvt); |
f192c7b16 amd64_edac: Simpl... |
449 |
void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643c amd64_edac: Reorg... |
450 |
struct err_info *); |
a597d2a5d amd64_edac: Add F... |
451 452 |
int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode, int cs_mask_nr); |
cfe40fdb4 amd64_edac: add d... |
453 454 455 456 |
}; struct amd64_family_type { const char *ctl_name; |
f1cbbec9f EDAC, amd64: Add ... |
457 |
u16 f0_id, f1_id, f2_id, f6_id; |
5e4c55276 EDAC/amd64: Save ... |
458 459 |
/* Maximum number of memory controllers per die/node. */ u8 max_mcs; |
cfe40fdb4 amd64_edac: add d... |
460 461 |
struct low_ops ops; }; |
66fed2d46 amd64_edac: Impro... |
462 463 |
int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, u32 *val, const char *func); |
b2b0c6054 amd64_edac: Add s... |
464 465 |
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, u32 val, const char *func); |
6ba5dcdc4 amd64_edac: wrap-... |
466 |
|
b2b0c6054 amd64_edac: Add s... |
467 468 |
#define amd64_read_pci_cfg(pdev, offset, val) \ __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) |
6ba5dcdc4 amd64_edac: wrap-... |
469 |
|
b2b0c6054 amd64_edac: Add s... |
470 471 |
#define amd64_write_pci_cfg(pdev, offset, val) \ __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) |
6ba5dcdc4 amd64_edac: wrap-... |
472 |
|
cfe40fdb4 amd64_edac: add d... |
473 474 |
int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, u64 *hole_offset, u64 *hole_size); |
c56087595 amd64_edac: conve... |
475 476 |
#define to_mci(k) container_of(k, struct mem_ctl_info, dev) |
66fed2d46 amd64_edac: Impro... |
477 478 479 480 481 482 483 484 485 486 487 488 |
/* Injection helpers */ static inline void disable_caches(void *dummy) { write_cr0(read_cr0() | X86_CR0_CD); wbinvd(); } static inline void enable_caches(void *dummy) { write_cr0(read_cr0() & ~X86_CR0_CD); } |
18b94f66f amd64_edac: Add E... |
489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 |
static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) { if (pvt->fam == 0x15 && pvt->model >= 0x30) { u32 tmp; amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); return (u8) tmp & 0xF; } return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; } static inline u8 dhar_valid(struct amd64_pvt *pvt) { if (pvt->fam == 0x15 && pvt->model >= 0x30) { u32 tmp; amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); return (tmp >> 1) & BIT(0); } return (pvt)->dhar & BIT(0); } static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) { if (pvt->fam == 0x15 && pvt->model >= 0x30) { u32 tmp; amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); return (tmp >> 11) & 0x1FFF; } return (pvt)->dct_sel_lo & 0xFFFFF800; } |