Blame view
drivers/irqchip/irq-vt8500.c
5.83 KB
1a59d1b8e treewide: Replace... |
1 |
// SPDX-License-Identifier: GPL-2.0-or-later |
21f47fbc5 ARM: 6597/1: Add ... |
2 3 4 |
/* * arch/arm/mach-vt8500/irq.c * |
e9a91de76 arm: vt8500: Upda... |
5 |
* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> |
21f47fbc5 ARM: 6597/1: Add ... |
6 |
* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> |
21f47fbc5 ARM: 6597/1: Add ... |
7 |
*/ |
e9a91de76 arm: vt8500: Upda... |
8 9 10 11 12 13 |
/* * This file is copied and modified from the original irq.c provided by * Alexey Charkov. Minor changes have been made for Device Tree Support. */ #include <linux/slab.h> |
21f47fbc5 ARM: 6597/1: Add ... |
14 15 |
#include <linux/io.h> #include <linux/irq.h> |
41a83e06e irqchip: Prepare ... |
16 |
#include <linux/irqchip.h> |
e9a91de76 arm: vt8500: Upda... |
17 |
#include <linux/irqdomain.h> |
21f47fbc5 ARM: 6597/1: Add ... |
18 |
#include <linux/interrupt.h> |
e9a91de76 arm: vt8500: Upda... |
19 20 21 22 23 |
#include <linux/bitops.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/of_address.h> |
21f47fbc5 ARM: 6597/1: Add ... |
24 25 |
#include <asm/irq.h> |
0c464d588 arm: vt8500: Conv... |
26 |
#include <asm/exception.h> |
06ff14c05 irqchip: vt8500: ... |
27 |
#include <asm/mach/irq.h> |
e9a91de76 arm: vt8500: Upda... |
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 |
#define VT8500_ICPC_IRQ 0x20 #define VT8500_ICPC_FIQ 0x24 #define VT8500_ICDC 0x40 /* Destination Control 64*u32 */ #define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */ /* ICPC */ #define ICPC_MASK 0x3F #define ICPC_ROTATE BIT(6) /* IC_DCTR */ #define ICDC_IRQ 0x00 #define ICDC_FIQ 0x01 #define ICDC_DSS0 0x02 #define ICDC_DSS1 0x03 #define ICDC_DSS2 0x04 #define ICDC_DSS3 0x05 #define ICDC_DSS4 0x06 #define ICDC_DSS5 0x07 #define VT8500_INT_DISABLE 0 #define VT8500_INT_ENABLE BIT(3) #define VT8500_TRIGGER_HIGH 0 #define VT8500_TRIGGER_RISING BIT(5) #define VT8500_TRIGGER_FALLING BIT(6) |
21f47fbc5 ARM: 6597/1: Add ... |
53 54 |
#define VT8500_EDGE ( VT8500_TRIGGER_RISING \ | VT8500_TRIGGER_FALLING) |
21f47fbc5 ARM: 6597/1: Add ... |
55 |
|
0c464d588 arm: vt8500: Conv... |
56 57 |
/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */ #define VT8500_INTC_MAX 2 |
e9a91de76 arm: vt8500: Upda... |
58 |
|
0c464d588 arm: vt8500: Conv... |
59 60 61 |
struct vt8500_irq_data { void __iomem *base; /* IO Memory base address */ struct irq_domain *domain; /* Domain for this controller */ |
e9a91de76 arm: vt8500: Upda... |
62 |
}; |
21f47fbc5 ARM: 6597/1: Add ... |
63 |
|
0c464d588 arm: vt8500: Conv... |
64 65 66 |
/* Global variable for accessing io-mem addresses */ static struct vt8500_irq_data intc[VT8500_INTC_MAX]; static u32 active_cnt = 0; |
2eb5af44b ARM: 6979/1: mach... |
67 |
static void vt8500_irq_mask(struct irq_data *d) |
21f47fbc5 ARM: 6597/1: Add ... |
68 |
{ |
0c464d588 arm: vt8500: Conv... |
69 |
struct vt8500_irq_data *priv = d->domain->host_data; |
e9a91de76 arm: vt8500: Upda... |
70 |
void __iomem *base = priv->base; |
0c464d588 arm: vt8500: Conv... |
71 72 73 |
void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4); u8 edge, dctr; u32 status; |
21f47fbc5 ARM: 6597/1: Add ... |
74 |
|
e9a91de76 arm: vt8500: Upda... |
75 |
edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE; |
21f47fbc5 ARM: 6597/1: Add ... |
76 |
if (edge) { |
0c464d588 arm: vt8500: Conv... |
77 |
status = readl(stat_reg); |
21f47fbc5 ARM: 6597/1: Add ... |
78 |
|
e9a91de76 arm: vt8500: Upda... |
79 |
status |= (1 << (d->hwirq & 0x1f)); |
21f47fbc5 ARM: 6597/1: Add ... |
80 81 |
writel(status, stat_reg); } else { |
0c464d588 arm: vt8500: Conv... |
82 |
dctr = readb(base + VT8500_ICDC + d->hwirq); |
21f47fbc5 ARM: 6597/1: Add ... |
83 |
dctr &= ~VT8500_INT_ENABLE; |
e9a91de76 arm: vt8500: Upda... |
84 |
writeb(dctr, base + VT8500_ICDC + d->hwirq); |
21f47fbc5 ARM: 6597/1: Add ... |
85 86 |
} } |
2eb5af44b ARM: 6979/1: mach... |
87 |
static void vt8500_irq_unmask(struct irq_data *d) |
21f47fbc5 ARM: 6597/1: Add ... |
88 |
{ |
0c464d588 arm: vt8500: Conv... |
89 |
struct vt8500_irq_data *priv = d->domain->host_data; |
e9a91de76 arm: vt8500: Upda... |
90 |
void __iomem *base = priv->base; |
21f47fbc5 ARM: 6597/1: Add ... |
91 |
u8 dctr; |
e9a91de76 arm: vt8500: Upda... |
92 |
dctr = readb(base + VT8500_ICDC + d->hwirq); |
21f47fbc5 ARM: 6597/1: Add ... |
93 |
dctr |= VT8500_INT_ENABLE; |
e9a91de76 arm: vt8500: Upda... |
94 |
writeb(dctr, base + VT8500_ICDC + d->hwirq); |
21f47fbc5 ARM: 6597/1: Add ... |
95 |
} |
2eb5af44b ARM: 6979/1: mach... |
96 |
static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type) |
21f47fbc5 ARM: 6597/1: Add ... |
97 |
{ |
0c464d588 arm: vt8500: Conv... |
98 |
struct vt8500_irq_data *priv = d->domain->host_data; |
e9a91de76 arm: vt8500: Upda... |
99 |
void __iomem *base = priv->base; |
21f47fbc5 ARM: 6597/1: Add ... |
100 |
u8 dctr; |
e9a91de76 arm: vt8500: Upda... |
101 |
dctr = readb(base + VT8500_ICDC + d->hwirq); |
21f47fbc5 ARM: 6597/1: Add ... |
102 103 104 105 106 107 108 |
dctr &= ~VT8500_EDGE; switch (flow_type) { case IRQF_TRIGGER_LOW: return -EINVAL; case IRQF_TRIGGER_HIGH: dctr |= VT8500_TRIGGER_HIGH; |
d2aa914d2 irqchip/vt8500: U... |
109 |
irq_set_handler_locked(d, handle_level_irq); |
21f47fbc5 ARM: 6597/1: Add ... |
110 111 112 |
break; case IRQF_TRIGGER_FALLING: dctr |= VT8500_TRIGGER_FALLING; |
d2aa914d2 irqchip/vt8500: U... |
113 |
irq_set_handler_locked(d, handle_edge_irq); |
21f47fbc5 ARM: 6597/1: Add ... |
114 115 116 |
break; case IRQF_TRIGGER_RISING: dctr |= VT8500_TRIGGER_RISING; |
d2aa914d2 irqchip/vt8500: U... |
117 |
irq_set_handler_locked(d, handle_edge_irq); |
21f47fbc5 ARM: 6597/1: Add ... |
118 119 |
break; } |
e9a91de76 arm: vt8500: Upda... |
120 |
writeb(dctr, base + VT8500_ICDC + d->hwirq); |
21f47fbc5 ARM: 6597/1: Add ... |
121 122 123 124 125 |
return 0; } static struct irq_chip vt8500_irq_chip = { |
2eb5af44b ARM: 6979/1: mach... |
126 127 128 129 130 |
.name = "vt8500", .irq_ack = vt8500_irq_mask, .irq_mask = vt8500_irq_mask, .irq_unmask = vt8500_irq_unmask, .irq_set_type = vt8500_irq_set_type, |
21f47fbc5 ARM: 6597/1: Add ... |
131 |
}; |
e9a91de76 arm: vt8500: Upda... |
132 |
static void __init vt8500_init_irq_hw(void __iomem *base) |
21f47fbc5 ARM: 6597/1: Add ... |
133 |
{ |
0c464d588 arm: vt8500: Conv... |
134 |
u32 i; |
21f47fbc5 ARM: 6597/1: Add ... |
135 |
|
e9a91de76 arm: vt8500: Upda... |
136 137 138 |
/* Enable rotating priority for IRQ */ writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ); writel(0x00, base + VT8500_ICPC_FIQ); |
21f47fbc5 ARM: 6597/1: Add ... |
139 |
|
0c464d588 arm: vt8500: Conv... |
140 141 142 |
/* Disable all interrupts and route them to IRQ */ for (i = 0; i < 64; i++) writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i); |
e9a91de76 arm: vt8500: Upda... |
143 |
} |
21f47fbc5 ARM: 6597/1: Add ... |
144 |
|
e9a91de76 arm: vt8500: Upda... |
145 146 147 148 |
static int vt8500_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq); |
21f47fbc5 ARM: 6597/1: Add ... |
149 |
|
e9a91de76 arm: vt8500: Upda... |
150 |
return 0; |
21f47fbc5 ARM: 6597/1: Add ... |
151 |
} |
960097365 irqchip: Constify... |
152 |
static const struct irq_domain_ops vt8500_irq_domain_ops = { |
e9a91de76 arm: vt8500: Upda... |
153 154 155 |
.map = vt8500_irq_map, .xlate = irq_domain_xlate_onecell, }; |
8783dd3a3 irqchip: Remove a... |
156 |
static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs) |
0c464d588 arm: vt8500: Conv... |
157 158 |
{ u32 stat, i; |
0beb65041 irqchip: vt8500: ... |
159 |
int irqnr; |
0c464d588 arm: vt8500: Conv... |
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 |
void __iomem *base; /* Loop through each active controller */ for (i=0; i<active_cnt; i++) { base = intc[i].base; irqnr = readl_relaxed(base) & 0x3F; /* Highest Priority register default = 63, so check that this is a real interrupt by checking the status register */ if (irqnr == 63) { stat = readl_relaxed(base + VT8500_ICIS + 4); if (!(stat & BIT(31))) continue; } |
0beb65041 irqchip: vt8500: ... |
175 |
handle_domain_irq(intc[i].domain, irqnr, regs); |
0c464d588 arm: vt8500: Conv... |
176 177 |
} } |
e658718e4 irqchip: vt8500: ... |
178 179 |
static int __init vt8500_irq_init(struct device_node *node, struct device_node *parent) |
21f47fbc5 ARM: 6597/1: Add ... |
180 |
{ |
e9a91de76 arm: vt8500: Upda... |
181 182 |
int irq, i; struct device_node *np = node; |
0c464d588 arm: vt8500: Conv... |
183 184 185 186 187 188 189 190 191 192 |
if (active_cnt == VT8500_INTC_MAX) { pr_err("%s: Interrupt controllers > VT8500_INTC_MAX ", __func__); goto out; } intc[active_cnt].base = of_iomap(np, 0); intc[active_cnt].domain = irq_domain_add_linear(node, 64, &vt8500_irq_domain_ops, &intc[active_cnt]); |
e9a91de76 arm: vt8500: Upda... |
193 |
|
0c464d588 arm: vt8500: Conv... |
194 195 196 197 198 199 200 201 202 203 204 |
if (!intc[active_cnt].base) { pr_err("%s: Unable to map IO memory ", __func__); goto out; } if (!intc[active_cnt].domain) { pr_err("%s: Unable to add irq domain! ", __func__); goto out; } |
e9a91de76 arm: vt8500: Upda... |
205 |
|
06ff14c05 irqchip: vt8500: ... |
206 |
set_handle_irq(vt8500_handle_irq); |
0c464d588 arm: vt8500: Conv... |
207 |
vt8500_init_irq_hw(intc[active_cnt].base); |
e9a91de76 arm: vt8500: Upda... |
208 |
|
0c464d588 arm: vt8500: Conv... |
209 210 |
pr_info("vt8500-irq: Added interrupt controller "); |
21f47fbc5 ARM: 6597/1: Add ... |
211 |
|
0c464d588 arm: vt8500: Conv... |
212 |
active_cnt++; |
e9a91de76 arm: vt8500: Upda... |
213 214 215 216 217 |
/* check if this is a slaved controller */ if (of_irq_count(np) != 0) { /* check that we have the correct number of interrupts */ if (of_irq_count(np) != 8) { |
0c464d588 arm: vt8500: Conv... |
218 219 |
pr_err("%s: Incorrect IRQ map for slaved controller ", |
e9a91de76 arm: vt8500: Upda... |
220 221 |
__func__); return -EINVAL; |
21f47fbc5 ARM: 6597/1: Add ... |
222 |
} |
e9a91de76 arm: vt8500: Upda... |
223 224 225 226 227 228 229 230 |
for (i = 0; i < 8; i++) { irq = irq_of_parse_and_map(np, i); enable_irq(irq); } pr_info("vt8500-irq: Enabled slave->parent interrupts "); |
21f47fbc5 ARM: 6597/1: Add ... |
231 |
} |
0c464d588 arm: vt8500: Conv... |
232 |
out: |
e9a91de76 arm: vt8500: Upda... |
233 |
return 0; |
21f47fbc5 ARM: 6597/1: Add ... |
234 |
} |
e9a91de76 arm: vt8500: Upda... |
235 |
|
06ff14c05 irqchip: vt8500: ... |
236 |
IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init); |