Eric Lee / smarc-fsl-linux-kernel

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arch/mips/kernel/csrc-sb1250.c 2.1 KB
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217dd11e9   Ralf Baechle   [MIPS] Sibyte: Sp... 
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  /*
   * Copyright (C) 2000, 2001 Broadcom Corporation
   *
   * This program is free software; you can redistribute it and/or
   * modify it under the terms of the GNU General Public License
   * as published by the Free Software Foundation; either version 2
   * of the License, or (at your option) any later version.
   *
   * This program is distributed in the hope that it will be useful,
   * but WITHOUT ANY WARRANTY; without even the implied warranty of
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   * GNU General Public License for more details.
   *
   * You should have received a copy of the GNU General Public License
   * along with this program; if not, write to the Free Software
   * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   */
  #include <linux/clocksource.h>
  
  #include <asm/addrspace.h>
  #include <asm/io.h>
  #include <asm/time.h>
  
  #include <asm/sibyte/sb1250.h>
  #include <asm/sibyte/sb1250_regs.h>
  #include <asm/sibyte/sb1250_int.h>
  #include <asm/sibyte/sb1250_scd.h>
  
  #define SB1250_HPT_NUM		3
  #define SB1250_HPT_VALUE	M_SCD_TIMER_CNT /* max value */
  
  /*
   * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
   * again.
   */
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  static cycle_t sb1250_hpt_read(struct clocksource *cs)
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  {
  	unsigned int count;
  
  	count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
  
  	return SB1250_HPT_VALUE - count;
  }
  
  struct clocksource bcm1250_clocksource = {
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  	.name	= "bcm1250-counter-3",
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  	.rating	= 200,
  	.read	= sb1250_hpt_read,
  	.mask	= CLOCKSOURCE_MASK(23),
  	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
  };
  
  void __init sb1250_clocksource_init(void)
  {
  	struct clocksource *cs = &bcm1250_clocksource;
  
  	/* Setup hpt using timer #3 but do not enable irq for it */
  	__raw_writeq(0,
  		     IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
  						 R_SCD_TIMER_CFG)));
  	__raw_writeq(SB1250_HPT_VALUE,
  		     IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
  						 R_SCD_TIMER_INIT)));
  	__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
  		     IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
  						 R_SCD_TIMER_CFG)));
75c4fd8c7   John Stultz   mips: convert to ... 
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  	clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
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  }