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arch/mips/sni/pcit.c
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/* * PCI Tower specific code * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) */ #include <linux/init.h> #include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/pci.h> #include <linux/serial_8250.h> |
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#include <asm/sni.h> #include <asm/time.h> #include <asm/irq_cpu.h> #define PORT(_base,_irq) \ { \ .iobase = _base, \ .irq = _irq, \ .uartclk = 1843200, \ .iotype = UPIO_PORT, \ .flags = UPF_BOOT_AUTOCONF, \ } static struct plat_serial8250_port pcit_data[] = { PORT(0x3f8, 0), PORT(0x2f8, 3), { }, }; static struct platform_device pcit_serial8250_device = { .name = "serial8250", .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = pcit_data, }, }; static struct plat_serial8250_port pcit_cplus_data[] = { |
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PORT(0x3f8, 0), |
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PORT(0x2f8, 3), PORT(0x3e8, 4), PORT(0x2e8, 3), { }, }; static struct platform_device pcit_cplus_serial8250_device = { .name = "serial8250", .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = pcit_cplus_data, }, }; |
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static struct resource pcit_cmos_rsrc[] = { { .start = 0x70, .end = 0x71, .flags = IORESOURCE_IO }, { .start = 8, .end = 8, .flags = IORESOURCE_IRQ } }; static struct platform_device pcit_cmos_device = { .name = "rtc_cmos", .num_resources = ARRAY_SIZE(pcit_cmos_rsrc), .resource = pcit_cmos_rsrc }; |
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static struct platform_device pcit_pcspeaker_pdev = { .name = "pcspkr", .id = -1, }; |
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static struct resource sni_io_resource = { |
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.start = 0x00000000UL, |
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.end = 0x03bfffffUL, |
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.name = "PCIT IO", |
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.flags = IORESOURCE_IO, }; static struct resource pcit_io_resources[] = { { .start = 0x00, .end = 0x1f, .name = "dma1", .flags = IORESOURCE_BUSY }, { .start = 0x40, .end = 0x5f, .name = "timer", .flags = IORESOURCE_BUSY }, { .start = 0x60, .end = 0x6f, .name = "keyboard", .flags = IORESOURCE_BUSY }, { .start = 0x80, .end = 0x8f, .name = "dma page reg", .flags = IORESOURCE_BUSY }, { .start = 0xc0, .end = 0xdf, .name = "dma2", .flags = IORESOURCE_BUSY }, { |
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.start = 0xcf8, .end = 0xcfb, .name = "PCI config addr", .flags = IORESOURCE_BUSY }, { |
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.start = 0xcfc, .end = 0xcff, .name = "PCI config data", .flags = IORESOURCE_BUSY } }; static struct resource sni_mem_resource = { |
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.start = 0x18000000UL, .end = 0x1fbfffffUL, |
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.name = "PCIT PCI MEM", .flags = IORESOURCE_MEM }; |
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static void __init sni_pcit_resource_init(void) { int i; /* request I/O space for devices used on all i[345]86 PCs */ for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++) |
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request_resource(&sni_io_resource, pcit_io_resources + i); |
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} extern struct pci_ops sni_pcit_ops; static struct pci_controller sni_pcit_controller = { .pci_ops = &sni_pcit_ops, .mem_resource = &sni_mem_resource, |
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.mem_offset = 0x00000000UL, |
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.io_resource = &sni_io_resource, |
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.io_offset = 0x00000000UL, .io_map_base = SNI_PORT_BASE |
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}; |
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static void enable_pcit_irq(struct irq_data *d) |
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{ |
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u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24); |
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*(volatile u32 *)SNI_PCIT_INT_REG |= mask; } |
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void disable_pcit_irq(struct irq_data *d) |
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{ |
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u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24); |
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*(volatile u32 *)SNI_PCIT_INT_REG &= ~mask; } |
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static struct irq_chip pcit_irq_type = { |
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.name = "PCIT", |
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.irq_mask = disable_pcit_irq, .irq_unmask = enable_pcit_irq, |
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}; static void pcit_hwint1(void) { u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG; int irq; clear_c0_status(IE_IRQ1); irq = ffs((pending >> 16) & 0x7f); if (likely(irq > 0)) |
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do_IRQ(irq + SNI_PCIT_INT_START - 1); set_c0_status(IE_IRQ1); |
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} static void pcit_hwint0(void) { u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG; int irq; clear_c0_status(IE_IRQ0); |
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irq = ffs((pending >> 16) & 0x3f); |
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if (likely(irq > 0)) |
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do_IRQ(irq + SNI_PCIT_INT_START - 1); set_c0_status(IE_IRQ0); |
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} static void sni_pcit_hwint(void) { |
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u32 pending = read_c0_cause() & read_c0_status(); |
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if (pending & C_IRQ1) pcit_hwint1(); else if (pending & C_IRQ2) |
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do_IRQ(MIPS_CPU_IRQ_BASE + 4); |
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else if (pending & C_IRQ3) |
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do_IRQ(MIPS_CPU_IRQ_BASE + 5); |
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else if (pending & C_IRQ5) |
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do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
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} static void sni_pcit_hwint_cplus(void) { |
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u32 pending = read_c0_cause() & read_c0_status(); |
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if (pending & C_IRQ0) pcit_hwint0(); |
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else if (pending & C_IRQ1) |
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do_IRQ(MIPS_CPU_IRQ_BASE + 3); |
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else if (pending & C_IRQ2) |
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do_IRQ(MIPS_CPU_IRQ_BASE + 4); |
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else if (pending & C_IRQ3) |
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do_IRQ(MIPS_CPU_IRQ_BASE + 5); |
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else if (pending & C_IRQ5) |
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do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
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} void __init sni_pcit_irq_init(void) { int i; mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) |
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irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); |
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*(volatile u32 *)SNI_PCIT_INT_REG = 0; sni_hwint = sni_pcit_hwint; change_c0_status(ST0_IM, IE_IRQ1); |
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setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq); |
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} void __init sni_pcit_cplus_irq_init(void) { int i; mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) |
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irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); |
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*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; |
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sni_hwint = sni_pcit_hwint_cplus; change_c0_status(ST0_IM, IE_IRQ0); |
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setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); |
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} |
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void __init sni_pcit_init(void) |
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{ |
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ioport_resource.end = sni_io_resource.end; |
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#ifdef CONFIG_PCI |
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PCIBIOS_MIN_IO = 0x9000; |
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register_pci_controller(&sni_pcit_controller); #endif |
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sni_pcit_resource_init(); |
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} static int __init snirm_pcit_setup_devinit(void) { switch (sni_brd_type) { case SNI_BRD_PCI_TOWER: platform_device_register(&pcit_serial8250_device); |
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platform_device_register(&pcit_cmos_device); |
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platform_device_register(&pcit_pcspeaker_pdev); |
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break; case SNI_BRD_PCI_TOWER_CPLUS: platform_device_register(&pcit_cplus_serial8250_device); |
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platform_device_register(&pcit_cmos_device); |
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platform_device_register(&pcit_pcspeaker_pdev); |
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break; } return 0; } device_initcall(snirm_pcit_setup_devinit); |