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drivers/ata/sata_nv.c
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/* * sata_nv.c - NVIDIA nForce SATA * * Copyright 2004 NVIDIA Corp. All rights reserved. * Copyright 2004 Andrew Chew * |
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* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. If not, write to * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
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* |
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* * libata documentation is available via 'make {ps|pdf}docs', * as Documentation/DocBook/libata.* * * No hardware documentation available outside of NVIDIA. * This driver programs the NVIDIA SATA controller in a similar * fashion as with other PCI IDE BMDMA controllers, with a few * NV-specific details such as register offsets, SATA phy location, * hotplug info, etc. * |
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* CK804/MCP04 controllers support an alternate programming interface * similar to the ADMA specification (with some modifications). * This allows the use of NCQ. Non-DMA-mapped ATA commands are still * sent through the legacy interface. * |
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*/ |
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#include <linux/kernel.h> #include <linux/module.h> |
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#include <linux/gfp.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> #include <linux/delay.h> #include <linux/interrupt.h> |
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#include <linux/device.h> |
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#include <scsi/scsi_host.h> |
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#include <scsi/scsi_device.h> |
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#include <linux/libata.h> #define DRV_NAME "sata_nv" |
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#define DRV_VERSION "3.5" |
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#define NV_ADMA_DMA_BOUNDARY 0xffffffffUL |
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enum { |
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NV_MMIO_BAR = 5, |
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NV_PORTS = 2, |
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NV_PIO_MASK = ATA_PIO4, NV_MWDMA_MASK = ATA_MWDMA2, NV_UDMA_MASK = ATA_UDMA6, |
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NV_PORT0_SCR_REG_OFFSET = 0x00, NV_PORT1_SCR_REG_OFFSET = 0x40, |
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/* INT_STATUS/ENABLE */ |
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NV_INT_STATUS = 0x10, |
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NV_INT_ENABLE = 0x11, |
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NV_INT_STATUS_CK804 = 0x440, |
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NV_INT_ENABLE_CK804 = 0x441, |
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/* INT_STATUS/ENABLE bits */ NV_INT_DEV = 0x01, NV_INT_PM = 0x02, NV_INT_ADDED = 0x04, NV_INT_REMOVED = 0x08, NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */ |
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NV_INT_ALL = 0x0f, |
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NV_INT_MASK = NV_INT_DEV | NV_INT_ADDED | NV_INT_REMOVED, |
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/* INT_CONFIG */ |
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NV_INT_CONFIG = 0x12, NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI |
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// For PCI config register 20 NV_MCP_SATA_CFG_20 = 0x50, NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04, |
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NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17), NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16), NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14), NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12), NV_ADMA_MAX_CPBS = 32, NV_ADMA_CPB_SZ = 128, NV_ADMA_APRD_SZ = 16, NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) / NV_ADMA_APRD_SZ, NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5, NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ, NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS * (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ), /* BAR5 offset to ADMA general registers */ NV_ADMA_GEN = 0x400, NV_ADMA_GEN_CTL = 0x00, NV_ADMA_NOTIFIER_CLEAR = 0x30, /* BAR5 offset to ADMA ports */ NV_ADMA_PORT = 0x480, /* size of ADMA port register space */ NV_ADMA_PORT_SIZE = 0x100, /* ADMA port registers */ NV_ADMA_CTL = 0x40, NV_ADMA_CPB_COUNT = 0x42, NV_ADMA_NEXT_CPB_IDX = 0x43, NV_ADMA_STAT = 0x44, NV_ADMA_CPB_BASE_LOW = 0x48, NV_ADMA_CPB_BASE_HIGH = 0x4C, NV_ADMA_APPEND = 0x50, NV_ADMA_NOTIFIER = 0x68, NV_ADMA_NOTIFIER_ERROR = 0x6C, /* NV_ADMA_CTL register bits */ NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0), NV_ADMA_CTL_CHANNEL_RESET = (1 << 5), NV_ADMA_CTL_GO = (1 << 7), NV_ADMA_CTL_AIEN = (1 << 8), NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11), NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12), /* CPB response flag bits */ NV_CPB_RESP_DONE = (1 << 0), NV_CPB_RESP_ATA_ERR = (1 << 3), NV_CPB_RESP_CMD_ERR = (1 << 4), NV_CPB_RESP_CPB_ERR = (1 << 7), /* CPB control flag bits */ NV_CPB_CTL_CPB_VALID = (1 << 0), NV_CPB_CTL_QUEUE = (1 << 1), NV_CPB_CTL_APRD_VALID = (1 << 2), NV_CPB_CTL_IEN = (1 << 3), NV_CPB_CTL_FPDMA = (1 << 4), /* APRD flags */ NV_APRD_WRITE = (1 << 1), NV_APRD_END = (1 << 2), NV_APRD_CONT = (1 << 3), /* NV_ADMA_STAT flags */ NV_ADMA_STAT_TIMEOUT = (1 << 0), NV_ADMA_STAT_HOTUNPLUG = (1 << 1), NV_ADMA_STAT_HOTPLUG = (1 << 2), NV_ADMA_STAT_CPBERR = (1 << 4), NV_ADMA_STAT_SERROR = (1 << 5), NV_ADMA_STAT_CMD_COMPLETE = (1 << 6), NV_ADMA_STAT_IDLE = (1 << 8), NV_ADMA_STAT_LEGACY = (1 << 9), NV_ADMA_STAT_STOPPED = (1 << 10), NV_ADMA_STAT_DONE = (1 << 12), NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR | |
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NV_ADMA_STAT_TIMEOUT, |
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/* port flags */ NV_ADMA_PORT_REGISTER_MODE = (1 << 0), |
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NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1), |
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/* MCP55 reg offset */ NV_CTL_MCP55 = 0x400, NV_INT_STATUS_MCP55 = 0x440, NV_INT_ENABLE_MCP55 = 0x444, NV_NCQ_REG_MCP55 = 0x448, /* MCP55 */ NV_INT_ALL_MCP55 = 0xffff, NV_INT_PORT_SHIFT_MCP55 = 16, /* each port occupies 16 bits */ NV_INT_MASK_MCP55 = NV_INT_ALL_MCP55 & 0xfffd, /* SWNCQ ENABLE BITS*/ NV_CTL_PRI_SWNCQ = 0x02, NV_CTL_SEC_SWNCQ = 0x04, /* SW NCQ status bits*/ NV_SWNCQ_IRQ_DEV = (1 << 0), NV_SWNCQ_IRQ_PM = (1 << 1), NV_SWNCQ_IRQ_ADDED = (1 << 2), NV_SWNCQ_IRQ_REMOVED = (1 << 3), NV_SWNCQ_IRQ_BACKOUT = (1 << 4), NV_SWNCQ_IRQ_SDBFIS = (1 << 5), NV_SWNCQ_IRQ_DHREGFIS = (1 << 6), NV_SWNCQ_IRQ_DMASETUP = (1 << 7), NV_SWNCQ_IRQ_HOTPLUG = NV_SWNCQ_IRQ_ADDED | NV_SWNCQ_IRQ_REMOVED, |
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}; /* ADMA Physical Region Descriptor - one SG segment */ struct nv_adma_prd { __le64 addr; __le32 len; u8 flags; u8 packet_len; __le16 reserved; }; enum nv_adma_regbits { CMDEND = (1 << 15), /* end of command list */ WNB = (1 << 14), /* wait-not-BSY */ IGN = (1 << 13), /* ignore this entry */ CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */ DA2 = (1 << (2 + 8)), DA1 = (1 << (1 + 8)), DA0 = (1 << (0 + 8)), }; /* ADMA Command Parameter Block The first 5 SG segments are stored inside the Command Parameter Block itself. If there are more than 5 segments the remainder are stored in a separate memory area indicated by next_aprd. */ struct nv_adma_cpb { u8 resp_flags; /* 0 */ u8 reserved1; /* 1 */ u8 ctl_flags; /* 2 */ /* len is length of taskfile in 64 bit words */ |
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u8 len; /* 3 */ |
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u8 tag; /* 4 */ u8 next_cpb_idx; /* 5 */ __le16 reserved2; /* 6-7 */ __le16 tf[12]; /* 8-31 */ struct nv_adma_prd aprd[5]; /* 32-111 */ __le64 next_aprd; /* 112-119 */ __le64 reserved3; /* 120-127 */ |
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}; |
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struct nv_adma_port_priv { struct nv_adma_cpb *cpb; dma_addr_t cpb_dma; struct nv_adma_prd *aprd; dma_addr_t aprd_dma; |
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void __iomem *ctl_block; void __iomem *gen_block; void __iomem *notifier_clear_block; |
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u64 adma_dma_mask; |
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u8 flags; |
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int last_issue_ncq; |
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}; |
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struct nv_host_priv { unsigned long type; }; |
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struct defer_queue { u32 defer_bits; unsigned int head; unsigned int tail; unsigned int tag[ATA_MAX_QUEUE]; }; enum ncq_saw_flag_list { ncq_saw_d2h = (1U << 0), ncq_saw_dmas = (1U << 1), ncq_saw_sdb = (1U << 2), ncq_saw_backout = (1U << 3), }; struct nv_swncq_port_priv { |
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struct ata_bmdma_prd *prd; /* our SG list */ |
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dma_addr_t prd_dma; /* and its DMA mapping */ void __iomem *sactive_block; void __iomem *irq_block; void __iomem *tag_block; u32 qc_active; unsigned int last_issue_tag; /* fifo circular queue to store deferral command */ struct defer_queue defer_queue; /* for NCQ interrupt analysis */ u32 dhfis_bits; u32 dmafis_bits; u32 sdbfis_bits; unsigned int ncq_flags; }; |
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#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT))))) |
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static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
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#ifdef CONFIG_PM_SLEEP |
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static int nv_pci_device_resume(struct pci_dev *pdev); |
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#endif |
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static void nv_ck804_host_stop(struct ata_host *host); |
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static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance); static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance); static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance); |
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static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); |
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static int nv_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline); |
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static void nv_nf2_freeze(struct ata_port *ap); static void nv_nf2_thaw(struct ata_port *ap); static void nv_ck804_freeze(struct ata_port *ap); static void nv_ck804_thaw(struct ata_port *ap); |
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static int nv_adma_slave_config(struct scsi_device *sdev); |
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static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc); |
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static void nv_adma_qc_prep(struct ata_queued_cmd *qc); static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc); static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance); static void nv_adma_irq_clear(struct ata_port *ap); static int nv_adma_port_start(struct ata_port *ap); static void nv_adma_port_stop(struct ata_port *ap); |
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#ifdef CONFIG_PM |
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static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg); static int nv_adma_port_resume(struct ata_port *ap); |
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#endif |
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static void nv_adma_freeze(struct ata_port *ap); static void nv_adma_thaw(struct ata_port *ap); |
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static void nv_adma_error_handler(struct ata_port *ap); static void nv_adma_host_stop(struct ata_host *host); |
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static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc); |
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static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
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static void nv_mcp55_thaw(struct ata_port *ap); static void nv_mcp55_freeze(struct ata_port *ap); static void nv_swncq_error_handler(struct ata_port *ap); static int nv_swncq_slave_config(struct scsi_device *sdev); static int nv_swncq_port_start(struct ata_port *ap); static void nv_swncq_qc_prep(struct ata_queued_cmd *qc); static void nv_swncq_fill_sg(struct ata_queued_cmd *qc); static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc); static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis); static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance); #ifdef CONFIG_PM static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg); static int nv_swncq_port_resume(struct ata_port *ap); #endif |
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enum nv_host_type { GENERIC, NFORCE2, |
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NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */ |
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CK804, |
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ADMA, |
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MCP5x, |
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SWNCQ, |
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}; |
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static const struct pci_device_id nv_pci_tbl[] = { |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), MCP5x }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), MCP5x }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), MCP5x }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), MCP5x }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC }, { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC }, |
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{ } /* terminate list */ |
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}; |
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static struct pci_driver nv_pci_driver = { .name = DRV_NAME, .id_table = nv_pci_tbl, .probe = nv_init_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, .resume = nv_pci_device_resume, |
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#endif |
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.remove = ata_pci_remove_one, |
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}; |
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static struct scsi_host_template nv_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static struct scsi_host_template nv_adma_sht = { |
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ATA_NCQ_SHT(DRV_NAME), |
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.can_queue = NV_ADMA_MAX_CPBS, |
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.sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN, |
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.dma_boundary = NV_ADMA_DMA_BOUNDARY, .slave_configure = nv_adma_slave_config, |
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}; |
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static struct scsi_host_template nv_swncq_sht = { |
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ATA_NCQ_SHT(DRV_NAME), |
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.can_queue = ATA_MAX_QUEUE, |
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.sg_tablesize = LIBATA_MAX_PRD, |
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.dma_boundary = ATA_DMA_BOUNDARY, .slave_configure = nv_swncq_slave_config, |
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}; |
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/* * NV SATA controllers have various different problems with hardreset * protocol depending on the specific controller and device. * * GENERIC: * * bko11195 reports that link doesn't come online after hardreset on * generic nv's and there have been several other similar reports on * linux-ide. * * bko12351#c23 reports that warmplug on MCP61 doesn't work with * softreset. * * NF2/3: * * bko3352 reports nf2/3 controllers can't determine device signature * reliably after hardreset. The following thread reports detection * failure on cold boot with the standard debouncing timing. * * http://thread.gmane.org/gmane.linux.ide/34098 * * bko12176 reports that hardreset fails to bring up the link during * boot on nf2. * * CK804: * * For initial probing after boot and hot plugging, hardreset mostly * works fine on CK804 but curiously, reprobing on the initial port * by rescanning or rmmod/insmod fails to acquire the initial D2H Reg * FIS in somewhat undeterministic way. * * SWNCQ: * * bko12351 reports that when SWNCQ is enabled, for hotplug to work, * hardreset should be used and hardreset can't report proper * signature, which suggests that mcp5x is closer to nf2 as long as * reset quirkiness is concerned. * * bko12703 reports that boot probing fails for intel SSD with * hardreset. Link fails to come online. Softreset works fine. * * The failures are varied but the following patterns seem true for * all flavors. * * - Softreset during boot always works. * * - Hardreset during boot sometimes fails to bring up the link on * certain comibnations and device signature acquisition is * unreliable. * * - Hardreset is often necessary after hotplug. * * So, preferring softreset for boot probing and error handling (as * hardreset might bring down the link) but using hardreset for * post-boot probing should work around the above issues in most * cases. Define nv_hardreset() which only kicks in for post-boot * probing and use it for all variants. */ static struct ata_port_operations nv_generic_ops = { |
029cfd6b7 libata: implement... |
453 |
.inherits = &ata_bmdma_port_ops, |
c96f1732e [libata] Improve ... |
454 |
.lost_interrupt = ATA_OP_NULL, |
1da177e4c Linux-2.6.12-rc2 |
455 456 |
.scr_read = nv_scr_read, .scr_write = nv_scr_write, |
7f4774b38 sata_nv: use hard... |
457 |
.hardreset = nv_hardreset, |
1da177e4c Linux-2.6.12-rc2 |
458 |
}; |
029cfd6b7 libata: implement... |
459 |
static struct ata_port_operations nv_nf2_ops = { |
7dac745b8 sata_nv: give up ... |
460 |
.inherits = &nv_generic_ops, |
39f875825 [PATCH] sata_nv: ... |
461 462 |
.freeze = nv_nf2_freeze, .thaw = nv_nf2_thaw, |
ada364e88 [PATCH] sata_nv: ... |
463 |
}; |
029cfd6b7 libata: implement... |
464 |
static struct ata_port_operations nv_ck804_ops = { |
7f4774b38 sata_nv: use hard... |
465 |
.inherits = &nv_generic_ops, |
39f875825 [PATCH] sata_nv: ... |
466 467 |
.freeze = nv_ck804_freeze, .thaw = nv_ck804_thaw, |
ada364e88 [PATCH] sata_nv: ... |
468 469 |
.host_stop = nv_ck804_host_stop, }; |
029cfd6b7 libata: implement... |
470 |
static struct ata_port_operations nv_adma_ops = { |
3c324283e sata_nv: fix gene... |
471 |
.inherits = &nv_ck804_ops, |
029cfd6b7 libata: implement... |
472 |
|
2dec7555e [PATCH] sata_nv: ... |
473 |
.check_atapi_dma = nv_adma_check_atapi_dma, |
5682ed33a libata: rename SF... |
474 |
.sff_tf_read = nv_adma_tf_read, |
31cc23b34 libata-pmp-prep: ... |
475 |
.qc_defer = ata_std_qc_defer, |
fbbb262d9 [PATCH] sata_nv A... |
476 477 |
.qc_prep = nv_adma_qc_prep, .qc_issue = nv_adma_qc_issue, |
5682ed33a libata: rename SF... |
478 |
.sff_irq_clear = nv_adma_irq_clear, |
029cfd6b7 libata: implement... |
479 |
|
53014e252 sata_nv: fix ADMA... |
480 481 |
.freeze = nv_adma_freeze, .thaw = nv_adma_thaw, |
fbbb262d9 [PATCH] sata_nv A... |
482 |
.error_handler = nv_adma_error_handler, |
f5ecac2d8 sata_nv: kill old... |
483 |
.post_internal_cmd = nv_adma_post_internal_cmd, |
029cfd6b7 libata: implement... |
484 |
|
fbbb262d9 [PATCH] sata_nv A... |
485 486 |
.port_start = nv_adma_port_start, .port_stop = nv_adma_port_stop, |
438ac6d5e libata: add missi... |
487 |
#ifdef CONFIG_PM |
cdf56bcf1 sata_nv: add susp... |
488 489 |
.port_suspend = nv_adma_port_suspend, .port_resume = nv_adma_port_resume, |
438ac6d5e libata: add missi... |
490 |
#endif |
fbbb262d9 [PATCH] sata_nv A... |
491 492 |
.host_stop = nv_adma_host_stop, }; |
029cfd6b7 libata: implement... |
493 |
static struct ata_port_operations nv_swncq_ops = { |
7f4774b38 sata_nv: use hard... |
494 |
.inherits = &nv_generic_ops, |
029cfd6b7 libata: implement... |
495 |
|
f140f0f12 [libata] sata_nv:... |
496 497 498 |
.qc_defer = ata_std_qc_defer, .qc_prep = nv_swncq_qc_prep, .qc_issue = nv_swncq_qc_issue, |
029cfd6b7 libata: implement... |
499 |
|
f140f0f12 [libata] sata_nv:... |
500 501 502 |
.freeze = nv_mcp55_freeze, .thaw = nv_mcp55_thaw, .error_handler = nv_swncq_error_handler, |
029cfd6b7 libata: implement... |
503 |
|
f140f0f12 [libata] sata_nv:... |
504 505 506 507 508 509 |
#ifdef CONFIG_PM .port_suspend = nv_swncq_port_suspend, .port_resume = nv_swncq_port_resume, #endif .port_start = nv_swncq_port_start, }; |
959471936 libata: kill port... |
510 511 512 513 514 515 516 |
struct nv_pi_priv { irq_handler_t irq_handler; struct scsi_host_template *sht; }; #define NV_PI_PRIV(_irq_handler, _sht) \ &(struct nv_pi_priv){ .irq_handler = _irq_handler, .sht = _sht } |
1626aeb88 libata: clean up ... |
517 |
static const struct ata_port_info nv_port_info[] = { |
ada364e88 [PATCH] sata_nv: ... |
518 519 |
/* generic */ { |
9cbe056f6 libata: remove AT... |
520 |
.flags = ATA_FLAG_SATA, |
ada364e88 [PATCH] sata_nv: ... |
521 522 523 524 |
.pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_generic_ops, |
959471936 libata: kill port... |
525 |
.private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht), |
ada364e88 [PATCH] sata_nv: ... |
526 527 528 |
}, /* nforce2/3 */ { |
9cbe056f6 libata: remove AT... |
529 |
.flags = ATA_FLAG_SATA, |
ada364e88 [PATCH] sata_nv: ... |
530 531 532 533 |
.pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_nf2_ops, |
959471936 libata: kill port... |
534 |
.private_data = NV_PI_PRIV(nv_nf2_interrupt, &nv_sht), |
ada364e88 [PATCH] sata_nv: ... |
535 536 537 |
}, /* ck804 */ { |
9cbe056f6 libata: remove AT... |
538 |
.flags = ATA_FLAG_SATA, |
ada364e88 [PATCH] sata_nv: ... |
539 540 541 542 |
.pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_ck804_ops, |
959471936 libata: kill port... |
543 |
.private_data = NV_PI_PRIV(nv_ck804_interrupt, &nv_sht), |
ada364e88 [PATCH] sata_nv: ... |
544 |
}, |
fbbb262d9 [PATCH] sata_nv A... |
545 546 |
/* ADMA */ { |
9cbe056f6 libata: remove AT... |
547 |
.flags = ATA_FLAG_SATA | ATA_FLAG_NCQ, |
fbbb262d9 [PATCH] sata_nv A... |
548 549 550 551 |
.pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_adma_ops, |
959471936 libata: kill port... |
552 |
.private_data = NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht), |
fbbb262d9 [PATCH] sata_nv A... |
553 |
}, |
2d775708b sata_nv: fix MCP5... |
554 555 |
/* MCP5x */ { |
9cbe056f6 libata: remove AT... |
556 |
.flags = ATA_FLAG_SATA, |
2d775708b sata_nv: fix MCP5... |
557 558 559 |
.pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, |
7f4774b38 sata_nv: use hard... |
560 |
.port_ops = &nv_generic_ops, |
2d775708b sata_nv: fix MCP5... |
561 562 |
.private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht), }, |
f140f0f12 [libata] sata_nv:... |
563 564 |
/* SWNCQ */ { |
9cbe056f6 libata: remove AT... |
565 |
.flags = ATA_FLAG_SATA | ATA_FLAG_NCQ, |
f140f0f12 [libata] sata_nv:... |
566 567 568 569 |
.pio_mask = NV_PIO_MASK, .mwdma_mask = NV_MWDMA_MASK, .udma_mask = NV_UDMA_MASK, .port_ops = &nv_swncq_ops, |
959471936 libata: kill port... |
570 |
.private_data = NV_PI_PRIV(nv_swncq_interrupt, &nv_swncq_sht), |
f140f0f12 [libata] sata_nv:... |
571 |
}, |
1da177e4c Linux-2.6.12-rc2 |
572 573 574 575 576 577 578 |
}; MODULE_AUTHOR("NVIDIA"); MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, nv_pci_tbl); MODULE_VERSION(DRV_VERSION); |
90ab5ee94 module_param: mak... |
579 |
static bool adma_enabled; |
c13aff321 ata:sata_nv - Cha... |
580 |
static bool swncq_enabled = true; |
90ab5ee94 module_param: mak... |
581 |
static bool msi_enabled; |
fbbb262d9 [PATCH] sata_nv A... |
582 |
|
2dec7555e [PATCH] sata_nv: ... |
583 584 |
static void nv_adma_register_mode(struct ata_port *ap) { |
2dec7555e [PATCH] sata_nv: ... |
585 |
struct nv_adma_port_priv *pp = ap->private_data; |
cdf56bcf1 sata_nv: add susp... |
586 |
void __iomem *mmio = pp->ctl_block; |
a2cfe81a5 sata_nv: wait for... |
587 588 |
u16 tmp, status; int count = 0; |
2dec7555e [PATCH] sata_nv: ... |
589 590 591 |
if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) return; |
a2cfe81a5 sata_nv: wait for... |
592 |
status = readw(mmio + NV_ADMA_STAT); |
2dcb407e6 [libata] checkpat... |
593 |
while (!(status & NV_ADMA_STAT_IDLE) && count < 20) { |
a2cfe81a5 sata_nv: wait for... |
594 595 596 597 |
ndelay(50); status = readw(mmio + NV_ADMA_STAT); count++; } |
2dcb407e6 [libata] checkpat... |
598 |
if (count == 20) |
a9a79dfec ata: Convert ata_... |
599 600 601 |
ata_port_warn(ap, "timeout waiting for ADMA IDLE, stat=0x%hx ", status); |
a2cfe81a5 sata_nv: wait for... |
602 |
|
2dec7555e [PATCH] sata_nv: ... |
603 604 |
tmp = readw(mmio + NV_ADMA_CTL); writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); |
a2cfe81a5 sata_nv: wait for... |
605 606 |
count = 0; status = readw(mmio + NV_ADMA_STAT); |
2dcb407e6 [libata] checkpat... |
607 |
while (!(status & NV_ADMA_STAT_LEGACY) && count < 20) { |
a2cfe81a5 sata_nv: wait for... |
608 609 610 611 |
ndelay(50); status = readw(mmio + NV_ADMA_STAT); count++; } |
2dcb407e6 [libata] checkpat... |
612 |
if (count == 20) |
a9a79dfec ata: Convert ata_... |
613 614 615 616 |
ata_port_warn(ap, "timeout waiting for ADMA LEGACY, stat=0x%hx ", status); |
a2cfe81a5 sata_nv: wait for... |
617 |
|
2dec7555e [PATCH] sata_nv: ... |
618 619 620 621 622 |
pp->flags |= NV_ADMA_PORT_REGISTER_MODE; } static void nv_adma_mode(struct ata_port *ap) { |
2dec7555e [PATCH] sata_nv: ... |
623 |
struct nv_adma_port_priv *pp = ap->private_data; |
cdf56bcf1 sata_nv: add susp... |
624 |
void __iomem *mmio = pp->ctl_block; |
a2cfe81a5 sata_nv: wait for... |
625 626 |
u16 tmp, status; int count = 0; |
2dec7555e [PATCH] sata_nv: ... |
627 628 629 |
if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) return; |
f20b16ff7 [libata] trim tra... |
630 |
|
2dec7555e [PATCH] sata_nv: ... |
631 632 633 634 |
WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE); tmp = readw(mmio + NV_ADMA_CTL); writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); |
a2cfe81a5 sata_nv: wait for... |
635 |
status = readw(mmio + NV_ADMA_STAT); |
2dcb407e6 [libata] checkpat... |
636 |
while (((status & NV_ADMA_STAT_LEGACY) || |
a2cfe81a5 sata_nv: wait for... |
637 638 639 640 641 |
!(status & NV_ADMA_STAT_IDLE)) && count < 20) { ndelay(50); status = readw(mmio + NV_ADMA_STAT); count++; } |
2dcb407e6 [libata] checkpat... |
642 |
if (count == 20) |
a9a79dfec ata: Convert ata_... |
643 |
ata_port_warn(ap, |
a2cfe81a5 sata_nv: wait for... |
644 645 646 |
"timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx ", status); |
2dec7555e [PATCH] sata_nv: ... |
647 648 |
pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE; } |
fbbb262d9 [PATCH] sata_nv A... |
649 650 651 |
static int nv_adma_slave_config(struct scsi_device *sdev) { struct ata_port *ap = ata_shost_to_port(sdev->host); |
2dec7555e [PATCH] sata_nv: ... |
652 |
struct nv_adma_port_priv *pp = ap->private_data; |
8959d300a sata_nv: fix ATAP... |
653 654 |
struct nv_adma_port_priv *port0, *port1; struct scsi_device *sdev0, *sdev1; |
2dec7555e [PATCH] sata_nv: ... |
655 |
struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
8959d300a sata_nv: fix ATAP... |
656 |
unsigned long segment_boundary, flags; |
fbbb262d9 [PATCH] sata_nv A... |
657 658 |
unsigned short sg_tablesize; int rc; |
2dec7555e [PATCH] sata_nv: ... |
659 660 |
int adma_enable; u32 current_reg, new_reg, config_mask; |
fbbb262d9 [PATCH] sata_nv A... |
661 662 663 664 665 666 |
rc = ata_scsi_slave_config(sdev); if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun) /* Not a proper libata device, ignore */ return rc; |
8959d300a sata_nv: fix ATAP... |
667 |
spin_lock_irqsave(ap->lock, flags); |
9af5c9c97 libata-link: intr... |
668 |
if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) { |
fbbb262d9 [PATCH] sata_nv A... |
669 670 671 672 673 674 675 |
/* * NVIDIA reports that ADMA mode does not support ATAPI commands. * Therefore ATAPI commands are sent through the legacy interface. * However, the legacy interface only supports 32-bit DMA. * Restrict DMA parameters as required by the legacy interface * when an ATAPI device is connected. */ |
fbbb262d9 [PATCH] sata_nv A... |
676 677 678 679 |
segment_boundary = ATA_DMA_BOUNDARY; /* Subtract 1 since an extra entry may be needed for padding, see libata-scsi.c */ sg_tablesize = LIBATA_MAX_PRD - 1; |
f20b16ff7 [libata] trim tra... |
680 |
|
2dec7555e [PATCH] sata_nv: ... |
681 682 683 684 |
/* Since the legacy DMA engine is in use, we need to disable ADMA on the port. */ adma_enable = 0; nv_adma_register_mode(ap); |
2dcb407e6 [libata] checkpat... |
685 |
} else { |
fbbb262d9 [PATCH] sata_nv A... |
686 687 |
segment_boundary = NV_ADMA_DMA_BOUNDARY; sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN; |
2dec7555e [PATCH] sata_nv: ... |
688 |
adma_enable = 1; |
fbbb262d9 [PATCH] sata_nv A... |
689 |
} |
f20b16ff7 [libata] trim tra... |
690 |
|
2dec7555e [PATCH] sata_nv: ... |
691 |
pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, ¤t_reg); |
2dcb407e6 [libata] checkpat... |
692 |
if (ap->port_no == 1) |
2dec7555e [PATCH] sata_nv: ... |
693 694 695 696 697 |
config_mask = NV_MCP_SATA_CFG_20_PORT1_EN | NV_MCP_SATA_CFG_20_PORT1_PWB_EN; else config_mask = NV_MCP_SATA_CFG_20_PORT0_EN | NV_MCP_SATA_CFG_20_PORT0_PWB_EN; |
f20b16ff7 [libata] trim tra... |
698 |
|
2dcb407e6 [libata] checkpat... |
699 |
if (adma_enable) { |
2dec7555e [PATCH] sata_nv: ... |
700 701 |
new_reg = current_reg | config_mask; pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE; |
2dcb407e6 [libata] checkpat... |
702 |
} else { |
2dec7555e [PATCH] sata_nv: ... |
703 704 705 |
new_reg = current_reg & ~config_mask; pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE; } |
f20b16ff7 [libata] trim tra... |
706 |
|
2dcb407e6 [libata] checkpat... |
707 |
if (current_reg != new_reg) |
2dec7555e [PATCH] sata_nv: ... |
708 |
pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg); |
f20b16ff7 [libata] trim tra... |
709 |
|
8959d300a sata_nv: fix ATAP... |
710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 |
port0 = ap->host->ports[0]->private_data; port1 = ap->host->ports[1]->private_data; sdev0 = ap->host->ports[0]->link.device[0].sdev; sdev1 = ap->host->ports[1]->link.device[0].sdev; if ((port0->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) || (port1->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)) { /** We have to set the DMA mask to 32-bit if either port is in ATAPI mode, since they are on the same PCI device which is used for DMA mapping. If we set the mask we also need to set the bounce limit on both ports to ensure that the block layer doesn't feed addresses that cause DMA mapping to choke. If either SCSI device is not allocated yet, it's OK since that port will discover its correct setting when it does get allocated. Note: Setting 32-bit mask should not fail. */ if (sdev0) blk_queue_bounce_limit(sdev0->request_queue, ATA_DMA_MASK); if (sdev1) blk_queue_bounce_limit(sdev1->request_queue, ATA_DMA_MASK); |
c54c719b5 ata: remove depre... |
731 |
dma_set_mask(&pdev->dev, ATA_DMA_MASK); |
8959d300a sata_nv: fix ATAP... |
732 733 |
} else { /** This shouldn't fail as it was set to this value before */ |
c54c719b5 ata: remove depre... |
734 |
dma_set_mask(&pdev->dev, pp->adma_dma_mask); |
8959d300a sata_nv: fix ATAP... |
735 736 737 738 739 740 741 |
if (sdev0) blk_queue_bounce_limit(sdev0->request_queue, pp->adma_dma_mask); if (sdev1) blk_queue_bounce_limit(sdev1->request_queue, pp->adma_dma_mask); } |
fbbb262d9 [PATCH] sata_nv A... |
742 |
blk_queue_segment_boundary(sdev->request_queue, segment_boundary); |
8a78362c4 block: Consolidat... |
743 |
blk_queue_max_segments(sdev->request_queue, sg_tablesize); |
a9a79dfec ata: Convert ata_... |
744 745 746 747 748 |
ata_port_info(ap, "DMA mask 0x%llX, segment boundary 0x%lX, hw segs %hu ", (unsigned long long)*ap->host->dev->dma_mask, segment_boundary, sg_tablesize); |
8959d300a sata_nv: fix ATAP... |
749 750 |
spin_unlock_irqrestore(ap->lock, flags); |
fbbb262d9 [PATCH] sata_nv A... |
751 752 |
return rc; } |
2dec7555e [PATCH] sata_nv: ... |
753 754 755 756 757 |
static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc) { struct nv_adma_port_priv *pp = qc->ap->private_data; return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE); } |
f2fb344be sata_nv: don't re... |
758 759 |
static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf) { |
3f3debdbf sata_nv: don't us... |
760 761 762 763 764 765 766 |
/* Other than when internal or pass-through commands are executed, the only time this function will be called in ADMA mode will be if a command fails. In the failure case we don't care about going into register mode with ADMA commands pending, as the commands will all shortly be aborted anyway. We assume that NCQ commands are not issued via passthrough, which is the only way that switching into ADMA mode could abort outstanding commands. */ |
f2fb344be sata_nv: don't re... |
767 |
nv_adma_register_mode(ap); |
9363c3825 libata: rename SF... |
768 |
ata_sff_tf_read(ap, tf); |
f2fb344be sata_nv: don't re... |
769 |
} |
2dec7555e [PATCH] sata_nv: ... |
770 |
static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb) |
fbbb262d9 [PATCH] sata_nv A... |
771 772 |
{ unsigned int idx = 0; |
2dcb407e6 [libata] checkpat... |
773 |
if (tf->flags & ATA_TFLAG_ISADDR) { |
ac3d6b869 sata_nv: Cleanup ... |
774 775 776 777 778 779 780 781 782 |
if (tf->flags & ATA_TFLAG_LBA48) { cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB); cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect); cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal); cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam); cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah); cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature); } else cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB); |
a84471fe2 [libata] Trim tra... |
783 |
|
ac3d6b869 sata_nv: Cleanup ... |
784 785 786 787 |
cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect); cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal); cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam); cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah); |
fbbb262d9 [PATCH] sata_nv A... |
788 |
} |
a84471fe2 [libata] Trim tra... |
789 |
|
2dcb407e6 [libata] checkpat... |
790 |
if (tf->flags & ATA_TFLAG_DEVICE) |
ac3d6b869 sata_nv: Cleanup ... |
791 |
cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device); |
fbbb262d9 [PATCH] sata_nv A... |
792 793 |
cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND); |
a84471fe2 [libata] Trim tra... |
794 |
|
2dcb407e6 [libata] checkpat... |
795 |
while (idx < 12) |
ac3d6b869 sata_nv: Cleanup ... |
796 |
cpb[idx++] = cpu_to_le16(IGN); |
fbbb262d9 [PATCH] sata_nv A... |
797 798 799 |
return idx; } |
5bd28a4b6 sata_nv: cleanup ... |
800 |
static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err) |
fbbb262d9 [PATCH] sata_nv A... |
801 802 |
{ struct nv_adma_port_priv *pp = ap->private_data; |
2dec7555e [PATCH] sata_nv: ... |
803 |
u8 flags = pp->cpb[cpb_num].resp_flags; |
fbbb262d9 [PATCH] sata_nv A... |
804 805 806 |
VPRINTK("CPB %d, flags=0x%x ", cpb_num, flags); |
5bd28a4b6 sata_nv: cleanup ... |
807 808 809 810 |
if (unlikely((force_err || flags & (NV_CPB_RESP_ATA_ERR | NV_CPB_RESP_CMD_ERR | NV_CPB_RESP_CPB_ERR)))) { |
9af5c9c97 libata-link: intr... |
811 |
struct ata_eh_info *ehi = &ap->link.eh_info; |
5bd28a4b6 sata_nv: cleanup ... |
812 813 814 |
int freeze = 0; ata_ehi_clear_desc(ehi); |
2dcb407e6 [libata] checkpat... |
815 |
__ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags); |
5bd28a4b6 sata_nv: cleanup ... |
816 |
if (flags & NV_CPB_RESP_ATA_ERR) { |
b64bbc39f libata: improve E... |
817 |
ata_ehi_push_desc(ehi, "ATA error"); |
5bd28a4b6 sata_nv: cleanup ... |
818 819 |
ehi->err_mask |= AC_ERR_DEV; } else if (flags & NV_CPB_RESP_CMD_ERR) { |
b64bbc39f libata: improve E... |
820 |
ata_ehi_push_desc(ehi, "CMD error"); |
5bd28a4b6 sata_nv: cleanup ... |
821 822 |
ehi->err_mask |= AC_ERR_DEV; } else if (flags & NV_CPB_RESP_CPB_ERR) { |
b64bbc39f libata: improve E... |
823 |
ata_ehi_push_desc(ehi, "CPB error"); |
5bd28a4b6 sata_nv: cleanup ... |
824 825 826 827 |
ehi->err_mask |= AC_ERR_SYSTEM; freeze = 1; } else { /* notifier error, but no error in CPB flags? */ |
b64bbc39f libata: improve E... |
828 |
ata_ehi_push_desc(ehi, "unknown"); |
5bd28a4b6 sata_nv: cleanup ... |
829 830 831 832 833 834 835 836 |
ehi->err_mask |= AC_ERR_OTHER; freeze = 1; } /* Kill all commands. EH will determine what actually failed. */ if (freeze) ata_port_freeze(ap); else ata_port_abort(ap); |
1aadf5c3b libata: always us... |
837 |
return -1; |
fbbb262d9 [PATCH] sata_nv A... |
838 |
} |
5bd28a4b6 sata_nv: cleanup ... |
839 |
|
1aadf5c3b libata: always us... |
840 841 |
if (likely(flags & NV_CPB_RESP_DONE)) return 1; |
5bd28a4b6 sata_nv: cleanup ... |
842 |
return 0; |
fbbb262d9 [PATCH] sata_nv A... |
843 |
} |
2dec7555e [PATCH] sata_nv: ... |
844 845 |
static int nv_host_intr(struct ata_port *ap, u8 irq_stat) { |
9af5c9c97 libata-link: intr... |
846 |
struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); |
2dec7555e [PATCH] sata_nv: ... |
847 848 849 850 851 852 853 854 855 856 857 858 859 |
/* freeze if hotplugged */ if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) { ata_port_freeze(ap); return 1; } /* bail out if not our interrupt */ if (!(irq_stat & NV_INT_DEV)) return 0; /* DEV interrupt w/ no active qc? */ if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { |
9363c3825 libata: rename SF... |
860 |
ata_sff_check_status(ap); |
2dec7555e [PATCH] sata_nv: ... |
861 862 863 864 |
return 1; } /* handle interrupt */ |
c3b288942 libata-sff: separ... |
865 |
return ata_bmdma_port_intr(ap, qc); |
2dec7555e [PATCH] sata_nv: ... |
866 |
} |
fbbb262d9 [PATCH] sata_nv A... |
867 868 869 870 |
static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance) { struct ata_host *host = dev_instance; int i, handled = 0; |
2dec7555e [PATCH] sata_nv: ... |
871 |
u32 notifier_clears[2]; |
fbbb262d9 [PATCH] sata_nv A... |
872 873 874 875 876 |
spin_lock(&host->lock); for (i = 0; i < host->n_ports; i++) { struct ata_port *ap = host->ports[i]; |
3e4ec3443 libata: kill ATA_... |
877 878 879 880 881 |
struct nv_adma_port_priv *pp = ap->private_data; void __iomem *mmio = pp->ctl_block; u16 status; u32 gen_ctl; u32 notifier, notifier_error; |
2dec7555e [PATCH] sata_nv: ... |
882 |
notifier_clears[i] = 0; |
fbbb262d9 [PATCH] sata_nv A... |
883 |
|
3e4ec3443 libata: kill ATA_... |
884 885 886 887 888 889 890 |
/* if ADMA is disabled, use standard ata interrupt handler */ if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) { u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804) >> (NV_INT_PORT_SHIFT * i); handled += nv_host_intr(ap, irq_stat); continue; } |
fbbb262d9 [PATCH] sata_nv A... |
891 |
|
3e4ec3443 libata: kill ATA_... |
892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 |
/* if in ATA register mode, check for standard interrupts */ if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) { u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804) >> (NV_INT_PORT_SHIFT * i); if (ata_tag_valid(ap->link.active_tag)) /** NV_INT_DEV indication seems unreliable at times at least in ADMA mode. Force it on always when a command is active, to prevent losing interrupts. */ irq_stat |= NV_INT_DEV; handled += nv_host_intr(ap, irq_stat); } notifier = readl(mmio + NV_ADMA_NOTIFIER); notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); notifier_clears[i] = notifier | notifier_error; gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL); if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier && !notifier_error) /* Nothing to do */ continue; status = readw(mmio + NV_ADMA_STAT); /* * Clear status. Ensure the controller sees the * clearing before we start looking at any of the CPB * statuses, so that any CPB completions after this * point in the handler will raise another interrupt. */ writew(status, mmio + NV_ADMA_STAT); readw(mmio + NV_ADMA_STAT); /* flush posted write */ rmb(); |
fbbb262d9 [PATCH] sata_nv A... |
927 |
|
3e4ec3443 libata: kill ATA_... |
928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 |
handled++; /* irq handled if we got here */ /* freeze if hotplugged or controller error */ if (unlikely(status & (NV_ADMA_STAT_HOTPLUG | NV_ADMA_STAT_HOTUNPLUG | NV_ADMA_STAT_TIMEOUT | NV_ADMA_STAT_SERROR))) { struct ata_eh_info *ehi = &ap->link.eh_info; ata_ehi_clear_desc(ehi); __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status); if (status & NV_ADMA_STAT_TIMEOUT) { ehi->err_mask |= AC_ERR_SYSTEM; ata_ehi_push_desc(ehi, "timeout"); } else if (status & NV_ADMA_STAT_HOTPLUG) { ata_ehi_hotplugged(ehi); ata_ehi_push_desc(ehi, "hotplug"); } else if (status & NV_ADMA_STAT_HOTUNPLUG) { ata_ehi_hotplugged(ehi); ata_ehi_push_desc(ehi, "hot unplug"); } else if (status & NV_ADMA_STAT_SERROR) { /* let EH analyze SError and figure out cause */ ata_ehi_push_desc(ehi, "SError"); } else ata_ehi_push_desc(ehi, "unknown"); ata_port_freeze(ap); continue; } if (status & (NV_ADMA_STAT_DONE | NV_ADMA_STAT_CPBERR | NV_ADMA_STAT_CMD_COMPLETE)) { u32 check_commands = notifier_clears[i]; |
1aadf5c3b libata: always us... |
961 |
u32 done_mask = 0; |
752e386c2 sata_fsl,mv,nv: p... |
962 |
int pos, rc; |
3e4ec3443 libata: kill ATA_... |
963 964 965 966 967 968 969 970 |
if (status & NV_ADMA_STAT_CPBERR) { /* check all active commands */ if (ata_tag_valid(ap->link.active_tag)) check_commands = 1 << ap->link.active_tag; else check_commands = ap->link.sactive; |
fbbb262d9 [PATCH] sata_nv A... |
971 |
} |
3e4ec3443 libata: kill ATA_... |
972 |
/* check CPBs for completed commands */ |
752e386c2 sata_fsl,mv,nv: p... |
973 |
while ((pos = ffs(check_commands))) { |
3e4ec3443 libata: kill ATA_... |
974 |
pos--; |
752e386c2 sata_fsl,mv,nv: p... |
975 |
rc = nv_adma_check_cpb(ap, pos, |
5796d1c4c [libata] Address ... |
976 |
notifier_error & (1 << pos)); |
1aadf5c3b libata: always us... |
977 978 979 |
if (rc > 0) done_mask |= 1 << pos; else if (unlikely(rc < 0)) |
752e386c2 sata_fsl,mv,nv: p... |
980 |
check_commands = 0; |
3e4ec3443 libata: kill ATA_... |
981 |
check_commands &= ~(1 << pos); |
fbbb262d9 [PATCH] sata_nv A... |
982 |
} |
1aadf5c3b libata: always us... |
983 |
ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); |
fbbb262d9 [PATCH] sata_nv A... |
984 985 |
} } |
f20b16ff7 [libata] trim tra... |
986 |
|
b447916e2 [libata] fix 'if(... |
987 |
if (notifier_clears[0] || notifier_clears[1]) { |
2dec7555e [PATCH] sata_nv: ... |
988 989 |
/* Note: Both notifier clear registers must be written if either is set, even if one is zero, according to NVIDIA. */ |
cdf56bcf1 sata_nv: add susp... |
990 991 992 993 |
struct nv_adma_port_priv *pp = host->ports[0]->private_data; writel(notifier_clears[0], pp->notifier_clear_block); pp = host->ports[1]->private_data; writel(notifier_clears[1], pp->notifier_clear_block); |
2dec7555e [PATCH] sata_nv: ... |
994 |
} |
fbbb262d9 [PATCH] sata_nv A... |
995 996 997 998 999 |
spin_unlock(&host->lock); return IRQ_RETVAL(handled); } |
53014e252 sata_nv: fix ADMA... |
1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 |
static void nv_adma_freeze(struct ata_port *ap) { struct nv_adma_port_priv *pp = ap->private_data; void __iomem *mmio = pp->ctl_block; u16 tmp; nv_ck804_freeze(ap); if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) return; /* clear any outstanding CK804 notifications */ |
2dcb407e6 [libata] checkpat... |
1012 |
writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT), |
53014e252 sata_nv: fix ADMA... |
1013 1014 1015 1016 |
ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); /* Disable interrupt */ tmp = readw(mmio + NV_ADMA_CTL); |
2dcb407e6 [libata] checkpat... |
1017 |
writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN), |
53014e252 sata_nv: fix ADMA... |
1018 |
mmio + NV_ADMA_CTL); |
5796d1c4c [libata] Address ... |
1019 |
readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
53014e252 sata_nv: fix ADMA... |
1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 |
} static void nv_adma_thaw(struct ata_port *ap) { struct nv_adma_port_priv *pp = ap->private_data; void __iomem *mmio = pp->ctl_block; u16 tmp; nv_ck804_thaw(ap); if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) return; /* Enable interrupt */ tmp = readw(mmio + NV_ADMA_CTL); |
2dcb407e6 [libata] checkpat... |
1035 |
writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN), |
53014e252 sata_nv: fix ADMA... |
1036 |
mmio + NV_ADMA_CTL); |
5796d1c4c [libata] Address ... |
1037 |
readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
53014e252 sata_nv: fix ADMA... |
1038 |
} |
fbbb262d9 [PATCH] sata_nv A... |
1039 1040 |
static void nv_adma_irq_clear(struct ata_port *ap) { |
cdf56bcf1 sata_nv: add susp... |
1041 1042 |
struct nv_adma_port_priv *pp = ap->private_data; void __iomem *mmio = pp->ctl_block; |
53014e252 sata_nv: fix ADMA... |
1043 |
u32 notifier_clears[2]; |
fbbb262d9 [PATCH] sata_nv A... |
1044 |
|
53014e252 sata_nv: fix ADMA... |
1045 |
if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) { |
37f65b8bc libata-sff: ata_s... |
1046 |
ata_bmdma_irq_clear(ap); |
53014e252 sata_nv: fix ADMA... |
1047 1048 1049 1050 |
return; } /* clear any outstanding CK804 notifications */ |
2dcb407e6 [libata] checkpat... |
1051 |
writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT), |
53014e252 sata_nv: fix ADMA... |
1052 |
ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); |
fbbb262d9 [PATCH] sata_nv A... |
1053 |
|
53014e252 sata_nv: fix ADMA... |
1054 1055 |
/* clear ADMA status */ writew(0xffff, mmio + NV_ADMA_STAT); |
a617c09f6 libata: Trim trai... |
1056 |
|
53014e252 sata_nv: fix ADMA... |
1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 |
/* clear notifiers - note both ports need to be written with something even though we are only clearing on one */ if (ap->port_no == 0) { notifier_clears[0] = 0xFFFFFFFF; notifier_clears[1] = 0; } else { notifier_clears[0] = 0; notifier_clears[1] = 0xFFFFFFFF; } pp = ap->host->ports[0]->private_data; writel(notifier_clears[0], pp->notifier_clear_block); pp = ap->host->ports[1]->private_data; writel(notifier_clears[1], pp->notifier_clear_block); |
fbbb262d9 [PATCH] sata_nv A... |
1070 |
} |
f5ecac2d8 sata_nv: kill old... |
1071 |
static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc) |
fbbb262d9 [PATCH] sata_nv A... |
1072 |
{ |
f5ecac2d8 sata_nv: kill old... |
1073 |
struct nv_adma_port_priv *pp = qc->ap->private_data; |
fbbb262d9 [PATCH] sata_nv A... |
1074 |
|
b447916e2 [libata] fix 'if(... |
1075 |
if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) |
fe06e5f9b libata-sff: separ... |
1076 |
ata_bmdma_post_internal_cmd(qc); |
fbbb262d9 [PATCH] sata_nv A... |
1077 1078 1079 1080 1081 1082 1083 1084 1085 |
} static int nv_adma_port_start(struct ata_port *ap) { struct device *dev = ap->host->dev; struct nv_adma_port_priv *pp; int rc; void *mem; dma_addr_t mem_dma; |
cdf56bcf1 sata_nv: add susp... |
1086 |
void __iomem *mmio; |
8959d300a sata_nv: fix ATAP... |
1087 |
struct pci_dev *pdev = to_pci_dev(dev); |
fbbb262d9 [PATCH] sata_nv A... |
1088 1089 1090 1091 |
u16 tmp; VPRINTK("ENTER "); |
8959d300a sata_nv: fix ATAP... |
1092 1093 |
/* Ensure DMA mask is set to 32-bit before allocating legacy PRD and pad buffers */ |
c54c719b5 ata: remove depre... |
1094 |
rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
8959d300a sata_nv: fix ATAP... |
1095 1096 |
if (rc) return rc; |
c54c719b5 ata: remove depre... |
1097 |
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
8959d300a sata_nv: fix ATAP... |
1098 1099 |
if (rc) return rc; |
c7087652e libata-sff: clean... |
1100 1101 |
/* we might fallback to bmdma, allocate bmdma resources */ rc = ata_bmdma_port_start(ap); |
fbbb262d9 [PATCH] sata_nv A... |
1102 1103 |
if (rc) return rc; |
24dc5f33e libata: update li... |
1104 1105 1106 |
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); if (!pp) return -ENOMEM; |
fbbb262d9 [PATCH] sata_nv A... |
1107 |
|
0d5ff5667 libata: convert t... |
1108 |
mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT + |
cdf56bcf1 sata_nv: add susp... |
1109 1110 |
ap->port_no * NV_ADMA_PORT_SIZE; pp->ctl_block = mmio; |
0d5ff5667 libata: convert t... |
1111 |
pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN; |
cdf56bcf1 sata_nv: add susp... |
1112 1113 |
pp->notifier_clear_block = pp->gen_block + NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no); |
8959d300a sata_nv: fix ATAP... |
1114 1115 1116 1117 1118 |
/* Now that the legacy PRD and padding buffer are allocated we can safely raise the DMA mask to allocate the CPB/APRD table. These are allowed to fail since we store the value that ends up being used to set as the bounce limit in slave_config later if needed. */ |
c54c719b5 ata: remove depre... |
1119 1120 |
dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
8959d300a sata_nv: fix ATAP... |
1121 |
pp->adma_dma_mask = *dev->dma_mask; |
24dc5f33e libata: update li... |
1122 1123 1124 1125 |
mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); if (!mem) return -ENOMEM; |
fbbb262d9 [PATCH] sata_nv A... |
1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 |
memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ); /* * First item in chunk of DMA memory: * 128-byte command parameter block (CPB) * one for each command tag */ pp->cpb = mem; pp->cpb_dma = mem_dma; writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW); |
5796d1c4c [libata] Address ... |
1137 |
writel((mem_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH); |
fbbb262d9 [PATCH] sata_nv A... |
1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 |
mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ; mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ; /* * Second item: block of ADMA_SGTBL_LEN s/g entries */ pp->aprd = mem; pp->aprd_dma = mem_dma; ap->private_data = pp; /* clear any outstanding interrupt conditions */ writew(0xffff, mmio + NV_ADMA_STAT); /* initialize port variables */ pp->flags = NV_ADMA_PORT_REGISTER_MODE; /* clear CPB fetch count */ writew(0, mmio + NV_ADMA_CPB_COUNT); |
cdf56bcf1 sata_nv: add susp... |
1158 |
/* clear GO for register mode, enable interrupt */ |
fbbb262d9 [PATCH] sata_nv A... |
1159 |
tmp = readw(mmio + NV_ADMA_CTL); |
5796d1c4c [libata] Address ... |
1160 1161 |
writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL); |
fbbb262d9 [PATCH] sata_nv A... |
1162 1163 1164 |
tmp = readw(mmio + NV_ADMA_CTL); writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
5796d1c4c [libata] Address ... |
1165 |
readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
fbbb262d9 [PATCH] sata_nv A... |
1166 1167 |
udelay(1); writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
5796d1c4c [libata] Address ... |
1168 |
readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
fbbb262d9 [PATCH] sata_nv A... |
1169 1170 |
return 0; |
fbbb262d9 [PATCH] sata_nv A... |
1171 1172 1173 1174 |
} static void nv_adma_port_stop(struct ata_port *ap) { |
fbbb262d9 [PATCH] sata_nv A... |
1175 |
struct nv_adma_port_priv *pp = ap->private_data; |
cdf56bcf1 sata_nv: add susp... |
1176 |
void __iomem *mmio = pp->ctl_block; |
fbbb262d9 [PATCH] sata_nv A... |
1177 1178 1179 |
VPRINTK("ENTER "); |
fbbb262d9 [PATCH] sata_nv A... |
1180 |
writew(0, mmio + NV_ADMA_CTL); |
fbbb262d9 [PATCH] sata_nv A... |
1181 |
} |
438ac6d5e libata: add missi... |
1182 |
#ifdef CONFIG_PM |
cdf56bcf1 sata_nv: add susp... |
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 |
static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg) { struct nv_adma_port_priv *pp = ap->private_data; void __iomem *mmio = pp->ctl_block; /* Go to register mode - clears GO */ nv_adma_register_mode(ap); /* clear CPB fetch count */ writew(0, mmio + NV_ADMA_CPB_COUNT); /* disable interrupt, shut down port */ writew(0, mmio + NV_ADMA_CTL); return 0; } static int nv_adma_port_resume(struct ata_port *ap) { struct nv_adma_port_priv *pp = ap->private_data; void __iomem *mmio = pp->ctl_block; u16 tmp; /* set CPB block location */ writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW); |
5796d1c4c [libata] Address ... |
1208 |
writel((pp->cpb_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH); |
cdf56bcf1 sata_nv: add susp... |
1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 |
/* clear any outstanding interrupt conditions */ writew(0xffff, mmio + NV_ADMA_STAT); /* initialize port variables */ pp->flags |= NV_ADMA_PORT_REGISTER_MODE; /* clear CPB fetch count */ writew(0, mmio + NV_ADMA_CPB_COUNT); /* clear GO for register mode, enable interrupt */ tmp = readw(mmio + NV_ADMA_CTL); |
5796d1c4c [libata] Address ... |
1221 1222 |
writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL); |
cdf56bcf1 sata_nv: add susp... |
1223 1224 1225 |
tmp = readw(mmio + NV_ADMA_CTL); writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
5796d1c4c [libata] Address ... |
1226 |
readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
cdf56bcf1 sata_nv: add susp... |
1227 1228 |
udelay(1); writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
5796d1c4c [libata] Address ... |
1229 |
readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
cdf56bcf1 sata_nv: add susp... |
1230 1231 1232 |
return 0; } |
438ac6d5e libata: add missi... |
1233 |
#endif |
fbbb262d9 [PATCH] sata_nv A... |
1234 |
|
9a829ccfc libata: convert a... |
1235 |
static void nv_adma_setup_port(struct ata_port *ap) |
fbbb262d9 [PATCH] sata_nv A... |
1236 |
{ |
9a829ccfc libata: convert a... |
1237 1238 |
void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; struct ata_ioports *ioport = &ap->ioaddr; |
fbbb262d9 [PATCH] sata_nv A... |
1239 1240 1241 |
VPRINTK("ENTER "); |
9a829ccfc libata: convert a... |
1242 |
mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE; |
fbbb262d9 [PATCH] sata_nv A... |
1243 |
|
0d5ff5667 libata: convert t... |
1244 1245 |
ioport->cmd_addr = mmio; ioport->data_addr = mmio + (ATA_REG_DATA * 4); |
fbbb262d9 [PATCH] sata_nv A... |
1246 |
ioport->error_addr = |
0d5ff5667 libata: convert t... |
1247 1248 1249 1250 1251 1252 |
ioport->feature_addr = mmio + (ATA_REG_ERR * 4); ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4); ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4); ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4); ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4); ioport->device_addr = mmio + (ATA_REG_DEVICE * 4); |
fbbb262d9 [PATCH] sata_nv A... |
1253 |
ioport->status_addr = |
0d5ff5667 libata: convert t... |
1254 |
ioport->command_addr = mmio + (ATA_REG_STATUS * 4); |
fbbb262d9 [PATCH] sata_nv A... |
1255 |
ioport->altstatus_addr = |
0d5ff5667 libata: convert t... |
1256 |
ioport->ctl_addr = mmio + 0x20; |
fbbb262d9 [PATCH] sata_nv A... |
1257 |
} |
9a829ccfc libata: convert a... |
1258 |
static int nv_adma_host_init(struct ata_host *host) |
fbbb262d9 [PATCH] sata_nv A... |
1259 |
{ |
9a829ccfc libata: convert a... |
1260 |
struct pci_dev *pdev = to_pci_dev(host->dev); |
fbbb262d9 [PATCH] sata_nv A... |
1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 |
unsigned int i; u32 tmp32; VPRINTK("ENTER "); /* enable ADMA on the ports */ pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN | NV_MCP_SATA_CFG_20_PORT0_PWB_EN | NV_MCP_SATA_CFG_20_PORT1_EN | NV_MCP_SATA_CFG_20_PORT1_PWB_EN; pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); |
9a829ccfc libata: convert a... |
1275 1276 |
for (i = 0; i < host->n_ports; i++) nv_adma_setup_port(host->ports[i]); |
fbbb262d9 [PATCH] sata_nv A... |
1277 |
|
fbbb262d9 [PATCH] sata_nv A... |
1278 1279 1280 1281 1282 1283 1284 1285 |
return 0; } static void nv_adma_fill_aprd(struct ata_queued_cmd *qc, struct scatterlist *sg, int idx, struct nv_adma_prd *aprd) { |
41949ed5c sata_nv: cleanup ... |
1286 |
u8 flags = 0; |
fbbb262d9 [PATCH] sata_nv A... |
1287 1288 1289 1290 1291 1292 1293 1294 1295 |
if (qc->tf.flags & ATA_TFLAG_WRITE) flags |= NV_APRD_WRITE; if (idx == qc->n_elem - 1) flags |= NV_APRD_END; else if (idx != 4) flags |= NV_APRD_CONT; aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg))); aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */ |
2dec7555e [PATCH] sata_nv: ... |
1296 |
aprd->flags = flags; |
41949ed5c sata_nv: cleanup ... |
1297 |
aprd->packet_len = 0; |
fbbb262d9 [PATCH] sata_nv A... |
1298 1299 1300 1301 1302 |
} static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb) { struct nv_adma_port_priv *pp = qc->ap->private_data; |
fbbb262d9 [PATCH] sata_nv A... |
1303 1304 |
struct nv_adma_prd *aprd; struct scatterlist *sg; |
ff2aeb1eb libata: convert t... |
1305 |
unsigned int si; |
fbbb262d9 [PATCH] sata_nv A... |
1306 1307 1308 |
VPRINTK("ENTER "); |
ff2aeb1eb libata: convert t... |
1309 1310 1311 1312 |
for_each_sg(qc->sg, sg, qc->n_elem, si) { aprd = (si < 5) ? &cpb->aprd[si] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)]; nv_adma_fill_aprd(qc, sg, si, aprd); |
fbbb262d9 [PATCH] sata_nv A... |
1313 |
} |
ff2aeb1eb libata: convert t... |
1314 |
if (si > 5) |
fbbb262d9 [PATCH] sata_nv A... |
1315 |
cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag))); |
41949ed5c sata_nv: cleanup ... |
1316 1317 |
else cpb->next_aprd = cpu_to_le64(0); |
fbbb262d9 [PATCH] sata_nv A... |
1318 |
} |
382a6652e sata_nv: use ADMA... |
1319 1320 1321 1322 1323 |
static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc) { struct nv_adma_port_priv *pp = qc->ap->private_data; /* ADMA engine can only be used for non-ATAPI DMA commands, |
3f3debdbf sata_nv: don't us... |
1324 |
or interrupt-driven no-data commands. */ |
b447916e2 [libata] fix 'if(... |
1325 |
if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) || |
3f3debdbf sata_nv: don't us... |
1326 |
(qc->tf.flags & ATA_TFLAG_POLLING)) |
382a6652e sata_nv: use ADMA... |
1327 |
return 1; |
b447916e2 [libata] fix 'if(... |
1328 |
if ((qc->flags & ATA_QCFLAG_DMAMAP) || |
382a6652e sata_nv: use ADMA... |
1329 1330 1331 1332 1333 |
(qc->tf.protocol == ATA_PROT_NODATA)) return 0; return 1; } |
fbbb262d9 [PATCH] sata_nv A... |
1334 1335 1336 1337 1338 |
static void nv_adma_qc_prep(struct ata_queued_cmd *qc) { struct nv_adma_port_priv *pp = qc->ap->private_data; struct nv_adma_cpb *cpb = &pp->cpb[qc->tag]; u8 ctl_flags = NV_CPB_CTL_CPB_VALID | |
fbbb262d9 [PATCH] sata_nv A... |
1339 |
NV_CPB_CTL_IEN; |
382a6652e sata_nv: use ADMA... |
1340 |
if (nv_adma_use_reg_mode(qc)) { |
3f3debdbf sata_nv: don't us... |
1341 1342 |
BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) && (qc->flags & ATA_QCFLAG_DMAMAP)); |
2dec7555e [PATCH] sata_nv: ... |
1343 |
nv_adma_register_mode(qc->ap); |
f47451c45 libata-sff: ata_s... |
1344 |
ata_bmdma_qc_prep(qc); |
fbbb262d9 [PATCH] sata_nv A... |
1345 1346 |
return; } |
41949ed5c sata_nv: cleanup ... |
1347 1348 1349 1350 |
cpb->resp_flags = NV_CPB_RESP_DONE; wmb(); cpb->ctl_flags = 0; wmb(); |
fbbb262d9 [PATCH] sata_nv A... |
1351 1352 1353 1354 1355 1356 1357 1358 |
cpb->len = 3; cpb->tag = qc->tag; cpb->next_cpb_idx = 0; /* turn on NCQ flags for NCQ commands */ if (qc->tf.protocol == ATA_PROT_NCQ) ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA; |
cdf56bcf1 sata_nv: add susp... |
1359 1360 |
VPRINTK("qc->flags = 0x%lx ", qc->flags); |
fbbb262d9 [PATCH] sata_nv A... |
1361 |
nv_adma_tf_to_cpb(&qc->tf, cpb->tf); |
b447916e2 [libata] fix 'if(... |
1362 |
if (qc->flags & ATA_QCFLAG_DMAMAP) { |
382a6652e sata_nv: use ADMA... |
1363 1364 1365 1366 |
nv_adma_fill_sg(qc, cpb); ctl_flags |= NV_CPB_CTL_APRD_VALID; } else memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5); |
fbbb262d9 [PATCH] sata_nv A... |
1367 |
|
5796d1c4c [libata] Address ... |
1368 1369 |
/* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are finished filling in all of the contents */ |
fbbb262d9 [PATCH] sata_nv A... |
1370 1371 |
wmb(); cpb->ctl_flags = ctl_flags; |
41949ed5c sata_nv: cleanup ... |
1372 1373 |
wmb(); cpb->resp_flags = 0; |
fbbb262d9 [PATCH] sata_nv A... |
1374 1375 1376 1377 |
} static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc) { |
2dec7555e [PATCH] sata_nv: ... |
1378 |
struct nv_adma_port_priv *pp = qc->ap->private_data; |
cdf56bcf1 sata_nv: add susp... |
1379 |
void __iomem *mmio = pp->ctl_block; |
5e5c74a5e sata_nv: delay on... |
1380 |
int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ); |
fbbb262d9 [PATCH] sata_nv A... |
1381 1382 1383 |
VPRINTK("ENTER "); |
3f3debdbf sata_nv: don't us... |
1384 1385 1386 1387 1388 |
/* We can't handle result taskfile with NCQ commands, since retrieving the taskfile switches us out of ADMA mode and would abort existing commands. */ if (unlikely(qc->tf.protocol == ATA_PROT_NCQ && (qc->flags & ATA_QCFLAG_RESULT_TF))) { |
a9a79dfec ata: Convert ata_... |
1389 1390 |
ata_dev_err(qc->dev, "NCQ w/ RESULT_TF not allowed "); |
3f3debdbf sata_nv: don't us... |
1391 1392 |
return AC_ERR_SYSTEM; } |
382a6652e sata_nv: use ADMA... |
1393 |
if (nv_adma_use_reg_mode(qc)) { |
fbbb262d9 [PATCH] sata_nv A... |
1394 |
/* use ATA register mode */ |
382a6652e sata_nv: use ADMA... |
1395 1396 |
VPRINTK("using ATA register mode: 0x%lx ", qc->flags); |
3f3debdbf sata_nv: don't us... |
1397 1398 |
BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) && (qc->flags & ATA_QCFLAG_DMAMAP)); |
fbbb262d9 [PATCH] sata_nv A... |
1399 |
nv_adma_register_mode(qc->ap); |
360ff7833 libata-sff: separ... |
1400 |
return ata_bmdma_qc_issue(qc); |
fbbb262d9 [PATCH] sata_nv A... |
1401 1402 1403 1404 1405 1406 |
} else nv_adma_mode(qc->ap); /* write append register, command tag in lower 8 bits and (number of cpbs to append -1) in top 8 bits */ wmb(); |
5e5c74a5e sata_nv: delay on... |
1407 |
|
b447916e2 [libata] fix 'if(... |
1408 |
if (curr_ncq != pp->last_issue_ncq) { |
5796d1c4c [libata] Address ... |
1409 1410 |
/* Seems to need some delay before switching between NCQ and non-NCQ commands, else we get command timeouts and such. */ |
5e5c74a5e sata_nv: delay on... |
1411 1412 1413 |
udelay(20); pp->last_issue_ncq = curr_ncq; } |
fbbb262d9 [PATCH] sata_nv A... |
1414 |
writew(qc->tag, mmio + NV_ADMA_APPEND); |
5796d1c4c [libata] Address ... |
1415 1416 |
DPRINTK("Issued tag %u ", qc->tag); |
fbbb262d9 [PATCH] sata_nv A... |
1417 1418 1419 |
return 0; } |
7d12e780e IRQ: Maintain reg... |
1420 |
static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance) |
1da177e4c Linux-2.6.12-rc2 |
1421 |
{ |
cca3974e4 libata: Grand ren... |
1422 |
struct ata_host *host = dev_instance; |
1da177e4c Linux-2.6.12-rc2 |
1423 1424 1425 |
unsigned int i; unsigned int handled = 0; unsigned long flags; |
cca3974e4 libata: Grand ren... |
1426 |
spin_lock_irqsave(&host->lock, flags); |
1da177e4c Linux-2.6.12-rc2 |
1427 |
|
cca3974e4 libata: Grand ren... |
1428 |
for (i = 0; i < host->n_ports; i++) { |
3e4ec3443 libata: kill ATA_... |
1429 1430 |
struct ata_port *ap = host->ports[i]; struct ata_queued_cmd *qc; |
1da177e4c Linux-2.6.12-rc2 |
1431 |
|
3e4ec3443 libata: kill ATA_... |
1432 1433 |
qc = ata_qc_from_tag(ap, ap->link.active_tag); if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
c3b288942 libata-sff: separ... |
1434 |
handled += ata_bmdma_port_intr(ap, qc); |
3e4ec3443 libata: kill ATA_... |
1435 1436 1437 1438 1439 1440 1441 |
} else { /* * No request pending? Clear interrupt status * anyway, in case there's one pending. */ ap->ops->sff_check_status(ap); } |
1da177e4c Linux-2.6.12-rc2 |
1442 |
} |
cca3974e4 libata: Grand ren... |
1443 |
spin_unlock_irqrestore(&host->lock, flags); |
1da177e4c Linux-2.6.12-rc2 |
1444 1445 1446 |
return IRQ_RETVAL(handled); } |
cca3974e4 libata: Grand ren... |
1447 |
static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat) |
ada364e88 [PATCH] sata_nv: ... |
1448 1449 |
{ int i, handled = 0; |
cca3974e4 libata: Grand ren... |
1450 |
for (i = 0; i < host->n_ports; i++) { |
3e4ec3443 libata: kill ATA_... |
1451 |
handled += nv_host_intr(host->ports[i], irq_stat); |
ada364e88 [PATCH] sata_nv: ... |
1452 1453 1454 1455 1456 |
irq_stat >>= NV_INT_PORT_SHIFT; } return IRQ_RETVAL(handled); } |
7d12e780e IRQ: Maintain reg... |
1457 |
static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance) |
ada364e88 [PATCH] sata_nv: ... |
1458 |
{ |
cca3974e4 libata: Grand ren... |
1459 |
struct ata_host *host = dev_instance; |
ada364e88 [PATCH] sata_nv: ... |
1460 1461 |
u8 irq_stat; irqreturn_t ret; |
cca3974e4 libata: Grand ren... |
1462 |
spin_lock(&host->lock); |
0d5ff5667 libata: convert t... |
1463 |
irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); |
cca3974e4 libata: Grand ren... |
1464 1465 |
ret = nv_do_interrupt(host, irq_stat); spin_unlock(&host->lock); |
ada364e88 [PATCH] sata_nv: ... |
1466 1467 1468 |
return ret; } |
7d12e780e IRQ: Maintain reg... |
1469 |
static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance) |
ada364e88 [PATCH] sata_nv: ... |
1470 |
{ |
cca3974e4 libata: Grand ren... |
1471 |
struct ata_host *host = dev_instance; |
ada364e88 [PATCH] sata_nv: ... |
1472 1473 |
u8 irq_stat; irqreturn_t ret; |
cca3974e4 libata: Grand ren... |
1474 |
spin_lock(&host->lock); |
0d5ff5667 libata: convert t... |
1475 |
irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); |
cca3974e4 libata: Grand ren... |
1476 1477 |
ret = nv_do_interrupt(host, irq_stat); spin_unlock(&host->lock); |
ada364e88 [PATCH] sata_nv: ... |
1478 1479 1480 |
return ret; } |
82ef04fb4 libata: make SCR ... |
1481 |
static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
1da177e4c Linux-2.6.12-rc2 |
1482 |
{ |
1da177e4c Linux-2.6.12-rc2 |
1483 |
if (sc_reg > SCR_CONTROL) |
da3dbb17a libata: make ->sc... |
1484 |
return -EINVAL; |
1da177e4c Linux-2.6.12-rc2 |
1485 |
|
82ef04fb4 libata: make SCR ... |
1486 |
*val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17a libata: make ->sc... |
1487 |
return 0; |
1da177e4c Linux-2.6.12-rc2 |
1488 |
} |
82ef04fb4 libata: make SCR ... |
1489 |
static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
1da177e4c Linux-2.6.12-rc2 |
1490 |
{ |
1da177e4c Linux-2.6.12-rc2 |
1491 |
if (sc_reg > SCR_CONTROL) |
da3dbb17a libata: make ->sc... |
1492 |
return -EINVAL; |
1da177e4c Linux-2.6.12-rc2 |
1493 |
|
82ef04fb4 libata: make SCR ... |
1494 |
iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17a libata: make ->sc... |
1495 |
return 0; |
1da177e4c Linux-2.6.12-rc2 |
1496 |
} |
7f4774b38 sata_nv: use hard... |
1497 1498 |
static int nv_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline) |
e8caa3c70 sata_nv: rename n... |
1499 |
{ |
7f4774b38 sata_nv: use hard... |
1500 |
struct ata_eh_context *ehc = &link->eh_context; |
e8caa3c70 sata_nv: rename n... |
1501 |
|
7f4774b38 sata_nv: use hard... |
1502 1503 1504 1505 1506 1507 1508 |
/* Do hardreset iff it's post-boot probing, please read the * comment above port ops for details. */ if (!(link->ap->pflags & ATA_PFLAG_LOADING) && !ata_dev_enabled(link->device)) sata_link_hardreset(link, sata_deb_timing_hotplug, deadline, NULL, NULL); |
6489e3262 sata_nv: make sur... |
1509 1510 1511 1512 1513 |
else { const unsigned long *timing = sata_ehc_deb_timing(ehc); int rc; if (!(ehc->i.flags & ATA_EHI_QUIET)) |
a9a79dfec ata: Convert ata_... |
1514 1515 1516 |
ata_link_info(link, "nv: skipping hardreset on occupied port "); |
6489e3262 sata_nv: make sur... |
1517 1518 1519 1520 1521 |
/* make sure the link is online */ rc = sata_link_resume(link, timing, deadline); /* whine about phy resume failure but proceed */ if (rc && rc != -EOPNOTSUPP) |
a9a79dfec ata: Convert ata_... |
1522 1523 1524 |
ata_link_warn(link, "failed to resume link (errno=%d) ", rc); |
6489e3262 sata_nv: make sur... |
1525 |
} |
7f4774b38 sata_nv: use hard... |
1526 1527 1528 |
/* device signature acquisition is unreliable */ return -EAGAIN; |
e8caa3c70 sata_nv: rename n... |
1529 |
} |
39f875825 [PATCH] sata_nv: ... |
1530 1531 |
static void nv_nf2_freeze(struct ata_port *ap) { |
0d5ff5667 libata: convert t... |
1532 |
void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; |
39f875825 [PATCH] sata_nv: ... |
1533 1534 |
int shift = ap->port_no * NV_INT_PORT_SHIFT; u8 mask; |
0d5ff5667 libata: convert t... |
1535 |
mask = ioread8(scr_addr + NV_INT_ENABLE); |
39f875825 [PATCH] sata_nv: ... |
1536 |
mask &= ~(NV_INT_ALL << shift); |
0d5ff5667 libata: convert t... |
1537 |
iowrite8(mask, scr_addr + NV_INT_ENABLE); |
39f875825 [PATCH] sata_nv: ... |
1538 1539 1540 1541 |
} static void nv_nf2_thaw(struct ata_port *ap) { |
0d5ff5667 libata: convert t... |
1542 |
void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; |
39f875825 [PATCH] sata_nv: ... |
1543 1544 |
int shift = ap->port_no * NV_INT_PORT_SHIFT; u8 mask; |
0d5ff5667 libata: convert t... |
1545 |
iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS); |
39f875825 [PATCH] sata_nv: ... |
1546 |
|
0d5ff5667 libata: convert t... |
1547 |
mask = ioread8(scr_addr + NV_INT_ENABLE); |
39f875825 [PATCH] sata_nv: ... |
1548 |
mask |= (NV_INT_MASK << shift); |
0d5ff5667 libata: convert t... |
1549 |
iowrite8(mask, scr_addr + NV_INT_ENABLE); |
39f875825 [PATCH] sata_nv: ... |
1550 1551 1552 1553 |
} static void nv_ck804_freeze(struct ata_port *ap) { |
0d5ff5667 libata: convert t... |
1554 |
void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; |
39f875825 [PATCH] sata_nv: ... |
1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 |
int shift = ap->port_no * NV_INT_PORT_SHIFT; u8 mask; mask = readb(mmio_base + NV_INT_ENABLE_CK804); mask &= ~(NV_INT_ALL << shift); writeb(mask, mmio_base + NV_INT_ENABLE_CK804); } static void nv_ck804_thaw(struct ata_port *ap) { |
0d5ff5667 libata: convert t... |
1565 |
void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; |
39f875825 [PATCH] sata_nv: ... |
1566 1567 1568 1569 1570 1571 1572 1573 1574 |
int shift = ap->port_no * NV_INT_PORT_SHIFT; u8 mask; writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804); mask = readb(mmio_base + NV_INT_ENABLE_CK804); mask |= (NV_INT_MASK << shift); writeb(mask, mmio_base + NV_INT_ENABLE_CK804); } |
f140f0f12 [libata] sata_nv:... |
1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 |
static void nv_mcp55_freeze(struct ata_port *ap) { void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55; u32 mask; writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55); mask = readl(mmio_base + NV_INT_ENABLE_MCP55); mask &= ~(NV_INT_ALL_MCP55 << shift); writel(mask, mmio_base + NV_INT_ENABLE_MCP55); |
f140f0f12 [libata] sata_nv:... |
1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 |
} static void nv_mcp55_thaw(struct ata_port *ap) { void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55; u32 mask; writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55); mask = readl(mmio_base + NV_INT_ENABLE_MCP55); mask |= (NV_INT_MASK_MCP55 << shift); writel(mask, mmio_base + NV_INT_ENABLE_MCP55); |
f140f0f12 [libata] sata_nv:... |
1599 |
} |
fbbb262d9 [PATCH] sata_nv A... |
1600 1601 1602 |
static void nv_adma_error_handler(struct ata_port *ap) { struct nv_adma_port_priv *pp = ap->private_data; |
b447916e2 [libata] fix 'if(... |
1603 |
if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) { |
cdf56bcf1 sata_nv: add susp... |
1604 |
void __iomem *mmio = pp->ctl_block; |
fbbb262d9 [PATCH] sata_nv A... |
1605 1606 |
int i; u16 tmp; |
a84471fe2 [libata] Trim tra... |
1607 |
|
b447916e2 [libata] fix 'if(... |
1608 |
if (ata_tag_valid(ap->link.active_tag) || ap->link.sactive) { |
2cb27853b sata_nv: add back... |
1609 1610 1611 1612 |
u32 notifier = readl(mmio + NV_ADMA_NOTIFIER); u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL); u32 status = readw(mmio + NV_ADMA_STAT); |
08af74147 sata_nv: Add CPB ... |
1613 1614 |
u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT); u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX); |
2cb27853b sata_nv: add back... |
1615 |
|
a9a79dfec ata: Convert ata_... |
1616 |
ata_port_err(ap, |
5796d1c4c [libata] Address ... |
1617 |
"EH in ADMA mode, notifier 0x%X " |
08af74147 sata_nv: Add CPB ... |
1618 1619 1620 1621 1622 |
"notifier_error 0x%X gen_ctl 0x%X status 0x%X " "next cpb count 0x%X next cpb idx 0x%x ", notifier, notifier_error, gen_ctl, status, cpb_count, next_cpb_idx); |
2cb27853b sata_nv: add back... |
1623 |
|
b447916e2 [libata] fix 'if(... |
1624 |
for (i = 0; i < NV_ADMA_MAX_CPBS; i++) { |
2cb27853b sata_nv: add back... |
1625 |
struct nv_adma_cpb *cpb = &pp->cpb[i]; |
b447916e2 [libata] fix 'if(... |
1626 |
if ((ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) || |
5796d1c4c [libata] Address ... |
1627 |
ap->link.sactive & (1 << i)) |
a9a79dfec ata: Convert ata_... |
1628 |
ata_port_err(ap, |
2cb27853b sata_nv: add back... |
1629 1630 1631 1632 1633 |
"CPB %d: ctl_flags 0x%x, resp_flags 0x%x ", i, cpb->ctl_flags, cpb->resp_flags); } } |
fbbb262d9 [PATCH] sata_nv A... |
1634 |
|
fbbb262d9 [PATCH] sata_nv A... |
1635 1636 |
/* Push us back into port register mode for error handling. */ nv_adma_register_mode(ap); |
5796d1c4c [libata] Address ... |
1637 1638 |
/* Mark all of the CPBs as invalid to prevent them from being executed */ |
b447916e2 [libata] fix 'if(... |
1639 |
for (i = 0; i < NV_ADMA_MAX_CPBS; i++) |
fbbb262d9 [PATCH] sata_nv A... |
1640 1641 1642 1643 1644 1645 1646 1647 |
pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID; /* clear CPB fetch count */ writew(0, mmio + NV_ADMA_CPB_COUNT); /* Reset channel */ tmp = readw(mmio + NV_ADMA_CTL); writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
b447916e2 [libata] fix 'if(... |
1648 |
readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
fbbb262d9 [PATCH] sata_nv A... |
1649 1650 |
udelay(1); writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
b447916e2 [libata] fix 'if(... |
1651 |
readw(mmio + NV_ADMA_CTL); /* flush posted write */ |
fbbb262d9 [PATCH] sata_nv A... |
1652 |
} |
fe06e5f9b libata-sff: separ... |
1653 |
ata_bmdma_error_handler(ap); |
fbbb262d9 [PATCH] sata_nv A... |
1654 |
} |
f140f0f12 [libata] sata_nv:... |
1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 |
static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc) { struct nv_swncq_port_priv *pp = ap->private_data; struct defer_queue *dq = &pp->defer_queue; /* queue is full */ WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE); dq->defer_bits |= (1 << qc->tag); dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag; } static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap) { struct nv_swncq_port_priv *pp = ap->private_data; struct defer_queue *dq = &pp->defer_queue; unsigned int tag; if (dq->head == dq->tail) /* null queue */ return NULL; tag = dq->tag[dq->head & (ATA_MAX_QUEUE - 1)]; dq->tag[dq->head++ & (ATA_MAX_QUEUE - 1)] = ATA_TAG_POISON; WARN_ON(!(dq->defer_bits & (1 << tag))); dq->defer_bits &= ~(1 << tag); return ata_qc_from_tag(ap, tag); } static void nv_swncq_fis_reinit(struct ata_port *ap) { struct nv_swncq_port_priv *pp = ap->private_data; pp->dhfis_bits = 0; pp->dmafis_bits = 0; pp->sdbfis_bits = 0; pp->ncq_flags = 0; } static void nv_swncq_pp_reinit(struct ata_port *ap) { struct nv_swncq_port_priv *pp = ap->private_data; struct defer_queue *dq = &pp->defer_queue; dq->head = 0; dq->tail = 0; dq->defer_bits = 0; pp->qc_active = 0; pp->last_issue_tag = ATA_TAG_POISON; nv_swncq_fis_reinit(ap); } static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis) { struct nv_swncq_port_priv *pp = ap->private_data; writew(fis, pp->irq_block); } static void __ata_bmdma_stop(struct ata_port *ap) { struct ata_queued_cmd qc; qc.ap = ap; ata_bmdma_stop(&qc); } static void nv_swncq_ncq_stop(struct ata_port *ap) { struct nv_swncq_port_priv *pp = ap->private_data; unsigned int i; u32 sactive; u32 done_mask; |
a9a79dfec ata: Convert ata_... |
1727 1728 1729 1730 |
ata_port_err(ap, "EH in SWNCQ mode,QC:qc_active 0x%X sactive 0x%X ", ap->qc_active, ap->link.sactive); ata_port_err(ap, |
f140f0f12 [libata] sata_nv:... |
1731 1732 1733 1734 1735 1736 |
"SWNCQ:qc_active 0x%X defer_bits 0x%X last_issue_tag 0x%x " "dhfis 0x%X dmafis 0x%X sdbfis 0x%X ", pp->qc_active, pp->defer_queue.defer_bits, pp->last_issue_tag, pp->dhfis_bits, pp->dmafis_bits, pp->sdbfis_bits); |
a9a79dfec ata: Convert ata_... |
1737 1738 1739 1740 |
ata_port_err(ap, "ATA_REG 0x%X ERR_REG 0x%X ", ap->ops->sff_check_status(ap), ioread8(ap->ioaddr.error_addr)); |
f140f0f12 [libata] sata_nv:... |
1741 1742 1743 |
sactive = readl(pp->sactive_block); done_mask = pp->qc_active ^ sactive; |
a9a79dfec ata: Convert ata_... |
1744 1745 |
ata_port_err(ap, "tag : dhfis dmafis sdbfis sactive "); |
f140f0f12 [libata] sata_nv:... |
1746 1747 1748 1749 1750 1751 1752 1753 |
for (i = 0; i < ATA_MAX_QUEUE; i++) { u8 err = 0; if (pp->qc_active & (1 << i)) err = 0; else if (done_mask & (1 << i)) err = 1; else continue; |
a9a79dfec ata: Convert ata_... |
1754 1755 1756 1757 1758 1759 1760 1761 |
ata_port_err(ap, "tag 0x%x: %01x %01x %01x %01x %s ", i, (pp->dhfis_bits >> i) & 0x1, (pp->dmafis_bits >> i) & 0x1, (pp->sdbfis_bits >> i) & 0x1, (sactive >> i) & 0x1, (err ? "error! tag doesn't exit" : " ")); |
f140f0f12 [libata] sata_nv:... |
1762 1763 1764 |
} nv_swncq_pp_reinit(ap); |
5682ed33a libata: rename SF... |
1765 |
ap->ops->sff_irq_clear(ap); |
f140f0f12 [libata] sata_nv:... |
1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 |
__ata_bmdma_stop(ap); nv_swncq_irq_clear(ap, 0xffff); } static void nv_swncq_error_handler(struct ata_port *ap) { struct ata_eh_context *ehc = &ap->link.eh_context; if (ap->link.sactive) { nv_swncq_ncq_stop(ap); |
cf4806265 libata: prefer ha... |
1776 |
ehc->i.action |= ATA_EH_RESET; |
f140f0f12 [libata] sata_nv:... |
1777 |
} |
fe06e5f9b libata-sff: separ... |
1778 |
ata_bmdma_error_handler(ap); |
f140f0f12 [libata] sata_nv:... |
1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 |
} #ifdef CONFIG_PM static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg) { void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; u32 tmp; /* clear irq */ writel(~0, mmio + NV_INT_STATUS_MCP55); /* disable irq */ writel(0, mmio + NV_INT_ENABLE_MCP55); /* disable swncq */ tmp = readl(mmio + NV_CTL_MCP55); tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ); writel(tmp, mmio + NV_CTL_MCP55); return 0; } static int nv_swncq_port_resume(struct ata_port *ap) { void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; u32 tmp; /* clear irq */ writel(~0, mmio + NV_INT_STATUS_MCP55); /* enable irq */ writel(0x00fd00fd, mmio + NV_INT_ENABLE_MCP55); /* enable swncq */ tmp = readl(mmio + NV_CTL_MCP55); writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55); return 0; } #endif static void nv_swncq_host_init(struct ata_host *host) { u32 tmp; void __iomem *mmio = host->iomap[NV_MMIO_BAR]; struct pci_dev *pdev = to_pci_dev(host->dev); u8 regval; /* disable ECO 398 */ pci_read_config_byte(pdev, 0x7f, ®val); regval &= ~(1 << 7); pci_write_config_byte(pdev, 0x7f, regval); /* enable swncq */ tmp = readl(mmio + NV_CTL_MCP55); VPRINTK("HOST_CTL:0x%X ", tmp); writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55); /* enable irq intr */ tmp = readl(mmio + NV_INT_ENABLE_MCP55); VPRINTK("HOST_ENABLE:0x%X ", tmp); writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55); /* clear port irq */ writel(~0x0, mmio + NV_INT_STATUS_MCP55); } static int nv_swncq_slave_config(struct scsi_device *sdev) { struct ata_port *ap = ata_shost_to_port(sdev->host); struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct ata_device *dev; int rc; u8 rev; u8 check_maxtor = 0; unsigned char model_num[ATA_ID_PROD_LEN + 1]; rc = ata_scsi_slave_config(sdev); if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun) /* Not a proper libata device, ignore */ return rc; dev = &ap->link.device[sdev->id]; if (!(ap->flags & ATA_FLAG_NCQ) || dev->class == ATA_DEV_ATAPI) return rc; /* if MCP51 and Maxtor, then disable ncq */ if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA || pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2) check_maxtor = 1; /* if MCP55 and rev <= a2 and Maxtor, then disable ncq */ if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA || pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2) { pci_read_config_byte(pdev, 0x8, &rev); if (rev <= 0xa2) check_maxtor = 1; } if (!check_maxtor) return rc; ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); if (strncmp(model_num, "Maxtor", 6) == 0) { |
db5ed4dfd scsi: drop reason... |
1886 |
ata_scsi_change_queue_depth(sdev, 1); |
a9a79dfec ata: Convert ata_... |
1887 1888 1889 |
ata_dev_notice(dev, "Disabling SWNCQ mode (depth %x) ", sdev->queue_depth); |
f140f0f12 [libata] sata_nv:... |
1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 |
} return rc; } static int nv_swncq_port_start(struct ata_port *ap) { struct device *dev = ap->host->dev; void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; struct nv_swncq_port_priv *pp; int rc; |
c7087652e libata-sff: clean... |
1901 1902 |
/* we might fallback to bmdma, allocate bmdma resources */ rc = ata_bmdma_port_start(ap); |
f140f0f12 [libata] sata_nv:... |
1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 |
if (rc) return rc; pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); if (!pp) return -ENOMEM; pp->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE, &pp->prd_dma, GFP_KERNEL); if (!pp->prd) return -ENOMEM; memset(pp->prd, 0, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE); ap->private_data = pp; pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE; pp->irq_block = mmio + NV_INT_STATUS_MCP55 + ap->port_no * 2; pp->tag_block = mmio + NV_NCQ_REG_MCP55 + ap->port_no * 2; return 0; } static void nv_swncq_qc_prep(struct ata_queued_cmd *qc) { if (qc->tf.protocol != ATA_PROT_NCQ) { |
f47451c45 libata-sff: ata_s... |
1927 |
ata_bmdma_qc_prep(qc); |
f140f0f12 [libata] sata_nv:... |
1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 |
return; } if (!(qc->flags & ATA_QCFLAG_DMAMAP)) return; nv_swncq_fill_sg(qc); } static void nv_swncq_fill_sg(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct scatterlist *sg; |
f140f0f12 [libata] sata_nv:... |
1941 |
struct nv_swncq_port_priv *pp = ap->private_data; |
f60d70113 libata-sff: prd i... |
1942 |
struct ata_bmdma_prd *prd; |
ff2aeb1eb libata: convert t... |
1943 |
unsigned int si, idx; |
f140f0f12 [libata] sata_nv:... |
1944 1945 1946 1947 |
prd = pp->prd + ATA_MAX_PRD * qc->tag; idx = 0; |
ff2aeb1eb libata: convert t... |
1948 |
for_each_sg(qc->sg, sg, qc->n_elem, si) { |
f140f0f12 [libata] sata_nv:... |
1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 |
u32 addr, offset; u32 sg_len, len; addr = (u32)sg_dma_address(sg); sg_len = sg_dma_len(sg); while (sg_len) { offset = addr & 0xffff; len = sg_len; if ((offset + sg_len) > 0x10000) len = 0x10000 - offset; prd[idx].addr = cpu_to_le32(addr); prd[idx].flags_len = cpu_to_le32(len & 0xffff); idx++; sg_len -= len; addr += len; } } |
ff2aeb1eb libata: convert t... |
1969 |
prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f140f0f12 [libata] sata_nv:... |
1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 |
} static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap, struct ata_queued_cmd *qc) { struct nv_swncq_port_priv *pp = ap->private_data; if (qc == NULL) return 0; DPRINTK("Enter "); writel((1 << qc->tag), pp->sactive_block); pp->last_issue_tag = qc->tag; pp->dhfis_bits &= ~(1 << qc->tag); pp->dmafis_bits &= ~(1 << qc->tag); pp->qc_active |= (0x1 << qc->tag); |
5682ed33a libata: rename SF... |
1988 1989 |
ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ ap->ops->sff_exec_command(ap, &qc->tf); |
f140f0f12 [libata] sata_nv:... |
1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 |
DPRINTK("Issued tag %u ", qc->tag); return 0; } static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct nv_swncq_port_priv *pp = ap->private_data; if (qc->tf.protocol != ATA_PROT_NCQ) |
360ff7833 libata-sff: separ... |
2003 |
return ata_bmdma_qc_issue(qc); |
f140f0f12 [libata] sata_nv:... |
2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 |
DPRINTK("Enter "); if (!pp->qc_active) nv_swncq_issue_atacmd(ap, qc); else nv_swncq_qc_to_dq(ap, qc); /* add qc to defer queue */ return 0; } static void nv_swncq_hotplug(struct ata_port *ap, u32 fis) { u32 serror; struct ata_eh_info *ehi = &ap->link.eh_info; ata_ehi_clear_desc(ehi); /* AHCI needs SError cleared; otherwise, it might lock up */ sata_scr_read(&ap->link, SCR_ERROR, &serror); sata_scr_write(&ap->link, SCR_ERROR, serror); /* analyze @irq_stat */ if (fis & NV_SWNCQ_IRQ_ADDED) ata_ehi_push_desc(ehi, "hot plug"); else if (fis & NV_SWNCQ_IRQ_REMOVED) ata_ehi_push_desc(ehi, "hot unplug"); ata_ehi_hotplugged(ehi); /* okay, let's hand over to EH */ ehi->serror |= serror; ata_port_freeze(ap); } static int nv_swncq_sdbfis(struct ata_port *ap) { struct ata_queued_cmd *qc; struct nv_swncq_port_priv *pp = ap->private_data; struct ata_eh_info *ehi = &ap->link.eh_info; u32 sactive; |
f140f0f12 [libata] sata_nv:... |
2047 |
u32 done_mask; |
f140f0f12 [libata] sata_nv:... |
2048 2049 2050 2051 2052 |
u8 host_stat; u8 lack_dhfis = 0; host_stat = ap->ops->bmdma_status(ap); if (unlikely(host_stat & ATA_DMA_ERR)) { |
25985edce Fix common misspe... |
2053 |
/* error when transferring data to/from memory */ |
f140f0f12 [libata] sata_nv:... |
2054 2055 2056 |
ata_ehi_clear_desc(ehi); ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); ehi->err_mask |= AC_ERR_HOST_BUS; |
cf4806265 libata: prefer ha... |
2057 |
ehi->action |= ATA_EH_RESET; |
f140f0f12 [libata] sata_nv:... |
2058 2059 |
return -EINVAL; } |
5682ed33a libata: rename SF... |
2060 |
ap->ops->sff_irq_clear(ap); |
f140f0f12 [libata] sata_nv:... |
2061 2062 2063 2064 |
__ata_bmdma_stop(ap); sactive = readl(pp->sactive_block); done_mask = pp->qc_active ^ sactive; |
1aadf5c3b libata: always us... |
2065 2066 2067 2068 2069 |
pp->qc_active &= ~done_mask; pp->dhfis_bits &= ~done_mask; pp->dmafis_bits &= ~done_mask; pp->sdbfis_bits |= done_mask; ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); |
f140f0f12 [libata] sata_nv:... |
2070 2071 2072 2073 2074 |
if (!ap->qc_active) { DPRINTK("over "); nv_swncq_pp_reinit(ap); |
752e386c2 sata_fsl,mv,nv: p... |
2075 |
return 0; |
f140f0f12 [libata] sata_nv:... |
2076 2077 2078 |
} if (pp->qc_active & pp->dhfis_bits) |
752e386c2 sata_fsl,mv,nv: p... |
2079 |
return 0; |
f140f0f12 [libata] sata_nv:... |
2080 2081 2082 |
if ((pp->ncq_flags & ncq_saw_backout) || (pp->qc_active ^ pp->dhfis_bits)) |
752e386c2 sata_fsl,mv,nv: p... |
2083 |
/* if the controller can't get a device to host register FIS, |
f140f0f12 [libata] sata_nv:... |
2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 |
* The driver needs to reissue the new command. */ lack_dhfis = 1; DPRINTK("id 0x%x QC: qc_active 0x%x," "SWNCQ:qc_active 0x%X defer_bits %X " "dhfis 0x%X dmafis 0x%X last_issue_tag %x ", ap->print_id, ap->qc_active, pp->qc_active, pp->defer_queue.defer_bits, pp->dhfis_bits, pp->dmafis_bits, pp->last_issue_tag); nv_swncq_fis_reinit(ap); if (lack_dhfis) { qc = ata_qc_from_tag(ap, pp->last_issue_tag); nv_swncq_issue_atacmd(ap, qc); |
752e386c2 sata_fsl,mv,nv: p... |
2101 |
return 0; |
f140f0f12 [libata] sata_nv:... |
2102 2103 2104 2105 2106 2107 2108 2109 |
} if (pp->defer_queue.defer_bits) { /* send deferral queue command */ qc = nv_swncq_qc_from_dq(ap); WARN_ON(qc == NULL); nv_swncq_issue_atacmd(ap, qc); } |
752e386c2 sata_fsl,mv,nv: p... |
2110 |
return 0; |
f140f0f12 [libata] sata_nv:... |
2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 |
} static inline u32 nv_swncq_tag(struct ata_port *ap) { struct nv_swncq_port_priv *pp = ap->private_data; u32 tag; tag = readb(pp->tag_block) >> 2; return (tag & 0x1f); } |
752e386c2 sata_fsl,mv,nv: p... |
2121 |
static void nv_swncq_dmafis(struct ata_port *ap) |
f140f0f12 [libata] sata_nv:... |
2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 |
{ struct ata_queued_cmd *qc; unsigned int rw; u8 dmactl; u32 tag; struct nv_swncq_port_priv *pp = ap->private_data; __ata_bmdma_stop(ap); tag = nv_swncq_tag(ap); DPRINTK("dma setup tag 0x%x ", tag); qc = ata_qc_from_tag(ap, tag); if (unlikely(!qc)) |
752e386c2 sata_fsl,mv,nv: p... |
2137 |
return; |
f140f0f12 [libata] sata_nv:... |
2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 |
rw = qc->tf.flags & ATA_TFLAG_WRITE; /* load PRD table addr. */ iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); /* specify data direction, triple-check start bit is clear */ dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); dmactl &= ~ATA_DMA_WR; if (!rw) dmactl |= ATA_DMA_WR; iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
f140f0f12 [libata] sata_nv:... |
2152 2153 2154 2155 2156 2157 2158 2159 2160 |
} static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis) { struct nv_swncq_port_priv *pp = ap->private_data; struct ata_queued_cmd *qc; struct ata_eh_info *ehi = &ap->link.eh_info; u32 serror; u8 ata_stat; |
f140f0f12 [libata] sata_nv:... |
2161 |
|
5682ed33a libata: rename SF... |
2162 |
ata_stat = ap->ops->sff_check_status(ap); |
f140f0f12 [libata] sata_nv:... |
2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 |
nv_swncq_irq_clear(ap, fis); if (!fis) return; if (ap->pflags & ATA_PFLAG_FROZEN) return; if (fis & NV_SWNCQ_IRQ_HOTPLUG) { nv_swncq_hotplug(ap, fis); return; } if (!pp->qc_active) return; |
82ef04fb4 libata: make SCR ... |
2177 |
if (ap->ops->scr_read(&ap->link, SCR_ERROR, &serror)) |
f140f0f12 [libata] sata_nv:... |
2178 |
return; |
82ef04fb4 libata: make SCR ... |
2179 |
ap->ops->scr_write(&ap->link, SCR_ERROR, serror); |
f140f0f12 [libata] sata_nv:... |
2180 2181 2182 2183 2184 2185 |
if (ata_stat & ATA_ERR) { ata_ehi_clear_desc(ehi); ata_ehi_push_desc(ehi, "Ata error. fis:0x%X", fis); ehi->err_mask |= AC_ERR_DEV; ehi->serror |= serror; |
cf4806265 libata: prefer ha... |
2186 |
ehi->action |= ATA_EH_RESET; |
f140f0f12 [libata] sata_nv:... |
2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 |
ata_port_freeze(ap); return; } if (fis & NV_SWNCQ_IRQ_BACKOUT) { /* If the IRQ is backout, driver must issue * the new command again some time later. */ pp->ncq_flags |= ncq_saw_backout; } if (fis & NV_SWNCQ_IRQ_SDBFIS) { pp->ncq_flags |= ncq_saw_sdb; DPRINTK("id 0x%x SWNCQ: qc_active 0x%X " "dhfis 0x%X dmafis 0x%X sactive 0x%X ", ap->print_id, pp->qc_active, pp->dhfis_bits, pp->dmafis_bits, readl(pp->sactive_block)); |
752e386c2 sata_fsl,mv,nv: p... |
2205 |
if (nv_swncq_sdbfis(ap) < 0) |
f140f0f12 [libata] sata_nv:... |
2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 |
goto irq_error; } if (fis & NV_SWNCQ_IRQ_DHREGFIS) { /* The interrupt indicates the new command * was transmitted correctly to the drive. */ pp->dhfis_bits |= (0x1 << pp->last_issue_tag); pp->ncq_flags |= ncq_saw_d2h; if (pp->ncq_flags & (ncq_saw_sdb | ncq_saw_backout)) { ata_ehi_push_desc(ehi, "illegal fis transaction"); ehi->err_mask |= AC_ERR_HSM; |
cf4806265 libata: prefer ha... |
2218 |
ehi->action |= ATA_EH_RESET; |
f140f0f12 [libata] sata_nv:... |
2219 2220 2221 2222 2223 |
goto irq_error; } if (!(fis & NV_SWNCQ_IRQ_DMASETUP) && !(pp->ncq_flags & ncq_saw_dmas)) { |
5682ed33a libata: rename SF... |
2224 |
ata_stat = ap->ops->sff_check_status(ap); |
f140f0f12 [libata] sata_nv:... |
2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 |
if (ata_stat & ATA_BUSY) goto irq_exit; if (pp->defer_queue.defer_bits) { DPRINTK("send next command "); qc = nv_swncq_qc_from_dq(ap); nv_swncq_issue_atacmd(ap, qc); } } } if (fis & NV_SWNCQ_IRQ_DMASETUP) { /* program the dma controller with appropriate PRD buffers * and start the DMA transfer for requested command. */ pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap)); pp->ncq_flags |= ncq_saw_dmas; |
752e386c2 sata_fsl,mv,nv: p... |
2243 |
nv_swncq_dmafis(ap); |
f140f0f12 [libata] sata_nv:... |
2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 |
} irq_exit: return; irq_error: ata_ehi_push_desc(ehi, "fis:0x%x", fis); ata_port_freeze(ap); return; } static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance) { struct ata_host *host = dev_instance; unsigned int i; unsigned int handled = 0; unsigned long flags; u32 irq_stat; spin_lock_irqsave(&host->lock, flags); irq_stat = readl(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_MCP55); for (i = 0; i < host->n_ports; i++) { struct ata_port *ap = host->ports[i]; |
3e4ec3443 libata: kill ATA_... |
2268 2269 2270 2271 2272 2273 |
if (ap->link.sactive) { nv_swncq_host_interrupt(ap, (u16)irq_stat); handled = 1; } else { if (irq_stat) /* reserve Hotplug */ nv_swncq_irq_clear(ap, 0xfff0); |
f140f0f12 [libata] sata_nv:... |
2274 |
|
3e4ec3443 libata: kill ATA_... |
2275 |
handled += nv_host_intr(ap, (u8)irq_stat); |
f140f0f12 [libata] sata_nv:... |
2276 2277 2278 2279 2280 2281 2282 2283 |
} irq_stat >>= NV_INT_PORT_SHIFT_MCP55; } spin_unlock_irqrestore(&host->lock, flags); return IRQ_RETVAL(handled); } |
5796d1c4c [libata] Address ... |
2284 |
static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4c Linux-2.6.12-rc2 |
2285 |
{ |
1626aeb88 libata: clean up ... |
2286 |
const struct ata_port_info *ppi[] = { NULL, NULL }; |
959471936 libata: kill port... |
2287 |
struct nv_pi_priv *ipriv; |
9a829ccfc libata: convert a... |
2288 |
struct ata_host *host; |
cdf56bcf1 sata_nv: add susp... |
2289 |
struct nv_host_priv *hpriv; |
1da177e4c Linux-2.6.12-rc2 |
2290 2291 |
int rc; u32 bar; |
0d5ff5667 libata: convert t... |
2292 |
void __iomem *base; |
fbbb262d9 [PATCH] sata_nv A... |
2293 |
unsigned long type = ent->driver_data; |
1da177e4c Linux-2.6.12-rc2 |
2294 2295 2296 2297 |
// Make sure this is a SATA controller by counting the number of bars // (NVIDIA SATA controllers will always have six bars). Otherwise, // it's an IDE controller and we ignore it. |
5796d1c4c [libata] Address ... |
2298 |
for (bar = 0; bar < 6; bar++) |
1da177e4c Linux-2.6.12-rc2 |
2299 2300 |
if (pci_resource_start(pdev, bar) == 0) return -ENODEV; |
06296a1e6 ata: Add and use ... |
2301 |
ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4c Linux-2.6.12-rc2 |
2302 |
|
24dc5f33e libata: update li... |
2303 |
rc = pcim_enable_device(pdev); |
1da177e4c Linux-2.6.12-rc2 |
2304 |
if (rc) |
24dc5f33e libata: update li... |
2305 |
return rc; |
1da177e4c Linux-2.6.12-rc2 |
2306 |
|
9a829ccfc libata: convert a... |
2307 |
/* determine type and allocate host */ |
f140f0f12 [libata] sata_nv:... |
2308 |
if (type == CK804 && adma_enabled) { |
a44fec1fc ata: Convert dev_... |
2309 2310 |
dev_notice(&pdev->dev, "Using ADMA mode "); |
fbbb262d9 [PATCH] sata_nv A... |
2311 |
type = ADMA; |
2d775708b sata_nv: fix MCP5... |
2312 |
} else if (type == MCP5x && swncq_enabled) { |
a44fec1fc ata: Convert dev_... |
2313 2314 |
dev_notice(&pdev->dev, "Using SWNCQ mode "); |
2d775708b sata_nv: fix MCP5... |
2315 |
type = SWNCQ; |
360737a98 [libata] sata_nv:... |
2316 |
} |
1626aeb88 libata: clean up ... |
2317 |
ppi[0] = &nv_port_info[type]; |
959471936 libata: kill port... |
2318 |
ipriv = ppi[0]->private_data; |
1c5afdf7a libata-sff: separ... |
2319 |
rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
9a829ccfc libata: convert a... |
2320 2321 |
if (rc) return rc; |
1da177e4c Linux-2.6.12-rc2 |
2322 |
|
24dc5f33e libata: update li... |
2323 |
hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
cdf56bcf1 sata_nv: add susp... |
2324 |
if (!hpriv) |
24dc5f33e libata: update li... |
2325 |
return -ENOMEM; |
9a829ccfc libata: convert a... |
2326 2327 |
hpriv->type = type; host->private_data = hpriv; |
cdf56bcf1 sata_nv: add susp... |
2328 |
|
9a829ccfc libata: convert a... |
2329 2330 2331 2332 |
/* request and iomap NV_MMIO_BAR */ rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME); if (rc) return rc; |
1da177e4c Linux-2.6.12-rc2 |
2333 |
|
9a829ccfc libata: convert a... |
2334 2335 2336 2337 |
/* configure SCR access */ base = host->iomap[NV_MMIO_BAR]; host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET; host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET; |
1da177e4c Linux-2.6.12-rc2 |
2338 |
|
ada364e88 [PATCH] sata_nv: ... |
2339 |
/* enable SATA space for CK804 */ |
fbbb262d9 [PATCH] sata_nv A... |
2340 |
if (type >= CK804) { |
ada364e88 [PATCH] sata_nv: ... |
2341 2342 2343 2344 2345 2346 |
u8 regval; pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); } |
9a829ccfc libata: convert a... |
2347 |
/* init ADMA */ |
fbbb262d9 [PATCH] sata_nv A... |
2348 |
if (type == ADMA) { |
9a829ccfc libata: convert a... |
2349 |
rc = nv_adma_host_init(host); |
fbbb262d9 [PATCH] sata_nv A... |
2350 |
if (rc) |
24dc5f33e libata: update li... |
2351 |
return rc; |
360737a98 [libata] sata_nv:... |
2352 |
} else if (type == SWNCQ) |
f140f0f12 [libata] sata_nv:... |
2353 |
nv_swncq_host_init(host); |
fbbb262d9 [PATCH] sata_nv A... |
2354 |
|
51c894995 sata_nv: MSI supp... |
2355 |
if (msi_enabled) { |
a44fec1fc ata: Convert dev_... |
2356 2357 |
dev_notice(&pdev->dev, "Using MSI "); |
51c894995 sata_nv: MSI supp... |
2358 2359 |
pci_enable_msi(pdev); } |
9a829ccfc libata: convert a... |
2360 |
pci_set_master(pdev); |
95cc2c70c sata_nv: use ata_... |
2361 |
return ata_pci_sff_activate_host(host, ipriv->irq_handler, ipriv->sht); |
1da177e4c Linux-2.6.12-rc2 |
2362 |
} |
58eb8cd56 ata: use CONFIG_P... |
2363 |
#ifdef CONFIG_PM_SLEEP |
cdf56bcf1 sata_nv: add susp... |
2364 2365 |
static int nv_pci_device_resume(struct pci_dev *pdev) { |
0a86e1c85 ata: use pci_get_... |
2366 |
struct ata_host *host = pci_get_drvdata(pdev); |
cdf56bcf1 sata_nv: add susp... |
2367 |
struct nv_host_priv *hpriv = host->private_data; |
ce053fa8b sata_nv: propagat... |
2368 |
int rc; |
cdf56bcf1 sata_nv: add susp... |
2369 |
|
ce053fa8b sata_nv: propagat... |
2370 |
rc = ata_pci_device_do_resume(pdev); |
b447916e2 [libata] fix 'if(... |
2371 |
if (rc) |
ce053fa8b sata_nv: propagat... |
2372 |
return rc; |
cdf56bcf1 sata_nv: add susp... |
2373 2374 |
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
b447916e2 [libata] fix 'if(... |
2375 |
if (hpriv->type >= CK804) { |
cdf56bcf1 sata_nv: add susp... |
2376 2377 2378 2379 2380 2381 |
u8 regval; pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); } |
b447916e2 [libata] fix 'if(... |
2382 |
if (hpriv->type == ADMA) { |
cdf56bcf1 sata_nv: add susp... |
2383 2384 2385 2386 2387 2388 |
u32 tmp32; struct nv_adma_port_priv *pp; /* enable/disable ADMA on the ports appropriately */ pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); pp = host->ports[0]->private_data; |
b447916e2 [libata] fix 'if(... |
2389 |
if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) |
cdf56bcf1 sata_nv: add susp... |
2390 |
tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN | |
5796d1c4c [libata] Address ... |
2391 |
NV_MCP_SATA_CFG_20_PORT0_PWB_EN); |
cdf56bcf1 sata_nv: add susp... |
2392 2393 |
else tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN | |
5796d1c4c [libata] Address ... |
2394 |
NV_MCP_SATA_CFG_20_PORT0_PWB_EN); |
cdf56bcf1 sata_nv: add susp... |
2395 |
pp = host->ports[1]->private_data; |
b447916e2 [libata] fix 'if(... |
2396 |
if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) |
cdf56bcf1 sata_nv: add susp... |
2397 |
tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN | |
5796d1c4c [libata] Address ... |
2398 |
NV_MCP_SATA_CFG_20_PORT1_PWB_EN); |
cdf56bcf1 sata_nv: add susp... |
2399 2400 |
else tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN | |
5796d1c4c [libata] Address ... |
2401 |
NV_MCP_SATA_CFG_20_PORT1_PWB_EN); |
cdf56bcf1 sata_nv: add susp... |
2402 2403 2404 2405 2406 2407 2408 2409 2410 |
pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); } } ata_host_resume(host); return 0; } |
438ac6d5e libata: add missi... |
2411 |
#endif |
cdf56bcf1 sata_nv: add susp... |
2412 |
|
cca3974e4 libata: Grand ren... |
2413 |
static void nv_ck804_host_stop(struct ata_host *host) |
ada364e88 [PATCH] sata_nv: ... |
2414 |
{ |
cca3974e4 libata: Grand ren... |
2415 |
struct pci_dev *pdev = to_pci_dev(host->dev); |
ada364e88 [PATCH] sata_nv: ... |
2416 2417 2418 2419 2420 2421 |
u8 regval; /* disable SATA space for CK804 */ pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN; pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); |
ada364e88 [PATCH] sata_nv: ... |
2422 |
} |
fbbb262d9 [PATCH] sata_nv A... |
2423 2424 2425 |
static void nv_adma_host_stop(struct ata_host *host) { struct pci_dev *pdev = to_pci_dev(host->dev); |
fbbb262d9 [PATCH] sata_nv A... |
2426 |
u32 tmp32; |
fbbb262d9 [PATCH] sata_nv A... |
2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 |
/* disable ADMA on the ports */ pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN | NV_MCP_SATA_CFG_20_PORT0_PWB_EN | NV_MCP_SATA_CFG_20_PORT1_EN | NV_MCP_SATA_CFG_20_PORT1_PWB_EN); pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); nv_ck804_host_stop(host); } |
2fc75da0c ata: use module_p... |
2438 |
module_pci_driver(nv_pci_driver); |
1da177e4c Linux-2.6.12-rc2 |
2439 |
|
fbbb262d9 [PATCH] sata_nv A... |
2440 |
module_param_named(adma, adma_enabled, bool, 0444); |
55f784c82 sata_nv: fix modu... |
2441 |
MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: false)"); |
f140f0f12 [libata] sata_nv:... |
2442 |
module_param_named(swncq, swncq_enabled, bool, 0444); |
d21279f41 ata: SWNCQ should... |
2443 |
MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: true)"); |
51c894995 sata_nv: MSI supp... |
2444 2445 |
module_param_named(msi, msi_enabled, bool, 0444); MODULE_PARM_DESC(msi, "Enable use of MSI (Default: false)"); |