Blame view
drivers/bus/mvebu-mbus.c
36.4 KB
fddddb52a bus: introduce an... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 |
/* * Address map functions for Marvell EBU SoCs (Kirkwood, Armada * 370/XP, Dove, Orion5x and MV78xx0) * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. * * The Marvell EBU SoCs have a configurable physical address space: * the physical address at which certain devices (PCIe, NOR, NAND, * etc.) sit can be configured. The configuration takes place through * two sets of registers: * * - One to configure the access of the CPU to the devices. Depending * on the families, there are between 8 and 20 configurable windows, * each can be use to create a physical memory window that maps to a * specific device. Devices are identified by a tuple (target, * attribute). * * - One to configure the access to the CPU to the SDRAM. There are * either 2 (for Dove) or 4 (for other families) windows to map the * SDRAM into the physical address space. * * This driver: * * - Reads out the SDRAM address decoding windows at initialization * time, and fills the mvebu_mbus_dram_info structure with these * informations. The exported function mv_mbus_dram_info() allow * device drivers to get those informations related to the SDRAM * address decoding windows. This is because devices also have their * own windows (configured through registers that are part of each * device register space), and therefore the drivers for Marvell * devices have to configure those device -> SDRAM windows to ensure * that DMA works properly. * * - Provides an API for platform code or device drivers to * dynamically add or remove address decoding windows for the CPU -> |
6275afef7 bus: mvebu-mbus: ... |
38 39 40 |
* device accesses. This API is mvebu_mbus_add_window_by_id(), * mvebu_mbus_add_window_remap_by_id() and * mvebu_mbus_del_window(). |
fddddb52a bus: introduce an... |
41 42 43 44 45 46 |
* * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to * see the list of CPU -> SDRAM windows and their configuration * (file 'sdram') and the list of CPU -> devices windows and their * configuration (file 'devices'). */ |
b15d0b525 bus: mvebu-mbus: ... |
47 |
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
fddddb52a bus: introduce an... |
48 49 50 51 52 53 54 55 56 |
#include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> #include <linux/ioport.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/debugfs.h> |
09752a12f bus: mvebu-mbus: ... |
57 |
#include <linux/log2.h> |
bfa1ce5f3 bus: mvebu-mbus: ... |
58 |
#include <linux/memblock.h> |
a0e89c02d bus: mvebu-mbus: ... |
59 |
#include <linux/syscore_ops.h> |
fddddb52a bus: introduce an... |
60 61 62 63 64 65 66 67 68 69 70 |
/* * DDR target is the same on all platforms. */ #define TARGET_DDR 0 /* * CPU Address Decode Windows registers */ #define WIN_CTRL_OFF 0x0000 #define WIN_CTRL_ENABLE BIT(0) |
8c9e06e64 bus: mvebu-mbus: ... |
71 |
/* Only on HW I/O coherency capable platforms */ |
a0b5cd4ac bus: mvebu-mbus: ... |
72 |
#define WIN_CTRL_SYNCBARRIER BIT(1) |
fddddb52a bus: introduce an... |
73 74 75 76 77 78 79 80 81 82 83 84 |
#define WIN_CTRL_TGT_MASK 0xf0 #define WIN_CTRL_TGT_SHIFT 4 #define WIN_CTRL_ATTR_MASK 0xff00 #define WIN_CTRL_ATTR_SHIFT 8 #define WIN_CTRL_SIZE_MASK 0xffff0000 #define WIN_CTRL_SIZE_SHIFT 16 #define WIN_BASE_OFF 0x0004 #define WIN_BASE_LOW 0xffff0000 #define WIN_BASE_HIGH 0xf #define WIN_REMAP_LO_OFF 0x0008 #define WIN_REMAP_LOW 0xffff0000 #define WIN_REMAP_HI_OFF 0x000c |
a0b5cd4ac bus: mvebu-mbus: ... |
85 86 |
#define UNIT_SYNC_BARRIER_OFF 0x84 #define UNIT_SYNC_BARRIER_ALL 0xFFFF |
fddddb52a bus: introduce an... |
87 88 89 90 91 92 93 94 95 96 97 98 |
#define ATTR_HW_COHERENCY (0x1 << 4) #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) #define DDR_BASE_CS_HIGH_MASK 0xf #define DDR_BASE_CS_LOW_MASK 0xff000000 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) #define DDR_SIZE_ENABLED BIT(0) #define DDR_SIZE_CS_MASK 0x1c #define DDR_SIZE_CS_SHIFT 2 #define DDR_SIZE_MASK 0xff000000 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4) |
a0e89c02d bus: mvebu-mbus: ... |
99 100 101 102 103 104 |
/* Relative to mbusbridge_base */ #define MBUS_BRIDGE_CTRL_OFF 0x0 #define MBUS_BRIDGE_BASE_OFF 0x4 /* Maximum number of windows, for all known platforms */ #define MBUS_WINS_MAX 20 |
fddddb52a bus: introduce an... |
105 106 107 108 |
struct mvebu_mbus_state; struct mvebu_mbus_soc_data { unsigned int num_wins; |
a0e89c02d bus: mvebu-mbus: ... |
109 |
bool has_mbus_bridge; |
fddddb52a bus: introduce an... |
110 |
unsigned int (*win_cfg_offset)(const int win); |
7fdf3d8a0 bus: mvebu-mbus: ... |
111 |
unsigned int (*win_remap_offset)(const int win); |
fddddb52a bus: introduce an... |
112 |
void (*setup_cpu_target)(struct mvebu_mbus_state *s); |
4749c02b8 bus: mvebu-mbus: ... |
113 |
int (*save_cpu_target)(struct mvebu_mbus_state *s, |
fce7b5ae1 bus: mvebu-mbus: ... |
114 |
u32 __iomem *store_addr); |
fddddb52a bus: introduce an... |
115 116 |
int (*show_cpu_target)(struct mvebu_mbus_state *s, struct seq_file *seq, void *v); |
fddddb52a bus: introduce an... |
117 |
}; |
a0e89c02d bus: mvebu-mbus: ... |
118 119 120 121 122 123 124 125 126 |
/* * Used to store the state of one MBus window accross suspend/resume. */ struct mvebu_mbus_win_data { u32 ctrl; u32 base; u32 remap_lo; u32 remap_hi; }; |
fddddb52a bus: introduce an... |
127 128 129 |
struct mvebu_mbus_state { void __iomem *mbuswins_base; void __iomem *sdramwins_base; |
a0e89c02d bus: mvebu-mbus: ... |
130 |
void __iomem *mbusbridge_base; |
4749c02b8 bus: mvebu-mbus: ... |
131 |
phys_addr_t sdramwins_phys_base; |
fddddb52a bus: introduce an... |
132 133 134 |
struct dentry *debugfs_root; struct dentry *debugfs_sdram; struct dentry *debugfs_devs; |
79d946837 bus: mvebu-mbus: ... |
135 136 |
struct resource pcie_mem_aperture; struct resource pcie_io_aperture; |
fddddb52a bus: introduce an... |
137 138 |
const struct mvebu_mbus_soc_data *soc; int hw_io_coherency; |
a0e89c02d bus: mvebu-mbus: ... |
139 140 141 142 143 |
/* Used during suspend/resume */ u32 mbus_bridge_ctrl; u32 mbus_bridge_base; struct mvebu_mbus_win_data wins[MBUS_WINS_MAX]; |
fddddb52a bus: introduce an... |
144 145 146 |
}; static struct mvebu_mbus_state mbus_state; |
bfa1ce5f3 bus: mvebu-mbus: ... |
147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 |
/* * We provide two variants of the mv_mbus_dram_info() function: * * - The normal one, where the described DRAM ranges may overlap with * the I/O windows, but for which the DRAM ranges are guaranteed to * have a power of two size. Such ranges are suitable for the DMA * masters that only DMA between the RAM and the device, which is * actually all devices except the crypto engines. * * - The 'nooverlap' one, where the described DRAM ranges are * guaranteed to not overlap with the I/O windows, but for which the * DRAM ranges will not have power of two sizes. They will only be * aligned on a 64 KB boundary, and have a size multiple of 64 * KB. Such ranges are suitable for the DMA masters that DMA between * the crypto SRAM (which is mapped through an I/O window) and a * device. This is the case for the crypto engines. */ |
fddddb52a bus: introduce an... |
164 |
static struct mbus_dram_target_info mvebu_mbus_dram_info; |
bfa1ce5f3 bus: mvebu-mbus: ... |
165 |
static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap; |
fddddb52a bus: introduce an... |
166 167 168 169 170 |
const struct mbus_dram_target_info *mv_mbus_dram_info(void) { return &mvebu_mbus_dram_info; } EXPORT_SYMBOL_GPL(mv_mbus_dram_info); |
bfa1ce5f3 bus: mvebu-mbus: ... |
171 172 173 174 175 |
const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void) { return &mvebu_mbus_dram_info_nooverlap; } EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap); |
7fdf3d8a0 bus: mvebu-mbus: ... |
176 177 178 179 180 181 |
/* Checks whether the given window has remap capability */ static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus, const int win) { return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP; } |
fddddb52a bus: introduce an... |
182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 |
/* * Functions to manipulate the address decoding windows */ static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus, int win, int *enabled, u64 *base, u32 *size, u8 *target, u8 *attr, u64 *remap) { void __iomem *addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); u32 basereg = readl(addr + WIN_BASE_OFF); u32 ctrlreg = readl(addr + WIN_CTRL_OFF); if (!(ctrlreg & WIN_CTRL_ENABLE)) { *enabled = 0; return; } *enabled = 1; *base = ((u64)basereg & WIN_BASE_HIGH) << 32; *base |= (basereg & WIN_BASE_LOW); *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1; if (target) *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT; if (attr) *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT; if (remap) { |
7fdf3d8a0 bus: mvebu-mbus: ... |
213 214 215 216 217 218 |
if (mvebu_mbus_window_is_remappable(mbus, win)) { u32 remap_low, remap_hi; void __iomem *addr_rmp = mbus->mbuswins_base + mbus->soc->win_remap_offset(win); remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF); remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF); |
fddddb52a bus: introduce an... |
219 220 221 222 223 224 225 226 227 228 229 230 |
*remap = ((u64)remap_hi << 32) | remap_low; } else *remap = 0; } } static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus, int win) { void __iomem *addr; addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); |
fddddb52a bus: introduce an... |
231 232 |
writel(0, addr + WIN_BASE_OFF); writel(0, addr + WIN_CTRL_OFF); |
7fdf3d8a0 bus: mvebu-mbus: ... |
233 234 235 |
if (mvebu_mbus_window_is_remappable(mbus, win)) { addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win); |
fddddb52a bus: introduce an... |
236 237 238 239 240 241 |
writel(0, addr + WIN_REMAP_LO_OFF); writel(0, addr + WIN_REMAP_HI_OFF); } } /* Checks whether the given window number is available */ |
38bdf45f4 bus: mvebu-mbus: ... |
242 |
|
fddddb52a bus: introduce an... |
243 244 245 246 247 248 |
static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus, const int win) { void __iomem *addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); u32 ctrl = readl(addr + WIN_CTRL_OFF); |
38bdf45f4 bus: mvebu-mbus: ... |
249 |
|
fddddb52a bus: introduce an... |
250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 |
return !(ctrl & WIN_CTRL_ENABLE); } /* * Checks whether the given (base, base+size) area doesn't overlap an * existing region */ static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size, u8 target, u8 attr) { u64 end = (u64)base + size; int win; for (win = 0; win < mbus->soc->num_wins; win++) { u64 wbase, wend; u32 wsize; u8 wtarget, wattr; int enabled; mvebu_mbus_read_window(mbus, win, &enabled, &wbase, &wsize, &wtarget, &wattr, NULL); if (!enabled) continue; wend = wbase + wsize; /* * Check if the current window overlaps with the * proposed physical range */ if ((u64)base < wend && end > wbase) return 0; |
fddddb52a bus: introduce an... |
285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 |
} return 1; } static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size) { int win; for (win = 0; win < mbus->soc->num_wins; win++) { u64 wbase; u32 wsize; int enabled; mvebu_mbus_read_window(mbus, win, &enabled, &wbase, &wsize, NULL, NULL, NULL); if (!enabled) continue; if (base == wbase && size == wsize) return win; } return -ENODEV; } static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, int win, phys_addr_t base, size_t size, phys_addr_t remap, u8 target, u8 attr) { void __iomem *addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); u32 ctrl, remap_addr; |
09752a12f bus: mvebu-mbus: ... |
322 323 324 325 326 327 328 329 330 331 332 333 |
if (!is_power_of_2(size)) { WARN(true, "Invalid MBus window size: 0x%zx ", size); return -EINVAL; } if ((base & (phys_addr_t)(size - 1)) != 0) { WARN(true, "Invalid MBus base/size: %pa len 0x%zx ", &base, size); return -EINVAL; } |
fddddb52a bus: introduce an... |
334 335 336 337 |
ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | (attr << WIN_CTRL_ATTR_SHIFT) | (target << WIN_CTRL_TGT_SHIFT) | WIN_CTRL_ENABLE; |
8c9e06e64 bus: mvebu-mbus: ... |
338 339 |
if (mbus->hw_io_coherency) ctrl |= WIN_CTRL_SYNCBARRIER; |
fddddb52a bus: introduce an... |
340 341 342 |
writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF); writel(ctrl, addr + WIN_CTRL_OFF); |
7fdf3d8a0 bus: mvebu-mbus: ... |
343 344 345 346 |
if (mvebu_mbus_window_is_remappable(mbus, win)) { void __iomem *addr_rmp = mbus->mbuswins_base + mbus->soc->win_remap_offset(win); |
fddddb52a bus: introduce an... |
347 348 349 350 |
if (remap == MVEBU_MBUS_NO_REMAP) remap_addr = base; else remap_addr = remap; |
7fdf3d8a0 bus: mvebu-mbus: ... |
351 352 |
writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF); writel(0, addr_rmp + WIN_REMAP_HI_OFF); |
fddddb52a bus: introduce an... |
353 354 355 356 357 358 359 360 361 362 363 364 365 |
} return 0; } static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size, phys_addr_t remap, u8 target, u8 attr) { int win; if (remap == MVEBU_MBUS_NO_REMAP) { |
7fdf3d8a0 bus: mvebu-mbus: ... |
366 367 368 |
for (win = 0; win < mbus->soc->num_wins; win++) { if (mvebu_mbus_window_is_remappable(mbus, win)) continue; |
fddddb52a bus: introduce an... |
369 370 371 372 |
if (mvebu_mbus_window_is_free(mbus, win)) return mvebu_mbus_setup_window(mbus, win, base, size, remap, target, attr); |
7fdf3d8a0 bus: mvebu-mbus: ... |
373 |
} |
fddddb52a bus: introduce an... |
374 |
} |
7fdf3d8a0 bus: mvebu-mbus: ... |
375 376 377 378 379 |
for (win = 0; win < mbus->soc->num_wins; win++) { /* Skip window if need remap but is not supported */ if ((remap != MVEBU_MBUS_NO_REMAP) && !mvebu_mbus_window_is_remappable(mbus, win)) continue; |
fddddb52a bus: introduce an... |
380 |
|
fddddb52a bus: introduce an... |
381 382 383 |
if (mvebu_mbus_window_is_free(mbus, win)) return mvebu_mbus_setup_window(mbus, win, base, size, remap, target, attr); |
7fdf3d8a0 bus: mvebu-mbus: ... |
384 |
} |
fddddb52a bus: introduce an... |
385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 |
return -ENOMEM; } /* * Debugfs debugging */ /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */ static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus, struct seq_file *seq, void *v) { int i; for (i = 0; i < 4; i++) { u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); u64 base; u32 size; if (!(sizereg & DDR_SIZE_ENABLED)) { seq_printf(seq, "[%d] disabled ", i); continue; } base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32; base |= basereg & DDR_BASE_CS_LOW_MASK; size = (sizereg | ~DDR_SIZE_MASK); seq_printf(seq, "[%d] %016llx - %016llx : cs%d ", i, (unsigned long long)base, (unsigned long long)base + size + 1, (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT); } return 0; } /* Special function for Dove */ static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus, struct seq_file *seq, void *v) { int i; for (i = 0; i < 2; i++) { u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); u64 base; u32 size; if (!(map & 1)) { seq_printf(seq, "[%d] disabled ", i); continue; } base = map & 0xff800000; size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); seq_printf(seq, "[%d] %016llx - %016llx : cs%d ", i, (unsigned long long)base, (unsigned long long)base + size, i); } return 0; } static int mvebu_sdram_debug_show(struct seq_file *seq, void *v) { struct mvebu_mbus_state *mbus = &mbus_state; return mbus->soc->show_cpu_target(mbus, seq, v); } static int mvebu_sdram_debug_open(struct inode *inode, struct file *file) { return single_open(file, mvebu_sdram_debug_show, inode->i_private); } static const struct file_operations mvebu_sdram_debug_fops = { .open = mvebu_sdram_debug_open, .read = seq_read, .llseek = seq_lseek, .release = single_release, }; static int mvebu_devs_debug_show(struct seq_file *seq, void *v) { struct mvebu_mbus_state *mbus = &mbus_state; int win; for (win = 0; win < mbus->soc->num_wins; win++) { u64 wbase, wremap; u32 wsize; u8 wtarget, wattr; |
ed843a7d6 bus: mvebu-mbus: ... |
481 |
int enabled; |
fddddb52a bus: introduce an... |
482 483 484 485 486 487 488 489 490 491 |
mvebu_mbus_read_window(mbus, win, &enabled, &wbase, &wsize, &wtarget, &wattr, &wremap); if (!enabled) { seq_printf(seq, "[%02d] disabled ", win); continue; } |
ed843a7d6 bus: mvebu-mbus: ... |
492 |
seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x", |
fddddb52a bus: introduce an... |
493 |
win, (unsigned long long)wbase, |
ed843a7d6 bus: mvebu-mbus: ... |
494 |
(unsigned long long)(wbase + wsize), wtarget, wattr); |
fddddb52a bus: introduce an... |
495 |
|
09752a12f bus: mvebu-mbus: ... |
496 497 498 |
if (!is_power_of_2(wsize) || ((wbase & (u64)(wsize - 1)) != 0)) seq_puts(seq, " (Invalid base/size!!)"); |
7fdf3d8a0 bus: mvebu-mbus: ... |
499 |
if (mvebu_mbus_window_is_remappable(mbus, win)) { |
fddddb52a bus: introduce an... |
500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 |
seq_printf(seq, " (remap %016llx) ", (unsigned long long)wremap); } else seq_printf(seq, " "); } return 0; } static int mvebu_devs_debug_open(struct inode *inode, struct file *file) { return single_open(file, mvebu_devs_debug_show, inode->i_private); } static const struct file_operations mvebu_devs_debug_fops = { .open = mvebu_devs_debug_open, .read = seq_read, .llseek = seq_lseek, .release = single_release, }; /* * SoC-specific functions and definitions */ |
7fdf3d8a0 bus: mvebu-mbus: ... |
526 |
static unsigned int generic_mbus_win_cfg_offset(int win) |
fddddb52a bus: introduce an... |
527 528 529 |
{ return win << 4; } |
7fdf3d8a0 bus: mvebu-mbus: ... |
530 |
static unsigned int armada_370_xp_mbus_win_cfg_offset(int win) |
fddddb52a bus: introduce an... |
531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 |
{ /* The register layout is a bit annoying and the below code * tries to cope with it. * - At offset 0x0, there are the registers for the first 8 * windows, with 4 registers of 32 bits per window (ctrl, * base, remap low, remap high) * - Then at offset 0x80, there is a hole of 0x10 bytes for * the internal registers base address and internal units * sync barrier register. * - Then at offset 0x90, there the registers for 12 * windows, with only 2 registers of 32 bits per window * (ctrl, base). */ if (win < 8) return win << 4; else return 0x90 + ((win - 8) << 3); } |
7fdf3d8a0 bus: mvebu-mbus: ... |
549 |
static unsigned int mv78xx0_mbus_win_cfg_offset(int win) |
fddddb52a bus: introduce an... |
550 551 552 553 554 555 |
{ if (win < 8) return win << 4; else return 0x900 + ((win - 8) << 4); } |
7fdf3d8a0 bus: mvebu-mbus: ... |
556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 |
static unsigned int generic_mbus_win_remap_2_offset(int win) { if (win < 2) return generic_mbus_win_cfg_offset(win); else return MVEBU_MBUS_NO_REMAP; } static unsigned int generic_mbus_win_remap_4_offset(int win) { if (win < 4) return generic_mbus_win_cfg_offset(win); else return MVEBU_MBUS_NO_REMAP; } static unsigned int generic_mbus_win_remap_8_offset(int win) { if (win < 8) return generic_mbus_win_cfg_offset(win); else return MVEBU_MBUS_NO_REMAP; } static unsigned int armada_xp_mbus_win_remap_offset(int win) { if (win < 8) return generic_mbus_win_cfg_offset(win); else if (win == 13) return 0xF0 - WIN_REMAP_LO_OFF; else return MVEBU_MBUS_NO_REMAP; } |
bfa1ce5f3 bus: mvebu-mbus: ... |
589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 |
/* * Use the memblock information to find the MBus bridge hole in the * physical address space. */ static void __init mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end) { struct memblock_region *r; uint64_t s = 0; for_each_memblock(memory, r) { /* * This part of the memory is above 4 GB, so we don't * care for the MBus bridge hole. */ if (r->base >= 0x100000000ULL) continue; /* * The MBus bridge hole is at the end of the RAM under * the 4 GB limit. */ if (r->base + r->size > s) s = r->base + r->size; } *start = s; *end = 0x100000000ULL; } /* * This function fills in the mvebu_mbus_dram_info_nooverlap data * structure, by looking at the mvebu_mbus_dram_info data, and * removing the parts of it that overlap with I/O windows. */ static void __init mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus) { uint64_t mbus_bridge_base, mbus_bridge_end; int cs_nooverlap = 0; int i; mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end); for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) { struct mbus_dram_window *w; u64 base, size, end; w = &mvebu_mbus_dram_info.cs[i]; base = w->base; size = w->size; end = base + size; /* * The CS is fully enclosed inside the MBus bridge * area, so ignore it. */ if (base >= mbus_bridge_base && end <= mbus_bridge_end) continue; /* * Beginning of CS overlaps with end of MBus, raise CS * base address, and shrink its size. */ if (base >= mbus_bridge_base && end > mbus_bridge_end) { size -= mbus_bridge_end - base; base = mbus_bridge_end; } /* * End of CS overlaps with beginning of MBus, shrink * CS size. */ if (base < mbus_bridge_base && end > mbus_bridge_base) size -= end - mbus_bridge_base; w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); if (mbus->hw_io_coherency) w->mbus_attr |= ATTR_HW_COHERENCY; w->base = base; w->size = size; } mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR; mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap; } |
fddddb52a bus: introduce an... |
677 678 679 680 681 682 683 684 685 |
static void __init mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) { int i; int cs; mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 4; i++) { |
885dbd154 Revert "bus: mveb... |
686 687 |
u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); |
1737cac69 bus: mvebu-mbus: ... |
688 689 |
/* |
885dbd154 Revert "bus: mveb... |
690 691 692 693 |
* We only take care of entries for which the chip * select is enabled, and that don't have high base * address bits set (devices can only access the first * 32 bits of the memory). |
1737cac69 bus: mvebu-mbus: ... |
694 |
*/ |
885dbd154 Revert "bus: mveb... |
695 696 697 698 699 700 701 702 703 704 705 |
if ((size & DDR_SIZE_ENABLED) && !(base & DDR_BASE_CS_HIGH_MASK)) { struct mbus_dram_window *w; w = &mvebu_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); if (mbus->hw_io_coherency) w->mbus_attr |= ATTR_HW_COHERENCY; w->base = base & DDR_BASE_CS_LOW_MASK; w->size = (size | ~DDR_SIZE_MASK) + 1; |
fddddb52a bus: introduce an... |
706 707 708 709 |
} } mvebu_mbus_dram_info.num_cs = cs; } |
4749c02b8 bus: mvebu-mbus: ... |
710 711 |
static int mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus, |
fce7b5ae1 bus: mvebu-mbus: ... |
712 |
u32 __iomem *store_addr) |
4749c02b8 bus: mvebu-mbus: ... |
713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 |
{ int i; for (i = 0; i < 4; i++) { u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i), store_addr++); writel(base, store_addr++); writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i), store_addr++); writel(size, store_addr++); } /* We've written 16 words to the store address */ return 16; } |
fddddb52a bus: introduce an... |
731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 |
static void __init mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus) { int i; int cs; mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 2; i++) { u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); /* * Chip select enabled? */ if (map & 1) { struct mbus_dram_window *w; w = &mvebu_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0; /* CS address decoding done inside */ /* the DDR controller, no need to */ /* provide attributes */ w->base = map & 0xff800000; w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); } } mvebu_mbus_dram_info.num_cs = cs; } |
4749c02b8 bus: mvebu-mbus: ... |
760 761 |
static int mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus, |
fce7b5ae1 bus: mvebu-mbus: ... |
762 |
u32 __iomem *store_addr) |
4749c02b8 bus: mvebu-mbus: ... |
763 764 765 766 767 768 769 770 771 772 773 774 775 776 |
{ int i; for (i = 0; i < 2; i++) { u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i), store_addr++); writel(map, store_addr++); } /* We've written 4 words to the store address */ return 4; } |
fce7b5ae1 bus: mvebu-mbus: ... |
777 |
int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr) |
4749c02b8 bus: mvebu-mbus: ... |
778 779 780 |
{ return mbus_state.soc->save_cpu_target(&mbus_state, store_addr); } |
7fdf3d8a0 bus: mvebu-mbus: ... |
781 |
static const struct mvebu_mbus_soc_data armada_370_mbus_data = { |
fddddb52a bus: introduce an... |
782 |
.num_wins = 20, |
a0e89c02d bus: mvebu-mbus: ... |
783 |
.has_mbus_bridge = true, |
7fdf3d8a0 bus: mvebu-mbus: ... |
784 785 786 787 |
.win_cfg_offset = armada_370_xp_mbus_win_cfg_offset, .win_remap_offset = generic_mbus_win_remap_8_offset, .setup_cpu_target = mvebu_mbus_default_setup_cpu_target, .show_cpu_target = mvebu_sdram_debug_show_orion, |
4749c02b8 bus: mvebu-mbus: ... |
788 |
.save_cpu_target = mvebu_mbus_default_save_cpu_target, |
7fdf3d8a0 bus: mvebu-mbus: ... |
789 790 791 792 793 794 795 |
}; static const struct mvebu_mbus_soc_data armada_xp_mbus_data = { .num_wins = 20, .has_mbus_bridge = true, .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset, .win_remap_offset = armada_xp_mbus_win_remap_offset, |
fddddb52a bus: introduce an... |
796 797 |
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target, .show_cpu_target = mvebu_sdram_debug_show_orion, |
7fdf3d8a0 bus: mvebu-mbus: ... |
798 |
.save_cpu_target = mvebu_mbus_default_save_cpu_target, |
fddddb52a bus: introduce an... |
799 800 801 802 |
}; static const struct mvebu_mbus_soc_data kirkwood_mbus_data = { .num_wins = 8, |
7fdf3d8a0 bus: mvebu-mbus: ... |
803 |
.win_cfg_offset = generic_mbus_win_cfg_offset, |
4749c02b8 bus: mvebu-mbus: ... |
804 |
.save_cpu_target = mvebu_mbus_default_save_cpu_target, |
7fdf3d8a0 bus: mvebu-mbus: ... |
805 |
.win_remap_offset = generic_mbus_win_remap_4_offset, |
fddddb52a bus: introduce an... |
806 807 |
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target, .show_cpu_target = mvebu_sdram_debug_show_orion, |
fddddb52a bus: introduce an... |
808 809 810 811 |
}; static const struct mvebu_mbus_soc_data dove_mbus_data = { .num_wins = 8, |
7fdf3d8a0 bus: mvebu-mbus: ... |
812 |
.win_cfg_offset = generic_mbus_win_cfg_offset, |
4749c02b8 bus: mvebu-mbus: ... |
813 |
.save_cpu_target = mvebu_mbus_dove_save_cpu_target, |
7fdf3d8a0 bus: mvebu-mbus: ... |
814 |
.win_remap_offset = generic_mbus_win_remap_4_offset, |
fddddb52a bus: introduce an... |
815 816 |
.setup_cpu_target = mvebu_mbus_dove_setup_cpu_target, .show_cpu_target = mvebu_sdram_debug_show_dove, |
fddddb52a bus: introduce an... |
817 818 819 820 821 822 823 824 |
}; /* * Some variants of Orion5x have 4 remappable windows, some other have * only two of them. */ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = { .num_wins = 8, |
7fdf3d8a0 bus: mvebu-mbus: ... |
825 |
.win_cfg_offset = generic_mbus_win_cfg_offset, |
4749c02b8 bus: mvebu-mbus: ... |
826 |
.save_cpu_target = mvebu_mbus_default_save_cpu_target, |
7fdf3d8a0 bus: mvebu-mbus: ... |
827 |
.win_remap_offset = generic_mbus_win_remap_4_offset, |
fddddb52a bus: introduce an... |
828 829 |
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target, .show_cpu_target = mvebu_sdram_debug_show_orion, |
fddddb52a bus: introduce an... |
830 831 832 833 |
}; static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = { .num_wins = 8, |
7fdf3d8a0 bus: mvebu-mbus: ... |
834 |
.win_cfg_offset = generic_mbus_win_cfg_offset, |
4749c02b8 bus: mvebu-mbus: ... |
835 |
.save_cpu_target = mvebu_mbus_default_save_cpu_target, |
7fdf3d8a0 bus: mvebu-mbus: ... |
836 |
.win_remap_offset = generic_mbus_win_remap_2_offset, |
fddddb52a bus: introduce an... |
837 838 |
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target, .show_cpu_target = mvebu_sdram_debug_show_orion, |
fddddb52a bus: introduce an... |
839 840 841 842 |
}; static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = { .num_wins = 14, |
7fdf3d8a0 bus: mvebu-mbus: ... |
843 |
.win_cfg_offset = mv78xx0_mbus_win_cfg_offset, |
4749c02b8 bus: mvebu-mbus: ... |
844 |
.save_cpu_target = mvebu_mbus_default_save_cpu_target, |
7fdf3d8a0 bus: mvebu-mbus: ... |
845 |
.win_remap_offset = generic_mbus_win_remap_8_offset, |
fddddb52a bus: introduce an... |
846 847 |
.setup_cpu_target = mvebu_mbus_default_setup_cpu_target, .show_cpu_target = mvebu_sdram_debug_show_orion, |
fddddb52a bus: introduce an... |
848 |
}; |
fddddb52a bus: introduce an... |
849 850 |
static const struct of_device_id of_mvebu_mbus_ids[] = { { .compatible = "marvell,armada370-mbus", |
7fdf3d8a0 bus: mvebu-mbus: ... |
851 852 853 854 855 |
.data = &armada_370_mbus_data, }, { .compatible = "marvell,armada375-mbus", .data = &armada_xp_mbus_data, }, { .compatible = "marvell,armada380-mbus", .data = &armada_xp_mbus_data, }, |
fddddb52a bus: introduce an... |
856 |
{ .compatible = "marvell,armadaxp-mbus", |
7fdf3d8a0 bus: mvebu-mbus: ... |
857 |
.data = &armada_xp_mbus_data, }, |
fddddb52a bus: introduce an... |
858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 |
{ .compatible = "marvell,kirkwood-mbus", .data = &kirkwood_mbus_data, }, { .compatible = "marvell,dove-mbus", .data = &dove_mbus_data, }, { .compatible = "marvell,orion5x-88f5281-mbus", .data = &orion5x_4win_mbus_data, }, { .compatible = "marvell,orion5x-88f5182-mbus", .data = &orion5x_2win_mbus_data, }, { .compatible = "marvell,orion5x-88f5181-mbus", .data = &orion5x_2win_mbus_data, }, { .compatible = "marvell,orion5x-88f6183-mbus", .data = &orion5x_4win_mbus_data, }, { .compatible = "marvell,mv78xx0-mbus", .data = &mv78xx0_mbus_data, }, { }, }; /* * Public API of the driver */ |
6a63b098f bus: mvebu-mbus: ... |
878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 |
int mvebu_mbus_add_window_remap_by_id(unsigned int target, unsigned int attribute, phys_addr_t base, size_t size, phys_addr_t remap) { struct mvebu_mbus_state *s = &mbus_state; if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) { pr_err("cannot add window '%x:%x', conflicts with another window ", target, attribute); return -EINVAL; } return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute); } |
6a63b098f bus: mvebu-mbus: ... |
894 895 896 897 898 899 |
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, phys_addr_t base, size_t size) { return mvebu_mbus_add_window_remap_by_id(target, attribute, base, size, MVEBU_MBUS_NO_REMAP); } |
fddddb52a bus: introduce an... |
900 901 902 903 904 905 906 907 908 909 910 |
int mvebu_mbus_del_window(phys_addr_t base, size_t size) { int win; win = mvebu_mbus_find_window(&mbus_state, base, size); if (win < 0) return win; mvebu_mbus_disable_window(&mbus_state, win); return 0; } |
79d946837 bus: mvebu-mbus: ... |
911 912 913 914 915 916 917 918 919 920 921 922 923 |
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res) { if (!res) return; *res = mbus_state.pcie_mem_aperture; } void mvebu_mbus_get_pcie_io_aperture(struct resource *res) { if (!res) return; *res = mbus_state.pcie_io_aperture; } |
f2900acea bus: mvebu-mbus: ... |
924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 |
int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr) { const struct mbus_dram_target_info *dram; int i; /* Get dram info */ dram = mv_mbus_dram_info(); if (!dram) { pr_err("missing DRAM information "); return -ENODEV; } /* Try to find matching DRAM window for phyaddr */ for (i = 0; i < dram->num_cs; i++) { const struct mbus_dram_window *cs = dram->cs + i; if (cs->base <= phyaddr && phyaddr <= (cs->base + cs->size - 1)) { *target = dram->mbus_dram_target_id; *attr = cs->mbus_attr; return 0; } } |
77644ad86 bus: mvebu-mbus: ... |
948 949 |
pr_err("invalid dram address %pa ", &phyaddr); |
f2900acea bus: mvebu-mbus: ... |
950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 |
return -EINVAL; } EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info); int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target, u8 *attr) { int win; for (win = 0; win < mbus_state.soc->num_wins; win++) { u64 wbase; int enabled; mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase, size, target, attr, NULL); if (!enabled) continue; if (wbase <= phyaddr && phyaddr <= wbase + *size) return win; } return -EINVAL; } EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info); |
fddddb52a bus: introduce an... |
976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 |
static __init int mvebu_mbus_debugfs_init(void) { struct mvebu_mbus_state *s = &mbus_state; /* * If no base has been initialized, doesn't make sense to * register the debugfs entries. We may be on a multiplatform * kernel that isn't running a Marvell EBU SoC. */ if (!s->mbuswins_base) return 0; s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL); if (s->debugfs_root) { s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO, s->debugfs_root, NULL, &mvebu_sdram_debug_fops); s->debugfs_devs = debugfs_create_file("devices", S_IRUGO, s->debugfs_root, NULL, &mvebu_devs_debug_fops); } return 0; } fs_initcall(mvebu_mbus_debugfs_init); |
a0e89c02d bus: mvebu-mbus: ... |
1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 |
static int mvebu_mbus_suspend(void) { struct mvebu_mbus_state *s = &mbus_state; int win; if (!s->mbusbridge_base) return -ENODEV; for (win = 0; win < s->soc->num_wins; win++) { void __iomem *addr = s->mbuswins_base + s->soc->win_cfg_offset(win); |
7fdf3d8a0 bus: mvebu-mbus: ... |
1012 |
void __iomem *addr_rmp; |
a0e89c02d bus: mvebu-mbus: ... |
1013 1014 1015 |
s->wins[win].base = readl(addr + WIN_BASE_OFF); s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF); |
7fdf3d8a0 bus: mvebu-mbus: ... |
1016 |
if (!mvebu_mbus_window_is_remappable(s, win)) |
a0e89c02d bus: mvebu-mbus: ... |
1017 |
continue; |
7fdf3d8a0 bus: mvebu-mbus: ... |
1018 1019 1020 1021 1022 |
addr_rmp = s->mbuswins_base + s->soc->win_remap_offset(win); s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF); s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF); |
a0e89c02d bus: mvebu-mbus: ... |
1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 |
} s->mbus_bridge_ctrl = readl(s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF); s->mbus_bridge_base = readl(s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF); return 0; } static void mvebu_mbus_resume(void) { struct mvebu_mbus_state *s = &mbus_state; int win; writel(s->mbus_bridge_ctrl, s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF); writel(s->mbus_bridge_base, s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF); for (win = 0; win < s->soc->num_wins; win++) { void __iomem *addr = s->mbuswins_base + s->soc->win_cfg_offset(win); |
7fdf3d8a0 bus: mvebu-mbus: ... |
1046 |
void __iomem *addr_rmp; |
a0e89c02d bus: mvebu-mbus: ... |
1047 1048 1049 |
writel(s->wins[win].base, addr + WIN_BASE_OFF); writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF); |
7fdf3d8a0 bus: mvebu-mbus: ... |
1050 |
if (!mvebu_mbus_window_is_remappable(s, win)) |
a0e89c02d bus: mvebu-mbus: ... |
1051 |
continue; |
7fdf3d8a0 bus: mvebu-mbus: ... |
1052 1053 1054 1055 1056 |
addr_rmp = s->mbuswins_base + s->soc->win_remap_offset(win); writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF); writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF); |
a0e89c02d bus: mvebu-mbus: ... |
1057 1058 |
} } |
ac29abf38 bus: mvebu-mbus: ... |
1059 |
static struct syscore_ops mvebu_mbus_syscore_ops = { |
a0e89c02d bus: mvebu-mbus: ... |
1060 1061 1062 |
.suspend = mvebu_mbus_suspend, .resume = mvebu_mbus_resume, }; |
6bd6b3cb8 bus: mvebu-mbus: ... |
1063 1064 1065 1066 |
static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, phys_addr_t mbuswins_phys_base, size_t mbuswins_size, phys_addr_t sdramwins_phys_base, |
a0e89c02d bus: mvebu-mbus: ... |
1067 1068 |
size_t sdramwins_size, phys_addr_t mbusbridge_phys_base, |
a0b5cd4ac bus: mvebu-mbus: ... |
1069 1070 |
size_t mbusbridge_size, bool is_coherent) |
fddddb52a bus: introduce an... |
1071 |
{ |
fddddb52a bus: introduce an... |
1072 |
int win; |
fddddb52a bus: introduce an... |
1073 1074 1075 1076 1077 1078 1079 1080 1081 |
mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size); if (!mbus->mbuswins_base) return -ENOMEM; mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size); if (!mbus->sdramwins_base) { iounmap(mbus_state.mbuswins_base); return -ENOMEM; } |
4749c02b8 bus: mvebu-mbus: ... |
1082 |
mbus->sdramwins_phys_base = sdramwins_phys_base; |
a0e89c02d bus: mvebu-mbus: ... |
1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 |
if (mbusbridge_phys_base) { mbus->mbusbridge_base = ioremap(mbusbridge_phys_base, mbusbridge_size); if (!mbus->mbusbridge_base) { iounmap(mbus->sdramwins_base); iounmap(mbus->mbuswins_base); return -ENOMEM; } } else mbus->mbusbridge_base = NULL; |
fddddb52a bus: introduce an... |
1093 1094 1095 1096 |
for (win = 0; win < mbus->soc->num_wins; win++) mvebu_mbus_disable_window(mbus, win); mbus->soc->setup_cpu_target(mbus); |
bfa1ce5f3 bus: mvebu-mbus: ... |
1097 |
mvebu_mbus_setup_cpu_target_nooverlap(mbus); |
fddddb52a bus: introduce an... |
1098 |
|
a0b5cd4ac bus: mvebu-mbus: ... |
1099 1100 1101 |
if (is_coherent) writel(UNIT_SYNC_BARRIER_ALL, mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF); |
a0e89c02d bus: mvebu-mbus: ... |
1102 |
register_syscore_ops(&mvebu_mbus_syscore_ops); |
fddddb52a bus: introduce an... |
1103 1104 |
return 0; } |
6bd6b3cb8 bus: mvebu-mbus: ... |
1105 1106 1107 1108 1109 1110 1111 |
int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base, size_t mbuswins_size, phys_addr_t sdramwins_phys_base, size_t sdramwins_size) { const struct of_device_id *of_id; |
7663cfd3f bus: mvebu-mbus: ... |
1112 |
for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++) |
6bd6b3cb8 bus: mvebu-mbus: ... |
1113 1114 |
if (!strcmp(of_id->compatible, soc)) break; |
7663cfd3f bus: mvebu-mbus: ... |
1115 |
if (!of_id->compatible[0]) { |
6bd6b3cb8 bus: mvebu-mbus: ... |
1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 |
pr_err("could not find a matching SoC family "); return -ENODEV; } mbus_state.soc = of_id->data; return mvebu_mbus_common_init(&mbus_state, mbuswins_phys_base, mbuswins_size, sdramwins_phys_base, |
a0b5cd4ac bus: mvebu-mbus: ... |
1127 |
sdramwins_size, 0, 0, false); |
6bd6b3cb8 bus: mvebu-mbus: ... |
1128 |
} |
6839cfa82 bus: mvebu-mbus: ... |
1129 1130 |
#ifdef CONFIG_OF |
bb24cab39 bus: mvebu-mbus: ... |
1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 |
/* * The window IDs in the ranges DT property have the following format: * - bits 28 to 31: MBus custom field * - bits 24 to 27: window target ID * - bits 16 to 23: window attribute ID * - bits 0 to 15: unused */ #define CUSTOM(id) (((id) & 0xF0000000) >> 24) #define TARGET(id) (((id) & 0x0F000000) >> 24) #define ATTR(id) (((id) & 0x00FF0000) >> 16) static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus, u32 base, u32 size, u8 target, u8 attr) { |
bb24cab39 bus: mvebu-mbus: ... |
1146 |
if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) { |
ed843a7d6 bus: mvebu-mbus: ... |
1147 1148 1149 |
pr_err("cannot add window '%04x:%04x', conflicts with another window ", target, attr); |
bb24cab39 bus: mvebu-mbus: ... |
1150 1151 1152 1153 1154 |
return -EBUSY; } if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP, target, attr)) { |
ed843a7d6 bus: mvebu-mbus: ... |
1155 1156 1157 |
pr_err("cannot add window '%04x:%04x', too many windows ", target, attr); |
bb24cab39 bus: mvebu-mbus: ... |
1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 |
return -ENOMEM; } return 0; } static int __init mbus_parse_ranges(struct device_node *node, int *addr_cells, int *c_addr_cells, int *c_size_cells, int *cell_count, const __be32 **ranges_start, const __be32 **ranges_end) { const __be32 *prop; int ranges_len, tuple_len; /* Allow a node with no 'ranges' property */ *ranges_start = of_get_property(node, "ranges", &ranges_len); if (*ranges_start == NULL) { *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0; *ranges_start = *ranges_end = NULL; return 0; } *ranges_end = *ranges_start + ranges_len / sizeof(__be32); *addr_cells = of_n_addr_cells(node); prop = of_get_property(node, "#address-cells", NULL); *c_addr_cells = be32_to_cpup(prop); prop = of_get_property(node, "#size-cells", NULL); *c_size_cells = be32_to_cpup(prop); *cell_count = *addr_cells + *c_addr_cells + *c_size_cells; tuple_len = (*cell_count) * sizeof(__be32); if (ranges_len % tuple_len) { pr_warn("malformed ranges entry '%s' ", node->name); return -EINVAL; } return 0; } static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus, struct device_node *np) { int addr_cells, c_addr_cells, c_size_cells; int i, ret, cell_count; const __be32 *r, *ranges_start, *ranges_end; ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells, &c_size_cells, &cell_count, &ranges_start, &ranges_end); if (ret < 0) return ret; for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) { u32 windowid, base, size; u8 target, attr; /* * An entry with a non-zero custom field do not * correspond to a static window, so skip it. */ windowid = of_read_number(r, 1); if (CUSTOM(windowid)) continue; target = TARGET(windowid); attr = ATTR(windowid); base = of_read_number(r + c_addr_cells, addr_cells); size = of_read_number(r + c_addr_cells + addr_cells, c_size_cells); ret = mbus_dt_setup_win(mbus, base, size, target, attr); if (ret < 0) return ret; } return 0; } |
79d946837 bus: mvebu-mbus: ... |
1237 1238 1239 1240 1241 1242 1243 1244 |
static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, struct resource *mem, struct resource *io) { u32 reg[2]; int ret; /* |
8553bcad3 bus: mvebu-mbus: ... |
1245 1246 |
* These are optional, so we make sure that resource_size(x) will * return 0. |
79d946837 bus: mvebu-mbus: ... |
1247 1248 |
*/ memset(mem, 0, sizeof(struct resource)); |
8553bcad3 bus: mvebu-mbus: ... |
1249 |
mem->end = -1; |
79d946837 bus: mvebu-mbus: ... |
1250 |
memset(io, 0, sizeof(struct resource)); |
8553bcad3 bus: mvebu-mbus: ... |
1251 |
io->end = -1; |
79d946837 bus: mvebu-mbus: ... |
1252 1253 1254 1255 |
ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg)); if (!ret) { mem->start = reg[0]; |
a723e7523 bus: mvebu-mbus: ... |
1256 |
mem->end = mem->start + reg[1] - 1; |
79d946837 bus: mvebu-mbus: ... |
1257 1258 1259 1260 1261 1262 |
mem->flags = IORESOURCE_MEM; } ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg)); if (!ret) { io->start = reg[0]; |
a723e7523 bus: mvebu-mbus: ... |
1263 |
io->end = io->start + reg[1] - 1; |
79d946837 bus: mvebu-mbus: ... |
1264 1265 1266 |
io->flags = IORESOURCE_IO; } } |
5686a1e5a bus: mvebu: pass ... |
1267 |
int __init mvebu_mbus_dt_init(bool is_coherent) |
6839cfa82 bus: mvebu-mbus: ... |
1268 |
{ |
a0e89c02d bus: mvebu-mbus: ... |
1269 |
struct resource mbuswins_res, sdramwins_res, mbusbridge_res; |
6839cfa82 bus: mvebu-mbus: ... |
1270 1271 1272 1273 |
struct device_node *np, *controller; const struct of_device_id *of_id; const __be32 *prop; int ret; |
087a4ab27 bus: mvebu-mbus: ... |
1274 |
np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id); |
6839cfa82 bus: mvebu-mbus: ... |
1275 1276 1277 1278 1279 |
if (!np) { pr_err("could not find a matching SoC family "); return -ENODEV; } |
6839cfa82 bus: mvebu-mbus: ... |
1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 |
mbus_state.soc = of_id->data; prop = of_get_property(np, "controller", NULL); if (!prop) { pr_err("required 'controller' property missing "); return -EINVAL; } controller = of_find_node_by_phandle(be32_to_cpup(prop)); if (!controller) { pr_err("could not find an 'mbus-controller' node "); return -ENODEV; } if (of_address_to_resource(controller, 0, &mbuswins_res)) { pr_err("cannot get MBUS register address "); return -EINVAL; } if (of_address_to_resource(controller, 1, &sdramwins_res)) { pr_err("cannot get SDRAM register address "); return -EINVAL; } |
a0e89c02d bus: mvebu-mbus: ... |
1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 |
/* * Set the resource to 0 so that it can be left unmapped by * mvebu_mbus_common_init() if the DT doesn't carry the * necessary information. This is needed to preserve backward * compatibility. */ memset(&mbusbridge_res, 0, sizeof(mbusbridge_res)); if (mbus_state.soc->has_mbus_bridge) { if (of_address_to_resource(controller, 2, &mbusbridge_res)) pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work "); } |
5686a1e5a bus: mvebu: pass ... |
1320 |
mbus_state.hw_io_coherency = is_coherent; |
79d946837 bus: mvebu-mbus: ... |
1321 1322 1323 |
/* Get optional pcie-{mem,io}-aperture properties */ mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture, &mbus_state.pcie_io_aperture); |
6839cfa82 bus: mvebu-mbus: ... |
1324 1325 1326 1327 |
ret = mvebu_mbus_common_init(&mbus_state, mbuswins_res.start, resource_size(&mbuswins_res), sdramwins_res.start, |
a0e89c02d bus: mvebu-mbus: ... |
1328 1329 |
resource_size(&sdramwins_res), mbusbridge_res.start, |
a0b5cd4ac bus: mvebu-mbus: ... |
1330 1331 |
resource_size(&mbusbridge_res), is_coherent); |
bb24cab39 bus: mvebu-mbus: ... |
1332 1333 1334 1335 1336 |
if (ret) return ret; /* Setup statically declared windows in the DT */ return mbus_dt_setup(&mbus_state, np); |
6839cfa82 bus: mvebu-mbus: ... |
1337 1338 |
} #endif |