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drivers/crypto/hifn_795x.c
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/* * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru> * All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. |
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*/ #include <linux/kernel.h> #include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/mod_devicetable.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/mm.h> |
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#include <linux/dma-mapping.h> #include <linux/scatterlist.h> |
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#include <linux/highmem.h> #include <linux/crypto.h> |
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#include <linux/hw_random.h> #include <linux/ktime.h> |
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#include <crypto/algapi.h> |
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#include <crypto/des.h> |
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static char hifn_pll_ref[sizeof("extNNN")] = "ext"; module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444); MODULE_PARM_DESC(hifn_pll_ref, "PLL reference clock (pci[freq] or ext[freq], default ext)"); |
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static atomic_t hifn_dev_number; #define ACRYPTO_OP_DECRYPT 0 #define ACRYPTO_OP_ENCRYPT 1 #define ACRYPTO_OP_HMAC 2 #define ACRYPTO_OP_RNG 3 #define ACRYPTO_MODE_ECB 0 #define ACRYPTO_MODE_CBC 1 #define ACRYPTO_MODE_CFB 2 #define ACRYPTO_MODE_OFB 3 #define ACRYPTO_TYPE_AES_128 0 #define ACRYPTO_TYPE_AES_192 1 #define ACRYPTO_TYPE_AES_256 2 #define ACRYPTO_TYPE_3DES 3 #define ACRYPTO_TYPE_DES 4 #define PCI_VENDOR_ID_HIFN 0x13A3 #define PCI_DEVICE_ID_HIFN_7955 0x0020 #define PCI_DEVICE_ID_HIFN_7956 0x001d /* I/O region sizes */ #define HIFN_BAR0_SIZE 0x1000 #define HIFN_BAR1_SIZE 0x2000 #define HIFN_BAR2_SIZE 0x8000 /* DMA registres */ |
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#define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */ #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */ |
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#define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */ #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */ #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */ |
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#define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */ |
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#define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */ #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */ #define HIFN_CHIP_ID 0x98 /* Chip ID */ /* * Processing Unit Registers (offset from BASEREG0) */ #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ #define HIFN_0_SPACESIZE 0x20 /* Register space size */ /* Processing Unit Control Register (HIFN_0_PUCTRL) */ #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ /* FIFO Status Register (HIFN_0_FIFOSTAT) */ #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */ /* * DMA Interface Registers (offset from BASEREG1) */ #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ #define HIFN_1_PLL 0x4c /* 795x: PLL config */ #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ #define HIFN_1_REVID 0x98 /* Revision ID */ #define HIFN_1_UNLOCK_SECRET1 0xf4 #define HIFN_1_UNLOCK_SECRET2 0xfc #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */ #define HIFN_1_PUB_OP 0x308 /* Public Operand */ #define HIFN_1_PUB_STATUS 0x30c /* Public Status */ #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ #define HIFN_1_RNG_DATA 0x318 /* RNG data */ #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ /* DMA Status and Control Register (HIFN_1_DMA_CSR) */ #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ /* DMA Configuration Register (HIFN_1_DMA_CNFG) */ #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ #define HIFN_DMACNFG_UNLOCK 0x00000800 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ |
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/* PLL configuration register */ #define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */ #define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */ #define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */ #define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */ #define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */ #define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */ #define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */ #define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */ #define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */ #define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */ #define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */ #define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */ #define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */ #define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */ #define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */ #define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */ #define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */ #define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */ |
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/* Public key reset register (HIFN_1_PUB_RESET) */ #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ /* Public base address register (HIFN_1_PUB_BASE) */ #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */ /* Public operand length register (HIFN_1_PUB_OPLEN) */ #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */ #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */ #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */ |
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#define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */ |
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#define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */ #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */ /* Public operation register (HIFN_1_PUB_OP) */ #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */ #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */ #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */ #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */ #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */ #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */ #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */ #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */ /* Public status register (HIFN_1_PUB_STATUS) */ #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ /* Public interrupt enable register (HIFN_1_PUB_IEN) */ #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ /* Random number generator config register (HIFN_1_RNG_CONFIG) */ #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ #define HIFN_NAMESIZE 32 #define HIFN_MAX_RESULT_ORDER 5 |
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#define HIFN_D_CMD_RSIZE (24 * 1) #define HIFN_D_SRC_RSIZE (80 * 1) #define HIFN_D_DST_RSIZE (80 * 1) #define HIFN_D_RES_RSIZE (24 * 1) |
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#define HIFN_D_DST_DALIGN 4 |
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#define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1) |
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#define AES_MIN_KEY_SIZE 16 #define AES_MAX_KEY_SIZE 32 #define HIFN_DES_KEY_LENGTH 8 #define HIFN_3DES_KEY_LENGTH 24 #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE #define HIFN_IV_LENGTH 8 #define HIFN_AES_IV_LENGTH 16 #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH #define HIFN_MAC_KEY_LENGTH 64 #define HIFN_MD5_LENGTH 16 #define HIFN_SHA1_LENGTH 20 #define HIFN_MAC_TRUNC_LENGTH 12 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4) #define HIFN_USED_RESULT 12 |
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struct hifn_desc { |
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volatile __le32 l; volatile __le32 p; |
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}; struct hifn_dma { |
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struct hifn_desc cmdr[HIFN_D_CMD_RSIZE + 1]; struct hifn_desc srcr[HIFN_D_SRC_RSIZE + 1]; struct hifn_desc dstr[HIFN_D_DST_RSIZE + 1]; struct hifn_desc resr[HIFN_D_RES_RSIZE + 1]; |
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u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; |
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/* * Our current positions for insertion and removal from the descriptor * rings. */ volatile int cmdi, srci, dsti, resi; volatile int cmdu, srcu, dstu, resu; int cmdk, srck, dstk, resk; }; |
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#define HIFN_FLAG_CMD_BUSY (1 << 0) #define HIFN_FLAG_SRC_BUSY (1 << 1) #define HIFN_FLAG_DST_BUSY (1 << 2) #define HIFN_FLAG_RES_BUSY (1 << 3) #define HIFN_FLAG_OLD_KEY (1 << 4) |
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#define HIFN_DEFAULT_ACTIVE_NUM 5 |
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struct hifn_device { |
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char name[HIFN_NAMESIZE]; int irq; struct pci_dev *pdev; void __iomem *bar[3]; |
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void *desc_virt; dma_addr_t desc_dma; u32 dmareg; |
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void *sa[HIFN_D_RES_RSIZE]; |
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spinlock_t lock; |
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u32 flags; int active, started; struct delayed_work work; unsigned long reset; unsigned long success; unsigned long prev_success; u8 snum; |
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struct tasklet_struct tasklet; |
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struct crypto_queue queue; |
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struct list_head alg_list; |
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424 425 |
unsigned int pk_clk_freq; |
f881d8290 [HIFN]: Fix inval... |
426 |
#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd067559 [HIFN]: Add suppo... |
427 428 429 430 |
unsigned int rng_wait_time; ktime_t rngtime; struct hwrng rng; #endif |
f7d0561ea [CRYPTO] hifn_795... |
431 432 433 434 435 436 437 438 439 440 |
}; #define HIFN_D_LENGTH 0x0000ffff #define HIFN_D_NOINVALID 0x01000000 #define HIFN_D_MASKDONEIRQ 0x02000000 #define HIFN_D_DESTOVER 0x04000000 #define HIFN_D_OVER 0x08000000 #define HIFN_D_LAST 0x20000000 #define HIFN_D_JUMP 0x40000000 #define HIFN_D_VALID 0x80000000 |
16f56e8b7 crypto: hifn_795x... |
441 |
struct hifn_base_command { |
e68970cdd drivers/crypto/hi... |
442 443 444 445 |
volatile __le16 masks; volatile __le16 session_num; volatile __le16 total_source_count; volatile __le16 total_dest_count; |
f7d0561ea [CRYPTO] hifn_795... |
446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 |
}; #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */ #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */ #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */ #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */ #define HIFN_BASE_CMD_DECODE 0x2000 #define HIFN_BASE_CMD_SRCLEN_M 0xc000 #define HIFN_BASE_CMD_SRCLEN_S 14 #define HIFN_BASE_CMD_DSTLEN_M 0x3000 #define HIFN_BASE_CMD_DSTLEN_S 12 #define HIFN_BASE_CMD_LENMASK_HI 0x30000 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff /* * Structure to help build up the command data structure. */ |
16f56e8b7 crypto: hifn_795x... |
463 464 465 466 467 |
struct hifn_crypt_command { volatile __le16 masks; volatile __le16 header_skip; volatile __le16 source_count; volatile __le16 reserved; |
f7d0561ea [CRYPTO] hifn_795... |
468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 |
}; #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 #define HIFN_CRYPT_CMD_SRCLEN_S 14 /* * Structure to help build up the command data structure. */ |
16f56e8b7 crypto: hifn_795x... |
493 494 495 496 497 |
struct hifn_mac_command { volatile __le16 masks; volatile __le16 header_skip; volatile __le16 source_count; volatile __le16 reserved; |
f7d0561ea [CRYPTO] hifn_795... |
498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 |
}; #define HIFN_MAC_CMD_ALG_MASK 0x0001 #define HIFN_MAC_CMD_ALG_SHA1 0x0000 #define HIFN_MAC_CMD_ALG_MD5 0x0001 #define HIFN_MAC_CMD_MODE_MASK 0x000c #define HIFN_MAC_CMD_MODE_HMAC 0x0000 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 #define HIFN_MAC_CMD_MODE_HASH 0x0008 #define HIFN_MAC_CMD_MODE_FULL 0x0004 #define HIFN_MAC_CMD_TRUNC 0x0010 #define HIFN_MAC_CMD_RESULT 0x0020 #define HIFN_MAC_CMD_APPEND 0x0040 #define HIFN_MAC_CMD_SRCLEN_M 0xc000 #define HIFN_MAC_CMD_SRCLEN_S 14 /* * MAC POS IPsec initiates authentication after encryption on encodes * and before decryption on decodes. */ #define HIFN_MAC_CMD_POS_IPSEC 0x0200 #define HIFN_MAC_CMD_NEW_KEY 0x0800 |
16f56e8b7 crypto: hifn_795x... |
520 521 522 523 524 |
struct hifn_comp_command { volatile __le16 masks; volatile __le16 header_skip; volatile __le16 source_count; volatile __le16 reserved; |
f7d0561ea [CRYPTO] hifn_795... |
525 526 527 528 529 530 531 532 533 534 535 536 |
}; #define HIFN_COMP_CMD_SRCLEN_M 0xc000 #define HIFN_COMP_CMD_SRCLEN_S 14 #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */ #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */ #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */ #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */ #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */ #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */ #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */ #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */ |
16f56e8b7 crypto: hifn_795x... |
537 538 539 540 541 |
struct hifn_base_result { volatile __le16 flags; volatile __le16 session; volatile __le16 src_cnt; /* 15:0 of source count */ volatile __le16 dst_cnt; /* 15:0 of dest count */ |
f7d0561ea [CRYPTO] hifn_795... |
542 543 544 545 546 547 548 |
}; #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */ #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */ #define HIFN_BASE_RES_SRCLEN_S 14 #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */ #define HIFN_BASE_RES_DSTLEN_S 12 |
16f56e8b7 crypto: hifn_795x... |
549 |
struct hifn_comp_result { |
3c42cbc2e [HIFN]: Endianess... |
550 551 |
volatile __le16 flags; volatile __le16 crc; |
f7d0561ea [CRYPTO] hifn_795... |
552 553 554 555 556 557 558 |
}; #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */ #define HIFN_COMP_RES_LCB_S 8 #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */ #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */ #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */ |
16f56e8b7 crypto: hifn_795x... |
559 560 561 |
struct hifn_mac_result { volatile __le16 flags; volatile __le16 reserved; |
f7d0561ea [CRYPTO] hifn_795... |
562 563 564 565 566 |
/* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */ }; #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */ #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */ |
16f56e8b7 crypto: hifn_795x... |
567 |
struct hifn_crypt_result { |
3c42cbc2e [HIFN]: Endianess... |
568 569 |
volatile __le16 flags; volatile __le16 reserved; |
f7d0561ea [CRYPTO] hifn_795... |
570 571 572 573 574 575 576 577 578 579 580 |
}; #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */ #ifndef HIFN_POLL_FREQUENCY #define HIFN_POLL_FREQUENCY 0x1 #endif #ifndef HIFN_POLL_SCALAR #define HIFN_POLL_SCALAR 0x0 #endif |
16f56e8b7 crypto: hifn_795x... |
581 |
#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ |
f7d0561ea [CRYPTO] hifn_795... |
582 |
#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ |
16f56e8b7 crypto: hifn_795x... |
583 |
struct hifn_crypto_alg { |
f7d0561ea [CRYPTO] hifn_795... |
584 585 586 587 588 589 |
struct list_head entry; struct crypto_alg alg; struct hifn_device *dev; }; #define ASYNC_SCATTERLIST_CACHE 16 |
16f56e8b7 crypto: hifn_795x... |
590 |
#define ASYNC_FLAGS_MISALIGNED (1 << 0) |
f7d0561ea [CRYPTO] hifn_795... |
591 |
|
16f56e8b7 crypto: hifn_795x... |
592 |
struct hifn_cipher_walk { |
f7d0561ea [CRYPTO] hifn_795... |
593 594 595 596 |
struct scatterlist cache[ASYNC_SCATTERLIST_CACHE]; u32 flags; int num; }; |
16f56e8b7 crypto: hifn_795x... |
597 |
struct hifn_context { |
5df4c0c67 crypto: hifn_795x... |
598 |
u8 key[HIFN_MAX_CRYPT_KEY_LENGTH]; |
f7d0561ea [CRYPTO] hifn_795... |
599 |
struct hifn_device *dev; |
5df4c0c67 crypto: hifn_795x... |
600 601 |
unsigned int keysize; }; |
16f56e8b7 crypto: hifn_795x... |
602 |
struct hifn_request_context { |
5df4c0c67 crypto: hifn_795x... |
603 604 |
u8 *iv; unsigned int ivsize; |
f7d0561ea [CRYPTO] hifn_795... |
605 |
u8 op, type, mode, unused; |
3385329a0 crypto: hifn_795x... |
606 |
struct hifn_cipher_walk walk; |
f7d0561ea [CRYPTO] hifn_795... |
607 |
}; |
b966b5465 [CRYPTO] hifn_795... |
608 |
#define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg) |
f7d0561ea [CRYPTO] hifn_795... |
609 610 611 |
static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg) { |
36e09e1f8 crypto: squash li... |
612 |
return readl(dev->bar[0] + reg); |
f7d0561ea [CRYPTO] hifn_795... |
613 614 615 616 |
} static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg) { |
36e09e1f8 crypto: squash li... |
617 |
return readl(dev->bar[1] + reg); |
f7d0561ea [CRYPTO] hifn_795... |
618 619 620 621 |
} static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) { |
3c42cbc2e [HIFN]: Endianess... |
622 |
writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); |
f7d0561ea [CRYPTO] hifn_795... |
623 624 625 626 |
} static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) { |
3c42cbc2e [HIFN]: Endianess... |
627 |
writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); |
f7d0561ea [CRYPTO] hifn_795... |
628 629 630 631 632 633 |
} static void hifn_wait_puc(struct hifn_device *dev) { int i; u32 ret; |
16f56e8b7 crypto: hifn_795x... |
634 |
for (i = 10000; i > 0; --i) { |
f7d0561ea [CRYPTO] hifn_795... |
635 636 637 638 639 640 641 642 |
ret = hifn_read_0(dev, HIFN_0_PUCTRL); if (!(ret & HIFN_PUCTRL_RESET)) break; udelay(1); } if (!i) |
cfeecab44 crypto: hifn_795x... |
643 644 |
dev_err(&dev->pdev->dev, "Failed to reset PUC unit. "); |
f7d0561ea [CRYPTO] hifn_795... |
645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 |
} static void hifn_reset_puc(struct hifn_device *dev) { hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); hifn_wait_puc(dev); } static void hifn_stop_device(struct hifn_device *dev) { hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS); hifn_write_0(dev, HIFN_0_PUIER, 0); hifn_write_1(dev, HIFN_1_DMA_IER, 0); } static void hifn_reset_dma(struct hifn_device *dev, int full) { hifn_stop_device(dev); /* * Setting poll frequency and others to 0. */ hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); mdelay(1); /* * Reset DMA. */ if (full) { hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); mdelay(1); } else { hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); hifn_reset_puc(dev); } hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); hifn_reset_puc(dev); } |
16f56e8b7 crypto: hifn_795x... |
690 |
static u32 hifn_next_signature(u32 a, u_int cnt) |
f7d0561ea [CRYPTO] hifn_795... |
691 692 693 694 695 |
{ int i; u32 v; for (i = 0; i < cnt; i++) { |
f7d0561ea [CRYPTO] hifn_795... |
696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 |
/* get the parity */ v = a & 0x80080125; v ^= v >> 16; v ^= v >> 8; v ^= v >> 4; v ^= v >> 2; v ^= v >> 1; a = (v & 1) ^ (a << 1); } return a; } static struct pci2id { u_short pci_vendor; u_short pci_prod; char card_id[13]; } pci2id[] = { { PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, { PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } }; |
f881d8290 [HIFN]: Fix inval... |
728 |
#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd067559 [HIFN]: Add suppo... |
729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 |
static int hifn_rng_data_present(struct hwrng *rng, int wait) { struct hifn_device *dev = (struct hifn_device *)rng->priv; s64 nsec; nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime)); nsec -= dev->rng_wait_time; if (nsec <= 0) return 1; if (!wait) return 0; ndelay(nsec); return 1; } static int hifn_rng_data_read(struct hwrng *rng, u32 *data) { struct hifn_device *dev = (struct hifn_device *)rng->priv; *data = hifn_read_1(dev, HIFN_1_RNG_DATA); dev->rngtime = ktime_get(); return 4; } static int hifn_register_rng(struct hifn_device *dev) { /* * We must wait at least 256 Pk_clk cycles between two reads of the rng. */ |
76f16f83e crypto: hifn_795x... |
758 759 |
dev->rng_wait_time = DIV_ROUND_UP_ULL(NSEC_PER_SEC, dev->pk_clk_freq) * 256; |
fcd067559 [HIFN]: Add suppo... |
760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 |
dev->rng.name = dev->name; dev->rng.data_present = hifn_rng_data_present, dev->rng.data_read = hifn_rng_data_read, dev->rng.priv = (unsigned long)dev; return hwrng_register(&dev->rng); } static void hifn_unregister_rng(struct hifn_device *dev) { hwrng_unregister(&dev->rng); } #else #define hifn_register_rng(dev) 0 #define hifn_unregister_rng(dev) #endif |
f7d0561ea [CRYPTO] hifn_795... |
777 778 779 780 781 782 |
static int hifn_init_pubrng(struct hifn_device *dev) { int i; hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); |
16f56e8b7 crypto: hifn_795x... |
783 |
for (i = 100; i > 0; --i) { |
f7d0561ea [CRYPTO] hifn_795... |
784 785 786 787 788 |
mdelay(1); if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0) break; } |
16f56e8b7 crypto: hifn_795x... |
789 |
if (!i) { |
cfeecab44 crypto: hifn_795x... |
790 791 |
dev_err(&dev->pdev->dev, "Failed to initialise public key engine. "); |
16f56e8b7 crypto: hifn_795x... |
792 |
} else { |
f7d0561ea [CRYPTO] hifn_795... |
793 794 795 |
hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); dev->dmareg |= HIFN_DMAIER_PUBDONE; hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); |
cfeecab44 crypto: hifn_795x... |
796 797 |
dev_dbg(&dev->pdev->dev, "Public key engine has been successfully initialised. "); |
f7d0561ea [CRYPTO] hifn_795... |
798 |
} |
16f56e8b7 crypto: hifn_795x... |
799 |
/* Enable RNG engine. */ |
f7d0561ea [CRYPTO] hifn_795... |
800 801 802 |
hifn_write_1(dev, HIFN_1_RNG_CONFIG, hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA); |
cfeecab44 crypto: hifn_795x... |
803 804 |
dev_dbg(&dev->pdev->dev, "RNG engine has been successfully initialised. "); |
f7d0561ea [CRYPTO] hifn_795... |
805 |
|
f881d8290 [HIFN]: Fix inval... |
806 |
#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd067559 [HIFN]: Add suppo... |
807 808 809 810 |
/* First value must be discarded */ hifn_read_1(dev, HIFN_1_RNG_DATA); dev->rngtime = ktime_get(); #endif |
f7d0561ea [CRYPTO] hifn_795... |
811 812 813 814 815 816 817 818 |
return 0; } static int hifn_enable_crypto(struct hifn_device *dev) { u32 dmacfg, addr; char *offtbl = NULL; int i; |
0936a9440 [CRYPTO] hifn: Si... |
819 |
for (i = 0; i < ARRAY_SIZE(pci2id); i++) { |
f7d0561ea [CRYPTO] hifn_795... |
820 821 822 823 824 825 |
if (pci2id[i].pci_vendor == dev->pdev->vendor && pci2id[i].pci_prod == dev->pdev->device) { offtbl = pci2id[i].card_id; break; } } |
16f56e8b7 crypto: hifn_795x... |
826 |
if (!offtbl) { |
cfeecab44 crypto: hifn_795x... |
827 828 |
dev_err(&dev->pdev->dev, "Unknown card! "); |
f7d0561ea [CRYPTO] hifn_795... |
829 830 831 832 833 834 835 836 837 838 839 840 841 |
return -ENODEV; } dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG); hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); mdelay(1); addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1); mdelay(1); hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0); mdelay(1); |
16f56e8b7 crypto: hifn_795x... |
842 |
for (i = 0; i < 12; ++i) { |
f7d0561ea [CRYPTO] hifn_795... |
843 844 845 846 847 848 |
addr = hifn_next_signature(addr, offtbl[i] + 0x101); hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr); mdelay(1); } hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg); |
cfeecab44 crypto: hifn_795x... |
849 850 |
dev_dbg(&dev->pdev->dev, "%s %s. ", dev->name, pci_name(dev->pdev)); |
f7d0561ea [CRYPTO] hifn_795... |
851 852 853 854 855 856 857 858 859 |
return 0; } static void hifn_init_dma(struct hifn_device *dev) { struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; u32 dptr = dev->desc_dma; int i; |
16f56e8b7 crypto: hifn_795x... |
860 |
for (i = 0; i < HIFN_D_CMD_RSIZE; ++i) |
f7d0561ea [CRYPTO] hifn_795... |
861 862 |
dma->cmdr[i].p = __cpu_to_le32(dptr + offsetof(struct hifn_dma, command_bufs[i][0])); |
16f56e8b7 crypto: hifn_795x... |
863 |
for (i = 0; i < HIFN_D_RES_RSIZE; ++i) |
f7d0561ea [CRYPTO] hifn_795... |
864 865 |
dma->resr[i].p = __cpu_to_le32(dptr + offsetof(struct hifn_dma, result_bufs[i][0])); |
16f56e8b7 crypto: hifn_795x... |
866 |
/* Setup LAST descriptors. */ |
f7d0561ea [CRYPTO] hifn_795... |
867 868 869 870 871 872 873 874 875 876 877 878 879 |
dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr + offsetof(struct hifn_dma, cmdr[0])); dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr + offsetof(struct hifn_dma, srcr[0])); dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr + offsetof(struct hifn_dma, dstr[0])); dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr + offsetof(struct hifn_dma, resr[0])); dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; } |
37a8023ce [HIFN]: Improve P... |
880 881 882 883 884 |
/* * Initialize the PLL. We need to know the frequency of the reference clock * to calculate the optimal multiplier. For PCI we assume 66MHz, since that * allows us to operate without the risk of overclocking the chip. If it * actually uses 33MHz, the chip will operate at half the speed, this can be |
16f56e8b7 crypto: hifn_795x... |
885 |
* overridden by specifying the frequency as module parameter (pci33). |
37a8023ce [HIFN]: Improve P... |
886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 |
* * Unfortunately the PCI clock is not very suitable since the HIFN needs a * stable clock and the PCI clock frequency may vary, so the default is the * external clock. There is no way to find out its frequency, we default to * 66MHz since according to Mike Ham of HiFn, almost every board in existence * has an external crystal populated at 66MHz. */ static void hifn_init_pll(struct hifn_device *dev) { unsigned int freq, m; u32 pllcfg; pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1; if (strncmp(hifn_pll_ref, "ext", 3) == 0) pllcfg |= HIFN_PLL_REF_CLK_PLL; else pllcfg |= HIFN_PLL_REF_CLK_HBI; if (hifn_pll_ref[3] != '\0') freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10); else { freq = 66; |
cfeecab44 crypto: hifn_795x... |
909 910 911 |
dev_info(&dev->pdev->dev, "assuming %uMHz clock speed, override with hifn_pll_ref=%.3s<frequency> ", freq, hifn_pll_ref); |
37a8023ce [HIFN]: Improve P... |
912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 |
} m = HIFN_PLL_FCK_MAX / freq; pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT; if (m <= 8) pllcfg |= HIFN_PLL_IS_1_8; else pllcfg |= HIFN_PLL_IS_9_12; /* Select clock source and enable clock bypass */ hifn_write_1(dev, HIFN_1_PLL, pllcfg | HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP); /* Let the chip lock to the input clock */ mdelay(10); /* Disable clock bypass */ hifn_write_1(dev, HIFN_1_PLL, pllcfg | HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI); /* Switch the engines to the PLL */ hifn_write_1(dev, HIFN_1_PLL, pllcfg | HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL); |
fcd067559 [HIFN]: Add suppo... |
936 937 938 939 940 941 942 943 |
/* * The Fpk_clk runs at half the total speed. Its frequency is needed to * calculate the minimum time between two reads of the rng. Since 33MHz * is actually 33.333... we overestimate the frequency here, resulting * in slightly larger intervals. */ dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2; |
37a8023ce [HIFN]: Improve P... |
944 |
} |
f7d0561ea [CRYPTO] hifn_795... |
945 946 947 948 949 950 951 952 953 954 |
static void hifn_init_registers(struct hifn_device *dev) { u32 dptr = dev->desc_dma; /* Initialization magic... */ hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); /* write all 4 ring address registers */ |
3c42cbc2e [HIFN]: Endianess... |
955 956 957 958 959 960 961 962 |
hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr + offsetof(struct hifn_dma, cmdr[0])); hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr + offsetof(struct hifn_dma, srcr[0])); hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr + offsetof(struct hifn_dma, dstr[0])); hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr + offsetof(struct hifn_dma, resr[0])); |
f7d0561ea [CRYPTO] hifn_795... |
963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 |
mdelay(2); #if 0 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | HIFN_DMACSR_S_WAIT | HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | HIFN_DMACSR_C_WAIT | HIFN_DMACSR_ENGINE | HIFN_DMACSR_PUBDONE); #else hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | HIFN_DMACSR_S_WAIT | HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | HIFN_DMACSR_C_WAIT | HIFN_DMACSR_ENGINE | HIFN_DMACSR_PUBDONE); #endif hifn_read_1(dev, HIFN_1_DMA_CSR); dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | HIFN_DMAIER_ENGINE; dev->dmareg &= ~HIFN_DMAIER_C_WAIT; hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); hifn_read_1(dev, HIFN_1_DMA_IER); #if 0 hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG | HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | HIFN_PUCNFG_DRAM); #else hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342); #endif |
37a8023ce [HIFN]: Improve P... |
1012 |
hifn_init_pll(dev); |
f7d0561ea [CRYPTO] hifn_795... |
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 |
hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); } static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf, unsigned dlen, unsigned slen, u16 mask, u8 snum) { struct hifn_base_command *base_cmd; u8 *buf_pos = buf; base_cmd = (struct hifn_base_command *)buf_pos; base_cmd->masks = __cpu_to_le16(mask); base_cmd->total_source_count = __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO); base_cmd->total_dest_count = __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO); dlen >>= 16; slen >>= 16; base_cmd->session_num = __cpu_to_le16(snum | ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); return sizeof(struct hifn_base_command); } static int hifn_setup_crypto_command(struct hifn_device *dev, u8 *buf, unsigned dlen, unsigned slen, u8 *key, int keylen, u8 *iv, int ivsize, u16 mode) { struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; struct hifn_crypt_command *cry_cmd; u8 *buf_pos = buf; u16 cmd_len; cry_cmd = (struct hifn_crypt_command *)buf_pos; cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff); dlen >>= 16; cry_cmd->masks = __cpu_to_le16(mode | ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); cry_cmd->header_skip = 0; cry_cmd->reserved = 0; buf_pos += sizeof(struct hifn_crypt_command); dma->cmdu++; if (dma->cmdu > 1) { dev->dmareg |= HIFN_DMAIER_C_WAIT; hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); } if (keylen) { memcpy(buf_pos, key, keylen); buf_pos += keylen; } if (ivsize) { memcpy(buf_pos, iv, ivsize); buf_pos += ivsize; } cmd_len = buf_pos - buf; return cmd_len; } |
85e7e60b8 [HIFN]: Move comm... |
1083 |
static int hifn_setup_cmd_desc(struct hifn_device *dev, |
5df4c0c67 crypto: hifn_795x... |
1084 1085 |
struct hifn_context *ctx, struct hifn_request_context *rctx, void *priv, unsigned int nbytes) |
f7d0561ea [CRYPTO] hifn_795... |
1086 1087 1088 1089 1090 |
{ struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; int cmd_len, sa_idx; u8 *buf, *buf_pos; u16 mask; |
85e7e60b8 [HIFN]: Move comm... |
1091 |
sa_idx = dma->cmdi; |
f7d0561ea [CRYPTO] hifn_795... |
1092 1093 1094 |
buf_pos = buf = dma->command_bufs[dma->cmdi]; mask = 0; |
5df4c0c67 crypto: hifn_795x... |
1095 |
switch (rctx->op) { |
16f56e8b7 crypto: hifn_795x... |
1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 |
case ACRYPTO_OP_DECRYPT: mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE; break; case ACRYPTO_OP_ENCRYPT: mask = HIFN_BASE_CMD_CRYPT; break; case ACRYPTO_OP_HMAC: mask = HIFN_BASE_CMD_MAC; break; default: goto err_out; |
f7d0561ea [CRYPTO] hifn_795... |
1107 1108 1109 1110 |
} buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes, nbytes, mask, dev->snum); |
5df4c0c67 crypto: hifn_795x... |
1111 |
if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) { |
f7d0561ea [CRYPTO] hifn_795... |
1112 1113 1114 1115 |
u16 md = 0; if (ctx->keysize) md |= HIFN_CRYPT_CMD_NEW_KEY; |
5df4c0c67 crypto: hifn_795x... |
1116 |
if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB) |
f7d0561ea [CRYPTO] hifn_795... |
1117 |
md |= HIFN_CRYPT_CMD_NEW_IV; |
5df4c0c67 crypto: hifn_795x... |
1118 |
switch (rctx->mode) { |
16f56e8b7 crypto: hifn_795x... |
1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 |
case ACRYPTO_MODE_ECB: md |= HIFN_CRYPT_CMD_MODE_ECB; break; case ACRYPTO_MODE_CBC: md |= HIFN_CRYPT_CMD_MODE_CBC; break; case ACRYPTO_MODE_CFB: md |= HIFN_CRYPT_CMD_MODE_CFB; break; case ACRYPTO_MODE_OFB: md |= HIFN_CRYPT_CMD_MODE_OFB; break; default: goto err_out; |
f7d0561ea [CRYPTO] hifn_795... |
1133 |
} |
5df4c0c67 crypto: hifn_795x... |
1134 |
switch (rctx->type) { |
16f56e8b7 crypto: hifn_795x... |
1135 1136 |
case ACRYPTO_TYPE_AES_128: if (ctx->keysize != 16) |
f7d0561ea [CRYPTO] hifn_795... |
1137 |
goto err_out; |
16f56e8b7 crypto: hifn_795x... |
1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 |
md |= HIFN_CRYPT_CMD_KSZ_128 | HIFN_CRYPT_CMD_ALG_AES; break; case ACRYPTO_TYPE_AES_192: if (ctx->keysize != 24) goto err_out; md |= HIFN_CRYPT_CMD_KSZ_192 | HIFN_CRYPT_CMD_ALG_AES; break; case ACRYPTO_TYPE_AES_256: if (ctx->keysize != 32) goto err_out; md |= HIFN_CRYPT_CMD_KSZ_256 | HIFN_CRYPT_CMD_ALG_AES; break; case ACRYPTO_TYPE_3DES: if (ctx->keysize != 24) goto err_out; md |= HIFN_CRYPT_CMD_ALG_3DES; break; case ACRYPTO_TYPE_DES: if (ctx->keysize != 8) goto err_out; md |= HIFN_CRYPT_CMD_ALG_DES; break; default: goto err_out; |
f7d0561ea [CRYPTO] hifn_795... |
1165 1166 1167 1168 |
} buf_pos += hifn_setup_crypto_command(dev, buf_pos, nbytes, nbytes, ctx->key, ctx->keysize, |
5df4c0c67 crypto: hifn_795x... |
1169 |
rctx->iv, rctx->ivsize, md); |
f7d0561ea [CRYPTO] hifn_795... |
1170 1171 1172 |
} dev->sa[sa_idx] = priv; |
d6a10c84a crypto: hifn_795x... |
1173 |
dev->started++; |
f7d0561ea [CRYPTO] hifn_795... |
1174 1175 1176 1177 1178 1179 |
cmd_len = buf_pos - buf; dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); if (++dma->cmdi == HIFN_D_CMD_RSIZE) { |
5df4c0c67 crypto: hifn_795x... |
1180 |
dma->cmdr[dma->cmdi].l = __cpu_to_le32( |
f7d0561ea [CRYPTO] hifn_795... |
1181 1182 1183 |
HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ | HIFN_D_JUMP); dma->cmdi = 0; |
16f56e8b7 crypto: hifn_795x... |
1184 1185 1186 |
} else { dma->cmdr[dma->cmdi - 1].l |= __cpu_to_le32(HIFN_D_VALID); } |
f7d0561ea [CRYPTO] hifn_795... |
1187 1188 1189 1190 1191 |
if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) { hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); dev->flags |= HIFN_FLAG_CMD_BUSY; } |
f7d0561ea [CRYPTO] hifn_795... |
1192 1193 1194 1195 1196 |
return 0; err_out: return -EINVAL; } |
85e7e60b8 [HIFN]: Move comm... |
1197 |
static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page, |
75741a034 crypto: hifn_795x... |
1198 |
unsigned int offset, unsigned int size, int last) |
85e7e60b8 [HIFN]: Move comm... |
1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 |
{ struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; int idx; dma_addr_t addr; addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE); idx = dma->srci; dma->srcr[idx].p = __cpu_to_le32(addr); dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | |
75741a034 crypto: hifn_795x... |
1210 |
HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); |
85e7e60b8 [HIFN]: Move comm... |
1211 1212 1213 |
if (++idx == HIFN_D_SRC_RSIZE) { dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID | |
75741a034 crypto: hifn_795x... |
1214 1215 |
HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); |
85e7e60b8 [HIFN]: Move comm... |
1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 |
idx = 0; } dma->srci = idx; dma->srcu++; if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) { hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); dev->flags |= HIFN_FLAG_SRC_BUSY; } return size; } static void hifn_setup_res_desc(struct hifn_device *dev) { struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT | HIFN_D_VALID | HIFN_D_LAST); /* * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID | |
692af5da7 [HIFN]: Have HW i... |
1238 |
* HIFN_D_LAST); |
85e7e60b8 [HIFN]: Move comm... |
1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 |
*/ if (++dma->resi == HIFN_D_RES_RSIZE) { dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST); dma->resi = 0; } dma->resu++; if (!(dev->flags & HIFN_FLAG_RES_BUSY)) { hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); dev->flags |= HIFN_FLAG_RES_BUSY; } } static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page, |
75741a034 crypto: hifn_795x... |
1256 |
unsigned offset, unsigned size, int last) |
85e7e60b8 [HIFN]: Move comm... |
1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 |
{ struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; int idx; dma_addr_t addr; addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE); idx = dma->dsti; dma->dstr[idx].p = __cpu_to_le32(addr); dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | |
75741a034 crypto: hifn_795x... |
1267 |
HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); |
85e7e60b8 [HIFN]: Move comm... |
1268 1269 1270 1271 |
if (++idx == HIFN_D_DST_RSIZE) { dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | |
75741a034 crypto: hifn_795x... |
1272 |
(last ? HIFN_D_LAST : 0)); |
85e7e60b8 [HIFN]: Move comm... |
1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 |
idx = 0; } dma->dsti = idx; dma->dstu++; if (!(dev->flags & HIFN_FLAG_DST_BUSY)) { hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); dev->flags |= HIFN_FLAG_DST_BUSY; } } |
5df4c0c67 crypto: hifn_795x... |
1283 1284 |
static int hifn_setup_dma(struct hifn_device *dev, struct hifn_context *ctx, struct hifn_request_context *rctx, |
75741a034 crypto: hifn_795x... |
1285 1286 |
struct scatterlist *src, struct scatterlist *dst, unsigned int nbytes, void *priv) |
85e7e60b8 [HIFN]: Move comm... |
1287 |
{ |
75741a034 crypto: hifn_795x... |
1288 1289 1290 1291 |
struct scatterlist *t; struct page *spage, *dpage; unsigned int soff, doff; unsigned int n, len; |
341615868 crypto: hifn_795x... |
1292 1293 1294 1295 1296 |
n = nbytes; while (n) { spage = sg_page(src); soff = src->offset; len = min(src->length, n); |
341615868 crypto: hifn_795x... |
1297 1298 1299 1300 1301 |
hifn_setup_src_desc(dev, spage, soff, len, n - len == 0); src++; n -= len; } |
5df4c0c67 crypto: hifn_795x... |
1302 |
t = &rctx->walk.cache[0]; |
75741a034 crypto: hifn_795x... |
1303 1304 |
n = nbytes; while (n) { |
5df4c0c67 crypto: hifn_795x... |
1305 |
if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { |
5f459f0ad crypto: hifn_795x... |
1306 |
BUG_ON(!sg_page(t)); |
341615868 crypto: hifn_795x... |
1307 1308 |
dpage = sg_page(t); doff = 0; |
75741a034 crypto: hifn_795x... |
1309 1310 |
len = t->length; } else { |
5f459f0ad crypto: hifn_795x... |
1311 |
BUG_ON(!sg_page(dst)); |
75741a034 crypto: hifn_795x... |
1312 1313 |
dpage = sg_page(dst); doff = dst->offset; |
75741a034 crypto: hifn_795x... |
1314 1315 1316 |
len = dst->length; } len = min(len, n); |
75741a034 crypto: hifn_795x... |
1317 |
hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0); |
75741a034 crypto: hifn_795x... |
1318 1319 1320 1321 |
dst++; t++; n -= len; } |
5df4c0c67 crypto: hifn_795x... |
1322 |
hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes); |
85e7e60b8 [HIFN]: Move comm... |
1323 1324 1325 |
hifn_setup_res_desc(dev); return 0; } |
3385329a0 crypto: hifn_795x... |
1326 |
static int hifn_cipher_walk_init(struct hifn_cipher_walk *w, |
f7d0561ea [CRYPTO] hifn_795... |
1327 1328 1329 1330 1331 1332 1333 1334 |
int num, gfp_t gfp_flags) { int i; num = min(ASYNC_SCATTERLIST_CACHE, num); sg_init_table(w->cache, num); w->num = 0; |
16f56e8b7 crypto: hifn_795x... |
1335 |
for (i = 0; i < num; ++i) { |
f7d0561ea [CRYPTO] hifn_795... |
1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 |
struct page *page = alloc_page(gfp_flags); struct scatterlist *s; if (!page) break; s = &w->cache[i]; sg_set_page(s, page, PAGE_SIZE, 0); w->num++; } return i; } |
3385329a0 crypto: hifn_795x... |
1350 |
static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w) |
f7d0561ea [CRYPTO] hifn_795... |
1351 1352 |
{ int i; |
16f56e8b7 crypto: hifn_795x... |
1353 |
for (i = 0; i < w->num; ++i) { |
f7d0561ea [CRYPTO] hifn_795... |
1354 1355 1356 1357 1358 1359 1360 1361 1362 |
struct scatterlist *s = &w->cache[i]; __free_page(sg_page(s)); s->length = 0; } w->num = 0; } |
341615868 crypto: hifn_795x... |
1363 |
static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst, |
f7d0561ea [CRYPTO] hifn_795... |
1364 1365 1366 1367 |
unsigned int size, unsigned int *nbytesp) { unsigned int copy, drest = *drestp, nbytes = *nbytesp; int idx = 0; |
f7d0561ea [CRYPTO] hifn_795... |
1368 1369 1370 1371 1372 |
if (drest < size || size > nbytes) return -EINVAL; while (size) { |
732eacc05 replace nested ma... |
1373 |
copy = min3(drest, size, dst->length); |
f7d0561ea [CRYPTO] hifn_795... |
1374 1375 1376 1377 |
size -= copy; drest -= copy; nbytes -= copy; |
f7d0561ea [CRYPTO] hifn_795... |
1378 |
|
cfeecab44 crypto: hifn_795x... |
1379 1380 1381 |
pr_debug("%s: copy: %u, size: %u, drest: %u, nbytes: %u. ", __func__, copy, size, drest, nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1382 |
|
341615868 crypto: hifn_795x... |
1383 |
dst++; |
f7d0561ea [CRYPTO] hifn_795... |
1384 1385 1386 1387 1388 1389 1390 1391 |
idx++; } *nbytesp = nbytes; *drestp = drest; return idx; } |
3385329a0 crypto: hifn_795x... |
1392 1393 |
static int hifn_cipher_walk(struct ablkcipher_request *req, struct hifn_cipher_walk *w) |
f7d0561ea [CRYPTO] hifn_795... |
1394 |
{ |
341615868 crypto: hifn_795x... |
1395 |
struct scatterlist *dst, *t; |
f7d0561ea [CRYPTO] hifn_795... |
1396 1397 1398 1399 1400 1401 1402 1403 |
unsigned int nbytes = req->nbytes, offset, copy, diff; int idx, tidx, err; tidx = idx = 0; offset = 0; while (nbytes) { if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED)) return -EINVAL; |
f7d0561ea [CRYPTO] hifn_795... |
1404 |
dst = &req->dst[idx]; |
cfeecab44 crypto: hifn_795x... |
1405 1406 1407 1408 |
pr_debug(" %s: dlen: %u, doff: %u, offset: %u, nbytes: %u. ", __func__, dst->length, dst->offset, offset, nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1409 |
|
d069033b4 [HIFN]: Fix data ... |
1410 1411 1412 |
if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) || !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) || offset) { |
341615868 crypto: hifn_795x... |
1413 |
unsigned slen = min(dst->length - offset, nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1414 1415 1416 |
unsigned dlen = PAGE_SIZE; t = &w->cache[idx]; |
341615868 crypto: hifn_795x... |
1417 |
err = ablkcipher_add(&dlen, dst, slen, &nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1418 |
if (err < 0) |
341615868 crypto: hifn_795x... |
1419 |
return err; |
f7d0561ea [CRYPTO] hifn_795... |
1420 1421 |
idx += err; |
d069033b4 [HIFN]: Fix data ... |
1422 1423 |
copy = slen & ~(HIFN_D_DST_DALIGN - 1); diff = slen & (HIFN_D_DST_DALIGN - 1); |
f7d0561ea [CRYPTO] hifn_795... |
1424 1425 1426 1427 1428 1429 1430 |
if (dlen < nbytes) { /* * Destination page does not have enough space * to put there additional blocksized chunk, * so we mark that page as containing only * blocksize aligned chunks: |
16f56e8b7 crypto: hifn_795x... |
1431 |
* t->length = (slen & ~(HIFN_D_DST_DALIGN - 1)); |
f7d0561ea [CRYPTO] hifn_795... |
1432 1433 |
* and increase number of bytes to be processed * in next chunk: |
16f56e8b7 crypto: hifn_795x... |
1434 |
* nbytes += diff; |
f7d0561ea [CRYPTO] hifn_795... |
1435 1436 1437 1438 1439 1440 1441 |
*/ nbytes += diff; /* * Temporary of course... * Kick author if you will catch this one. */ |
cfeecab44 crypto: hifn_795x... |
1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 |
pr_err("%s: dlen: %u, nbytes: %u, slen: %u, offset: %u. ", __func__, dlen, nbytes, slen, offset); pr_err("%s: please contact author to fix this " "issue, generally you should not catch " "this path under any condition but who " "knows how did you use crypto code. " "Thank you. ", __func__); |
f7d0561ea [CRYPTO] hifn_795... |
1452 1453 1454 |
BUG(); } else { copy += diff + nbytes; |
341615868 crypto: hifn_795x... |
1455 |
dst = &req->dst[idx]; |
f7d0561ea [CRYPTO] hifn_795... |
1456 |
|
341615868 crypto: hifn_795x... |
1457 |
err = ablkcipher_add(&dlen, dst, nbytes, &nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1458 |
if (err < 0) |
341615868 crypto: hifn_795x... |
1459 |
return err; |
f7d0561ea [CRYPTO] hifn_795... |
1460 1461 1462 1463 1464 1465 |
idx += err; } t->length = copy; t->offset = offset; |
f7d0561ea [CRYPTO] hifn_795... |
1466 |
} else { |
341615868 crypto: hifn_795x... |
1467 |
nbytes -= min(dst->length, nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1468 1469 1470 1471 1472 1473 1474 |
idx++; } tidx++; } return tidx; |
f7d0561ea [CRYPTO] hifn_795... |
1475 1476 1477 1478 1479 |
} static int hifn_setup_session(struct ablkcipher_request *req) { struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); |
5df4c0c67 crypto: hifn_795x... |
1480 |
struct hifn_request_context *rctx = ablkcipher_request_ctx(req); |
f7d0561ea [CRYPTO] hifn_795... |
1481 |
struct hifn_device *dev = ctx->dev; |
75741a034 crypto: hifn_795x... |
1482 1483 |
unsigned long dlen, flags; unsigned int nbytes = req->nbytes, idx = 0; |
f7d0561ea [CRYPTO] hifn_795... |
1484 |
int err = -EINVAL, sg_num; |
75741a034 crypto: hifn_795x... |
1485 |
struct scatterlist *dst; |
f7d0561ea [CRYPTO] hifn_795... |
1486 |
|
5df4c0c67 crypto: hifn_795x... |
1487 |
if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB) |
f7d0561ea [CRYPTO] hifn_795... |
1488 |
goto err_out_exit; |
5df4c0c67 crypto: hifn_795x... |
1489 |
rctx->walk.flags = 0; |
f7d0561ea [CRYPTO] hifn_795... |
1490 1491 |
while (nbytes) { |
f7d0561ea [CRYPTO] hifn_795... |
1492 |
dst = &req->dst[idx]; |
136f702f5 [HIFN]: Properly ... |
1493 |
dlen = min(dst->length, nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1494 |
|
d069033b4 [HIFN]: Fix data ... |
1495 |
if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) || |
136f702f5 [HIFN]: Properly ... |
1496 |
!IS_ALIGNED(dlen, HIFN_D_DST_DALIGN)) |
5df4c0c67 crypto: hifn_795x... |
1497 |
rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED; |
f7d0561ea [CRYPTO] hifn_795... |
1498 |
|
136f702f5 [HIFN]: Properly ... |
1499 |
nbytes -= dlen; |
f7d0561ea [CRYPTO] hifn_795... |
1500 1501 |
idx++; } |
5df4c0c67 crypto: hifn_795x... |
1502 |
if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { |
3385329a0 crypto: hifn_795x... |
1503 |
err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC); |
f7d0561ea [CRYPTO] hifn_795... |
1504 1505 1506 |
if (err < 0) return err; } |
3385329a0 crypto: hifn_795x... |
1507 |
sg_num = hifn_cipher_walk(req, &rctx->walk); |
94eaa1bd7 [HIFN]: Handle ab... |
1508 1509 1510 1511 |
if (sg_num < 0) { err = sg_num; goto err_out_exit; } |
f7d0561ea [CRYPTO] hifn_795... |
1512 1513 1514 1515 1516 1517 |
spin_lock_irqsave(&dev->lock, flags); if (dev->started + sg_num > HIFN_QUEUE_LENGTH) { err = -EAGAIN; goto err_out; } |
5df4c0c67 crypto: hifn_795x... |
1518 |
err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->nbytes, req); |
75741a034 crypto: hifn_795x... |
1519 1520 |
if (err) goto err_out; |
f7d0561ea [CRYPTO] hifn_795... |
1521 |
|
d6a10c84a crypto: hifn_795x... |
1522 |
dev->snum++; |
f7d0561ea [CRYPTO] hifn_795... |
1523 1524 1525 1526 1527 1528 1529 1530 |
dev->active = HIFN_DEFAULT_ACTIVE_NUM; spin_unlock_irqrestore(&dev->lock, flags); return 0; err_out: spin_unlock_irqrestore(&dev->lock, flags); err_out_exit: |
d6a10c84a crypto: hifn_795x... |
1531 |
if (err) { |
cfeecab44 crypto: hifn_795x... |
1532 1533 1534 1535 1536 1537 |
dev_info(&dev->pdev->dev, "iv: %p [%d], key: %p [%d], mode: %u, op: %u, " "type: %u, err: %d. ", rctx->iv, rctx->ivsize, ctx->key, ctx->keysize, rctx->mode, rctx->op, rctx->type, err); |
d6a10c84a crypto: hifn_795x... |
1538 |
} |
f7d0561ea [CRYPTO] hifn_795... |
1539 1540 1541 |
return err; } |
f7d0561ea [CRYPTO] hifn_795... |
1542 1543 1544 |
static int hifn_start_device(struct hifn_device *dev) { int err; |
d6a10c84a crypto: hifn_795x... |
1545 |
dev->started = dev->active = 0; |
f7d0561ea [CRYPTO] hifn_795... |
1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 |
hifn_reset_dma(dev, 1); err = hifn_enable_crypto(dev); if (err) return err; hifn_reset_puc(dev); hifn_init_dma(dev); hifn_init_registers(dev); hifn_init_pubrng(dev); return 0; } static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset, struct scatterlist *dst, unsigned int size, unsigned int *nbytesp) { unsigned int srest = *srestp, nbytes = *nbytesp, copy; void *daddr; int idx = 0; if (srest < size || size > nbytes) return -EINVAL; while (size) { |
732eacc05 replace nested ma... |
1574 |
copy = min3(srest, dst->length, size); |
f7d0561ea [CRYPTO] hifn_795... |
1575 |
|
237f259ce crypto: remove th... |
1576 |
daddr = kmap_atomic(sg_page(dst)); |
f7d0561ea [CRYPTO] hifn_795... |
1577 |
memcpy(daddr + dst->offset + offset, saddr, copy); |
237f259ce crypto: remove th... |
1578 |
kunmap_atomic(daddr); |
f7d0561ea [CRYPTO] hifn_795... |
1579 1580 1581 1582 1583 1584 |
nbytes -= copy; size -= copy; srest -= copy; saddr += copy; offset = 0; |
cfeecab44 crypto: hifn_795x... |
1585 1586 1587 |
pr_debug("%s: copy: %u, size: %u, srest: %u, nbytes: %u. ", __func__, copy, size, srest, nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 |
dst++; idx++; } *nbytesp = nbytes; *srestp = srest; return idx; } |
d6a10c84a crypto: hifn_795x... |
1598 |
static inline void hifn_complete_sa(struct hifn_device *dev, int i) |
f7d0561ea [CRYPTO] hifn_795... |
1599 |
{ |
d6a10c84a crypto: hifn_795x... |
1600 |
unsigned long flags; |
f7d0561ea [CRYPTO] hifn_795... |
1601 |
|
d6a10c84a crypto: hifn_795x... |
1602 1603 1604 1605 |
spin_lock_irqsave(&dev->lock, flags); dev->sa[i] = NULL; dev->started--; if (dev->started < 0) |
cfeecab44 crypto: hifn_795x... |
1606 1607 1608 |
dev_info(&dev->pdev->dev, "%s: started: %d. ", __func__, dev->started); |
d6a10c84a crypto: hifn_795x... |
1609 1610 1611 |
spin_unlock_irqrestore(&dev->lock, flags); BUG_ON(dev->started < 0); } |
f7d0561ea [CRYPTO] hifn_795... |
1612 |
|
d6a10c84a crypto: hifn_795x... |
1613 1614 1615 |
static void hifn_process_ready(struct ablkcipher_request *req, int error) { struct hifn_request_context *rctx = ablkcipher_request_ctx(req); |
f7d0561ea [CRYPTO] hifn_795... |
1616 |
|
5df4c0c67 crypto: hifn_795x... |
1617 |
if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { |
f7d0561ea [CRYPTO] hifn_795... |
1618 1619 1620 1621 |
unsigned int nbytes = req->nbytes; int idx = 0, err; struct scatterlist *dst, *t; void *saddr; |
75741a034 crypto: hifn_795x... |
1622 |
while (nbytes) { |
5df4c0c67 crypto: hifn_795x... |
1623 |
t = &rctx->walk.cache[idx]; |
75741a034 crypto: hifn_795x... |
1624 |
dst = &req->dst[idx]; |
f7d0561ea [CRYPTO] hifn_795... |
1625 |
|
cfeecab44 crypto: hifn_795x... |
1626 1627 |
pr_debug(" %s: sg_page(t): %p, t->length: %u, " |
75741a034 crypto: hifn_795x... |
1628 1629 1630 1631 1632 |
"sg_page(dst): %p, dst->length: %u, " "nbytes: %u. ", __func__, sg_page(t), t->length, sg_page(dst), dst->length, nbytes); |
f7d0561ea [CRYPTO] hifn_795... |
1633 |
|
75741a034 crypto: hifn_795x... |
1634 1635 1636 1637 1638 |
if (!t->length) { nbytes -= min(dst->length, nbytes); idx++; continue; } |
f7d0561ea [CRYPTO] hifn_795... |
1639 |
|
237f259ce crypto: remove th... |
1640 |
saddr = kmap_atomic(sg_page(t)); |
f7d0561ea [CRYPTO] hifn_795... |
1641 |
|
75741a034 crypto: hifn_795x... |
1642 1643 1644 |
err = ablkcipher_get(saddr, &t->length, t->offset, dst, nbytes, &nbytes); if (err < 0) { |
237f259ce crypto: remove th... |
1645 |
kunmap_atomic(saddr); |
75741a034 crypto: hifn_795x... |
1646 |
break; |
f7d0561ea [CRYPTO] hifn_795... |
1647 |
} |
75741a034 crypto: hifn_795x... |
1648 |
idx += err; |
237f259ce crypto: remove th... |
1649 |
kunmap_atomic(saddr); |
f7d0561ea [CRYPTO] hifn_795... |
1650 |
} |
3385329a0 crypto: hifn_795x... |
1651 |
hifn_cipher_walk_exit(&rctx->walk); |
f7d0561ea [CRYPTO] hifn_795... |
1652 |
} |
75741a034 crypto: hifn_795x... |
1653 1654 |
req->base.complete(&req->base, error); |
f7d0561ea [CRYPTO] hifn_795... |
1655 |
} |
d6a10c84a crypto: hifn_795x... |
1656 |
static void hifn_clear_rings(struct hifn_device *dev, int error) |
f7d0561ea [CRYPTO] hifn_795... |
1657 1658 1659 |
{ struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; int i, u; |
cfeecab44 crypto: hifn_795x... |
1660 |
dev_dbg(&dev->pdev->dev, "ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, " |
f7d0561ea [CRYPTO] hifn_795... |
1661 1662 |
"k: %d.%d.%d.%d. ", |
f7d0561ea [CRYPTO] hifn_795... |
1663 1664 1665 1666 1667 1668 1669 1670 |
dma->cmdi, dma->srci, dma->dsti, dma->resi, dma->cmdu, dma->srcu, dma->dstu, dma->resu, dma->cmdk, dma->srck, dma->dstk, dma->resk); i = dma->resk; u = dma->resu; while (u != 0) { if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID)) break; |
d6a10c84a crypto: hifn_795x... |
1671 1672 1673 1674 1675 1676 |
if (dev->sa[i]) { dev->success++; dev->reset = 0; hifn_process_ready(dev->sa[i], error); hifn_complete_sa(dev, i); } |
f7d0561ea [CRYPTO] hifn_795... |
1677 |
|
d6a10c84a crypto: hifn_795x... |
1678 |
if (++i == HIFN_D_RES_RSIZE) |
f7d0561ea [CRYPTO] hifn_795... |
1679 |
i = 0; |
d6a10c84a crypto: hifn_795x... |
1680 |
u--; |
f7d0561ea [CRYPTO] hifn_795... |
1681 1682 1683 1684 1685 |
} dma->resk = i; dma->resu = u; i = dma->srck; u = dma->srcu; while (u != 0) { |
f7d0561ea [CRYPTO] hifn_795... |
1686 1687 |
if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID)) break; |
d6a10c84a crypto: hifn_795x... |
1688 1689 1690 |
if (++i == HIFN_D_SRC_RSIZE) i = 0; u--; |
f7d0561ea [CRYPTO] hifn_795... |
1691 1692 1693 1694 1695 1696 1697 |
} dma->srck = i; dma->srcu = u; i = dma->cmdk; u = dma->cmdu; while (u != 0) { if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID)) break; |
d6a10c84a crypto: hifn_795x... |
1698 |
if (++i == HIFN_D_CMD_RSIZE) |
f7d0561ea [CRYPTO] hifn_795... |
1699 |
i = 0; |
d6a10c84a crypto: hifn_795x... |
1700 |
u--; |
f7d0561ea [CRYPTO] hifn_795... |
1701 1702 1703 1704 1705 |
} dma->cmdk = i; dma->cmdu = u; i = dma->dstk; u = dma->dstu; while (u != 0) { |
f7d0561ea [CRYPTO] hifn_795... |
1706 1707 |
if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID)) break; |
d6a10c84a crypto: hifn_795x... |
1708 1709 1710 |
if (++i == HIFN_D_DST_RSIZE) i = 0; u--; |
f7d0561ea [CRYPTO] hifn_795... |
1711 1712 |
} dma->dstk = i; dma->dstu = u; |
cfeecab44 crypto: hifn_795x... |
1713 |
dev_dbg(&dev->pdev->dev, "ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, " |
f7d0561ea [CRYPTO] hifn_795... |
1714 1715 |
"k: %d.%d.%d.%d. ", |
f7d0561ea [CRYPTO] hifn_795... |
1716 1717 1718 1719 1720 1721 1722 |
dma->cmdi, dma->srci, dma->dsti, dma->resi, dma->cmdu, dma->srcu, dma->dstu, dma->resu, dma->cmdk, dma->srck, dma->dstk, dma->resk); } static void hifn_work(struct work_struct *work) { |
bf6aede71 workqueue: add to... |
1723 |
struct delayed_work *dw = to_delayed_work(work); |
f7d0561ea [CRYPTO] hifn_795... |
1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 |
struct hifn_device *dev = container_of(dw, struct hifn_device, work); unsigned long flags; int reset = 0; u32 r = 0; spin_lock_irqsave(&dev->lock, flags); if (dev->active == 0) { struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) { dev->flags &= ~HIFN_FLAG_CMD_BUSY; r |= HIFN_DMACSR_C_CTRL_DIS; } if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) { dev->flags &= ~HIFN_FLAG_SRC_BUSY; r |= HIFN_DMACSR_S_CTRL_DIS; } if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) { dev->flags &= ~HIFN_FLAG_DST_BUSY; r |= HIFN_DMACSR_D_CTRL_DIS; } if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) { dev->flags &= ~HIFN_FLAG_RES_BUSY; r |= HIFN_DMACSR_R_CTRL_DIS; } if (r) hifn_write_1(dev, HIFN_1_DMA_CSR, r); } else dev->active--; |
d6a10c84a crypto: hifn_795x... |
1753 |
if ((dev->prev_success == dev->success) && dev->started) |
f7d0561ea [CRYPTO] hifn_795... |
1754 1755 1756 1757 1758 |
reset = 1; dev->prev_success = dev->success; spin_unlock_irqrestore(&dev->lock, flags); if (reset) { |
f7d0561ea [CRYPTO] hifn_795... |
1759 |
if (++dev->reset >= 5) { |
d6a10c84a crypto: hifn_795x... |
1760 1761 |
int i; struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; |
cfeecab44 crypto: hifn_795x... |
1762 1763 1764 1765 1766 1767 1768 |
dev_info(&dev->pdev->dev, "r: %08x, active: %d, started: %d, " "success: %lu: qlen: %u/%u, reset: %d. ", r, dev->active, dev->started, dev->success, dev->queue.qlen, dev->queue.max_qlen, reset); |
d6a10c84a crypto: hifn_795x... |
1769 |
|
cfeecab44 crypto: hifn_795x... |
1770 |
dev_info(&dev->pdev->dev, "%s: res: ", __func__); |
16f56e8b7 crypto: hifn_795x... |
1771 |
for (i = 0; i < HIFN_D_RES_RSIZE; ++i) { |
cfeecab44 crypto: hifn_795x... |
1772 |
pr_info("%x.%p ", dma->resr[i].l, dev->sa[i]); |
d6a10c84a crypto: hifn_795x... |
1773 1774 1775 1776 1777 |
if (dev->sa[i]) { hifn_process_ready(dev->sa[i], -ENODEV); hifn_complete_sa(dev, i); } } |
cfeecab44 crypto: hifn_795x... |
1778 1779 |
pr_info(" "); |
d6a10c84a crypto: hifn_795x... |
1780 |
|
f7d0561ea [CRYPTO] hifn_795... |
1781 1782 1783 1784 1785 |
hifn_reset_dma(dev, 1); hifn_stop_device(dev); hifn_start_device(dev); dev->reset = 0; } |
d6a10c84a crypto: hifn_795x... |
1786 |
tasklet_schedule(&dev->tasklet); |
f7d0561ea [CRYPTO] hifn_795... |
1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 |
} schedule_delayed_work(&dev->work, HZ); } static irqreturn_t hifn_interrupt(int irq, void *data) { struct hifn_device *dev = (struct hifn_device *)data; struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; u32 dmacsr, restart; dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); |
cfeecab44 crypto: hifn_795x... |
1799 |
dev_dbg(&dev->pdev->dev, "1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], " |
f7d0561ea [CRYPTO] hifn_795... |
1800 1801 |
"i: %d.%d.%d.%d, u: %d.%d.%d.%d. ", |
cfeecab44 crypto: hifn_795x... |
1802 |
dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi, |
d6a10c84a crypto: hifn_795x... |
1803 1804 |
dma->cmdi, dma->srci, dma->dsti, dma->resi, dma->cmdu, dma->srcu, dma->dstu, dma->resu); |
f7d0561ea [CRYPTO] hifn_795... |
1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 |
if ((dmacsr & dev->dmareg) == 0) return IRQ_NONE; hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); if (dmacsr & HIFN_DMACSR_ENGINE) hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR)); if (dmacsr & HIFN_DMACSR_PUBDONE) hifn_write_1(dev, HIFN_1_PUB_STATUS, hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER); if (restart) { u32 puisr = hifn_read_0(dev, HIFN_0_PUISR); |
cfeecab44 crypto: hifn_795x... |
1820 1821 1822 1823 |
dev_warn(&dev->pdev->dev, "overflow: r: %d, d: %d, puisr: %08x, d: %u. ", !!(dmacsr & HIFN_DMACSR_R_OVER), !!(dmacsr & HIFN_DMACSR_D_OVER), |
d6a10c84a crypto: hifn_795x... |
1824 |
puisr, !!(puisr & HIFN_PUISR_DSTOVER)); |
f7d0561ea [CRYPTO] hifn_795... |
1825 1826 1827 1828 1829 1830 1831 1832 1833 |
if (!!(puisr & HIFN_PUISR_DSTOVER)) hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER)); } restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); if (restart) { |
cfeecab44 crypto: hifn_795x... |
1834 1835 1836 1837 1838 1839 |
dev_warn(&dev->pdev->dev, "abort: c: %d, s: %d, d: %d, r: %d. ", !!(dmacsr & HIFN_DMACSR_C_ABORT), !!(dmacsr & HIFN_DMACSR_S_ABORT), !!(dmacsr & HIFN_DMACSR_D_ABORT), !!(dmacsr & HIFN_DMACSR_R_ABORT)); |
f7d0561ea [CRYPTO] hifn_795... |
1840 1841 1842 1843 1844 1845 |
hifn_reset_dma(dev, 1); hifn_init_dma(dev); hifn_init_registers(dev); } if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { |
cfeecab44 crypto: hifn_795x... |
1846 1847 |
dev_dbg(&dev->pdev->dev, "wait on command. "); |
f7d0561ea [CRYPTO] hifn_795... |
1848 1849 1850 |
dev->dmareg &= ~(HIFN_DMAIER_C_WAIT); hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); } |
a1e6ef2f1 [CRYPTO] hifn: Sc... |
1851 |
tasklet_schedule(&dev->tasklet); |
f7d0561ea [CRYPTO] hifn_795... |
1852 1853 1854 1855 1856 1857 1858 1859 |
return IRQ_HANDLED; } static void hifn_flush(struct hifn_device *dev) { unsigned long flags; struct crypto_async_request *async_req; |
f7d0561ea [CRYPTO] hifn_795... |
1860 1861 1862 |
struct ablkcipher_request *req; struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; int i; |
16f56e8b7 crypto: hifn_795x... |
1863 |
for (i = 0; i < HIFN_D_RES_RSIZE; ++i) { |
f7d0561ea [CRYPTO] hifn_795... |
1864 1865 1866 1867 |
struct hifn_desc *d = &dma->resr[i]; if (dev->sa[i]) { hifn_process_ready(dev->sa[i], |
16f56e8b7 crypto: hifn_795x... |
1868 |
(d->l & __cpu_to_le32(HIFN_D_VALID)) ? -ENODEV : 0); |
d6a10c84a crypto: hifn_795x... |
1869 |
hifn_complete_sa(dev, i); |
f7d0561ea [CRYPTO] hifn_795... |
1870 1871 |
} } |
d6a10c84a crypto: hifn_795x... |
1872 |
spin_lock_irqsave(&dev->lock, flags); |
f7d0561ea [CRYPTO] hifn_795... |
1873 |
while ((async_req = crypto_dequeue_request(&dev->queue))) { |
48d627648 crypto: hifn_795x... |
1874 |
req = ablkcipher_request_cast(async_req); |
d6a10c84a crypto: hifn_795x... |
1875 |
spin_unlock_irqrestore(&dev->lock, flags); |
f7d0561ea [CRYPTO] hifn_795... |
1876 1877 |
hifn_process_ready(req, -ENODEV); |
d6a10c84a crypto: hifn_795x... |
1878 1879 |
spin_lock_irqsave(&dev->lock, flags); |
f7d0561ea [CRYPTO] hifn_795... |
1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 |
} spin_unlock_irqrestore(&dev->lock, flags); } static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int len) { struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); struct hifn_context *ctx = crypto_tfm_ctx(tfm); struct hifn_device *dev = ctx->dev; if (len > HIFN_MAX_CRYPT_KEY_LENGTH) { crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); return -1; } |
c3041f9c9 [CRYPTO] hifn_795... |
1895 1896 1897 |
if (len == HIFN_DES_KEY_LENGTH) { u32 tmp[DES_EXPKEY_WORDS]; int ret = des_ekey(tmp, key); |
16f56e8b7 crypto: hifn_795x... |
1898 |
|
c3041f9c9 [CRYPTO] hifn_795... |
1899 1900 1901 1902 1903 |
if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) { tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; return -EINVAL; } } |
f7d0561ea [CRYPTO] hifn_795... |
1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 |
dev->flags &= ~HIFN_FLAG_OLD_KEY; memcpy(ctx->key, key, len); ctx->keysize = len; return 0; } static int hifn_handle_req(struct ablkcipher_request *req) { struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); struct hifn_device *dev = ctx->dev; int err = -EAGAIN; if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH) err = hifn_setup_session(req); if (err == -EAGAIN) { unsigned long flags; spin_lock_irqsave(&dev->lock, flags); err = ablkcipher_enqueue_request(&dev->queue, req); spin_unlock_irqrestore(&dev->lock, flags); } return err; } static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op, u8 type, u8 mode) { struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); |
5df4c0c67 crypto: hifn_795x... |
1936 |
struct hifn_request_context *rctx = ablkcipher_request_ctx(req); |
f7d0561ea [CRYPTO] hifn_795... |
1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 |
unsigned ivsize; ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req)); if (req->info && mode != ACRYPTO_MODE_ECB) { if (type == ACRYPTO_TYPE_AES_128) ivsize = HIFN_AES_IV_LENGTH; else if (type == ACRYPTO_TYPE_DES) ivsize = HIFN_DES_KEY_LENGTH; else if (type == ACRYPTO_TYPE_3DES) ivsize = HIFN_3DES_KEY_LENGTH; } if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) { if (ctx->keysize == 24) type = ACRYPTO_TYPE_AES_192; else if (ctx->keysize == 32) type = ACRYPTO_TYPE_AES_256; } |
5df4c0c67 crypto: hifn_795x... |
1956 1957 1958 1959 1960 |
rctx->op = op; rctx->mode = mode; rctx->type = type; rctx->iv = req->info; rctx->ivsize = ivsize; |
f7d0561ea [CRYPTO] hifn_795... |
1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 |
/* * HEAVY TODO: needs to kick Herbert XU to write documentation. * HEAVY TODO: needs to kick Herbert XU to write documentation. * HEAVY TODO: needs to kick Herbert XU to write documentation. */ return hifn_handle_req(req); } static int hifn_process_queue(struct hifn_device *dev) { |
ed4f92e37 crypto: hifn_795x... |
1973 |
struct crypto_async_request *async_req, *backlog; |
f7d0561ea [CRYPTO] hifn_795... |
1974 1975 1976 1977 1978 1979 |
struct ablkcipher_request *req; unsigned long flags; int err = 0; while (dev->started < HIFN_QUEUE_LENGTH) { spin_lock_irqsave(&dev->lock, flags); |
ed4f92e37 crypto: hifn_795x... |
1980 |
backlog = crypto_get_backlog(&dev->queue); |
f7d0561ea [CRYPTO] hifn_795... |
1981 1982 1983 1984 1985 |
async_req = crypto_dequeue_request(&dev->queue); spin_unlock_irqrestore(&dev->lock, flags); if (!async_req) break; |
ed4f92e37 crypto: hifn_795x... |
1986 1987 |
if (backlog) backlog->complete(backlog, -EINPROGRESS); |
48d627648 crypto: hifn_795x... |
1988 |
req = ablkcipher_request_cast(async_req); |
f7d0561ea [CRYPTO] hifn_795... |
1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 |
err = hifn_handle_req(req); if (err) break; } return err; } static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op, u8 type, u8 mode) { int err; struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); struct hifn_device *dev = ctx->dev; err = hifn_setup_crypto_req(req, op, type, mode); if (err) return err; if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen) |
9e70a408a [HIFN]: Indicate ... |
2010 |
hifn_process_queue(dev); |
f7d0561ea [CRYPTO] hifn_795... |
2011 |
|
9e70a408a [HIFN]: Indicate ... |
2012 |
return -EINPROGRESS; |
f7d0561ea [CRYPTO] hifn_795... |
2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 |
} /* * AES ecryption functions. */ static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB); } static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC); } static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB); } static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB); } /* * AES decryption functions. */ static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB); } static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC); } static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB); } static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB); } /* * DES ecryption functions. */ static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB); } static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC); } static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB); } static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB); } /* * DES decryption functions. */ static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB); } static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC); } static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB); } static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB); } /* * 3DES ecryption functions. */ static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB); } static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC); } static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB); } static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB); } |
16f56e8b7 crypto: hifn_795x... |
2134 |
/* 3DES decryption functions. */ |
f7d0561ea [CRYPTO] hifn_795... |
2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 |
static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB); } static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC); } static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB); } static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req) { return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB); } |
16f56e8b7 crypto: hifn_795x... |
2155 |
struct hifn_alg_template { |
f7d0561ea [CRYPTO] hifn_795... |
2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 |
char name[CRYPTO_MAX_ALG_NAME]; char drv_name[CRYPTO_MAX_ALG_NAME]; unsigned int bsize; struct ablkcipher_alg ablkcipher; }; static struct hifn_alg_template hifn_alg_templates[] = { /* * 3DES ECB, CBC, CFB and OFB modes. */ { |
281d6bd45 [HIFN]: Use uniqu... |
2167 |
.name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8, |
f7d0561ea [CRYPTO] hifn_795... |
2168 2169 2170 2171 2172 2173 2174 2175 2176 |
.ablkcipher = { .min_keysize = HIFN_3DES_KEY_LENGTH, .max_keysize = HIFN_3DES_KEY_LENGTH, .setkey = hifn_setkey, .encrypt = hifn_encrypt_3des_cfb, .decrypt = hifn_decrypt_3des_cfb, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2177 |
.name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8, |
f7d0561ea [CRYPTO] hifn_795... |
2178 2179 2180 2181 2182 2183 2184 2185 2186 |
.ablkcipher = { .min_keysize = HIFN_3DES_KEY_LENGTH, .max_keysize = HIFN_3DES_KEY_LENGTH, .setkey = hifn_setkey, .encrypt = hifn_encrypt_3des_ofb, .decrypt = hifn_decrypt_3des_ofb, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2187 |
.name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8, |
f7d0561ea [CRYPTO] hifn_795... |
2188 |
.ablkcipher = { |
4b804b53e [HIFN]: Properly ... |
2189 |
.ivsize = HIFN_IV_LENGTH, |
f7d0561ea [CRYPTO] hifn_795... |
2190 2191 2192 2193 2194 2195 2196 2197 |
.min_keysize = HIFN_3DES_KEY_LENGTH, .max_keysize = HIFN_3DES_KEY_LENGTH, .setkey = hifn_setkey, .encrypt = hifn_encrypt_3des_cbc, .decrypt = hifn_decrypt_3des_cbc, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2198 |
.name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8, |
f7d0561ea [CRYPTO] hifn_795... |
2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 |
.ablkcipher = { .min_keysize = HIFN_3DES_KEY_LENGTH, .max_keysize = HIFN_3DES_KEY_LENGTH, .setkey = hifn_setkey, .encrypt = hifn_encrypt_3des_ecb, .decrypt = hifn_decrypt_3des_ecb, }, }, /* * DES ECB, CBC, CFB and OFB modes. */ { |
281d6bd45 [HIFN]: Use uniqu... |
2212 |
.name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8, |
f7d0561ea [CRYPTO] hifn_795... |
2213 2214 2215 2216 2217 2218 2219 2220 2221 |
.ablkcipher = { .min_keysize = HIFN_DES_KEY_LENGTH, .max_keysize = HIFN_DES_KEY_LENGTH, .setkey = hifn_setkey, .encrypt = hifn_encrypt_des_cfb, .decrypt = hifn_decrypt_des_cfb, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2222 |
.name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8, |
f7d0561ea [CRYPTO] hifn_795... |
2223 2224 2225 2226 2227 2228 2229 2230 2231 |
.ablkcipher = { .min_keysize = HIFN_DES_KEY_LENGTH, .max_keysize = HIFN_DES_KEY_LENGTH, .setkey = hifn_setkey, .encrypt = hifn_encrypt_des_ofb, .decrypt = hifn_decrypt_des_ofb, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2232 |
.name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8, |
f7d0561ea [CRYPTO] hifn_795... |
2233 |
.ablkcipher = { |
4b804b53e [HIFN]: Properly ... |
2234 |
.ivsize = HIFN_IV_LENGTH, |
f7d0561ea [CRYPTO] hifn_795... |
2235 2236 2237 2238 2239 2240 2241 2242 |
.min_keysize = HIFN_DES_KEY_LENGTH, .max_keysize = HIFN_DES_KEY_LENGTH, .setkey = hifn_setkey, .encrypt = hifn_encrypt_des_cbc, .decrypt = hifn_decrypt_des_cbc, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2243 |
.name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8, |
f7d0561ea [CRYPTO] hifn_795... |
2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 |
.ablkcipher = { .min_keysize = HIFN_DES_KEY_LENGTH, .max_keysize = HIFN_DES_KEY_LENGTH, .setkey = hifn_setkey, .encrypt = hifn_encrypt_des_ecb, .decrypt = hifn_decrypt_des_ecb, }, }, /* * AES ECB, CBC, CFB and OFB modes. */ { |
281d6bd45 [HIFN]: Use uniqu... |
2257 |
.name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16, |
f7d0561ea [CRYPTO] hifn_795... |
2258 2259 2260 2261 2262 2263 2264 2265 2266 |
.ablkcipher = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .setkey = hifn_setkey, .encrypt = hifn_encrypt_aes_ecb, .decrypt = hifn_decrypt_aes_ecb, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2267 |
.name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16, |
f7d0561ea [CRYPTO] hifn_795... |
2268 |
.ablkcipher = { |
4b804b53e [HIFN]: Properly ... |
2269 |
.ivsize = HIFN_AES_IV_LENGTH, |
f7d0561ea [CRYPTO] hifn_795... |
2270 2271 2272 2273 2274 2275 2276 2277 |
.min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .setkey = hifn_setkey, .encrypt = hifn_encrypt_aes_cbc, .decrypt = hifn_decrypt_aes_cbc, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2278 |
.name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16, |
f7d0561ea [CRYPTO] hifn_795... |
2279 2280 2281 2282 2283 2284 2285 2286 2287 |
.ablkcipher = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .setkey = hifn_setkey, .encrypt = hifn_encrypt_aes_cfb, .decrypt = hifn_decrypt_aes_cfb, }, }, { |
281d6bd45 [HIFN]: Use uniqu... |
2288 |
.name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16, |
f7d0561ea [CRYPTO] hifn_795... |
2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 |
.ablkcipher = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .setkey = hifn_setkey, .encrypt = hifn_encrypt_aes_ofb, .decrypt = hifn_decrypt_aes_ofb, }, }, }; static int hifn_cra_init(struct crypto_tfm *tfm) { struct crypto_alg *alg = tfm->__crt_alg; struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg); struct hifn_context *ctx = crypto_tfm_ctx(tfm); ctx->dev = ha->dev; |
5df4c0c67 crypto: hifn_795x... |
2306 |
tfm->crt_ablkcipher.reqsize = sizeof(struct hifn_request_context); |
f7d0561ea [CRYPTO] hifn_795... |
2307 2308 2309 2310 2311 2312 2313 |
return 0; } static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t) { struct hifn_crypto_alg *alg; int err; |
16f56e8b7 crypto: hifn_795x... |
2314 |
alg = kzalloc(sizeof(*alg), GFP_KERNEL); |
f7d0561ea [CRYPTO] hifn_795... |
2315 2316 2317 2318 |
if (!alg) return -ENOMEM; snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name); |
281d6bd45 [HIFN]: Use uniqu... |
2319 2320 |
snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s", t->drv_name, dev->name); |
f7d0561ea [CRYPTO] hifn_795... |
2321 2322 |
alg->alg.cra_priority = 300; |
d912bb767 crypto: Add CRYPT... |
2323 2324 |
alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC; |
f7d0561ea [CRYPTO] hifn_795... |
2325 2326 |
alg->alg.cra_blocksize = t->bsize; alg->alg.cra_ctxsize = sizeof(struct hifn_context); |
d069033b4 [HIFN]: Fix data ... |
2327 |
alg->alg.cra_alignmask = 0; |
f7d0561ea [CRYPTO] hifn_795... |
2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 |
alg->alg.cra_type = &crypto_ablkcipher_type; alg->alg.cra_module = THIS_MODULE; alg->alg.cra_u.ablkcipher = t->ablkcipher; alg->alg.cra_init = hifn_cra_init; alg->dev = dev; list_add_tail(&alg->entry, &dev->alg_list); err = crypto_register_alg(&alg->alg); if (err) { list_del(&alg->entry); kfree(alg); } return err; } static void hifn_unregister_alg(struct hifn_device *dev) { struct hifn_crypto_alg *a, *n; list_for_each_entry_safe(a, n, &dev->alg_list, entry) { list_del(&a->entry); crypto_unregister_alg(&a->alg); kfree(a); } } static int hifn_register_alg(struct hifn_device *dev) { int i, err; |
16f56e8b7 crypto: hifn_795x... |
2360 |
for (i = 0; i < ARRAY_SIZE(hifn_alg_templates); ++i) { |
f7d0561ea [CRYPTO] hifn_795... |
2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 |
err = hifn_alg_alloc(dev, &hifn_alg_templates[i]); if (err) goto err_out_exit; } return 0; err_out_exit: hifn_unregister_alg(dev); return err; } |
a1e6ef2f1 [CRYPTO] hifn: Sc... |
2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 |
static void hifn_tasklet_callback(unsigned long data) { struct hifn_device *dev = (struct hifn_device *)data; /* * This is ok to call this without lock being held, * althogh it modifies some parameters used in parallel, * (like dev->success), but they are used in process * context or update is atomic (like setting dev->sa[i] to NULL). */ |
d6a10c84a crypto: hifn_795x... |
2382 |
hifn_clear_rings(dev, 0); |
ed4f92e37 crypto: hifn_795x... |
2383 2384 2385 |
if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen) hifn_process_queue(dev); |
a1e6ef2f1 [CRYPTO] hifn: Sc... |
2386 |
} |
49cfe4db2 Drivers: crypto: ... |
2387 |
static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
f7d0561ea [CRYPTO] hifn_795... |
2388 2389 2390 2391 2392 2393 2394 2395 2396 |
{ int err, i; struct hifn_device *dev; char name[8]; err = pci_enable_device(pdev); if (err) return err; pci_set_master(pdev); |
284901a90 dma-mapping: repl... |
2397 |
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
f7d0561ea [CRYPTO] hifn_795... |
2398 2399 2400 2401 |
if (err) goto err_out_disable_pci_device; snprintf(name, sizeof(name), "hifn%d", |
16f56e8b7 crypto: hifn_795x... |
2402 |
atomic_inc_return(&hifn_dev_number) - 1); |
f7d0561ea [CRYPTO] hifn_795... |
2403 2404 2405 2406 2407 2408 2409 2410 |
err = pci_request_regions(pdev, name); if (err) goto err_out_disable_pci_device; if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE || pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE || pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) { |
cfeecab44 crypto: hifn_795x... |
2411 2412 |
dev_err(&pdev->dev, "Broken hardware - I/O regions are too small. "); |
f7d0561ea [CRYPTO] hifn_795... |
2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 |
err = -ENODEV; goto err_out_free_regions; } dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg), GFP_KERNEL); if (!dev) { err = -ENOMEM; goto err_out_free_regions; } INIT_LIST_HEAD(&dev->alg_list); snprintf(dev->name, sizeof(dev->name), "%s", name); spin_lock_init(&dev->lock); |
16f56e8b7 crypto: hifn_795x... |
2428 |
for (i = 0; i < 3; ++i) { |
f7d0561ea [CRYPTO] hifn_795... |
2429 2430 2431 2432 2433 2434 |
unsigned long addr, size; addr = pci_resource_start(pdev, i); size = pci_resource_len(pdev, i); dev->bar[i] = ioremap_nocache(addr, size); |
c2ff861d9 crypto: hifn_795x... |
2435 2436 |
if (!dev->bar[i]) { err = -ENOMEM; |
f7d0561ea [CRYPTO] hifn_795... |
2437 |
goto err_out_unmap_bars; |
c2ff861d9 crypto: hifn_795x... |
2438 |
} |
f7d0561ea [CRYPTO] hifn_795... |
2439 |
} |
7e835084f crypto: use pci_z... |
2440 2441 |
dev->desc_virt = pci_zalloc_consistent(pdev, sizeof(struct hifn_dma), &dev->desc_dma); |
f7d0561ea [CRYPTO] hifn_795... |
2442 |
if (!dev->desc_virt) { |
cfeecab44 crypto: hifn_795x... |
2443 2444 |
dev_err(&pdev->dev, "Failed to allocate descriptor rings. "); |
c2ff861d9 crypto: hifn_795x... |
2445 |
err = -ENOMEM; |
3ec858de6 crypto: hifn_795x... |
2446 |
goto err_out_unmap_bars; |
f7d0561ea [CRYPTO] hifn_795... |
2447 |
} |
f7d0561ea [CRYPTO] hifn_795... |
2448 2449 2450 |
dev->pdev = pdev; dev->irq = pdev->irq; |
16f56e8b7 crypto: hifn_795x... |
2451 |
for (i = 0; i < HIFN_D_RES_RSIZE; ++i) |
f7d0561ea [CRYPTO] hifn_795... |
2452 2453 2454 |
dev->sa[i] = NULL; pci_set_drvdata(pdev, dev); |
a1e6ef2f1 [CRYPTO] hifn: Sc... |
2455 |
tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev); |
f7d0561ea [CRYPTO] hifn_795... |
2456 2457 2458 2459 |
crypto_init_queue(&dev->queue, 1); err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev); if (err) { |
cfeecab44 crypto: hifn_795x... |
2460 2461 2462 |
dev_err(&pdev->dev, "Failed to request IRQ%d: err: %d. ", dev->irq, err); |
f7d0561ea [CRYPTO] hifn_795... |
2463 2464 2465 2466 2467 2468 2469 |
dev->irq = 0; goto err_out_free_desc; } err = hifn_start_device(dev); if (err) goto err_out_free_irq; |
fcd067559 [HIFN]: Add suppo... |
2470 |
err = hifn_register_rng(dev); |
f7d0561ea [CRYPTO] hifn_795... |
2471 2472 |
if (err) goto err_out_stop_device; |
fcd067559 [HIFN]: Add suppo... |
2473 2474 2475 |
err = hifn_register_alg(dev); if (err) goto err_out_unregister_rng; |
f7d0561ea [CRYPTO] hifn_795... |
2476 2477 |
INIT_DELAYED_WORK(&dev->work, hifn_work); schedule_delayed_work(&dev->work, HZ); |
cfeecab44 crypto: hifn_795x... |
2478 2479 2480 2481 |
dev_dbg(&pdev->dev, "HIFN crypto accelerator card at %s has been " "successfully registered as %s. ", pci_name(pdev), dev->name); |
f7d0561ea [CRYPTO] hifn_795... |
2482 2483 |
return 0; |
fcd067559 [HIFN]: Add suppo... |
2484 2485 |
err_out_unregister_rng: hifn_unregister_rng(dev); |
f7d0561ea [CRYPTO] hifn_795... |
2486 2487 2488 2489 |
err_out_stop_device: hifn_reset_dma(dev, 1); hifn_stop_device(dev); err_out_free_irq: |
b02266531 crypto: hifn_795x... |
2490 |
free_irq(dev->irq, dev); |
a1e6ef2f1 [CRYPTO] hifn: Sc... |
2491 |
tasklet_kill(&dev->tasklet); |
f7d0561ea [CRYPTO] hifn_795... |
2492 2493 2494 |
err_out_free_desc: pci_free_consistent(pdev, sizeof(struct hifn_dma), dev->desc_virt, dev->desc_dma); |
f7d0561ea [CRYPTO] hifn_795... |
2495 |
err_out_unmap_bars: |
16f56e8b7 crypto: hifn_795x... |
2496 |
for (i = 0; i < 3; ++i) |
f7d0561ea [CRYPTO] hifn_795... |
2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 |
if (dev->bar[i]) iounmap(dev->bar[i]); err_out_free_regions: pci_release_regions(pdev); err_out_disable_pci_device: pci_disable_device(pdev); return err; } |
49cfe4db2 Drivers: crypto: ... |
2508 |
static void hifn_remove(struct pci_dev *pdev) |
f7d0561ea [CRYPTO] hifn_795... |
2509 2510 2511 2512 2513 2514 2515 |
{ int i; struct hifn_device *dev; dev = pci_get_drvdata(pdev); if (dev) { |
f4e523f2a crypto: hifn_795x... |
2516 |
cancel_delayed_work_sync(&dev->work); |
f7d0561ea [CRYPTO] hifn_795... |
2517 |
|
fcd067559 [HIFN]: Add suppo... |
2518 |
hifn_unregister_rng(dev); |
f7d0561ea [CRYPTO] hifn_795... |
2519 2520 2521 |
hifn_unregister_alg(dev); hifn_reset_dma(dev, 1); hifn_stop_device(dev); |
b02266531 crypto: hifn_795x... |
2522 |
free_irq(dev->irq, dev); |
a1e6ef2f1 [CRYPTO] hifn: Sc... |
2523 |
tasklet_kill(&dev->tasklet); |
f7d0561ea [CRYPTO] hifn_795... |
2524 2525 2526 2527 2528 |
hifn_flush(dev); pci_free_consistent(pdev, sizeof(struct hifn_dma), dev->desc_virt, dev->desc_dma); |
16f56e8b7 crypto: hifn_795x... |
2529 |
for (i = 0; i < 3; ++i) |
f7d0561ea [CRYPTO] hifn_795... |
2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 |
if (dev->bar[i]) iounmap(dev->bar[i]); kfree(dev); } pci_release_regions(pdev); pci_disable_device(pdev); } static struct pci_device_id hifn_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) }, { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) }, { 0 } }; MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); static struct pci_driver hifn_pci_driver = { .name = "hifn795x", .id_table = hifn_pci_tbl, .probe = hifn_probe, |
49cfe4db2 Drivers: crypto: ... |
2551 |
.remove = hifn_remove, |
f7d0561ea [CRYPTO] hifn_795... |
2552 |
}; |
f3d8fe404 crypto: hifn_795x... |
2553 |
static int __init hifn_init(void) |
f7d0561ea [CRYPTO] hifn_795... |
2554 |
{ |
37a8023ce [HIFN]: Improve P... |
2555 |
unsigned int freq; |
f7d0561ea [CRYPTO] hifn_795... |
2556 |
int err; |
75b766258 crypto: Make hifn... |
2557 2558 |
/* HIFN supports only 32-bit addresses */ BUILD_BUG_ON(sizeof(dma_addr_t) != 4); |
a44b56cc6 crypto: hifn - Di... |
2559 |
|
37a8023ce [HIFN]: Improve P... |
2560 2561 |
if (strncmp(hifn_pll_ref, "ext", 3) && strncmp(hifn_pll_ref, "pci", 3)) { |
cfeecab44 crypto: hifn_795x... |
2562 |
pr_err("hifn795x: invalid hifn_pll_ref clock, must be pci or ext"); |
37a8023ce [HIFN]: Improve P... |
2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 |
return -EINVAL; } /* * For the 7955/7956 the reference clock frequency must be in the * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz, * but this chip is currently not supported. */ if (hifn_pll_ref[3] != '\0') { freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10); if (freq < 20 || freq > 100) { |
cfeecab44 crypto: hifn_795x... |
2574 2575 |
pr_err("hifn795x: invalid hifn_pll_ref frequency, must" "be in the range of 20-100"); |
37a8023ce [HIFN]: Improve P... |
2576 2577 2578 |
return -EINVAL; } } |
f7d0561ea [CRYPTO] hifn_795... |
2579 2580 |
err = pci_register_driver(&hifn_pci_driver); if (err < 0) { |
cfeecab44 crypto: hifn_795x... |
2581 2582 2583 |
pr_err("Failed to register PCI driver for %s device. ", hifn_pci_driver.name); |
f7d0561ea [CRYPTO] hifn_795... |
2584 2585 |
return -ENODEV; } |
cfeecab44 crypto: hifn_795x... |
2586 2587 2588 |
pr_info("Driver for HIFN 795x crypto accelerator chip " "has been successfully registered. "); |
f7d0561ea [CRYPTO] hifn_795... |
2589 2590 2591 |
return 0; } |
f3d8fe404 crypto: hifn_795x... |
2592 |
static void __exit hifn_fini(void) |
f7d0561ea [CRYPTO] hifn_795... |
2593 2594 |
{ pci_unregister_driver(&hifn_pci_driver); |
cfeecab44 crypto: hifn_795x... |
2595 2596 2597 |
pr_info("Driver for HIFN 795x crypto accelerator chip " "has been successfully unregistered. "); |
f7d0561ea [CRYPTO] hifn_795... |
2598 2599 2600 2601 2602 2603 2604 2605 |
} module_init(hifn_init); module_exit(hifn_fini); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>"); MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip."); |