Blame view
drivers/staging/rtl8192u/r8192U_dm.c
118 KB
8fc8598e6 Staging: Added Re... |
1 2 3 4 5 6 7 8 9 10 |
/*++ Copyright-c Realtek Semiconductor Corp. All rights reserved. Module Name: r8192U_dm.c Abstract: HW dynamic mechanism. Major Change History: |
35997ff0c staging/rtl8192u:... |
11 |
When Who What |
8fc8598e6 Staging: Added Re... |
12 13 14 15 16 17 18 19 20 21 22 23 |
---------- --------------- ------------------------------- 2008-05-14 amy create version 0 porting from windows code. --*/ #include "r8192U.h" #include "r8192U_dm.h" #include "r8192U_hw.h" #include "r819xU_phy.h" #include "r819xU_phyreg.h" #include "r8190_rtl8256.h" #include "r819xU_cmdpkt.h" /*---------------------------Define Local Constant---------------------------*/ |
e1da1d573 staging: rtl8192u... |
24 |
/* Indicate different AP vendor for IOT issue. */ |
04d695d77 staging: rtl8192u... |
25 26 27 28 29 30 |
static u32 edca_setting_DL[HT_IOT_PEER_MAX] = { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0x00a44f, 0x5ea44f }; static u32 edca_setting_UL[HT_IOT_PEER_MAX] = { 0x5e4322, 0x00a44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f }; |
8fc8598e6 Staging: Added Re... |
31 32 33 34 35 36 37 |
#define RTK_UL_EDCA 0xa44f #define RTK_DL_EDCA 0x5e4322 /*---------------------------Define Local Constant---------------------------*/ /*------------------------Define global variable-----------------------------*/ |
e1da1d573 staging: rtl8192u... |
38 |
/* Debug variable ? */ |
70dada1a0 Staging: rtl8192u... |
39 |
struct dig dm_digtable; |
e1da1d573 staging: rtl8192u... |
40 |
/* Store current software write register content for MAC PHY. */ |
04d695d77 staging: rtl8192u... |
41 |
u8 dm_shadow[16][256] = { {0} }; |
e1da1d573 staging: rtl8192u... |
42 |
/* For Dynamic Rx Path Selection by Signal Strength */ |
3962d2af9 Staging: rtl8192u... |
43 |
struct dynamic_rx_path_sel DM_RxPathSelTable; |
70dada1a0 Staging: rtl8192u... |
44 |
|
8fc8598e6 Staging: Added Re... |
45 46 47 48 49 50 51 52 |
/*------------------------Define global variable-----------------------------*/ /*------------------------Define local variable------------------------------*/ /*------------------------Define local variable------------------------------*/ /*--------------------Define export function prototype-----------------------*/ |
8fc8598e6 Staging: Added Re... |
53 |
extern void dm_check_fsync(struct net_device *dev); |
8fc8598e6 Staging: Added Re... |
54 55 56 57 58 |
/*--------------------Define export function prototype-----------------------*/ /*---------------------Define local function prototype-----------------------*/ |
e1da1d573 staging: rtl8192u... |
59 |
/* DM --> Rate Adaptive */ |
8fc8598e6 Staging: Added Re... |
60 |
static void dm_check_rate_adaptive(struct net_device *dev); |
e1da1d573 staging: rtl8192u... |
61 |
/* DM --> Bandwidth switch */ |
8fc8598e6 Staging: Added Re... |
62 |
static void dm_init_bandwidth_autoswitch(struct net_device *dev); |
0009631bc rtl8192u: remove ... |
63 |
static void dm_bandwidth_autoswitch(struct net_device *dev); |
8fc8598e6 Staging: Added Re... |
64 |
|
e1da1d573 staging: rtl8192u... |
65 66 |
/* DM --> TX power control */ /*static void dm_initialize_txpower_tracking(struct net_device *dev);*/ |
8fc8598e6 Staging: Added Re... |
67 68 |
static void dm_check_txpower_tracking(struct net_device *dev); |
e1da1d573 staging: rtl8192u... |
69 |
/*static void dm_txpower_reset_recovery(struct net_device *dev);*/ |
8fc8598e6 Staging: Added Re... |
70 |
|
e1da1d573 staging: rtl8192u... |
71 |
/* DM --> Dynamic Init Gain by RSSI */ |
8fc8598e6 Staging: Added Re... |
72 73 74 |
static void dm_dig_init(struct net_device *dev); static void dm_ctrl_initgain_byrssi(struct net_device *dev); static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev); |
0009631bc rtl8192u: remove ... |
75 |
static void dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device *dev); |
8fc8598e6 Staging: Added Re... |
76 77 78 79 80 81 |
static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev); static void dm_initial_gain(struct net_device *dev); static void dm_pd_th(struct net_device *dev); static void dm_cs_ratio(struct net_device *dev); static void dm_init_ctstoself(struct net_device *dev); |
e1da1d573 staging: rtl8192u... |
82 |
/* DM --> EDCA turbo mode control */ |
8fc8598e6 Staging: Added Re... |
83 |
static void dm_check_edca_turbo(struct net_device *dev); |
e1da1d573 staging: rtl8192u... |
84 85 |
/*static void dm_gpio_change_rf(struct net_device *dev);*/ /* DM --> Check PBC */ |
8fc8598e6 Staging: Added Re... |
86 |
static void dm_check_pbc_gpio(struct net_device *dev); |
e1da1d573 staging: rtl8192u... |
87 |
/* DM --> Check current RX RF path state */ |
8fc8598e6 Staging: Added Re... |
88 |
static void dm_check_rx_path_selection(struct net_device *dev); |
35997ff0c staging/rtl8192u:... |
89 |
static void dm_init_rxpath_selection(struct net_device *dev); |
8fc8598e6 Staging: Added Re... |
90 |
static void dm_rxpath_sel_byrssi(struct net_device *dev); |
e1da1d573 staging: rtl8192u... |
91 |
/* DM --> Fsync for broadcom ap */ |
8fc8598e6 Staging: Added Re... |
92 93 |
static void dm_init_fsync(struct net_device *dev); static void dm_deInit_fsync(struct net_device *dev); |
e1da1d573 staging: rtl8192u... |
94 |
/* Added by vivi, 20080522 */ |
8fc8598e6 Staging: Added Re... |
95 96 97 |
static void dm_check_txrateandretrycount(struct net_device *dev); /*---------------------Define local function prototype-----------------------*/ |
e1da1d573 staging: rtl8192u... |
98 |
/*---------------------Define of Tx Power Control For Near/Far Range --------*/ /*Add by Jacken 2008/02/18 */ |
8fc8598e6 Staging: Added Re... |
99 100 |
static void dm_init_dynamic_txpower(struct net_device *dev); static void dm_dynamic_txpower(struct net_device *dev); |
e1da1d573 staging: rtl8192u... |
101 |
/* DM --> For rate adaptive and DIG, we must send RSSI to firmware */ |
8fc8598e6 Staging: Added Re... |
102 103 104 |
static void dm_send_rssi_tofw(struct net_device *dev); static void dm_ctstoself(struct net_device *dev); /*---------------------------Define function prototype------------------------*/ |
e1da1d573 staging: rtl8192u... |
105 106 107 108 109 110 111 112 113 114 |
/* * ================================================================================ * HW Dynamic mechanism interface. * ================================================================================ * * * Description: * Prepare SW resource for HW dynamic mechanism. * * Assumption: |
69e98df78 Staging: fixed mu... |
115 |
* This function is only invoked at driver initialization once. |
e1da1d573 staging: rtl8192u... |
116 |
*/ |
bf316434a staging: rtl8192u... |
117 |
void init_hal_dm(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
118 119 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
120 |
/* Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism. */ |
8fc8598e6 Staging: Added Re... |
121 |
priv->undecorated_smoothed_pwdb = -1; |
e1da1d573 staging: rtl8192u... |
122 |
/* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */ |
8fc8598e6 Staging: Added Re... |
123 124 |
dm_init_dynamic_txpower(dev); init_rate_adaptive(dev); |
e1da1d573 staging: rtl8192u... |
125 |
/*dm_initialize_txpower_tracking(dev);*/ |
8fc8598e6 Staging: Added Re... |
126 127 128 129 130 131 |
dm_dig_init(dev); dm_init_edca_turbo(dev); dm_init_bandwidth_autoswitch(dev); dm_init_fsync(dev); dm_init_rxpath_selection(dev); dm_init_ctstoself(dev); |
e1da1d573 staging: rtl8192u... |
132 |
} /* InitHalDm */ |
8fc8598e6 Staging: Added Re... |
133 |
|
c541fa875 staging:rtl8192u:... |
134 |
void deinit_hal_dm(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
135 |
{ |
8fc8598e6 Staging: Added Re... |
136 |
dm_deInit_fsync(dev); |
8fc8598e6 Staging: Added Re... |
137 |
} |
8fc8598e6 Staging: Added Re... |
138 |
#ifdef USB_RX_AGGREGATION_SUPPORT |
04d695d77 staging: rtl8192u... |
139 140 |
void dm_CheckRxAggregation(struct net_device *dev) { |
efdcb35a8 Staging: rtl8192u... |
141 |
struct r8192_priv *priv = ieee80211_priv(dev); |
8fc8598e6 Staging: Added Re... |
142 |
PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; |
de13a3dad staging/rtl8192u:... |
143 144 |
static unsigned long lastTxOkCnt; static unsigned long lastRxOkCnt; |
8fc8598e6 Staging: Added Re... |
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 |
unsigned long curTxOkCnt = 0; unsigned long curRxOkCnt = 0; /* if (pHalData->bForcedUsbRxAggr) { if (pHalData->ForcedUsbRxAggrInfo == 0) { if (pHalData->bCurrentRxAggrEnable) { Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE); } } else { if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) { Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE); } } return; } */ curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; |
2930d0b97 staging: rtl8192u... |
165 |
if ((curTxOkCnt + curRxOkCnt) < 15000000) |
8fc8598e6 Staging: Added Re... |
166 |
return; |
8fc8598e6 Staging: Added Re... |
167 |
|
04d695d77 staging: rtl8192u... |
168 |
if (curTxOkCnt > 4*curRxOkCnt) { |
8fc8598e6 Staging: Added Re... |
169 170 171 172 |
if (priv->bCurrentRxAggrEnable) { write_nic_dword(dev, 0x1a8, 0); priv->bCurrentRxAggrEnable = false; } |
04d695d77 staging: rtl8192u... |
173 |
} else { |
8fc8598e6 Staging: Added Re... |
174 175 |
if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) { u32 ulValue; |
04d695d77 staging: rtl8192u... |
176 |
|
8fc8598e6 Staging: Added Re... |
177 178 179 180 181 182 183 184 185 186 187 188 189 190 |
ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) | (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout); /* * If usb rx firmware aggregation is enabled, * when anyone of three threshold conditions above is reached, * firmware will send aggregated packet to driver. */ write_nic_dword(dev, 0x1a8, ulValue); priv->bCurrentRxAggrEnable = true; } } lastTxOkCnt = priv->stats.txbytesunicast; lastRxOkCnt = priv->stats.rxbytesunicast; |
e1da1d573 staging: rtl8192u... |
191 |
} /* dm_CheckEdcaTurbo */ |
8fc8598e6 Staging: Added Re... |
192 |
#endif |
bf316434a staging: rtl8192u... |
193 |
void hal_dm_watchdog(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
194 |
{ |
e1da1d573 staging: rtl8192u... |
195 |
/*struct r8192_priv *priv = ieee80211_priv(dev);*/ |
8fc8598e6 Staging: Added Re... |
196 |
|
e1da1d573 staging: rtl8192u... |
197 |
/*static u8 previous_bssid[6] ={0};*/ |
8fc8598e6 Staging: Added Re... |
198 199 200 201 202 203 204 205 206 |
/*Add by amy 2008/05/15 ,porting from windows code.*/ dm_check_rate_adaptive(dev); dm_dynamic_txpower(dev); dm_check_txrateandretrycount(dev); dm_check_txpower_tracking(dev); dm_ctrl_initgain_byrssi(dev); dm_check_edca_turbo(dev); dm_bandwidth_autoswitch(dev); |
8fc8598e6 Staging: Added Re... |
207 208 |
dm_check_rx_path_selection(dev); dm_check_fsync(dev); |
e1da1d573 staging: rtl8192u... |
209 |
/* Add by amy 2008-05-15 porting from windows code. */ |
8fc8598e6 Staging: Added Re... |
210 211 212 213 214 215 |
dm_check_pbc_gpio(dev); dm_send_rssi_tofw(dev); dm_ctstoself(dev); #ifdef USB_RX_AGGREGATION_SUPPORT dm_CheckRxAggregation(dev); #endif |
e1da1d573 staging: rtl8192u... |
216 |
} /* HalDmWatchDog */ |
8fc8598e6 Staging: Added Re... |
217 |
|
8fc8598e6 Staging: Added Re... |
218 |
/* |
e1da1d573 staging: rtl8192u... |
219 220 221 222 223 |
* Decide Rate Adaptive Set according to distance (signal strength) * 01/11/2008 MHC Modify input arguments and RATR table level. * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call * the function after making sure RF_Type. */ |
c541fa875 staging:rtl8192u:... |
224 |
void init_rate_adaptive(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
225 |
{ |
8fc8598e6 Staging: Added Re... |
226 227 228 229 230 231 232 233 234 235 236 |
struct r8192_priv *priv = ieee80211_priv(dev); prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive; pra->ratr_state = DM_RATR_STA_MAX; pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High; pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5; pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5; pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5; pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M; pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M; |
04d695d77 staging: rtl8192u... |
237 |
if (priv->CustomerID == RT_CID_819x_Netcore) |
8fc8598e6 Staging: Added Re... |
238 239 240 241 |
pra->ping_rssi_enable = 1; else pra->ping_rssi_enable = 0; pra->ping_rssi_thresh_for_ra = 15; |
04d695d77 staging: rtl8192u... |
242 |
if (priv->rf_type == RF_2T4R) { |
e1da1d573 staging: rtl8192u... |
243 244 245 246 |
/* * 07/10/08 MH Modify for RA smooth scheme. * 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code. */ |
35997ff0c staging/rtl8192u:... |
247 248 249 250 251 |
pra->upper_rssi_threshold_ratr = 0x8f0f0000; pra->middle_rssi_threshold_ratr = 0x8f0ff000; pra->low_rssi_threshold_ratr = 0x8f0ff001; pra->low_rssi_threshold_ratr_40M = 0x8f0ff005; pra->low_rssi_threshold_ratr_20M = 0x8f0ff001; |
e1da1d573 staging: rtl8192u... |
252 |
pra->ping_rssi_ratr = 0x0000000d;/* cosa add for test */ |
04d695d77 staging: rtl8192u... |
253 |
} else if (priv->rf_type == RF_1T2R) { |
35997ff0c staging/rtl8192u:... |
254 255 256 257 258 |
pra->upper_rssi_threshold_ratr = 0x000f0000; pra->middle_rssi_threshold_ratr = 0x000ff000; pra->low_rssi_threshold_ratr = 0x000ff001; pra->low_rssi_threshold_ratr_40M = 0x000ff005; pra->low_rssi_threshold_ratr_20M = 0x000ff001; |
e1da1d573 staging: rtl8192u... |
259 |
pra->ping_rssi_ratr = 0x0000000d;/* cosa add for test */ |
8fc8598e6 Staging: Added Re... |
260 |
} |
e1da1d573 staging: rtl8192u... |
261 |
} /* InitRateAdaptive */ |
8fc8598e6 Staging: Added Re... |
262 |
|
8fc8598e6 Staging: Added Re... |
263 264 265 266 267 268 269 270 271 272 273 274 275 |
/*----------------------------------------------------------------------------- * Function: dm_check_rate_adaptive() * * Overview: * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark |
35997ff0c staging/rtl8192u:... |
276 |
* 05/26/08 amy Create version 0 porting from windows code. |
8fc8598e6 Staging: Added Re... |
277 278 |
* *---------------------------------------------------------------------------*/ |
999d594b7 STAGING: rtl8192u... |
279 |
static void dm_check_rate_adaptive(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
280 281 282 283 284 285 286 |
{ struct r8192_priv *priv = ieee80211_priv(dev); PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive; u32 currentRATR, targetRATR = 0; u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0; bool bshort_gi_enabled = false; |
de13a3dad staging/rtl8192u:... |
287 |
static u8 ping_rssi_state; |
8fc8598e6 Staging: Added Re... |
288 |
|
04d695d77 staging: rtl8192u... |
289 |
if (!priv->up) { |
8fc8598e6 Staging: Added Re... |
290 291 292 293 |
RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload "); return; } |
04d695d77 staging: rtl8192u... |
294 |
if (pra->rate_adaptive_disabled) /* this variable is set by ioctl. */ |
8fc8598e6 Staging: Added Re... |
295 |
return; |
e1da1d573 staging: rtl8192u... |
296 |
/* TODO: Only 11n mode is implemented currently, */ |
04d695d77 staging: rtl8192u... |
297 298 299 |
if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G || priv->ieee80211->mode == WIRELESS_MODE_N_5G)) return; |
8fc8598e6 Staging: Added Re... |
300 |
|
04d695d77 staging: rtl8192u... |
301 |
if (priv->ieee80211->state == IEEE80211_LINKED) { |
e1da1d573 staging: rtl8192u... |
302 |
/*RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");*/ |
8fc8598e6 Staging: Added Re... |
303 |
|
e1da1d573 staging: rtl8192u... |
304 |
/* Check whether Short GI is enabled */ |
8fc8598e6 Staging: Added Re... |
305 306 |
bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) || (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz); |
8fc8598e6 Staging: Added Re... |
307 |
pra->upper_rssi_threshold_ratr = |
56b3152e5 rtl8192u: BIT() m... |
308 309 |
(pra->upper_rssi_threshold_ratr & (~BIT(31))) | ((bshort_gi_enabled) ? BIT(31) : 0); |
8fc8598e6 Staging: Added Re... |
310 311 |
pra->middle_rssi_threshold_ratr = |
56b3152e5 rtl8192u: BIT() m... |
312 313 |
(pra->middle_rssi_threshold_ratr & (~BIT(31))) | ((bshort_gi_enabled) ? BIT(31) : 0); |
8fc8598e6 Staging: Added Re... |
314 |
|
04d695d77 staging: rtl8192u... |
315 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
8fc8598e6 Staging: Added Re... |
316 |
pra->low_rssi_threshold_ratr = |
56b3152e5 rtl8192u: BIT() m... |
317 318 |
(pra->low_rssi_threshold_ratr_40M & (~BIT(31))) | ((bshort_gi_enabled) ? BIT(31) : 0); |
04d695d77 staging: rtl8192u... |
319 |
} else { |
8fc8598e6 Staging: Added Re... |
320 |
pra->low_rssi_threshold_ratr = |
56b3152e5 rtl8192u: BIT() m... |
321 322 |
(pra->low_rssi_threshold_ratr_20M & (~BIT(31))) | ((bshort_gi_enabled) ? BIT(31) : 0); |
8fc8598e6 Staging: Added Re... |
323 |
} |
e1da1d573 staging: rtl8192u... |
324 |
/* cosa add for test */ |
8fc8598e6 Staging: Added Re... |
325 |
pra->ping_rssi_ratr = |
56b3152e5 rtl8192u: BIT() m... |
326 327 |
(pra->ping_rssi_ratr & (~BIT(31))) | ((bshort_gi_enabled) ? BIT(31) : 0); |
8fc8598e6 Staging: Added Re... |
328 329 330 331 332 |
/* 2007/10/08 MH We support RA smooth scheme now. When it is the first time to link with AP. We will not change upper/lower threshold. If STA stay in high or low level, we must change two different threshold to prevent jumping frequently. */ |
04d695d77 staging: rtl8192u... |
333 |
if (pra->ratr_state == DM_RATR_STA_HIGH) { |
35997ff0c staging/rtl8192u:... |
334 |
HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra; |
04d695d77 staging: rtl8192u... |
335 |
LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? |
8fc8598e6 Staging: Added Re... |
336 |
(pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M); |
04d695d77 staging: rtl8192u... |
337 |
} else if (pra->ratr_state == DM_RATR_STA_LOW) { |
8fc8598e6 Staging: Added Re... |
338 |
HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; |
04d695d77 staging: rtl8192u... |
339 |
LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? |
8fc8598e6 Staging: Added Re... |
340 |
(pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M); |
04d695d77 staging: rtl8192u... |
341 |
} else { |
8fc8598e6 Staging: Added Re... |
342 |
HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; |
04d695d77 staging: rtl8192u... |
343 |
LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? |
8fc8598e6 Staging: Added Re... |
344 345 |
(pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M); } |
e1da1d573 staging: rtl8192u... |
346 347 |
/*DbgPrint("[DM] THresh H/L=%d/%d \r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);*/ |
04d695d77 staging: rtl8192u... |
348 |
if (priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) { |
e1da1d573 staging: rtl8192u... |
349 350 |
/*DbgPrint("[DM] RSSI=%d STA=HIGH \r", pHalData->UndecoratedSmoothedPWDB);*/ |
8fc8598e6 Staging: Added Re... |
351 352 |
pra->ratr_state = DM_RATR_STA_HIGH; targetRATR = pra->upper_rssi_threshold_ratr; |
04d695d77 staging: rtl8192u... |
353 |
} else if (priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) { |
e1da1d573 staging: rtl8192u... |
354 355 |
/*DbgPrint("[DM] RSSI=%d STA=Middle \r", pHalData->UndecoratedSmoothedPWDB);*/ |
8fc8598e6 Staging: Added Re... |
356 357 |
pra->ratr_state = DM_RATR_STA_MIDDLE; targetRATR = pra->middle_rssi_threshold_ratr; |
04d695d77 staging: rtl8192u... |
358 |
} else { |
e1da1d573 staging: rtl8192u... |
359 360 |
/*DbgPrint("[DM] RSSI=%d STA=LOW \r", pHalData->UndecoratedSmoothedPWDB);*/ |
8fc8598e6 Staging: Added Re... |
361 362 363 |
pra->ratr_state = DM_RATR_STA_LOW; targetRATR = pra->low_rssi_threshold_ratr; } |
e1da1d573 staging: rtl8192u... |
364 |
/* cosa add for test */ |
04d695d77 staging: rtl8192u... |
365 |
if (pra->ping_rssi_enable) { |
e1da1d573 staging: rtl8192u... |
366 |
/*pHalData->UndecoratedSmoothedPWDB = 19;*/ |
04d695d77 staging: rtl8192u... |
367 368 369 370 371 |
if (priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) { if ((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) || ping_rssi_state) { /*DbgPrint("TestRSSI = %d, set RATR to 0x%x ", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);*/ |
8fc8598e6 Staging: Added Re... |
372 373 374 375 |
pra->ratr_state = DM_RATR_STA_LOW; targetRATR = pra->ping_rssi_ratr; ping_rssi_state = 1; } |
e1da1d573 staging: rtl8192u... |
376 |
/*else |
04d695d77 staging: rtl8192u... |
377 378 379 380 381 |
DbgPrint("TestRSSI is between the range. ");*/ } else { /*DbgPrint("TestRSSI Recover to 0x%x ", targetRATR);*/ |
8fc8598e6 Staging: Added Re... |
382 383 384 |
ping_rssi_state = 0; } } |
e1da1d573 staging: rtl8192u... |
385 386 387 388 |
/* * 2008.04.01 * For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7. */ |
04d695d77 staging: rtl8192u... |
389 390 |
if (priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev)) targetRATR &= 0xf00fffff; |
8fc8598e6 Staging: Added Re... |
391 |
|
e1da1d573 staging: rtl8192u... |
392 |
/* Check whether updating of RATR0 is required */ |
b3d42bf18 staging: rtl8192u... |
393 |
read_nic_dword(dev, RATR0, ¤tRATR); |
04d695d77 staging: rtl8192u... |
394 |
if (targetRATR != currentRATR) { |
8fc8598e6 Staging: Added Re... |
395 |
u32 ratr_value; |
04d695d77 staging: rtl8192u... |
396 |
|
8fc8598e6 Staging: Added Re... |
397 |
ratr_value = targetRATR; |
04d695d77 staging: rtl8192u... |
398 399 |
RT_TRACE(COMP_RATE, "currentRATR = %x, targetRATR = %x ", currentRATR, targetRATR); |
16da78083 staging: rtl8192u... |
400 |
if (priv->rf_type == RF_1T2R) |
8fc8598e6 Staging: Added Re... |
401 |
ratr_value &= ~(RATE_ALL_OFDM_2SS); |
8fc8598e6 Staging: Added Re... |
402 403 404 405 406 |
write_nic_dword(dev, RATR0, ratr_value); write_nic_byte(dev, UFWP, 1); pra->last_ratr = targetRATR; } |
04d695d77 staging: rtl8192u... |
407 |
} else { |
8fc8598e6 Staging: Added Re... |
408 409 |
pra->ratr_state = DM_RATR_STA_MAX; } |
e1da1d573 staging: rtl8192u... |
410 |
} /* dm_CheckRateAdaptive */ |
8fc8598e6 Staging: Added Re... |
411 |
|
999d594b7 STAGING: rtl8192u... |
412 |
static void dm_init_bandwidth_autoswitch(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
413 414 415 416 417 418 419 |
{ struct r8192_priv *priv = ieee80211_priv(dev); priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH; priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW; priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false; priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false; |
e1da1d573 staging: rtl8192u... |
420 |
} /* dm_init_bandwidth_autoswitch */ |
8fc8598e6 Staging: Added Re... |
421 |
|
999d594b7 STAGING: rtl8192u... |
422 |
static void dm_bandwidth_autoswitch(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
423 424 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
16da78083 staging: rtl8192u... |
425 |
if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || !priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable) |
8fc8598e6 Staging: Added Re... |
426 |
return; |
f9bd549aa staging: rtl8192u... |
427 |
if (!priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz) { /* If send packets in 40 Mhz in 20/40 */ |
04d695d77 staging: rtl8192u... |
428 |
if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz) |
2fd8feab5 Staging: rtl8192u... |
429 |
priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true; |
04d695d77 staging: rtl8192u... |
430 431 |
} else { /* in force send packets in 20 Mhz in 20/40 */ if (priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz) |
2fd8feab5 Staging: rtl8192u... |
432 |
priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false; |
8fc8598e6 Staging: Added Re... |
433 |
} |
e1da1d573 staging: rtl8192u... |
434 |
} /* dm_BandwidthAutoSwitch */ |
8fc8598e6 Staging: Added Re... |
435 |
|
e1da1d573 staging: rtl8192u... |
436 |
/* OFDM default at 0db, index=6. */ |
8fc8598e6 Staging: Added Re... |
437 |
static u32 OFDMSwingTable[OFDM_Table_Length] = { |
e1da1d573 staging: rtl8192u... |
438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 |
0x7f8001fe, /* 0, +6db */ 0x71c001c7, /* 1, +5db */ 0x65400195, /* 2, +4db */ 0x5a400169, /* 3, +3db */ 0x50800142, /* 4, +2db */ 0x47c0011f, /* 5, +1db */ 0x40000100, /* 6, +0db ===> default, upper for higher temperature, lower for low temperature */ 0x390000e4, /* 7, -1db */ 0x32c000cb, /* 8, -2db */ 0x2d4000b5, /* 9, -3db */ 0x288000a2, /* 10, -4db */ 0x24000090, /* 11, -5db */ 0x20000080, /* 12, -6db */ 0x1c800072, /* 13, -7db */ 0x19800066, /* 14, -8db */ 0x26c0005b, /* 15, -9db */ 0x24400051, /* 16, -10db */ 0x12000048, /* 17, -11db */ 0x10000040 /* 18, -12db */ |
8fc8598e6 Staging: Added Re... |
457 458 459 |
}; static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = { |
e1da1d573 staging: rtl8192u... |
460 461 462 463 464 465 466 467 468 469 470 471 |
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0db ===> CCK40M default */ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 1, -1db */ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 2, -2db */ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 3, -3db */ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 4, -4db */ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 5, -5db */ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 6, -6db ===> CCK20M default */ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 7, -7db */ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 8, -8db */ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 9, -9db */ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 10, -10db */ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} /* 11, -11db */ |
8fc8598e6 Staging: Added Re... |
472 473 474 |
}; static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = { |
e1da1d573 staging: rtl8192u... |
475 476 477 478 479 480 481 482 483 484 485 486 |
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0db ===> CCK40M default */ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 1, -1db */ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 2, -2db */ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 3, -3db */ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 4, -4db */ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 5, -5db */ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 6, -6db ===> CCK20M default */ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 7, -7db */ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 8, -8db */ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 9, -9db */ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 10, -10db */ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} /* 11, -11db */ |
8fc8598e6 Staging: Added Re... |
487 |
}; |
999d594b7 STAGING: rtl8192u... |
488 |
static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
489 490 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
4b2faf802 Staging: rtl8192u... |
491 |
bool bHighpowerstate, viviflag = false; |
8fc8598e6 Staging: Added Re... |
492 493 |
DCMD_TXCMD_T tx_cmd; u8 powerlevelOFDM24G; |
04d695d77 staging: rtl8192u... |
494 495 |
int i = 0, j = 0, k = 0; u8 RF_Type, tmp_report[5] = {0, 0, 0, 0, 0}; |
8fc8598e6 Staging: Added Re... |
496 497 |
u32 Value; u8 Pwr_Flag; |
04d695d77 staging: rtl8192u... |
498 |
u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0; |
e1da1d573 staging: rtl8192u... |
499 |
/*RT_STATUS rtStatus = RT_STATUS_SUCCESS;*/ |
8fc8598e6 Staging: Added Re... |
500 |
bool rtStatus = true; |
04d695d77 staging: rtl8192u... |
501 |
u32 delta = 0; |
8fc8598e6 Staging: Added Re... |
502 503 504 505 506 507 508 509 510 511 512 513 |
write_nic_byte(dev, 0x1ba, 0); priv->ieee80211->bdynamic_txpower_enable = false; bHighpowerstate = priv->bDynamicTxHighPower; powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24); RF_Type = priv->rf_type; Value = (RF_Type<<8) | powerlevelOFDM24G; RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x ", powerlevelOFDM24G); |
04d695d77 staging: rtl8192u... |
514 515 516 517 518 |
for (j = 0; j <= 30; j++) { /* fill tx_cmd */ tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING; tx_cmd.Length = 4; tx_cmd.Value = Value; rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12); |
16da78083 staging: rtl8192u... |
519 |
if (rtStatus == RT_STATUS_FAILURE) |
04d695d77 staging: rtl8192u... |
520 521 |
RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail! "); |
04d695d77 staging: rtl8192u... |
522 523 524 525 526 527 528 529 530 531 532 533 534 |
mdelay(1); /*DbgPrint("hi, vivi, strange ");*/ for (i = 0; i <= 30; i++) { read_nic_byte(dev, 0x1ba, &Pwr_Flag); if (Pwr_Flag == 0) { mdelay(1); continue; } read_nic_word(dev, 0x13c, &Avg_TSSI_Meas); if (Avg_TSSI_Meas == 0) { write_nic_byte(dev, 0x1ba, 0); |
8fc8598e6 Staging: Added Re... |
535 536 |
break; } |
8fc8598e6 Staging: Added Re... |
537 |
|
04d695d77 staging: rtl8192u... |
538 539 540 541 542 543 544 545 |
for (k = 0; k < 5; k++) { if (k != 4) read_nic_byte(dev, 0x134+k, &tmp_report[k]); else read_nic_byte(dev, 0x13e, &tmp_report[k]); RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d ", tmp_report[k]); } |
8fc8598e6 Staging: Added Re... |
546 |
|
04d695d77 staging: rtl8192u... |
547 548 549 |
/* check if the report value is right */ for (k = 0; k < 5; k++) { if (tmp_report[k] <= 20) { |
4b2faf802 Staging: rtl8192u... |
550 |
viviflag = true; |
04d695d77 staging: rtl8192u... |
551 |
break; |
8fc8598e6 Staging: Added Re... |
552 553 |
} } |
c40753b5c staging: rtl8192u... |
554 |
if (viviflag) { |
04d695d77 staging: rtl8192u... |
555 |
write_nic_byte(dev, 0x1ba, 0); |
4b2faf802 Staging: rtl8192u... |
556 |
viviflag = false; |
04d695d77 staging: rtl8192u... |
557 558 559 560 561 562 |
RT_TRACE(COMP_POWER_TRACKING, "we filtered the data "); for (k = 0; k < 5; k++) tmp_report[k] = 0; break; } |
8fc8598e6 Staging: Added Re... |
563 |
|
16da78083 staging: rtl8192u... |
564 |
for (k = 0; k < 5; k++) |
04d695d77 staging: rtl8192u... |
565 |
Avg_TSSI_Meas_from_driver += tmp_report[k]; |
8fc8598e6 Staging: Added Re... |
566 |
|
04d695d77 staging: rtl8192u... |
567 568 569 570 571 572 573 574 575 576 577 |
Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5; RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d ", Avg_TSSI_Meas_from_driver); TSSI_13dBm = priv->TSSI_13dBm; RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d ", TSSI_13dBm); /*if (abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)*/ /* For MacOS-compatible */ if (Avg_TSSI_Meas_from_driver > TSSI_13dBm) delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm; |
8fc8598e6 Staging: Added Re... |
578 |
else |
04d695d77 staging: rtl8192u... |
579 580 581 |
delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver; if (delta <= E_FOR_TX_POWER_TRACK) { |
4b2faf802 Staging: rtl8192u... |
582 |
priv->ieee80211->bdynamic_txpower_enable = true; |
04d695d77 staging: rtl8192u... |
583 584 585 586 587 588 589 590 591 592 593 594 |
write_nic_byte(dev, 0x1ba, 0); RT_TRACE(COMP_POWER_TRACKING, "tx power track is done "); RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d ", priv->rfa_txpowertrackingindex); RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d ", priv->rfa_txpowertrackingindex_real); RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d ", priv->cck_present_attentuation_difference); RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d ", priv->cck_present_attentuation); return; |
16da78083 staging: rtl8192u... |
595 596 597 598 599 600 |
} if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) { if (priv->rfa_txpowertrackingindex > 0) { priv->rfa_txpowertrackingindex--; if (priv->rfa_txpowertrackingindex_real > 4) { priv->rfa_txpowertrackingindex_real--; |
04d695d77 staging: rtl8192u... |
601 |
rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); |
04d695d77 staging: rtl8192u... |
602 |
} |
8fc8598e6 Staging: Added Re... |
603 |
} |
16da78083 staging: rtl8192u... |
604 605 606 607 608 |
} else { if (priv->rfa_txpowertrackingindex < 36) { priv->rfa_txpowertrackingindex++; priv->rfa_txpowertrackingindex_real++; rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); |
04d695d77 staging: rtl8192u... |
609 |
|
04d695d77 staging: rtl8192u... |
610 |
} |
16da78083 staging: rtl8192u... |
611 612 613 |
} priv->cck_present_attentuation_difference = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default; |
04d695d77 staging: rtl8192u... |
614 |
|
16da78083 staging: rtl8192u... |
615 616 617 618 619 620 621 622 623 |
if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) priv->cck_present_attentuation = priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference; else priv->cck_present_attentuation = priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference; if (priv->cck_present_attentuation > -1 && priv->cck_present_attentuation < 23) { if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) { |
4b2faf802 Staging: rtl8192u... |
624 |
priv->bcck_in_ch14 = true; |
16da78083 staging: rtl8192u... |
625 626 |
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) { |
4b2faf802 Staging: rtl8192u... |
627 |
priv->bcck_in_ch14 = false; |
16da78083 staging: rtl8192u... |
628 629 630 631 632 633 634 635 636 637 638 639 |
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } else dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d ", priv->rfa_txpowertrackingindex); RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d ", priv->rfa_txpowertrackingindex_real); RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d ", priv->cck_present_attentuation_difference); RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d ", priv->cck_present_attentuation); |
04d695d77 staging: rtl8192u... |
640 |
|
16da78083 staging: rtl8192u... |
641 |
if (priv->cck_present_attentuation_difference <= -12 || priv->cck_present_attentuation_difference >= 24) { |
4b2faf802 Staging: rtl8192u... |
642 |
priv->ieee80211->bdynamic_txpower_enable = true; |
16da78083 staging: rtl8192u... |
643 644 645 646 |
write_nic_byte(dev, 0x1ba, 0); RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited "); return; |
8fc8598e6 Staging: Added Re... |
647 |
} |
16da78083 staging: rtl8192u... |
648 |
|
8fc8598e6 Staging: Added Re... |
649 |
write_nic_byte(dev, 0x1ba, 0); |
04d695d77 staging: rtl8192u... |
650 651 652 653 |
Avg_TSSI_Meas_from_driver = 0; for (k = 0; k < 5; k++) tmp_report[k] = 0; break; |
8fc8598e6 Staging: Added Re... |
654 |
} |
8fc8598e6 Staging: Added Re... |
655 |
} |
4b2faf802 Staging: rtl8192u... |
656 |
priv->ieee80211->bdynamic_txpower_enable = true; |
04d695d77 staging: rtl8192u... |
657 |
write_nic_byte(dev, 0x1ba, 0); |
8fc8598e6 Staging: Added Re... |
658 |
} |
999d594b7 STAGING: rtl8192u... |
659 |
static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
660 661 662 663 664 |
{ #define ThermalMeterVal 9 struct r8192_priv *priv = ieee80211_priv(dev); u32 tmpRegA, TempCCk; u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval; |
04d695d77 staging: rtl8192u... |
665 |
int i = 0, CCKSwingNeedUpdate = 0; |
8fc8598e6 Staging: Added Re... |
666 |
|
04d695d77 staging: rtl8192u... |
667 |
if (!priv->btxpower_trackingInit) { |
e1da1d573 staging: rtl8192u... |
668 |
/* Query OFDM default setting */ |
04d695d77 staging: rtl8192u... |
669 670 671 672 |
tmpRegA = rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord); for (i = 0; i < OFDM_Table_Length; i++) { /* find the index */ if (tmpRegA == OFDMSwingTable[i]) { priv->OFDM_index = (u8)i; |
8fc8598e6 Staging: Added Re... |
673 674 675 676 677 |
RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x ", rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index); } } |
e1da1d573 staging: rtl8192u... |
678 |
/* Query CCK default setting From 0xa22 */ |
8fc8598e6 Staging: Added Re... |
679 |
TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); |
04d695d77 staging: rtl8192u... |
680 681 682 |
for (i = 0; i < CCK_Table_length; i++) { if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) { priv->CCK_index = (u8) i; |
8fc8598e6 Staging: Added Re... |
683 684 685 686 687 688 |
RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x ", rCCK0_TxFilter1, TempCCk, priv->CCK_index); break; } } |
4b2faf802 Staging: rtl8192u... |
689 |
priv->btxpower_trackingInit = true; |
e1da1d573 staging: rtl8192u... |
690 |
/*pHalData->TXPowercount = 0;*/ |
8fc8598e6 Staging: Added Re... |
691 692 |
return; } |
e1da1d573 staging: rtl8192u... |
693 694 695 696 697 |
/* * ========================== * this is only for test, should be masked * ========================== */ |
8fc8598e6 Staging: Added Re... |
698 |
|
e1da1d573 staging: rtl8192u... |
699 700 |
/* read and filter out unreasonable value */ tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); /* 0x12: RF Reg[10:7] */ |
04d695d77 staging: rtl8192u... |
701 702 703 |
RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d ", tmpRegA); if (tmpRegA < 3 || tmpRegA > 13) |
8fc8598e6 Staging: Added Re... |
704 |
return; |
04d695d77 staging: rtl8192u... |
705 |
if (tmpRegA >= 12) /* if over 12, TP will be bad when high temperature */ |
8fc8598e6 Staging: Added Re... |
706 |
tmpRegA = 12; |
04d695d77 staging: rtl8192u... |
707 708 |
RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d ", tmpRegA); |
e1da1d573 staging: rtl8192u... |
709 710 |
priv->ThermalMeter[0] = ThermalMeterVal; /* We use fixed value by Bryant's suggestion */ priv->ThermalMeter[1] = ThermalMeterVal; /* We use fixed value by Bryant's suggestion */ |
8fc8598e6 Staging: Added Re... |
711 |
|
e1da1d573 staging: rtl8192u... |
712 |
/* Get current RF-A temperature index */ |
04d695d77 staging: rtl8192u... |
713 |
if (priv->ThermalMeter[0] >= (u8)tmpRegA) { /* lower temperature */ |
8fc8598e6 Staging: Added Re... |
714 715 |
tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA); tmpCCK40Mindex = tmpCCK20Mindex - 6; |
04d695d77 staging: rtl8192u... |
716 |
if (tmpOFDMindex >= OFDM_Table_Length) |
8fc8598e6 Staging: Added Re... |
717 |
tmpOFDMindex = OFDM_Table_Length-1; |
04d695d77 staging: rtl8192u... |
718 |
if (tmpCCK20Mindex >= CCK_Table_length) |
8fc8598e6 Staging: Added Re... |
719 |
tmpCCK20Mindex = CCK_Table_length-1; |
04d695d77 staging: rtl8192u... |
720 |
if (tmpCCK40Mindex >= CCK_Table_length) |
8fc8598e6 Staging: Added Re... |
721 |
tmpCCK40Mindex = CCK_Table_length-1; |
04d695d77 staging: rtl8192u... |
722 |
} else { |
2060f31ae Staging: rtl8192u... |
723 |
tmpval = (u8)tmpRegA - priv->ThermalMeter[0]; |
04d695d77 staging: rtl8192u... |
724 725 726 |
if (tmpval >= 6) /* higher temperature */ tmpOFDMindex = tmpCCK20Mindex = 0; /* max to +6dB */ |
8fc8598e6 Staging: Added Re... |
727 728 729 730 |
else tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval; tmpCCK40Mindex = 0; } |
e1da1d573 staging: rtl8192u... |
731 732 733 |
/*DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d", ((u1Byte)tmpRegA - pHalData->ThermalMeter[0]), tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);*/ |
04d695d77 staging: rtl8192u... |
734 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) /* 40M */ |
8fc8598e6 Staging: Added Re... |
735 736 737 |
tmpCCKindex = tmpCCK40Mindex; else tmpCCKindex = tmpCCK20Mindex; |
04d695d77 staging: rtl8192u... |
738 |
if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) { |
4b2faf802 Staging: rtl8192u... |
739 |
priv->bcck_in_ch14 = true; |
8fc8598e6 Staging: Added Re... |
740 |
CCKSwingNeedUpdate = 1; |
04d695d77 staging: rtl8192u... |
741 |
} else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) { |
4b2faf802 Staging: rtl8192u... |
742 |
priv->bcck_in_ch14 = false; |
8fc8598e6 Staging: Added Re... |
743 744 |
CCKSwingNeedUpdate = 1; } |
04d695d77 staging: rtl8192u... |
745 |
if (priv->CCK_index != tmpCCKindex) { |
8fc8598e6 Staging: Added Re... |
746 747 748 |
priv->CCK_index = tmpCCKindex; CCKSwingNeedUpdate = 1; } |
04d695d77 staging: rtl8192u... |
749 |
if (CCKSwingNeedUpdate) { |
e1da1d573 staging: rtl8192u... |
750 751 |
/*DbgPrint("Update CCK Swing, CCK_index = %d ", pHalData->CCK_index);*/ |
8fc8598e6 Staging: Added Re... |
752 753 |
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } |
04d695d77 staging: rtl8192u... |
754 |
if (priv->OFDM_index != tmpOFDMindex) { |
8fc8598e6 Staging: Added Re... |
755 756 757 758 759 760 761 762 |
priv->OFDM_index = tmpOFDMindex; rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]); RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x ", priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]); } priv->txpower_count = 0; } |
bf316434a staging: rtl8192u... |
763 |
void dm_txpower_trackingcallback(struct work_struct *work) |
8fc8598e6 Staging: Added Re... |
764 |
{ |
a5959f3f1 staging: rtl8192u... |
765 |
struct delayed_work *dwork = to_delayed_work(work); |
04d695d77 staging: rtl8192u... |
766 767 |
struct r8192_priv *priv = container_of(dwork, struct r8192_priv, txpower_tracking_wq); struct net_device *dev = priv->ieee80211->dev; |
8fc8598e6 Staging: Added Re... |
768 |
|
c40753b5c staging: rtl8192u... |
769 |
if (priv->bDcut) |
8fc8598e6 Staging: Added Re... |
770 771 772 |
dm_TXPowerTrackingCallback_TSSI(dev); else dm_TXPowerTrackingCallback_ThermalMeter(dev); |
8fc8598e6 Staging: Added Re... |
773 |
} |
8fc8598e6 Staging: Added Re... |
774 775 |
static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev) { |
8fc8598e6 Staging: Added Re... |
776 |
struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
777 |
/* Initial the Tx BB index and mapping value */ |
35997ff0c staging/rtl8192u:... |
778 |
priv->txbbgain_table[0].txbb_iq_amplifygain = 12; |
04d695d77 staging: rtl8192u... |
779 |
priv->txbbgain_table[0].txbbgain_value = 0x7f8001fe; |
35997ff0c staging/rtl8192u:... |
780 |
priv->txbbgain_table[1].txbb_iq_amplifygain = 11; |
04d695d77 staging: rtl8192u... |
781 |
priv->txbbgain_table[1].txbbgain_value = 0x788001e2; |
35997ff0c staging/rtl8192u:... |
782 |
priv->txbbgain_table[2].txbb_iq_amplifygain = 10; |
04d695d77 staging: rtl8192u... |
783 |
priv->txbbgain_table[2].txbbgain_value = 0x71c001c7; |
35997ff0c staging/rtl8192u:... |
784 |
priv->txbbgain_table[3].txbb_iq_amplifygain = 9; |
04d695d77 staging: rtl8192u... |
785 |
priv->txbbgain_table[3].txbbgain_value = 0x6b8001ae; |
35997ff0c staging/rtl8192u:... |
786 |
priv->txbbgain_table[4].txbb_iq_amplifygain = 8; |
04d695d77 staging: rtl8192u... |
787 |
priv->txbbgain_table[4].txbbgain_value = 0x65400195; |
35997ff0c staging/rtl8192u:... |
788 |
priv->txbbgain_table[5].txbb_iq_amplifygain = 7; |
04d695d77 staging: rtl8192u... |
789 |
priv->txbbgain_table[5].txbbgain_value = 0x5fc0017f; |
35997ff0c staging/rtl8192u:... |
790 |
priv->txbbgain_table[6].txbb_iq_amplifygain = 6; |
04d695d77 staging: rtl8192u... |
791 |
priv->txbbgain_table[6].txbbgain_value = 0x5a400169; |
35997ff0c staging/rtl8192u:... |
792 |
priv->txbbgain_table[7].txbb_iq_amplifygain = 5; |
04d695d77 staging: rtl8192u... |
793 |
priv->txbbgain_table[7].txbbgain_value = 0x55400155; |
35997ff0c staging/rtl8192u:... |
794 |
priv->txbbgain_table[8].txbb_iq_amplifygain = 4; |
04d695d77 staging: rtl8192u... |
795 |
priv->txbbgain_table[8].txbbgain_value = 0x50800142; |
35997ff0c staging/rtl8192u:... |
796 |
priv->txbbgain_table[9].txbb_iq_amplifygain = 3; |
04d695d77 staging: rtl8192u... |
797 |
priv->txbbgain_table[9].txbbgain_value = 0x4c000130; |
35997ff0c staging/rtl8192u:... |
798 |
priv->txbbgain_table[10].txbb_iq_amplifygain = 2; |
04d695d77 staging: rtl8192u... |
799 |
priv->txbbgain_table[10].txbbgain_value = 0x47c0011f; |
35997ff0c staging/rtl8192u:... |
800 |
priv->txbbgain_table[11].txbb_iq_amplifygain = 1; |
04d695d77 staging: rtl8192u... |
801 |
priv->txbbgain_table[11].txbbgain_value = 0x43c0010f; |
35997ff0c staging/rtl8192u:... |
802 |
priv->txbbgain_table[12].txbb_iq_amplifygain = 0; |
04d695d77 staging: rtl8192u... |
803 |
priv->txbbgain_table[12].txbbgain_value = 0x40000100; |
35997ff0c staging/rtl8192u:... |
804 |
priv->txbbgain_table[13].txbb_iq_amplifygain = -1; |
04d695d77 staging: rtl8192u... |
805 |
priv->txbbgain_table[13].txbbgain_value = 0x3c8000f2; |
35997ff0c staging/rtl8192u:... |
806 |
priv->txbbgain_table[14].txbb_iq_amplifygain = -2; |
04d695d77 staging: rtl8192u... |
807 |
priv->txbbgain_table[14].txbbgain_value = 0x390000e4; |
35997ff0c staging/rtl8192u:... |
808 |
priv->txbbgain_table[15].txbb_iq_amplifygain = -3; |
04d695d77 staging: rtl8192u... |
809 |
priv->txbbgain_table[15].txbbgain_value = 0x35c000d7; |
35997ff0c staging/rtl8192u:... |
810 |
priv->txbbgain_table[16].txbb_iq_amplifygain = -4; |
04d695d77 staging: rtl8192u... |
811 |
priv->txbbgain_table[16].txbbgain_value = 0x32c000cb; |
35997ff0c staging/rtl8192u:... |
812 |
priv->txbbgain_table[17].txbb_iq_amplifygain = -5; |
04d695d77 staging: rtl8192u... |
813 |
priv->txbbgain_table[17].txbbgain_value = 0x300000c0; |
35997ff0c staging/rtl8192u:... |
814 |
priv->txbbgain_table[18].txbb_iq_amplifygain = -6; |
04d695d77 staging: rtl8192u... |
815 |
priv->txbbgain_table[18].txbbgain_value = 0x2d4000b5; |
35997ff0c staging/rtl8192u:... |
816 |
priv->txbbgain_table[19].txbb_iq_amplifygain = -7; |
04d695d77 staging: rtl8192u... |
817 |
priv->txbbgain_table[19].txbbgain_value = 0x2ac000ab; |
35997ff0c staging/rtl8192u:... |
818 |
priv->txbbgain_table[20].txbb_iq_amplifygain = -8; |
04d695d77 staging: rtl8192u... |
819 |
priv->txbbgain_table[20].txbbgain_value = 0x288000a2; |
35997ff0c staging/rtl8192u:... |
820 |
priv->txbbgain_table[21].txbb_iq_amplifygain = -9; |
04d695d77 staging: rtl8192u... |
821 |
priv->txbbgain_table[21].txbbgain_value = 0x26000098; |
35997ff0c staging/rtl8192u:... |
822 |
priv->txbbgain_table[22].txbb_iq_amplifygain = -10; |
04d695d77 staging: rtl8192u... |
823 |
priv->txbbgain_table[22].txbbgain_value = 0x24000090; |
35997ff0c staging/rtl8192u:... |
824 |
priv->txbbgain_table[23].txbb_iq_amplifygain = -11; |
04d695d77 staging: rtl8192u... |
825 |
priv->txbbgain_table[23].txbbgain_value = 0x22000088; |
35997ff0c staging/rtl8192u:... |
826 |
priv->txbbgain_table[24].txbb_iq_amplifygain = -12; |
04d695d77 staging: rtl8192u... |
827 |
priv->txbbgain_table[24].txbbgain_value = 0x20000080; |
35997ff0c staging/rtl8192u:... |
828 |
priv->txbbgain_table[25].txbb_iq_amplifygain = -13; |
04d695d77 staging: rtl8192u... |
829 |
priv->txbbgain_table[25].txbbgain_value = 0x1a00006c; |
35997ff0c staging/rtl8192u:... |
830 |
priv->txbbgain_table[26].txbb_iq_amplifygain = -14; |
04d695d77 staging: rtl8192u... |
831 |
priv->txbbgain_table[26].txbbgain_value = 0x1c800072; |
35997ff0c staging/rtl8192u:... |
832 |
priv->txbbgain_table[27].txbb_iq_amplifygain = -15; |
04d695d77 staging: rtl8192u... |
833 |
priv->txbbgain_table[27].txbbgain_value = 0x18000060; |
35997ff0c staging/rtl8192u:... |
834 |
priv->txbbgain_table[28].txbb_iq_amplifygain = -16; |
04d695d77 staging: rtl8192u... |
835 |
priv->txbbgain_table[28].txbbgain_value = 0x19800066; |
35997ff0c staging/rtl8192u:... |
836 |
priv->txbbgain_table[29].txbb_iq_amplifygain = -17; |
04d695d77 staging: rtl8192u... |
837 |
priv->txbbgain_table[29].txbbgain_value = 0x15800056; |
35997ff0c staging/rtl8192u:... |
838 |
priv->txbbgain_table[30].txbb_iq_amplifygain = -18; |
04d695d77 staging: rtl8192u... |
839 |
priv->txbbgain_table[30].txbbgain_value = 0x26c0005b; |
35997ff0c staging/rtl8192u:... |
840 |
priv->txbbgain_table[31].txbb_iq_amplifygain = -19; |
04d695d77 staging: rtl8192u... |
841 |
priv->txbbgain_table[31].txbbgain_value = 0x14400051; |
35997ff0c staging/rtl8192u:... |
842 |
priv->txbbgain_table[32].txbb_iq_amplifygain = -20; |
04d695d77 staging: rtl8192u... |
843 |
priv->txbbgain_table[32].txbbgain_value = 0x24400051; |
35997ff0c staging/rtl8192u:... |
844 |
priv->txbbgain_table[33].txbb_iq_amplifygain = -21; |
04d695d77 staging: rtl8192u... |
845 |
priv->txbbgain_table[33].txbbgain_value = 0x1300004c; |
35997ff0c staging/rtl8192u:... |
846 |
priv->txbbgain_table[34].txbb_iq_amplifygain = -22; |
04d695d77 staging: rtl8192u... |
847 |
priv->txbbgain_table[34].txbbgain_value = 0x12000048; |
35997ff0c staging/rtl8192u:... |
848 |
priv->txbbgain_table[35].txbb_iq_amplifygain = -23; |
04d695d77 staging: rtl8192u... |
849 |
priv->txbbgain_table[35].txbbgain_value = 0x11000044; |
35997ff0c staging/rtl8192u:... |
850 |
priv->txbbgain_table[36].txbb_iq_amplifygain = -24; |
04d695d77 staging: rtl8192u... |
851 |
priv->txbbgain_table[36].txbbgain_value = 0x10000040; |
8fc8598e6 Staging: Added Re... |
852 |
|
e1da1d573 staging: rtl8192u... |
853 854 855 856 |
/* * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29 * This Table is for CH1~CH13 */ |
8fc8598e6 Staging: Added Re... |
857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 |
priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36; priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35; priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e; priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25; priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c; priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12; priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09; priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04; priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33; priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32; priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b; priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23; priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a; priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11; priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08; priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04; priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30; priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f; priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29; priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21; priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19; priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10; priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08; priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03; priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d; priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d; priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27; priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f; priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18; priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f; priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08; priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03; priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b; priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a; priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25; priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e; priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16; priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e; priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07; priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03; priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28; priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28; priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22; priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c; priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15; priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d; priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07; priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03; priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26; priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25; priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21; priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b; priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14; priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d; priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06; priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03; priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24; priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23; priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f; priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19; priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13; priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c; priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06; priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03; priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22; priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21; priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d; priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18; priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11; priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b; priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06; priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20; priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20; priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b; priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16; priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11; priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08; priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05; priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f; priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e; priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a; priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15; priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10; priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a; priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05; priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d; priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c; priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18; priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14; priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f; priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a; priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05; priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b; priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a; priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17; priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13; priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e; priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09; priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04; priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a; priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19; priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16; priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12; priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d; priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09; priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04; priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18; priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17; priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15; priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11; priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c; priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08; priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04; priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17; priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16; priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13; priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10; priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c; priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08; priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04; priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16; priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15; priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12; priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f; priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b; priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07; priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04; priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01; priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14; priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14; priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11; priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e; priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b; priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07; priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03; priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02; priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13; priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13; priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10; priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d; priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a; priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06; priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03; priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01; priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12; priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12; priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f; priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c; priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09; priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06; priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03; priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01; priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11; priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11; priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f; priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c; priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09; priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06; priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03; priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01; priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10; priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10; priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e; priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b; priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08; priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05; priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03; priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01; priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f; priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f; priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d; priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b; priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08; priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05; priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03; priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01; |
e1da1d573 staging: rtl8192u... |
1063 1064 1065 1066 |
/* * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29 * This Table is for CH14 */ |
8fc8598e6 Staging: Added Re... |
1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 |
priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36; priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35; priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e; priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b; priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33; priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32; priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b; priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19; priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30; priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f; priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29; priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18; priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d; priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d; priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27; priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17; priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b; priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a; priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25; priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15; priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28; priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28; priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22; priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14; priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26; priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25; priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21; priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13; priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24; priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23; priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f; priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12; priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22; priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21; priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d; priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11; priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20; priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20; priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b; priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10; priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f; priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e; priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a; priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f; priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d; priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c; priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18; priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e; priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b; priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a; priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17; priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e; priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a; priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19; priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16; priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d; priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18; priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17; priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15; priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c; priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17; priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16; priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13; priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b; priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16; priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15; priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12; priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b; priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14; priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14; priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11; priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a; priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13; priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13; priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10; priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a; priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12; priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12; priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f; priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09; priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11; priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11; priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f; priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09; priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10; priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10; priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e; priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08; priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00; priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f; priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f; priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d; priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08; priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00; priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00; priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00; priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00; |
4b2faf802 Staging: rtl8192u... |
1273 |
priv->btxpower_tracking = true; |
8fc8598e6 Staging: Added Re... |
1274 |
priv->txpower_count = 0; |
4b2faf802 Staging: rtl8192u... |
1275 |
priv->btxpower_trackingInit = false; |
8fc8598e6 Staging: Added Re... |
1276 1277 1278 1279 1280 1281 |
} static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
1282 1283 1284 1285 1286 |
/* * Tx Power tracking by Thermal Meter requires Firmware R/W 3-wire. This mechanism * can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w * 3-wire by driver causes RF to go into a wrong state. */ |
04d695d77 staging: rtl8192u... |
1287 |
if (priv->ieee80211->FwRWRF) |
4b2faf802 Staging: rtl8192u... |
1288 |
priv->btxpower_tracking = true; |
8fc8598e6 Staging: Added Re... |
1289 |
else |
4b2faf802 Staging: rtl8192u... |
1290 |
priv->btxpower_tracking = false; |
8fc8598e6 Staging: Added Re... |
1291 |
priv->txpower_count = 0; |
4b2faf802 Staging: rtl8192u... |
1292 |
priv->btxpower_trackingInit = false; |
8fc8598e6 Staging: Added Re... |
1293 |
} |
8fc8598e6 Staging: Added Re... |
1294 1295 1296 |
void dm_initialize_txpower_tracking(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d77 staging: rtl8192u... |
1297 |
|
c40753b5c staging: rtl8192u... |
1298 |
if (priv->bDcut) |
8fc8598e6 Staging: Added Re... |
1299 1300 1301 |
dm_InitializeTXPowerTracking_TSSI(dev); else dm_InitializeTXPowerTracking_ThermalMeter(dev); |
e1da1d573 staging: rtl8192u... |
1302 |
} /* dm_InitializeTXPowerTracking */ |
8fc8598e6 Staging: Added Re... |
1303 |
|
8fc8598e6 Staging: Added Re... |
1304 1305 1306 |
static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
de13a3dad staging/rtl8192u:... |
1307 |
static u32 tx_power_track_counter; |
8fc8598e6 Staging: Added Re... |
1308 |
|
04d695d77 staging: rtl8192u... |
1309 |
if (!priv->btxpower_tracking) |
8fc8598e6 Staging: Added Re... |
1310 |
return; |
16da78083 staging: rtl8192u... |
1311 1312 1313 |
if ((tx_power_track_counter % 30 == 0) && (tx_power_track_counter != 0)) queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0); tx_power_track_counter++; |
8fc8598e6 Staging: Added Re... |
1314 |
} |
8fc8598e6 Staging: Added Re... |
1315 1316 1317 |
static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
de13a3dad staging/rtl8192u:... |
1318 |
static u8 TM_Trigger; |
04d695d77 staging: rtl8192u... |
1319 1320 1321 |
/*DbgPrint("dm_CheckTXPowerTracking() ");*/ if (!priv->btxpower_tracking) |
8fc8598e6 Staging: Added Re... |
1322 |
return; |
16da78083 staging: rtl8192u... |
1323 1324 1325 |
if (priv->txpower_count <= 2) { priv->txpower_count++; return; |
8fc8598e6 Staging: Added Re... |
1326 |
} |
04d695d77 staging: rtl8192u... |
1327 |
if (!TM_Trigger) { |
e1da1d573 staging: rtl8192u... |
1328 1329 1330 1331 1332 1333 |
/* * Attention!! You have to write all 12bits of data to RF, or it may cause RF to crash * actually write reg0x02 bit1=0, then bit1=1. * DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f "); */ |
8fc8598e6 Staging: Added Re... |
1334 1335 1336 1337 1338 1339 |
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); TM_Trigger = 1; return; |
8fc8598e6 Staging: Added Re... |
1340 |
} |
16da78083 staging: rtl8192u... |
1341 1342 1343 1344 |
/*DbgPrint("Schedule TxPowerTrackingWorkItem ");*/ queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0); TM_Trigger = 0; |
8fc8598e6 Staging: Added Re... |
1345 |
} |
8fc8598e6 Staging: Added Re... |
1346 1347 1348 |
static void dm_check_txpower_tracking(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
1349 |
/*static u32 tx_power_track_counter = 0;*/ |
8fc8598e6 Staging: Added Re... |
1350 |
|
04d695d77 staging: rtl8192u... |
1351 |
#ifdef RTL8190P |
8fc8598e6 Staging: Added Re... |
1352 1353 |
dm_CheckTXPowerTracking_TSSI(dev); #else |
c40753b5c staging: rtl8192u... |
1354 |
if (priv->bDcut) |
8fc8598e6 Staging: Added Re... |
1355 1356 1357 1358 |
dm_CheckTXPowerTracking_TSSI(dev); else dm_CheckTXPowerTracking_ThermalMeter(dev); #endif |
e1da1d573 staging: rtl8192u... |
1359 |
} /* dm_CheckTXPowerTracking */ |
8fc8598e6 Staging: Added Re... |
1360 |
|
8fc8598e6 Staging: Added Re... |
1361 1362 1363 1364 |
static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14) { u32 TempVal; struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d77 staging: rtl8192u... |
1365 |
|
e1da1d573 staging: rtl8192u... |
1366 |
/* Write 0xa22 0xa23 */ |
8fc8598e6 Staging: Added Re... |
1367 |
TempVal = 0; |
04d695d77 staging: rtl8192u... |
1368 |
if (!bInCH14) { |
e1da1d573 staging: rtl8192u... |
1369 |
/* Write 0xa22 0xa23 */ |
35997ff0c staging/rtl8192u:... |
1370 |
TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] + |
04d695d77 staging: rtl8192u... |
1371 |
(priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8); |
8fc8598e6 Staging: Added Re... |
1372 |
|
0b4ef0a64 drivers: staging:... |
1373 |
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); |
e1da1d573 staging: rtl8192u... |
1374 |
/* Write 0xa24 ~ 0xa27 */ |
35997ff0c staging/rtl8192u:... |
1375 |
TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] + |
8fc8598e6 Staging: Added Re... |
1376 |
(priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) + |
0009631bc rtl8192u: remove ... |
1377 |
(priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16)+ |
8fc8598e6 Staging: Added Re... |
1378 |
(priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24); |
0b4ef0a64 drivers: staging:... |
1379 |
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); |
e1da1d573 staging: rtl8192u... |
1380 |
/* Write 0xa28 0xa29 */ |
35997ff0c staging/rtl8192u:... |
1381 |
TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] + |
04d695d77 staging: rtl8192u... |
1382 |
(priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8); |
8fc8598e6 Staging: Added Re... |
1383 |
|
0b4ef0a64 drivers: staging:... |
1384 |
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); |
04d695d77 staging: rtl8192u... |
1385 |
} else { |
35997ff0c staging/rtl8192u:... |
1386 |
TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] + |
04d695d77 staging: rtl8192u... |
1387 |
(priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8); |
8fc8598e6 Staging: Added Re... |
1388 |
|
0b4ef0a64 drivers: staging:... |
1389 |
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); |
e1da1d573 staging: rtl8192u... |
1390 |
/* Write 0xa24 ~ 0xa27 */ |
35997ff0c staging/rtl8192u:... |
1391 |
TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] + |
8fc8598e6 Staging: Added Re... |
1392 |
(priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) + |
0009631bc rtl8192u: remove ... |
1393 |
(priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16)+ |
8fc8598e6 Staging: Added Re... |
1394 |
(priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24); |
0b4ef0a64 drivers: staging:... |
1395 |
rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); |
e1da1d573 staging: rtl8192u... |
1396 |
/* Write 0xa28 0xa29 */ |
35997ff0c staging/rtl8192u:... |
1397 |
TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] + |
04d695d77 staging: rtl8192u... |
1398 |
(priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8); |
8fc8598e6 Staging: Added Re... |
1399 |
|
0b4ef0a64 drivers: staging:... |
1400 |
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); |
8fc8598e6 Staging: Added Re... |
1401 |
} |
8fc8598e6 Staging: Added Re... |
1402 |
} |
04d695d77 staging: rtl8192u... |
1403 |
static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14) |
8fc8598e6 Staging: Added Re... |
1404 1405 1406 1407 1408 |
{ u32 TempVal; struct r8192_priv *priv = ieee80211_priv(dev); TempVal = 0; |
04d695d77 staging: rtl8192u... |
1409 |
if (!bInCH14) { |
e1da1d573 staging: rtl8192u... |
1410 |
/* Write 0xa22 0xa23 */ |
35997ff0c staging/rtl8192u:... |
1411 |
TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] + |
04d695d77 staging: rtl8192u... |
1412 |
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8); |
8fc8598e6 Staging: Added Re... |
1413 1414 1415 1416 |
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x ", rCCK0_TxFilter1, TempVal); |
e1da1d573 staging: rtl8192u... |
1417 |
/* Write 0xa24 ~ 0xa27 */ |
35997ff0c staging/rtl8192u:... |
1418 |
TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] + |
8fc8598e6 Staging: Added Re... |
1419 |
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) + |
0009631bc rtl8192u: remove ... |
1420 |
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16)+ |
8fc8598e6 Staging: Added Re... |
1421 1422 1423 1424 1425 |
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24); rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x ", rCCK0_TxFilter2, TempVal); |
e1da1d573 staging: rtl8192u... |
1426 |
/* Write 0xa28 0xa29 */ |
35997ff0c staging/rtl8192u:... |
1427 |
TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] + |
04d695d77 staging: rtl8192u... |
1428 |
(CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8); |
8fc8598e6 Staging: Added Re... |
1429 1430 1431 1432 1433 |
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x ", rCCK0_DebugPort, TempVal); |
04d695d77 staging: rtl8192u... |
1434 |
} else { |
e1da1d573 staging: rtl8192u... |
1435 1436 |
/*priv->CCKTxPowerAdjustCntNotCh14++; cosa add for debug.*/ /* Write 0xa22 0xa23 */ |
35997ff0c staging/rtl8192u:... |
1437 |
TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] + |
04d695d77 staging: rtl8192u... |
1438 |
(CCKSwingTable_Ch14[priv->CCK_index][1]<<8); |
8fc8598e6 Staging: Added Re... |
1439 1440 1441 1442 1443 |
rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x ", rCCK0_TxFilter1, TempVal); |
e1da1d573 staging: rtl8192u... |
1444 |
/* Write 0xa24 ~ 0xa27 */ |
35997ff0c staging/rtl8192u:... |
1445 |
TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] + |
8fc8598e6 Staging: Added Re... |
1446 |
(CCKSwingTable_Ch14[priv->CCK_index][3]<<8) + |
0009631bc rtl8192u: remove ... |
1447 |
(CCKSwingTable_Ch14[priv->CCK_index][4]<<16)+ |
8fc8598e6 Staging: Added Re... |
1448 1449 1450 1451 1452 |
(CCKSwingTable_Ch14[priv->CCK_index][5]<<24); rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x ", rCCK0_TxFilter2, TempVal); |
e1da1d573 staging: rtl8192u... |
1453 |
/* Write 0xa28 0xa29 */ |
35997ff0c staging/rtl8192u:... |
1454 |
TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] + |
04d695d77 staging: rtl8192u... |
1455 |
(CCKSwingTable_Ch14[priv->CCK_index][7]<<8); |
8fc8598e6 Staging: Added Re... |
1456 1457 |
rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); |
0b4ef0a64 drivers: staging:... |
1458 1459 |
RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x ", |
8fc8598e6 Staging: Added Re... |
1460 1461 1462 |
rCCK0_DebugPort, TempVal); } } |
bf316434a staging: rtl8192u... |
1463 |
void dm_cck_txpower_adjust(struct net_device *dev, bool binch14) |
e1da1d573 staging: rtl8192u... |
1464 |
{ /* dm_CCKTxPowerAdjust */ |
8fc8598e6 Staging: Added Re... |
1465 |
struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d77 staging: rtl8192u... |
1466 |
|
c40753b5c staging: rtl8192u... |
1467 |
if (priv->bDcut) |
8fc8598e6 Staging: Added Re... |
1468 1469 1470 |
dm_CCKTxPowerAdjust_TSSI(dev, binch14); else dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14); |
8fc8598e6 Staging: Added Re... |
1471 |
} |
04d695d77 staging: rtl8192u... |
1472 |
#ifndef RTL8192U |
8fc8598e6 Staging: Added Re... |
1473 1474 1475 1476 1477 1478 1479 1480 1481 |
static void dm_txpower_reset_recovery( struct net_device *dev ) { struct r8192_priv *priv = ieee80211_priv(dev); RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==> "); rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); |
04d695d77 staging: rtl8192u... |
1482 1483 1484 1485 1486 1487 1488 1489 |
RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x ", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x ", priv->rfa_txpowertrackingindex); RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld ", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain); RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB ", priv->cck_present_attentuation); |
0b4ef0a64 drivers: staging:... |
1490 |
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); |
8fc8598e6 Staging: Added Re... |
1491 1492 |
rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); |
04d695d77 staging: rtl8192u... |
1493 1494 1495 1496 1497 1498 |
RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x ", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x ", priv->rfc_txpowertrackingindex); RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld ", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain); |
8fc8598e6 Staging: Added Re... |
1499 |
|
e1da1d573 staging: rtl8192u... |
1500 |
} /* dm_TXPowerResetRecovery */ |
8fc8598e6 Staging: Added Re... |
1501 |
|
bf316434a staging: rtl8192u... |
1502 |
void dm_restore_dynamic_mechanism_state(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
1503 1504 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
35997ff0c staging/rtl8192u:... |
1505 |
u32 reg_ratr = priv->rate_adaptive.last_ratr; |
8fc8598e6 Staging: Added Re... |
1506 |
|
04d695d77 staging: rtl8192u... |
1507 |
if (!priv->up) { |
8fc8598e6 Staging: Added Re... |
1508 1509 1510 1511 |
RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload "); return; } |
e1da1d573 staging: rtl8192u... |
1512 |
/* Restore previous state for rate adaptive */ |
04d695d77 staging: rtl8192u... |
1513 |
if (priv->rate_adaptive.rate_adaptive_disabled) |
8fc8598e6 Staging: Added Re... |
1514 |
return; |
e1da1d573 staging: rtl8192u... |
1515 |
/* TODO: Only 11n mode is implemented currently, */ |
04d695d77 staging: rtl8192u... |
1516 1517 1518 |
if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G || priv->ieee80211->mode == WIRELESS_MODE_N_5G)) return; |
8fc8598e6 Staging: Added Re... |
1519 1520 1521 |
{ /* 2007/11/15 MH Copy from 8190PCI. */ u32 ratr_value; |
04d695d77 staging: rtl8192u... |
1522 |
|
8fc8598e6 Staging: Added Re... |
1523 |
ratr_value = reg_ratr; |
04d695d77 staging: rtl8192u... |
1524 |
if (priv->rf_type == RF_1T2R) { /* 1T2R, Spatial Stream 2 should be disabled */ |
33c2aa14a rtl8192u: fix whi... |
1525 |
ratr_value &= ~(RATE_ALL_OFDM_2SS); |
e1da1d573 staging: rtl8192u... |
1526 1527 |
/*DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x ", ((pu4Byte)(val))[0], ratr_value);*/ |
8fc8598e6 Staging: Added Re... |
1528 |
} |
e1da1d573 staging: rtl8192u... |
1529 1530 1531 |
/*DbgPrint("set HW_VAR_TATR_0 = 0x%x ", ratr_value);*/ /*cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);*/ |
8fc8598e6 Staging: Added Re... |
1532 1533 |
write_nic_dword(dev, RATR0, ratr_value); write_nic_byte(dev, UFWP, 1); |
8fc8598e6 Staging: Added Re... |
1534 |
} |
e1da1d573 staging: rtl8192u... |
1535 |
/* Restore TX Power Tracking Index */ |
2930d0b97 staging: rtl8192u... |
1536 |
if (priv->btxpower_trackingInit && priv->btxpower_tracking) |
8fc8598e6 Staging: Added Re... |
1537 |
dm_txpower_reset_recovery(dev); |
8fc8598e6 Staging: Added Re... |
1538 |
|
e1da1d573 staging: rtl8192u... |
1539 |
/* Restore BB Initial Gain */ |
8fc8598e6 Staging: Added Re... |
1540 |
dm_bb_initialgain_restore(dev); |
e1da1d573 staging: rtl8192u... |
1541 |
} /* DM_RestoreDynamicMechanismState */ |
8fc8598e6 Staging: Added Re... |
1542 1543 1544 1545 |
static void dm_bb_initialgain_restore(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
1546 |
u32 bit_mask = 0x7f; /* Bit0~ Bit6 */ |
8fc8598e6 Staging: Added Re... |
1547 |
|
04d695d77 staging: rtl8192u... |
1548 |
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) |
8fc8598e6 Staging: Added Re... |
1549 |
return; |
e1da1d573 staging: rtl8192u... |
1550 1551 1552 |
/* Disable Initial Gain */ /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ |
8fc8598e6 Staging: Added Re... |
1553 1554 1555 1556 1557 1558 |
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1); rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1); rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1); bit_mask = bMaskByte2; rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca); |
04d695d77 staging: rtl8192u... |
1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 |
RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x ", priv->initgain_backup.xaagccore1); RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x ", priv->initgain_backup.xbagccore1); RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x ", priv->initgain_backup.xcagccore1); RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x ", priv->initgain_backup.xdagccore1); RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x ", priv->initgain_backup.cca); |
e1da1d573 staging: rtl8192u... |
1569 1570 1571 |
/* Enable Initial Gain */ /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);*/ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ |
8fc8598e6 Staging: Added Re... |
1572 |
|
e1da1d573 staging: rtl8192u... |
1573 |
} /* dm_BBInitialGainRestore */ |
8fc8598e6 Staging: Added Re... |
1574 |
|
bf316434a staging: rtl8192u... |
1575 |
void dm_backup_dynamic_mechanism_state(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
1576 1577 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
1578 |
/* Fsync to avoid reset */ |
8fc8598e6 Staging: Added Re... |
1579 1580 |
priv->bswitch_fsync = false; priv->bfsync_processing = false; |
e1da1d573 staging: rtl8192u... |
1581 |
/* Backup BB InitialGain */ |
8fc8598e6 Staging: Added Re... |
1582 |
dm_bb_initialgain_backup(dev); |
e1da1d573 staging: rtl8192u... |
1583 |
} /* DM_BackupDynamicMechanismState */ |
8fc8598e6 Staging: Added Re... |
1584 |
|
8fc8598e6 Staging: Added Re... |
1585 1586 1587 |
static void dm_bb_initialgain_backup(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
1588 |
u32 bit_mask = bMaskByte0; /* Bit0~ Bit6 */ |
8fc8598e6 Staging: Added Re... |
1589 |
|
04d695d77 staging: rtl8192u... |
1590 |
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) |
8fc8598e6 Staging: Added Re... |
1591 |
return; |
e1da1d573 staging: rtl8192u... |
1592 1593 |
/*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ |
8fc8598e6 Staging: Added Re... |
1594 1595 1596 1597 1598 1599 |
priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask); priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask); priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask); bit_mask = bMaskByte2; priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask); |
04d695d77 staging: rtl8192u... |
1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 |
RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x ", priv->initgain_backup.xaagccore1); RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x ", priv->initgain_backup.xbagccore1); RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x ", priv->initgain_backup.xcagccore1); RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x ", priv->initgain_backup.xdagccore1); RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x ", priv->initgain_backup.cca); |
8fc8598e6 Staging: Added Re... |
1610 |
|
e1da1d573 staging: rtl8192u... |
1611 |
} /* dm_BBInitialGainBakcup */ |
8fc8598e6 Staging: Added Re... |
1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 |
#endif /*----------------------------------------------------------------------------- * Function: dm_change_dynamic_initgain_thresh() * * Overview: * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 05/29/2008 amy Create Version 0 porting from windows code. * *---------------------------------------------------------------------------*/ |
bf316434a staging: rtl8192u... |
1630 1631 1632 |
void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value) |
8fc8598e6 Staging: Added Re... |
1633 |
{ |
f59140964 Staging: rtl8192u... |
1634 1635 |
switch (dm_type) { case DIG_TYPE_THRESH_HIGH: |
8fc8598e6 Staging: Added Re... |
1636 |
dm_digtable.rssi_high_thresh = dm_value; |
f59140964 Staging: rtl8192u... |
1637 1638 1639 |
break; case DIG_TYPE_THRESH_LOW: |
8fc8598e6 Staging: Added Re... |
1640 |
dm_digtable.rssi_low_thresh = dm_value; |
f59140964 Staging: rtl8192u... |
1641 1642 1643 |
break; case DIG_TYPE_THRESH_HIGHPWR_HIGH: |
8fc8598e6 Staging: Added Re... |
1644 |
dm_digtable.rssi_high_power_highthresh = dm_value; |
f59140964 Staging: rtl8192u... |
1645 1646 1647 |
break; case DIG_TYPE_THRESH_HIGHPWR_LOW: |
c5c15efba Staging: rtl8192u... |
1648 |
dm_digtable.rssi_high_power_lowthresh = dm_value; |
f59140964 Staging: rtl8192u... |
1649 1650 1651 |
break; case DIG_TYPE_ENABLE: |
8fc8598e6 Staging: Added Re... |
1652 1653 |
dm_digtable.dig_state = DM_STA_DIG_MAX; dm_digtable.dig_enable_flag = true; |
f59140964 Staging: rtl8192u... |
1654 1655 1656 |
break; case DIG_TYPE_DISABLE: |
8fc8598e6 Staging: Added Re... |
1657 1658 |
dm_digtable.dig_state = DM_STA_DIG_MAX; dm_digtable.dig_enable_flag = false; |
f59140964 Staging: rtl8192u... |
1659 1660 1661 |
break; case DIG_TYPE_DBG_MODE: |
04d695d77 staging: rtl8192u... |
1662 |
if (dm_value >= DM_DBG_MAX) |
8fc8598e6 Staging: Added Re... |
1663 1664 |
dm_value = DM_DBG_OFF; dm_digtable.dbg_mode = (u8)dm_value; |
f59140964 Staging: rtl8192u... |
1665 1666 1667 |
break; case DIG_TYPE_RSSI: |
04d695d77 staging: rtl8192u... |
1668 |
if (dm_value > 100) |
8fc8598e6 Staging: Added Re... |
1669 1670 |
dm_value = 30; dm_digtable.rssi_val = (long)dm_value; |
f59140964 Staging: rtl8192u... |
1671 1672 1673 |
break; case DIG_TYPE_ALGORITHM: |
8fc8598e6 Staging: Added Re... |
1674 1675 |
if (dm_value >= DIG_ALGO_MAX) dm_value = DIG_ALGO_BY_FALSE_ALARM; |
04d695d77 staging: rtl8192u... |
1676 |
if (dm_digtable.dig_algorithm != (u8)dm_value) |
8fc8598e6 Staging: Added Re... |
1677 1678 |
dm_digtable.dig_algorithm_switch = 1; dm_digtable.dig_algorithm = (u8)dm_value; |
f59140964 Staging: rtl8192u... |
1679 1680 1681 |
break; case DIG_TYPE_BACKOFF: |
04d695d77 staging: rtl8192u... |
1682 |
if (dm_value > 30) |
8fc8598e6 Staging: Added Re... |
1683 1684 |
dm_value = 30; dm_digtable.backoff_val = (u8)dm_value; |
f59140964 Staging: rtl8192u... |
1685 1686 1687 |
break; case DIG_TYPE_RX_GAIN_MIN: |
04d695d77 staging: rtl8192u... |
1688 |
if (dm_value == 0) |
8fc8598e6 Staging: Added Re... |
1689 1690 |
dm_value = 0x1; dm_digtable.rx_gain_range_min = (u8)dm_value; |
f59140964 Staging: rtl8192u... |
1691 1692 1693 |
break; case DIG_TYPE_RX_GAIN_MAX: |
04d695d77 staging: rtl8192u... |
1694 |
if (dm_value > 0x50) |
8fc8598e6 Staging: Added Re... |
1695 1696 |
dm_value = 0x50; dm_digtable.rx_gain_range_max = (u8)dm_value; |
f59140964 Staging: rtl8192u... |
1697 1698 1699 1700 |
break; default: break; |
8fc8598e6 Staging: Added Re... |
1701 |
} |
f59140964 Staging: rtl8192u... |
1702 |
|
8fc8598e6 Staging: Added Re... |
1703 |
} /* DM_ChangeDynamicInitGainThresh */ |
8fc8598e6 Staging: Added Re... |
1704 |
|
8fc8598e6 Staging: Added Re... |
1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 |
/*----------------------------------------------------------------------------- * Function: dm_dig_init() * * Overview: Set DIG scheme init value. * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 05/15/2008 amy Create Version 0 porting from windows code. * *---------------------------------------------------------------------------*/ static void dm_dig_init(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); /* 2007/10/05 MH Disable DIG scheme now. Not tested. */ dm_digtable.dig_enable_flag = true; dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI; |
e1da1d573 staging: rtl8192u... |
1727 |
dm_digtable.dbg_mode = DM_DBG_OFF; /* off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig */ |
8fc8598e6 Staging: Added Re... |
1728 |
dm_digtable.dig_algorithm_switch = 0; |
589b3d06f staging: rtl8192u... |
1729 |
/* 2007/10/04 MH Define init gain threshold. */ |
8fc8598e6 Staging: Added Re... |
1730 1731 1732 |
dm_digtable.dig_state = DM_STA_DIG_MAX; dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; dm_digtable.initialgain_lowerbound_state = false; |
35997ff0c staging/rtl8192u:... |
1733 1734 |
dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW; dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH; |
8fc8598e6 Staging: Added Re... |
1735 1736 1737 |
dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW; dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH; |
e1da1d573 staging: rtl8192u... |
1738 |
dm_digtable.rssi_val = 50; /* for new dig debug rssi value */ |
8fc8598e6 Staging: Added Re... |
1739 1740 |
dm_digtable.backoff_val = DM_DIG_BACKOFF; dm_digtable.rx_gain_range_max = DM_DIG_MAX; |
04d695d77 staging: rtl8192u... |
1741 |
if (priv->CustomerID == RT_CID_819x_Netcore) |
8fc8598e6 Staging: Added Re... |
1742 1743 1744 1745 1746 |
dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore; else dm_digtable.rx_gain_range_min = DM_DIG_MIN; } /* dm_dig_init */ |
8fc8598e6 Staging: Added Re... |
1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 |
/*----------------------------------------------------------------------------- * Function: dm_ctrl_initgain_byrssi() * * Overview: Driver must monitor RSSI and notify firmware to change initial * gain according to different threshold. BB team provide the * suggested solution. * * Input: struct net_device *dev * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 05/27/2008 amy Create Version 0 porting from windows code. *---------------------------------------------------------------------------*/ static void dm_ctrl_initgain_byrssi(struct net_device *dev) { |
f9bd549aa staging: rtl8192u... |
1766 |
if (!dm_digtable.dig_enable_flag) |
8fc8598e6 Staging: Added Re... |
1767 |
return; |
04d695d77 staging: rtl8192u... |
1768 |
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
8fc8598e6 Staging: Added Re... |
1769 |
dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev); |
04d695d77 staging: rtl8192u... |
1770 |
else if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) |
8fc8598e6 Staging: Added Re... |
1771 |
dm_ctrl_initgain_byrssi_by_driverrssi(dev); |
e1da1d573 staging: rtl8192u... |
1772 |
/* ; */ |
8fc8598e6 Staging: Added Re... |
1773 1774 1775 |
else return; } |
8fc8598e6 Staging: Added Re... |
1776 1777 1778 1779 1780 |
static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); u8 i; |
de13a3dad staging/rtl8192u:... |
1781 |
static u8 fw_dig; |
8fc8598e6 Staging: Added Re... |
1782 |
|
f9bd549aa staging: rtl8192u... |
1783 |
if (!dm_digtable.dig_enable_flag) |
8fc8598e6 Staging: Added Re... |
1784 |
return; |
04d695d77 staging: rtl8192u... |
1785 1786 1787 |
/*DbgPrint("Dig by Sw Rssi ");*/ if (dm_digtable.dig_algorithm_switch) /* if switched algorithm, we have to disable FW Dig. */ |
8fc8598e6 Staging: Added Re... |
1788 |
fw_dig = 0; |
04d695d77 staging: rtl8192u... |
1789 1790 |
if (fw_dig <= 3) { /* execute several times to make sure the FW Dig is disabled */ |
e1da1d573 staging: rtl8192u... |
1791 |
/* FW DIG Off */ |
04d695d77 staging: rtl8192u... |
1792 |
for (i = 0; i < 3; i++) |
e1da1d573 staging: rtl8192u... |
1793 |
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ |
8fc8598e6 Staging: Added Re... |
1794 |
fw_dig++; |
e1da1d573 staging: rtl8192u... |
1795 |
dm_digtable.dig_state = DM_STA_DIG_OFF; /* fw dig off. */ |
8fc8598e6 Staging: Added Re... |
1796 |
} |
04d695d77 staging: rtl8192u... |
1797 |
if (priv->ieee80211->state == IEEE80211_LINKED) |
8fc8598e6 Staging: Added Re... |
1798 1799 1800 |
dm_digtable.cur_connect_state = DIG_CONNECT; else dm_digtable.cur_connect_state = DIG_DISCONNECT; |
04d695d77 staging: rtl8192u... |
1801 1802 |
/*DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d ", |
e1da1d573 staging: rtl8192u... |
1803 |
DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);*/ |
8fc8598e6 Staging: Added Re... |
1804 |
|
04d695d77 staging: rtl8192u... |
1805 |
if (dm_digtable.dbg_mode == DM_DBG_OFF) |
8fc8598e6 Staging: Added Re... |
1806 |
dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb; |
04d695d77 staging: rtl8192u... |
1807 1808 |
/*DbgPrint("DM_DigTable.Rssi_val = %d ", DM_DigTable.Rssi_val);*/ |
8fc8598e6 Staging: Added Re... |
1809 1810 1811 |
dm_initial_gain(dev); dm_pd_th(dev); dm_cs_ratio(dev); |
04d695d77 staging: rtl8192u... |
1812 |
if (dm_digtable.dig_algorithm_switch) |
8fc8598e6 Staging: Added Re... |
1813 1814 1815 1816 1817 1818 1819 1820 1821 |
dm_digtable.dig_algorithm_switch = 0; dm_digtable.pre_connect_state = dm_digtable.cur_connect_state; } /* dm_CtrlInitGainByRssi */ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm( struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
de13a3dad staging/rtl8192u:... |
1822 |
static u32 reset_cnt; |
8fc8598e6 Staging: Added Re... |
1823 |
u8 i; |
f9bd549aa staging: rtl8192u... |
1824 |
if (!dm_digtable.dig_enable_flag) |
8fc8598e6 Staging: Added Re... |
1825 |
return; |
04d695d77 staging: rtl8192u... |
1826 |
if (dm_digtable.dig_algorithm_switch) { |
8fc8598e6 Staging: Added Re... |
1827 |
dm_digtable.dig_state = DM_STA_DIG_MAX; |
e1da1d573 staging: rtl8192u... |
1828 |
/* Fw DIG On. */ |
04d695d77 staging: rtl8192u... |
1829 |
for (i = 0; i < 3; i++) |
e1da1d573 staging: rtl8192u... |
1830 |
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite.*/ |
8fc8598e6 Staging: Added Re... |
1831 1832 1833 1834 1835 |
dm_digtable.dig_algorithm_switch = 0; } if (priv->ieee80211->state != IEEE80211_LINKED) return; |
e1da1d573 staging: rtl8192u... |
1836 |
/* For smooth, we can not change DIG state. */ |
8fc8598e6 Staging: Added Re... |
1837 1838 |
if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) && (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh)) |
8fc8598e6 Staging: Added Re... |
1839 |
return; |
04d695d77 staging: rtl8192u... |
1840 |
|
e1da1d573 staging: rtl8192u... |
1841 1842 1843 |
/*DbgPrint("Dig by Fw False Alarm ");*/ /*if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)*/ |
8fc8598e6 Staging: Added Re... |
1844 1845 1846 1847 |
/*DbgPrint("DIG Check \r RSSI=%d LOW=%d HIGH=%d STATE=%d", pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh, DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/ |
589b3d06f staging: rtl8192u... |
1848 |
/* 1. When RSSI decrease, We have to judge if it is smaller than a threshold |
8ef3a7ed3 staging:rtl8192u ... |
1849 |
and then execute the step below. */ |
16da78083 staging: rtl8192u... |
1850 |
if (priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh) { |
8fc8598e6 Staging: Added Re... |
1851 1852 1853 |
/* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters will be reset to init value. We must prevent the condition. */ if (dm_digtable.dig_state == DM_STA_DIG_OFF && |
04d695d77 staging: rtl8192u... |
1854 |
(priv->reset_count == reset_cnt)) { |
8fc8598e6 Staging: Added Re... |
1855 |
return; |
8fc8598e6 Staging: Added Re... |
1856 |
} |
16da78083 staging: rtl8192u... |
1857 |
reset_cnt = priv->reset_count; |
8fc8598e6 Staging: Added Re... |
1858 |
|
e1da1d573 staging: rtl8192u... |
1859 |
/* If DIG is off, DIG high power state must reset. */ |
8fc8598e6 Staging: Added Re... |
1860 1861 |
dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; dm_digtable.dig_state = DM_STA_DIG_OFF; |
e1da1d573 staging: rtl8192u... |
1862 1863 |
/* 1.1 DIG Off. */ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ |
8fc8598e6 Staging: Added Re... |
1864 |
|
e1da1d573 staging: rtl8192u... |
1865 |
/* 1.2 Set initial gain. */ |
8fc8598e6 Staging: Added Re... |
1866 1867 1868 1869 |
write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17); write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17); write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17); |
e1da1d573 staging: rtl8192u... |
1870 |
/* 1.3 Lower PD_TH for OFDM. */ |
04d695d77 staging: rtl8192u... |
1871 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
e1da1d573 staging: rtl8192u... |
1872 1873 1874 1875 |
/* * 2008/01/11 MH 40MHZ 90/92 register are not the same. * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. */ |
91e39f09e staging: rtl8192u... |
1876 |
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); |
8fc8598e6 Staging: Added Re... |
1877 1878 |
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40); |
e1da1d573 staging: rtl8192u... |
1879 1880 1881 |
else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E) else PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40); |
8fc8598e6 Staging: Added Re... |
1882 |
*/ |
04d695d77 staging: rtl8192u... |
1883 |
} else |
8fc8598e6 Staging: Added Re... |
1884 |
write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); |
e1da1d573 staging: rtl8192u... |
1885 |
/* 1.4 Lower CS ratio for CCK. */ |
8fc8598e6 Staging: Added Re... |
1886 |
write_nic_byte(dev, 0xa0a, 0x08); |
e1da1d573 staging: rtl8192u... |
1887 1888 |
/* 1.5 Higher EDCCA. */ /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);*/ |
8fc8598e6 Staging: Added Re... |
1889 1890 1891 |
return; } |
589b3d06f staging: rtl8192u... |
1892 |
/* 2. When RSSI increase, We have to judge if it is larger than a threshold |
8ef3a7ed3 staging:rtl8192u ... |
1893 |
and then execute the step below. */ |
16da78083 staging: rtl8192u... |
1894 |
if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) { |
8fc8598e6 Staging: Added Re... |
1895 1896 1897 |
u8 reset_flag = 0; if (dm_digtable.dig_state == DM_STA_DIG_ON && |
04d695d77 staging: rtl8192u... |
1898 |
(priv->reset_count == reset_cnt)) { |
8fc8598e6 Staging: Added Re... |
1899 1900 |
dm_ctrl_initgain_byrssi_highpwr(dev); return; |
8fc8598e6 Staging: Added Re... |
1901 |
} |
16da78083 staging: rtl8192u... |
1902 1903 1904 1905 |
if (priv->reset_count != reset_cnt) reset_flag = 1; reset_cnt = priv->reset_count; |
8fc8598e6 Staging: Added Re... |
1906 1907 |
dm_digtable.dig_state = DM_STA_DIG_ON; |
e1da1d573 staging: rtl8192u... |
1908 1909 |
/*DbgPrint("DIG ON \r");*/ |
8fc8598e6 Staging: Added Re... |
1910 |
|
e1da1d573 staging: rtl8192u... |
1911 1912 1913 1914 |
/* * 2.1 Set initial gain. * 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment. */ |
04d695d77 staging: rtl8192u... |
1915 |
if (reset_flag == 1) { |
8fc8598e6 Staging: Added Re... |
1916 1917 1918 1919 |
write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c); write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c); write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c); |
04d695d77 staging: rtl8192u... |
1920 |
} else { |
8fc8598e6 Staging: Added Re... |
1921 1922 1923 1924 1925 |
write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20); write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20); write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20); } |
e1da1d573 staging: rtl8192u... |
1926 |
/* 2.2 Higher PD_TH for OFDM. */ |
04d695d77 staging: rtl8192u... |
1927 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
e1da1d573 staging: rtl8192u... |
1928 1929 1930 1931 |
/* * 2008/01/11 MH 40MHZ 90/92 register are not the same. * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. */ |
91e39f09e staging: rtl8192u... |
1932 |
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); |
8fc8598e6 Staging: Added Re... |
1933 1934 1935 |
/* else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); |
e1da1d573 staging: rtl8192u... |
1936 1937 1938 |
else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E) else PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42); |
8fc8598e6 Staging: Added Re... |
1939 |
*/ |
04d695d77 staging: rtl8192u... |
1940 |
} else |
8fc8598e6 Staging: Added Re... |
1941 |
write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); |
e1da1d573 staging: rtl8192u... |
1942 |
/* 2.3 Higher CS ratio for CCK. */ |
8fc8598e6 Staging: Added Re... |
1943 |
write_nic_byte(dev, 0xa0a, 0xcd); |
e1da1d573 staging: rtl8192u... |
1944 1945 1946 1947 1948 |
/* * 2.4 Lower EDCCA. * 2008/01/11 MH 90/92 series are the same. */ /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);*/ |
8fc8598e6 Staging: Added Re... |
1949 |
|
e1da1d573 staging: rtl8192u... |
1950 1951 |
/* 2.5 DIG On. */ rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ |
8fc8598e6 Staging: Added Re... |
1952 1953 1954 1955 1956 1957 |
} dm_ctrl_initgain_byrssi_highpwr(dev); } /* dm_CtrlInitGainByRssi */ |
8fc8598e6 Staging: Added Re... |
1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 |
/*----------------------------------------------------------------------------- * Function: dm_ctrl_initgain_byrssi_highpwr() * * Overview: * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 05/28/2008 amy Create Version 0 porting from windows code. * *---------------------------------------------------------------------------*/ static void dm_ctrl_initgain_byrssi_highpwr( |
999d594b7 STAGING: rtl8192u... |
1975 |
struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
1976 1977 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
de13a3dad staging/rtl8192u:... |
1978 |
static u32 reset_cnt_highpwr; |
8fc8598e6 Staging: Added Re... |
1979 |
|
e1da1d573 staging: rtl8192u... |
1980 |
/* For smooth, we can not change high power DIG state in the range. */ |
8fc8598e6 Staging: Added Re... |
1981 1982 |
if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) && (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh)) |
8fc8598e6 Staging: Added Re... |
1983 |
return; |
8fc8598e6 Staging: Added Re... |
1984 |
|
e1da1d573 staging: rtl8192u... |
1985 1986 1987 1988 1989 1990 |
/* * 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if * it is larger than a threshold and then execute the step below. * * 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue. */ |
04d695d77 staging: rtl8192u... |
1991 |
if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) { |
8fc8598e6 Staging: Added Re... |
1992 1993 1994 |
if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON && (priv->reset_count == reset_cnt_highpwr)) return; |
16da78083 staging: rtl8192u... |
1995 |
dm_digtable.dig_highpwr_state = DM_STA_DIG_ON; |
8fc8598e6 Staging: Added Re... |
1996 |
|
e1da1d573 staging: rtl8192u... |
1997 |
/* 3.1 Higher PD_TH for OFDM for high power state. */ |
04d695d77 staging: rtl8192u... |
1998 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
91e39f09e staging: rtl8192u... |
1999 |
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); |
8fc8598e6 Staging: Added Re... |
2000 2001 2002 2003 |
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); */ |
04d695d77 staging: rtl8192u... |
2004 |
} else |
8fc8598e6 Staging: Added Re... |
2005 |
write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); |
04d695d77 staging: rtl8192u... |
2006 2007 |
} else { if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF && |
8fc8598e6 Staging: Added Re... |
2008 2009 |
(priv->reset_count == reset_cnt_highpwr)) return; |
16da78083 staging: rtl8192u... |
2010 |
dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF; |
8fc8598e6 Staging: Added Re... |
2011 2012 |
if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh && |
04d695d77 staging: rtl8192u... |
2013 |
priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) { |
e1da1d573 staging: rtl8192u... |
2014 |
/* 3.2 Recover PD_TH for OFDM for normal power region. */ |
04d695d77 staging: rtl8192u... |
2015 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
91e39f09e staging: rtl8192u... |
2016 |
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); |
8fc8598e6 Staging: Added Re... |
2017 2018 2019 |
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); */ |
04d695d77 staging: rtl8192u... |
2020 |
} else |
8fc8598e6 Staging: Added Re... |
2021 2022 2023 2024 2025 2026 2027 |
write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); } } reset_cnt_highpwr = priv->reset_count; } /* dm_CtrlInitGainByRssiHighPwr */ |
8fc8598e6 Staging: Added Re... |
2028 |
static void dm_initial_gain( |
999d594b7 STAGING: rtl8192u... |
2029 |
struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2030 2031 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d77 staging: rtl8192u... |
2032 |
u8 initial_gain = 0; |
de13a3dad staging/rtl8192u:... |
2033 2034 |
static u8 initialized, force_write; static u32 reset_cnt; |
b3d42bf18 staging: rtl8192u... |
2035 |
u8 tmp; |
8fc8598e6 Staging: Added Re... |
2036 |
|
04d695d77 staging: rtl8192u... |
2037 |
if (dm_digtable.dig_algorithm_switch) { |
8fc8598e6 Staging: Added Re... |
2038 2039 2040 |
initialized = 0; reset_cnt = 0; } |
04d695d77 staging: rtl8192u... |
2041 2042 2043 |
if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) { if (dm_digtable.cur_connect_state == DIG_CONNECT) { if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max) |
8fc8598e6 Staging: Added Re... |
2044 |
dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max; |
04d695d77 staging: rtl8192u... |
2045 |
else if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min) |
8fc8598e6 Staging: Added Re... |
2046 2047 2048 |
dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min; else dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val; |
04d695d77 staging: rtl8192u... |
2049 2050 |
} else { /* current state is disconnected */ if (dm_digtable.cur_ig_value == 0) |
8fc8598e6 Staging: Added Re... |
2051 2052 2053 2054 |
dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; else dm_digtable.cur_ig_value = dm_digtable.pre_ig_value; } |
04d695d77 staging: rtl8192u... |
2055 |
} else { /* disconnected -> connected or connected -> disconnected */ |
8fc8598e6 Staging: Added Re... |
2056 2057 2058 |
dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; dm_digtable.pre_ig_value = 0; } |
e1da1d573 staging: rtl8192u... |
2059 2060 |
/*DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x ", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);*/ |
8fc8598e6 Staging: Added Re... |
2061 |
|
e1da1d573 staging: rtl8192u... |
2062 |
/* if silent reset happened, we should rewrite the values back */ |
04d695d77 staging: rtl8192u... |
2063 |
if (priv->reset_count != reset_cnt) { |
8fc8598e6 Staging: Added Re... |
2064 2065 2066 |
force_write = 1; reset_cnt = priv->reset_count; } |
b3d42bf18 staging: rtl8192u... |
2067 2068 |
read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp); if (dm_digtable.pre_ig_value != tmp) |
8fc8598e6 Staging: Added Re... |
2069 2070 2071 |
force_write = 1; { |
04d695d77 staging: rtl8192u... |
2072 2073 |
if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value) || !initialized || force_write) { |
8fc8598e6 Staging: Added Re... |
2074 |
initial_gain = (u8)dm_digtable.cur_ig_value; |
e1da1d573 staging: rtl8192u... |
2075 2076 2077 |
/*DbgPrint("Write initial gain = 0x%x ", initial_gain);*/ /* Set initial gain. */ |
8fc8598e6 Staging: Added Re... |
2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 |
write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); dm_digtable.pre_ig_value = dm_digtable.cur_ig_value; initialized = 1; force_write = 0; } } } static void dm_pd_th( |
999d594b7 STAGING: rtl8192u... |
2090 |
struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2091 2092 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
de13a3dad staging/rtl8192u:... |
2093 2094 |
static u8 initialized, force_write; static u32 reset_cnt; |
8fc8598e6 Staging: Added Re... |
2095 |
|
04d695d77 staging: rtl8192u... |
2096 |
if (dm_digtable.dig_algorithm_switch) { |
8fc8598e6 Staging: Added Re... |
2097 2098 2099 |
initialized = 0; reset_cnt = 0; } |
04d695d77 staging: rtl8192u... |
2100 2101 |
if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) { if (dm_digtable.cur_connect_state == DIG_CONNECT) { |
8fc8598e6 Staging: Added Re... |
2102 2103 |
if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh) dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER; |
16da78083 staging: rtl8192u... |
2104 |
else if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh) |
8fc8598e6 Staging: Added Re... |
2105 2106 2107 2108 2109 2110 |
dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) && (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh)) dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER; else dm_digtable.curpd_thstate = dm_digtable.prepd_thstate; |
04d695d77 staging: rtl8192u... |
2111 |
} else { |
8fc8598e6 Staging: Added Re... |
2112 2113 |
dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; } |
04d695d77 staging: rtl8192u... |
2114 |
} else { /* disconnected -> connected or connected -> disconnected */ |
8fc8598e6 Staging: Added Re... |
2115 2116 |
dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; } |
e1da1d573 staging: rtl8192u... |
2117 |
/* if silent reset happened, we should rewrite the values back */ |
04d695d77 staging: rtl8192u... |
2118 |
if (priv->reset_count != reset_cnt) { |
8fc8598e6 Staging: Added Re... |
2119 2120 2121 2122 2123 |
force_write = 1; reset_cnt = priv->reset_count; } { |
04d695d77 staging: rtl8192u... |
2124 2125 |
if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) || (initialized <= 3) || force_write) { |
e1da1d573 staging: rtl8192u... |
2126 2127 |
/*DbgPrint("Write PD_TH state = %d ", DM_DigTable.CurPD_THState);*/ |
04d695d77 staging: rtl8192u... |
2128 |
if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) { |
e1da1d573 staging: rtl8192u... |
2129 |
/* Lower PD_TH for OFDM. */ |
04d695d77 staging: rtl8192u... |
2130 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
e1da1d573 staging: rtl8192u... |
2131 2132 2133 2134 |
/* * 2008/01/11 MH 40MHZ 90/92 register are not the same. * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. */ |
91e39f09e staging: rtl8192u... |
2135 |
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); |
8fc8598e6 Staging: Added Re... |
2136 2137 2138 |
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); */ |
04d695d77 staging: rtl8192u... |
2139 |
} else |
8fc8598e6 Staging: Added Re... |
2140 |
write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); |
04d695d77 staging: rtl8192u... |
2141 |
} else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) { |
e1da1d573 staging: rtl8192u... |
2142 |
/* Higher PD_TH for OFDM. */ |
04d695d77 staging: rtl8192u... |
2143 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
e1da1d573 staging: rtl8192u... |
2144 2145 2146 2147 |
/* * 2008/01/11 MH 40MHZ 90/92 register are not the same. * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. */ |
91e39f09e staging: rtl8192u... |
2148 |
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); |
8fc8598e6 Staging: Added Re... |
2149 2150 2151 |
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); */ |
04d695d77 staging: rtl8192u... |
2152 |
} else |
8fc8598e6 Staging: Added Re... |
2153 |
write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); |
04d695d77 staging: rtl8192u... |
2154 |
} else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) { |
e1da1d573 staging: rtl8192u... |
2155 |
/* Higher PD_TH for OFDM for high power state. */ |
04d695d77 staging: rtl8192u... |
2156 |
if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { |
91e39f09e staging: rtl8192u... |
2157 |
write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); |
8fc8598e6 Staging: Added Re... |
2158 2159 2160 |
/*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); */ |
04d695d77 staging: rtl8192u... |
2161 |
} else |
8fc8598e6 Staging: Added Re... |
2162 2163 2164 |
write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); } dm_digtable.prepd_thstate = dm_digtable.curpd_thstate; |
04d695d77 staging: rtl8192u... |
2165 |
if (initialized <= 3) |
8fc8598e6 Staging: Added Re... |
2166 2167 2168 2169 2170 2171 2172 |
initialized++; force_write = 0; } } } static void dm_cs_ratio( |
999d594b7 STAGING: rtl8192u... |
2173 |
struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2174 2175 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
0b4ef0a64 drivers: staging:... |
2176 |
static u8 initialized, force_write; |
de13a3dad staging/rtl8192u:... |
2177 |
static u32 reset_cnt; |
8fc8598e6 Staging: Added Re... |
2178 |
|
04d695d77 staging: rtl8192u... |
2179 |
if (dm_digtable.dig_algorithm_switch) { |
8fc8598e6 Staging: Added Re... |
2180 2181 2182 |
initialized = 0; reset_cnt = 0; } |
04d695d77 staging: rtl8192u... |
2183 2184 |
if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) { if (dm_digtable.cur_connect_state == DIG_CONNECT) { |
16da78083 staging: rtl8192u... |
2185 |
if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh) |
8fc8598e6 Staging: Added Re... |
2186 |
dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; |
16da78083 staging: rtl8192u... |
2187 |
else if (dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) |
8fc8598e6 Staging: Added Re... |
2188 2189 2190 |
dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER; else dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state; |
04d695d77 staging: rtl8192u... |
2191 |
} else { |
8fc8598e6 Staging: Added Re... |
2192 2193 |
dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; } |
04d695d77 staging: rtl8192u... |
2194 |
} else /* disconnected -> connected or connected -> disconnected */ |
8fc8598e6 Staging: Added Re... |
2195 |
dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; |
8fc8598e6 Staging: Added Re... |
2196 |
|
e1da1d573 staging: rtl8192u... |
2197 |
/* if silent reset happened, we should rewrite the values back */ |
04d695d77 staging: rtl8192u... |
2198 |
if (priv->reset_count != reset_cnt) { |
8fc8598e6 Staging: Added Re... |
2199 2200 2201 |
force_write = 1; reset_cnt = priv->reset_count; } |
8fc8598e6 Staging: Added Re... |
2202 |
{ |
04d695d77 staging: rtl8192u... |
2203 2204 |
if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) || !initialized || force_write) { |
e1da1d573 staging: rtl8192u... |
2205 2206 |
/*DbgPrint("Write CS_ratio state = %d ", DM_DigTable.CurCS_ratioState);*/ |
04d695d77 staging: rtl8192u... |
2207 |
if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) { |
e1da1d573 staging: rtl8192u... |
2208 |
/* Lower CS ratio for CCK. */ |
8fc8598e6 Staging: Added Re... |
2209 |
write_nic_byte(dev, 0xa0a, 0x08); |
04d695d77 staging: rtl8192u... |
2210 |
} else if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) { |
e1da1d573 staging: rtl8192u... |
2211 |
/* Higher CS ratio for CCK. */ |
8fc8598e6 Staging: Added Re... |
2212 2213 2214 2215 2216 2217 2218 2219 |
write_nic_byte(dev, 0xa0a, 0xcd); } dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state; initialized = 1; force_write = 0; } } } |
c541fa875 staging:rtl8192u:... |
2220 |
void dm_init_edca_turbo(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2221 2222 2223 2224 2225 2226 |
{ struct r8192_priv *priv = ieee80211_priv(dev); priv->bcurrent_turbo_EDCA = false; priv->ieee80211->bis_any_nonbepkts = false; priv->bis_cur_rdlstate = false; |
e1da1d573 staging: rtl8192u... |
2227 |
} /* dm_init_edca_turbo */ |
8fc8598e6 Staging: Added Re... |
2228 |
|
8fc8598e6 Staging: Added Re... |
2229 |
static void dm_check_edca_turbo( |
999d594b7 STAGING: rtl8192u... |
2230 |
struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2231 2232 2233 |
{ struct r8192_priv *priv = ieee80211_priv(dev); PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; |
e1da1d573 staging: rtl8192u... |
2234 |
/*PSTA_QOS pStaQos = pMgntInfo->pStaQos;*/ |
8fc8598e6 Staging: Added Re... |
2235 |
|
e1da1d573 staging: rtl8192u... |
2236 |
/* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */ |
de13a3dad staging/rtl8192u:... |
2237 2238 |
static unsigned long lastTxOkCnt; static unsigned long lastRxOkCnt; |
8fc8598e6 Staging: Added Re... |
2239 2240 |
unsigned long curTxOkCnt = 0; unsigned long curRxOkCnt = 0; |
e1da1d573 staging: rtl8192u... |
2241 2242 2243 2244 |
/* * Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters * should follow the settings from QAP. By Bruce, 2007-12-07. */ |
04d695d77 staging: rtl8192u... |
2245 |
if (priv->ieee80211->state != IEEE80211_LINKED) |
8fc8598e6 Staging: Added Re... |
2246 |
goto dm_CheckEdcaTurbo_EXIT; |
e1da1d573 staging: rtl8192u... |
2247 |
/* We do not turn on EDCA turbo mode for some AP that has IOT issue */ |
04d695d77 staging: rtl8192u... |
2248 |
if (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) |
8fc8598e6 Staging: Added Re... |
2249 |
goto dm_CheckEdcaTurbo_EXIT; |
04d695d77 staging: rtl8192u... |
2250 2251 |
/*printk("========>%s():bis_any_nonbepkts is %d ", __func__, priv->bis_any_nonbepkts);*/ |
e1da1d573 staging: rtl8192u... |
2252 |
/* Check the status for current condition. */ |
04d695d77 staging: rtl8192u... |
2253 |
if (!priv->ieee80211->bis_any_nonbepkts) { |
8fc8598e6 Staging: Added Re... |
2254 2255 |
curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; |
e1da1d573 staging: rtl8192u... |
2256 |
/* For RT-AP, we needs to turn it on when Rx>Tx */ |
04d695d77 staging: rtl8192u... |
2257 |
if (curRxOkCnt > 4*curTxOkCnt) { |
e1da1d573 staging: rtl8192u... |
2258 2259 |
/*printk("%s():curRxOkCnt > 4*curTxOkCnt ");*/ |
04d695d77 staging: rtl8192u... |
2260 |
if (!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) { |
8fc8598e6 Staging: Added Re... |
2261 2262 2263 |
write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]); priv->bis_cur_rdlstate = true; } |
04d695d77 staging: rtl8192u... |
2264 |
} else { |
e1da1d573 staging: rtl8192u... |
2265 2266 |
/*printk("%s():curRxOkCnt < 4*curTxOkCnt ");*/ |
04d695d77 staging: rtl8192u... |
2267 |
if (priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) { |
8fc8598e6 Staging: Added Re... |
2268 2269 2270 2271 2272 2273 2274 |
write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]); priv->bis_cur_rdlstate = false; } } priv->bcurrent_turbo_EDCA = true; |
04d695d77 staging: rtl8192u... |
2275 |
} else { |
e1da1d573 staging: rtl8192u... |
2276 2277 2278 2279 |
/* * Turn Off EDCA turbo here. * Restore original EDCA according to the declaration of AP. */ |
04d695d77 staging: rtl8192u... |
2280 |
if (priv->bcurrent_turbo_EDCA) { |
8fc8598e6 Staging: Added Re... |
2281 2282 2283 2284 2285 |
{ u8 u1bAIFS; u32 u4bAcParam; struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; u8 mode = priv->ieee80211->mode; |
e1da1d573 staging: rtl8192u... |
2286 |
/* For Each time updating EDCA parameter, reset EDCA turbo mode status. */ |
8fc8598e6 Staging: Added Re... |
2287 |
dm_init_edca_turbo(dev); |
04d695d77 staging: rtl8192u... |
2288 |
u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime; |
2060f31ae Staging: rtl8192u... |
2289 |
u4bAcParam = (((u32)(qos_parameters->tx_op_limit[0])) << AC_PARAM_TXOP_LIMIT_OFFSET)| |
04d695d77 staging: rtl8192u... |
2290 2291 |
(((u32)(qos_parameters->cw_max[0])) << AC_PARAM_ECW_MAX_OFFSET)| (((u32)(qos_parameters->cw_min[0])) << AC_PARAM_ECW_MIN_OFFSET)| |
2060f31ae Staging: rtl8192u... |
2292 |
((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET); |
e1da1d573 staging: rtl8192u... |
2293 |
/*write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);*/ |
8fc8598e6 Staging: Added Re... |
2294 |
write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); |
e1da1d573 staging: rtl8192u... |
2295 2296 2297 2298 |
/* * Check ACM bit. * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. */ |
8fc8598e6 Staging: Added Re... |
2299 |
{ |
e1da1d573 staging: rtl8192u... |
2300 |
/* TODO: Modified this part and try to set acm control in only 1 IO processing!! */ |
8fc8598e6 Staging: Added Re... |
2301 2302 |
PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]); |
b3d42bf18 staging: rtl8192u... |
2303 |
u8 AcmCtrl; |
04d695d77 staging: rtl8192u... |
2304 |
|
b3d42bf18 staging: rtl8192u... |
2305 |
read_nic_byte(dev, AcmHwCtrl, &AcmCtrl); |
04d695d77 staging: rtl8192u... |
2306 2307 |
if (pAciAifsn->f.ACM) { /* ACM bit is 1. */ |
8fc8598e6 Staging: Added Re... |
2308 |
AcmCtrl |= AcmHw_BeqEn; |
04d695d77 staging: rtl8192u... |
2309 |
} else { /* ACM bit is 0. */ |
8fc8598e6 Staging: Added Re... |
2310 2311 |
AcmCtrl &= (~AcmHw_BeqEn); } |
04d695d77 staging: rtl8192u... |
2312 2313 |
RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X ", AcmCtrl); |
0009631bc rtl8192u: remove ... |
2314 |
write_nic_byte(dev, AcmHwCtrl, AcmCtrl); |
8fc8598e6 Staging: Added Re... |
2315 2316 2317 2318 2319 |
} } priv->bcurrent_turbo_EDCA = false; } } |
8fc8598e6 Staging: Added Re... |
2320 |
dm_CheckEdcaTurbo_EXIT: |
e1da1d573 staging: rtl8192u... |
2321 |
/* Set variables for next time. */ |
8fc8598e6 Staging: Added Re... |
2322 2323 2324 |
priv->ieee80211->bis_any_nonbepkts = false; lastTxOkCnt = priv->stats.txbytesunicast; lastRxOkCnt = priv->stats.rxbytesunicast; |
e1da1d573 staging: rtl8192u... |
2325 |
} /* dm_CheckEdcaTurbo */ |
8fc8598e6 Staging: Added Re... |
2326 |
|
999d594b7 STAGING: rtl8192u... |
2327 |
static void dm_init_ctstoself(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2328 |
{ |
efdcb35a8 Staging: rtl8192u... |
2329 |
struct r8192_priv *priv = ieee80211_priv(dev); |
8fc8598e6 Staging: Added Re... |
2330 |
|
4b2faf802 Staging: rtl8192u... |
2331 |
priv->ieee80211->bCTSToSelfEnable = true; |
8fc8598e6 Staging: Added Re... |
2332 2333 2334 2335 2336 |
priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal; } static void dm_ctstoself(struct net_device *dev) { |
efdcb35a8 Staging: rtl8192u... |
2337 |
struct r8192_priv *priv = ieee80211_priv(dev); |
8fc8598e6 Staging: Added Re... |
2338 |
PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; |
de13a3dad staging/rtl8192u:... |
2339 2340 |
static unsigned long lastTxOkCnt; static unsigned long lastRxOkCnt; |
8fc8598e6 Staging: Added Re... |
2341 2342 |
unsigned long curTxOkCnt = 0; unsigned long curRxOkCnt = 0; |
4b2faf802 Staging: rtl8192u... |
2343 |
if (priv->ieee80211->bCTSToSelfEnable != true) { |
8fc8598e6 Staging: Added Re... |
2344 2345 2346 2347 2348 2349 2350 2351 |
pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; return; } /* 1. Uplink 2. Linksys350/Linksys300N 3. <50 disable, >55 enable */ |
04d695d77 staging: rtl8192u... |
2352 |
if (pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) { |
8fc8598e6 Staging: Added Re... |
2353 2354 |
curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; |
04d695d77 staging: rtl8192u... |
2355 |
if (curRxOkCnt > 4*curTxOkCnt) { /* downlink, disable CTS to self */ |
8fc8598e6 Staging: Added Re... |
2356 |
pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; |
e1da1d573 staging: rtl8192u... |
2357 2358 |
/*DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink ");*/ |
04d695d77 staging: rtl8192u... |
2359 |
} else { /* uplink */ |
8fc8598e6 Staging: Added Re... |
2360 |
pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; |
8fc8598e6 Staging: Added Re... |
2361 2362 2363 2364 2365 2366 |
} lastTxOkCnt = priv->stats.txbytesunicast; lastRxOkCnt = priv->stats.rxbytesunicast; } } |
8fc8598e6 Staging: Added Re... |
2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 |
/*----------------------------------------------------------------------------- * Function: dm_check_pbc_gpio() * * Overview: Check if PBC button is pressed. * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark |
35997ff0c staging/rtl8192u:... |
2380 |
* 05/28/2008 amy Create Version 0 porting from windows code. |
8fc8598e6 Staging: Added Re... |
2381 2382 2383 2384 |
* *---------------------------------------------------------------------------*/ static void dm_check_pbc_gpio(struct net_device *dev) { |
8fc8598e6 Staging: Added Re... |
2385 2386 |
struct r8192_priv *priv = ieee80211_priv(dev); u8 tmp1byte; |
b3d42bf18 staging: rtl8192u... |
2387 |
read_nic_byte(dev, GPI, &tmp1byte); |
04d695d77 staging: rtl8192u... |
2388 |
if (tmp1byte == 0xff) |
8fc8598e6 Staging: Added Re... |
2389 |
return; |
56b3152e5 rtl8192u: BIT() m... |
2390 |
if (tmp1byte & BIT(6) || tmp1byte & BIT(0)) { |
e1da1d573 staging: rtl8192u... |
2391 2392 2393 2394 |
/* * Here we only set bPbcPressed to TRUE * After trigger PBC, the variable will be set to FALSE */ |
8fc8598e6 Staging: Added Re... |
2395 2396 2397 2398 |
RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed "); priv->bpbc_pressed = true; } |
8fc8598e6 Staging: Added Re... |
2399 2400 |
} |
8fc8598e6 Staging: Added Re... |
2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 |
/*----------------------------------------------------------------------------- * Function: DM_RFPathCheckWorkItemCallBack() * * Overview: Check if Current RF RX path is enabled * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 01/30/2008 MHC Create Version 0. * *---------------------------------------------------------------------------*/ |
bf316434a staging: rtl8192u... |
2417 |
void dm_rf_pathcheck_workitemcallback(struct work_struct *work) |
8fc8598e6 Staging: Added Re... |
2418 |
{ |
a5959f3f1 staging: rtl8192u... |
2419 |
struct delayed_work *dwork = to_delayed_work(work); |
04d695d77 staging: rtl8192u... |
2420 2421 2422 |
struct r8192_priv *priv = container_of(dwork, struct r8192_priv, rfpath_check_wq); struct net_device *dev = priv->ieee80211->dev; /*bool bactually_set = false;*/ |
8fc8598e6 Staging: Added Re... |
2423 |
u8 rfpath = 0, i; |
8fc8598e6 Staging: Added Re... |
2424 2425 |
/* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will always be the same. We only read 0xc04 now. */ |
b3d42bf18 staging: rtl8192u... |
2426 |
read_nic_byte(dev, 0xc04, &rfpath); |
8fc8598e6 Staging: Added Re... |
2427 |
|
e1da1d573 staging: rtl8192u... |
2428 |
/* Check Bit 0-3, it means if RF A-D is enabled. */ |
04d695d77 staging: rtl8192u... |
2429 |
for (i = 0; i < RF90_PATH_MAX; i++) { |
8fc8598e6 Staging: Added Re... |
2430 |
if (rfpath & (0x01<<i)) |
19cd22972 Staging: drivers:... |
2431 |
priv->brfpath_rxenable[i] = true; |
8fc8598e6 Staging: Added Re... |
2432 |
else |
19cd22972 Staging: drivers:... |
2433 |
priv->brfpath_rxenable[i] = false; |
8fc8598e6 Staging: Added Re... |
2434 |
} |
04d695d77 staging: rtl8192u... |
2435 |
if (!DM_RxPathSelTable.Enable) |
8fc8598e6 Staging: Added Re... |
2436 2437 2438 2439 |
return; dm_rxpath_sel_byrssi(dev); } /* DM_RFPathCheckWorkItemCallBack */ |
999d594b7 STAGING: rtl8192u... |
2440 |
static void dm_init_rxpath_selection(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2441 2442 2443 |
{ u8 i; struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d77 staging: rtl8192u... |
2444 |
|
e1da1d573 staging: rtl8192u... |
2445 |
DM_RxPathSelTable.Enable = 1; /* default enabled */ |
8fc8598e6 Staging: Added Re... |
2446 2447 |
DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low; DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH; |
04d695d77 staging: rtl8192u... |
2448 |
if (priv->CustomerID == RT_CID_819x_Netcore) |
8fc8598e6 Staging: Added Re... |
2449 2450 2451 2452 2453 |
DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; else DM_RxPathSelTable.cck_method = CCK_Rx_Version_1; DM_RxPathSelTable.DbgMode = DM_DBG_OFF; DM_RxPathSelTable.disabledRF = 0; |
04d695d77 staging: rtl8192u... |
2454 |
for (i = 0; i < 4; i++) { |
8fc8598e6 Staging: Added Re... |
2455 2456 2457 2458 2459 |
DM_RxPathSelTable.rf_rssi[i] = 50; DM_RxPathSelTable.cck_pwdb_sta[i] = -64; DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; } } |
999d594b7 STAGING: rtl8192u... |
2460 |
static void dm_rxpath_sel_byrssi(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2461 2462 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d77 staging: rtl8192u... |
2463 2464 2465 2466 2467 2468 |
u8 i, max_rssi_index = 0, min_rssi_index = 0, sec_rssi_index = 0, rf_num = 0; u8 tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0; u8 cck_default_Rx = 0x2; /* RF-C */ u8 cck_optional_Rx = 0x3; /* RF-D */ long tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0; u8 cck_rx_ver2_max_index = 0, cck_rx_ver2_min_index = 0, cck_rx_ver2_sec_index = 0; |
8fc8598e6 Staging: Added Re... |
2469 2470 |
u8 cur_rf_rssi; long cur_cck_pwdb; |
de13a3dad staging/rtl8192u:... |
2471 |
static u8 disabled_rf_cnt, cck_Rx_Path_initialized; |
8fc8598e6 Staging: Added Re... |
2472 |
u8 update_cck_rx_path; |
04d695d77 staging: rtl8192u... |
2473 |
if (priv->rf_type != RF_2T4R) |
8fc8598e6 Staging: Added Re... |
2474 |
return; |
04d695d77 staging: rtl8192u... |
2475 |
if (!cck_Rx_Path_initialized) { |
b3d42bf18 staging: rtl8192u... |
2476 2477 |
read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_Rx_path); DM_RxPathSelTable.cck_Rx_path &= 0xf; |
8fc8598e6 Staging: Added Re... |
2478 2479 |
cck_Rx_Path_initialized = 1; } |
b3d42bf18 staging: rtl8192u... |
2480 2481 |
read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabledRF); DM_RxPathSelTable.disabledRF = ~DM_RxPathSelTable.disabledRF & 0xf; |
8fc8598e6 Staging: Added Re... |
2482 |
|
04d695d77 staging: rtl8192u... |
2483 |
if (priv->ieee80211->mode == WIRELESS_MODE_B) { |
e1da1d573 staging: rtl8192u... |
2484 |
DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; /* pure B mode, fixed cck version2 */ |
04d695d77 staging: rtl8192u... |
2485 2486 |
/*DbgPrint("Pure B mode, use cck rx version2 ");*/ |
8fc8598e6 Staging: Added Re... |
2487 |
} |
e1da1d573 staging: rtl8192u... |
2488 |
/* decide max/sec/min rssi index */ |
04d695d77 staging: rtl8192u... |
2489 2490 |
for (i = 0; i < RF90_PATH_MAX; i++) { if (!DM_RxPathSelTable.DbgMode) |
8fc8598e6 Staging: Added Re... |
2491 |
DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i]; |
04d695d77 staging: rtl8192u... |
2492 |
if (priv->brfpath_rxenable[i]) { |
8fc8598e6 Staging: Added Re... |
2493 2494 |
rf_num++; cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i]; |
04d695d77 staging: rtl8192u... |
2495 |
if (rf_num == 1) { /* find first enabled rf path and the rssi values */ |
e1da1d573 staging: rtl8192u... |
2496 |
/* initialize, set all rssi index to the same one */ |
8fc8598e6 Staging: Added Re... |
2497 2498 |
max_rssi_index = min_rssi_index = sec_rssi_index = i; tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi; |
04d695d77 staging: rtl8192u... |
2499 2500 |
} else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */ if (cur_rf_rssi >= tmp_max_rssi) { |
8fc8598e6 Staging: Added Re... |
2501 2502 |
tmp_max_rssi = cur_rf_rssi; max_rssi_index = i; |
04d695d77 staging: rtl8192u... |
2503 |
} else { |
8fc8598e6 Staging: Added Re... |
2504 2505 2506 |
tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi; sec_rssi_index = min_rssi_index = i; } |
04d695d77 staging: rtl8192u... |
2507 2508 |
} else { if (cur_rf_rssi > tmp_max_rssi) { |
8fc8598e6 Staging: Added Re... |
2509 2510 2511 2512 |
tmp_sec_rssi = tmp_max_rssi; sec_rssi_index = max_rssi_index; tmp_max_rssi = cur_rf_rssi; max_rssi_index = i; |
04d695d77 staging: rtl8192u... |
2513 |
} else if (cur_rf_rssi == tmp_max_rssi) { /* let sec and min point to the different index */ |
8fc8598e6 Staging: Added Re... |
2514 2515 |
tmp_sec_rssi = cur_rf_rssi; sec_rssi_index = i; |
04d695d77 staging: rtl8192u... |
2516 |
} else if ((cur_rf_rssi < tmp_max_rssi) && (cur_rf_rssi > tmp_sec_rssi)) { |
8fc8598e6 Staging: Added Re... |
2517 2518 |
tmp_sec_rssi = cur_rf_rssi; sec_rssi_index = i; |
04d695d77 staging: rtl8192u... |
2519 2520 2521 |
} else if (cur_rf_rssi == tmp_sec_rssi) { if (tmp_sec_rssi == tmp_min_rssi) { /* let sec and min point to the different index */ |
8fc8598e6 Staging: Added Re... |
2522 2523 |
tmp_sec_rssi = cur_rf_rssi; sec_rssi_index = i; |
04d695d77 staging: rtl8192u... |
2524 |
} else { |
e1da1d573 staging: rtl8192u... |
2525 |
/* This case we don't need to set any index */ |
8fc8598e6 Staging: Added Re... |
2526 |
} |
04d695d77 staging: rtl8192u... |
2527 |
} else if ((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi)) { |
e1da1d573 staging: rtl8192u... |
2528 |
/* This case we don't need to set any index */ |
04d695d77 staging: rtl8192u... |
2529 2530 2531 |
} else if (cur_rf_rssi == tmp_min_rssi) { if (tmp_sec_rssi == tmp_min_rssi) { /* let sec and min point to the different index */ |
8fc8598e6 Staging: Added Re... |
2532 2533 |
tmp_min_rssi = cur_rf_rssi; min_rssi_index = i; |
04d695d77 staging: rtl8192u... |
2534 |
} else { |
e1da1d573 staging: rtl8192u... |
2535 |
/* This case we don't need to set any index */ |
8fc8598e6 Staging: Added Re... |
2536 |
} |
04d695d77 staging: rtl8192u... |
2537 |
} else if (cur_rf_rssi < tmp_min_rssi) { |
8fc8598e6 Staging: Added Re... |
2538 2539 2540 2541 2542 2543 2544 2545 |
tmp_min_rssi = cur_rf_rssi; min_rssi_index = i; } } } } rf_num = 0; |
e1da1d573 staging: rtl8192u... |
2546 |
/* decide max/sec/min cck pwdb index */ |
04d695d77 staging: rtl8192u... |
2547 2548 2549 |
if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) { for (i = 0; i < RF90_PATH_MAX; i++) { if (priv->brfpath_rxenable[i]) { |
8fc8598e6 Staging: Added Re... |
2550 2551 |
rf_num++; cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i]; |
04d695d77 staging: rtl8192u... |
2552 2553 |
if (rf_num == 1) { /* find first enabled rf path and the rssi values */ /* initialize, set all rssi index to the same one */ |
8fc8598e6 Staging: Added Re... |
2554 2555 |
cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i; tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb; |
04d695d77 staging: rtl8192u... |
2556 2557 |
} else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */ if (cur_cck_pwdb >= tmp_cck_max_pwdb) { |
8fc8598e6 Staging: Added Re... |
2558 2559 |
tmp_cck_max_pwdb = cur_cck_pwdb; cck_rx_ver2_max_index = i; |
04d695d77 staging: rtl8192u... |
2560 |
} else { |
8fc8598e6 Staging: Added Re... |
2561 2562 2563 |
tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb; cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i; } |
04d695d77 staging: rtl8192u... |
2564 2565 |
} else { if (cur_cck_pwdb > tmp_cck_max_pwdb) { |
8fc8598e6 Staging: Added Re... |
2566 2567 2568 2569 |
tmp_cck_sec_pwdb = tmp_cck_max_pwdb; cck_rx_ver2_sec_index = cck_rx_ver2_max_index; tmp_cck_max_pwdb = cur_cck_pwdb; cck_rx_ver2_max_index = i; |
f0e0f8cff staging: rtl8192u... |
2570 2571 |
} else if (cur_cck_pwdb == tmp_cck_max_pwdb) { /* let sec and min point to the different index */ |
8fc8598e6 Staging: Added Re... |
2572 2573 |
tmp_cck_sec_pwdb = cur_cck_pwdb; cck_rx_ver2_sec_index = i; |
04d695d77 staging: rtl8192u... |
2574 |
} else if ((cur_cck_pwdb < tmp_cck_max_pwdb) && (cur_cck_pwdb > tmp_cck_sec_pwdb)) { |
8fc8598e6 Staging: Added Re... |
2575 2576 |
tmp_cck_sec_pwdb = cur_cck_pwdb; cck_rx_ver2_sec_index = i; |
f0e0f8cff staging: rtl8192u... |
2577 2578 2579 2580 2581 |
} else if (cur_cck_pwdb == tmp_cck_sec_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) { /* let sec and min point to the different index */ tmp_cck_sec_pwdb = cur_cck_pwdb; cck_rx_ver2_sec_index = i; /* otherwise we don't need to set any index */ |
04d695d77 staging: rtl8192u... |
2582 |
} else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb)) { |
e1da1d573 staging: rtl8192u... |
2583 |
/* This case we don't need to set any index */ |
f0e0f8cff staging: rtl8192u... |
2584 2585 2586 2587 2588 |
} else if (cur_cck_pwdb == tmp_cck_min_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) { /* let sec and min point to the different index */ tmp_cck_min_pwdb = cur_cck_pwdb; cck_rx_ver2_min_index = i; /* otherwise we don't need to set any index */ |
04d695d77 staging: rtl8192u... |
2589 |
} else if (cur_cck_pwdb < tmp_cck_min_pwdb) { |
8fc8598e6 Staging: Added Re... |
2590 2591 2592 2593 2594 2595 2596 2597 |
tmp_cck_min_pwdb = cur_cck_pwdb; cck_rx_ver2_min_index = i; } } } } } |
e1da1d573 staging: rtl8192u... |
2598 2599 2600 2601 |
/* * Set CCK Rx path * reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path. */ |
8fc8598e6 Staging: Added Re... |
2602 |
update_cck_rx_path = 0; |
04d695d77 staging: rtl8192u... |
2603 |
if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) { |
8fc8598e6 Staging: Added Re... |
2604 2605 |
cck_default_Rx = cck_rx_ver2_max_index; cck_optional_Rx = cck_rx_ver2_sec_index; |
04d695d77 staging: rtl8192u... |
2606 |
if (tmp_cck_max_pwdb != -64) |
8fc8598e6 Staging: Added Re... |
2607 2608 |
update_cck_rx_path = 1; } |
04d695d77 staging: rtl8192u... |
2609 2610 |
if (tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2) { if ((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH) { |
e1da1d573 staging: rtl8192u... |
2611 |
/* record the enabled rssi threshold */ |
8fc8598e6 Staging: Added Re... |
2612 |
DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5; |
e1da1d573 staging: rtl8192u... |
2613 2614 2615 |
/* disable the BB Rx path, OFDM */ rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); /* 0xc04[3:0] */ rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); /* 0xd04[3:0] */ |
8fc8598e6 Staging: Added Re... |
2616 2617 |
disabled_rf_cnt++; } |
04d695d77 staging: rtl8192u... |
2618 |
if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) { |
8fc8598e6 Staging: Added Re... |
2619 2620 |
cck_default_Rx = max_rssi_index; cck_optional_Rx = sec_rssi_index; |
04d695d77 staging: rtl8192u... |
2621 |
if (tmp_max_rssi) |
8fc8598e6 Staging: Added Re... |
2622 2623 2624 |
update_cck_rx_path = 1; } } |
04d695d77 staging: rtl8192u... |
2625 |
if (update_cck_rx_path) { |
8fc8598e6 Staging: Added Re... |
2626 2627 2628 |
DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx); rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path); } |
04d695d77 staging: rtl8192u... |
2629 2630 2631 2632 |
if (DM_RxPathSelTable.disabledRF) { for (i = 0; i < 4; i++) { if ((DM_RxPathSelTable.disabledRF>>i) & 0x1) { /* disabled rf */ if (tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) { |
e1da1d573 staging: rtl8192u... |
2633 |
/* enable the BB Rx path */ |
04d695d77 staging: rtl8192u... |
2634 2635 |
/*DbgPrint("RF-%d is enabled. ", 0x1<<i);*/ |
e1da1d573 staging: rtl8192u... |
2636 2637 |
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); /* 0xc04[3:0] */ rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); /* 0xd04[3:0] */ |
8fc8598e6 Staging: Added Re... |
2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 |
DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; disabled_rf_cnt--; } } } } } /*----------------------------------------------------------------------------- * Function: dm_check_rx_path_selection() * * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI. * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 05/28/2008 amy Create Version 0 porting from windows code. * *---------------------------------------------------------------------------*/ |
04d695d77 staging: rtl8192u... |
2662 |
static void dm_check_rx_path_selection(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2663 2664 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
8fc8598e6 Staging: Added Re... |
2665 |
|
04d695d77 staging: rtl8192u... |
2666 2667 |
queue_delayed_work(priv->priv_wq, &priv->rfpath_check_wq, 0); } /* dm_CheckRxRFPath */ |
8fc8598e6 Staging: Added Re... |
2668 |
|
04d695d77 staging: rtl8192u... |
2669 |
static void dm_init_fsync(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2670 2671 2672 2673 2674 2675 |
{ struct r8192_priv *priv = ieee80211_priv(dev); priv->ieee80211->fsync_time_interval = 500; priv->ieee80211->fsync_rate_bitmap = 0x0f000800; priv->ieee80211->fsync_rssi_threshold = 30; |
8fc8598e6 Staging: Added Re... |
2676 |
priv->ieee80211->bfsync_enable = false; |
8fc8598e6 Staging: Added Re... |
2677 |
priv->ieee80211->fsync_multiple_timeinterval = 3; |
04d695d77 staging: rtl8192u... |
2678 2679 |
priv->ieee80211->fsync_firstdiff_ratethreshold = 100; priv->ieee80211->fsync_seconddiff_ratethreshold = 200; |
8fc8598e6 Staging: Added Re... |
2680 |
priv->ieee80211->fsync_state = Default_Fsync; |
e1da1d573 staging: rtl8192u... |
2681 |
priv->framesyncMonitor = 1; /* current default 0xc38 monitor on */ |
acc6539fe Staging: rtl8192u... |
2682 2683 |
setup_timer(&priv->fsync_timer, dm_fsync_timer_callback, (unsigned long)dev); |
8fc8598e6 Staging: Added Re... |
2684 |
} |
8fc8598e6 Staging: Added Re... |
2685 2686 2687 |
static void dm_deInit_fsync(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d77 staging: rtl8192u... |
2688 |
|
8fc8598e6 Staging: Added Re... |
2689 2690 |
del_timer_sync(&priv->fsync_timer); } |
c541fa875 staging:rtl8192u:... |
2691 |
void dm_fsync_timer_callback(unsigned long data) |
8fc8598e6 Staging: Added Re... |
2692 2693 2694 |
{ struct net_device *dev = (struct net_device *)data; struct r8192_priv *priv = ieee80211_priv((struct net_device *)data); |
04d695d77 staging: rtl8192u... |
2695 |
u32 rate_index, rate_count = 0, rate_count_diff = 0; |
8fc8598e6 Staging: Added Re... |
2696 2697 |
bool bSwitchFromCountDiff = false; bool bDoubleTimeInterval = false; |
04d695d77 staging: rtl8192u... |
2698 |
if (priv->ieee80211->state == IEEE80211_LINKED && |
8fc8598e6 Staging: Added Re... |
2699 |
priv->ieee80211->bfsync_enable && |
04d695d77 staging: rtl8192u... |
2700 |
(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) { |
e1da1d573 staging: rtl8192u... |
2701 |
/* Count rate 54, MCS [7], [12, 13, 14, 15] */ |
8fc8598e6 Staging: Added Re... |
2702 |
u32 rate_bitmap; |
04d695d77 staging: rtl8192u... |
2703 2704 |
for (rate_index = 0; rate_index <= 27; rate_index++) { |
8fc8598e6 Staging: Added Re... |
2705 |
rate_bitmap = 1 << rate_index; |
04d695d77 staging: rtl8192u... |
2706 2707 |
if (priv->ieee80211->fsync_rate_bitmap & rate_bitmap) rate_count += priv->stats.received_rate_histogram[1][rate_index]; |
8fc8598e6 Staging: Added Re... |
2708 |
} |
04d695d77 staging: rtl8192u... |
2709 |
if (rate_count < priv->rate_record) |
8fc8598e6 Staging: Added Re... |
2710 2711 2712 |
rate_count_diff = 0xffffffff - rate_count + priv->rate_record; else rate_count_diff = rate_count - priv->rate_record; |
04d695d77 staging: rtl8192u... |
2713 |
if (rate_count_diff < priv->rateCountDiffRecord) { |
8fc8598e6 Staging: Added Re... |
2714 |
u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff; |
e1da1d573 staging: rtl8192u... |
2715 |
/* Continue count */ |
04d695d77 staging: rtl8192u... |
2716 |
if (DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold) |
4c234ebcf staging: "rtl8192... |
2717 |
priv->ContinueDiffCount++; |
8fc8598e6 Staging: Added Re... |
2718 |
else |
4c234ebcf staging: "rtl8192... |
2719 |
priv->ContinueDiffCount = 0; |
8fc8598e6 Staging: Added Re... |
2720 |
|
e1da1d573 staging: rtl8192u... |
2721 |
/* Continue count over */ |
04d695d77 staging: rtl8192u... |
2722 |
if (priv->ContinueDiffCount >= 2) { |
8fc8598e6 Staging: Added Re... |
2723 |
bSwitchFromCountDiff = true; |
4c234ebcf staging: "rtl8192... |
2724 |
priv->ContinueDiffCount = 0; |
8fc8598e6 Staging: Added Re... |
2725 |
} |
04d695d77 staging: rtl8192u... |
2726 |
} else { |
e1da1d573 staging: rtl8192u... |
2727 |
/* Stop the continued count */ |
4c234ebcf staging: "rtl8192... |
2728 |
priv->ContinueDiffCount = 0; |
8fc8598e6 Staging: Added Re... |
2729 |
} |
e1da1d573 staging: rtl8192u... |
2730 |
/* If Count diff <= FsyncRateCountThreshold */ |
04d695d77 staging: rtl8192u... |
2731 |
if (rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold) { |
8fc8598e6 Staging: Added Re... |
2732 |
bSwitchFromCountDiff = true; |
4c234ebcf staging: "rtl8192... |
2733 |
priv->ContinueDiffCount = 0; |
8fc8598e6 Staging: Added Re... |
2734 2735 2736 |
} priv->rate_record = rate_count; priv->rateCountDiffRecord = rate_count_diff; |
04d695d77 staging: rtl8192u... |
2737 2738 |
RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d ", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync); |
e1da1d573 staging: rtl8192u... |
2739 |
/* if we never receive those mcs rate and rssi > 30 % then switch fsyn */ |
04d695d77 staging: rtl8192u... |
2740 |
if (priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff) { |
8fc8598e6 Staging: Added Re... |
2741 2742 |
bDoubleTimeInterval = true; priv->bswitch_fsync = !priv->bswitch_fsync; |
04d695d77 staging: rtl8192u... |
2743 |
if (priv->bswitch_fsync) { |
0b4ef0a64 drivers: staging:... |
2744 |
write_nic_byte(dev, 0xC36, 0x1c); |
8fc8598e6 Staging: Added Re... |
2745 |
write_nic_byte(dev, 0xC3e, 0x90); |
04d695d77 staging: rtl8192u... |
2746 |
} else { |
8fc8598e6 Staging: Added Re... |
2747 |
write_nic_byte(dev, 0xC36, 0x5c); |
8fc8598e6 Staging: Added Re... |
2748 2749 |
write_nic_byte(dev, 0xC3e, 0x96); } |
04d695d77 staging: rtl8192u... |
2750 2751 |
} else if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) { if (priv->bswitch_fsync) { |
8fc8598e6 Staging: Added Re... |
2752 |
priv->bswitch_fsync = false; |
8fc8598e6 Staging: Added Re... |
2753 |
write_nic_byte(dev, 0xC36, 0x5c); |
8fc8598e6 Staging: Added Re... |
2754 2755 2756 |
write_nic_byte(dev, 0xC3e, 0x96); } } |
04d695d77 staging: rtl8192u... |
2757 2758 |
if (bDoubleTimeInterval) { if (timer_pending(&priv->fsync_timer)) |
8fc8598e6 Staging: Added Re... |
2759 |
del_timer_sync(&priv->fsync_timer); |
e6be66fff staging: rtl8192u... |
2760 2761 |
priv->fsync_timer.expires = jiffies + msecs_to_jiffies(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval); |
8fc8598e6 Staging: Added Re... |
2762 |
add_timer(&priv->fsync_timer); |
04d695d77 staging: rtl8192u... |
2763 2764 |
} else { if (timer_pending(&priv->fsync_timer)) |
8fc8598e6 Staging: Added Re... |
2765 |
del_timer_sync(&priv->fsync_timer); |
e6be66fff staging: rtl8192u... |
2766 2767 |
priv->fsync_timer.expires = jiffies + msecs_to_jiffies(priv->ieee80211->fsync_time_interval); |
8fc8598e6 Staging: Added Re... |
2768 2769 |
add_timer(&priv->fsync_timer); } |
04d695d77 staging: rtl8192u... |
2770 |
} else { |
e1da1d573 staging: rtl8192u... |
2771 |
/* Let Register return to default value; */ |
04d695d77 staging: rtl8192u... |
2772 |
if (priv->bswitch_fsync) { |
8fc8598e6 Staging: Added Re... |
2773 |
priv->bswitch_fsync = false; |
8fc8598e6 Staging: Added Re... |
2774 |
write_nic_byte(dev, 0xC36, 0x5c); |
8fc8598e6 Staging: Added Re... |
2775 2776 |
write_nic_byte(dev, 0xC3e, 0x96); } |
4c234ebcf staging: "rtl8192... |
2777 |
priv->ContinueDiffCount = 0; |
8fc8598e6 Staging: Added Re... |
2778 |
write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); |
8fc8598e6 Staging: Added Re... |
2779 |
} |
4c234ebcf staging: "rtl8192... |
2780 2781 |
RT_TRACE(COMP_HALDM, "ContinueDiffCount %d ", priv->ContinueDiffCount); |
04d695d77 staging: rtl8192u... |
2782 2783 |
RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d ", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync); |
8fc8598e6 Staging: Added Re... |
2784 2785 2786 2787 |
} static void dm_StartHWFsync(struct net_device *dev) { |
f8628a47b staging: Convert ... |
2788 2789 |
RT_TRACE(COMP_HALDM, "%s ", __func__); |
8fc8598e6 Staging: Added Re... |
2790 2791 2792 2793 2794 2795 2796 |
write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf); write_nic_byte(dev, 0xc3b, 0x41); } static void dm_EndSWFsync(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
f8628a47b staging: Convert ... |
2797 2798 |
RT_TRACE(COMP_HALDM, "%s ", __func__); |
8fc8598e6 Staging: Added Re... |
2799 |
del_timer_sync(&(priv->fsync_timer)); |
e1da1d573 staging: rtl8192u... |
2800 |
/* Let Register return to default value; */ |
04d695d77 staging: rtl8192u... |
2801 |
if (priv->bswitch_fsync) { |
8fc8598e6 Staging: Added Re... |
2802 |
priv->bswitch_fsync = false; |
91e39f09e staging: rtl8192u... |
2803 |
write_nic_byte(dev, 0xC36, 0x5c); |
8fc8598e6 Staging: Added Re... |
2804 2805 2806 |
write_nic_byte(dev, 0xC3e, 0x96); } |
4c234ebcf staging: "rtl8192... |
2807 |
priv->ContinueDiffCount = 0; |
8fc8598e6 Staging: Added Re... |
2808 |
write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); |
8fc8598e6 Staging: Added Re... |
2809 2810 2811 2812 2813 2814 |
} static void dm_StartSWFsync(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
35997ff0c staging/rtl8192u:... |
2815 2816 |
u32 rateIndex; u32 rateBitmap; |
8fc8598e6 Staging: Added Re... |
2817 |
|
0b4ef0a64 drivers: staging:... |
2818 2819 |
RT_TRACE(COMP_HALDM, "%s ", __func__); |
e1da1d573 staging: rtl8192u... |
2820 |
/* Initial rate record to zero, start to record. */ |
8fc8598e6 Staging: Added Re... |
2821 |
priv->rate_record = 0; |
e1da1d573 staging: rtl8192u... |
2822 |
/* Initialize continue diff count to zero, start to record. */ |
4c234ebcf staging: "rtl8192... |
2823 |
priv->ContinueDiffCount = 0; |
8fc8598e6 Staging: Added Re... |
2824 2825 |
priv->rateCountDiffRecord = 0; priv->bswitch_fsync = false; |
04d695d77 staging: rtl8192u... |
2826 2827 |
if (priv->ieee80211->mode == WIRELESS_MODE_N_24G) { priv->ieee80211->fsync_firstdiff_ratethreshold = 600; |
8fc8598e6 Staging: Added Re... |
2828 |
priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff; |
04d695d77 staging: rtl8192u... |
2829 2830 |
} else { priv->ieee80211->fsync_firstdiff_ratethreshold = 200; |
8fc8598e6 Staging: Added Re... |
2831 2832 |
priv->ieee80211->fsync_seconddiff_ratethreshold = 200; } |
04d695d77 staging: rtl8192u... |
2833 2834 2835 |
for (rateIndex = 0; rateIndex <= 27; rateIndex++) { rateBitmap = 1 << rateIndex; if (priv->ieee80211->fsync_rate_bitmap & rateBitmap) |
8fc8598e6 Staging: Added Re... |
2836 2837 |
priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex]; } |
04d695d77 staging: rtl8192u... |
2838 |
if (timer_pending(&priv->fsync_timer)) |
8fc8598e6 Staging: Added Re... |
2839 |
del_timer_sync(&priv->fsync_timer); |
e6be66fff staging: rtl8192u... |
2840 2841 |
priv->fsync_timer.expires = jiffies + msecs_to_jiffies(priv->ieee80211->fsync_time_interval); |
8fc8598e6 Staging: Added Re... |
2842 |
add_timer(&priv->fsync_timer); |
8fc8598e6 Staging: Added Re... |
2843 |
write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd); |
8fc8598e6 Staging: Added Re... |
2844 2845 2846 2847 2848 |
} static void dm_EndHWFsync(struct net_device *dev) { |
0b4ef0a64 drivers: staging:... |
2849 2850 |
RT_TRACE(COMP_HALDM, "%s ", __func__); |
8fc8598e6 Staging: Added Re... |
2851 2852 2853 2854 2855 2856 2857 2858 |
write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); write_nic_byte(dev, 0xc3b, 0x49); } void dm_check_fsync(struct net_device *dev) { #define RegC38_Default 0 |
04d695d77 staging: rtl8192u... |
2859 2860 |
#define RegC38_NonFsync_Other_AP 1 #define RegC38_Fsync_AP_BCM 2 |
8fc8598e6 Staging: Added Re... |
2861 |
struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
2862 |
/*u32 framesyncC34;*/ |
04d695d77 staging: rtl8192u... |
2863 |
static u8 reg_c38_State = RegC38_Default; |
de13a3dad staging/rtl8192u:... |
2864 |
static u32 reset_cnt; |
8fc8598e6 Staging: Added Re... |
2865 2866 2867 2868 2869 |
RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d ", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval); RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d ", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold); |
04d695d77 staging: rtl8192u... |
2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 |
if (priv->ieee80211->state == IEEE80211_LINKED && (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) { if (priv->ieee80211->bfsync_enable == 0) { switch (priv->ieee80211->fsync_state) { case Default_Fsync: dm_StartHWFsync(dev); priv->ieee80211->fsync_state = HW_Fsync; break; case SW_Fsync: dm_EndSWFsync(dev); dm_StartHWFsync(dev); priv->ieee80211->fsync_state = HW_Fsync; break; case HW_Fsync: default: break; |
8fc8598e6 Staging: Added Re... |
2886 |
} |
04d695d77 staging: rtl8192u... |
2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 |
} else { switch (priv->ieee80211->fsync_state) { case Default_Fsync: dm_StartSWFsync(dev); priv->ieee80211->fsync_state = SW_Fsync; break; case HW_Fsync: dm_EndHWFsync(dev); dm_StartSWFsync(dev); priv->ieee80211->fsync_state = SW_Fsync; break; case SW_Fsync: default: break; |
8fc8598e6 Staging: Added Re... |
2901 2902 |
} } |
04d695d77 staging: rtl8192u... |
2903 2904 2905 |
if (priv->framesyncMonitor) { if (reg_c38_State != RegC38_Fsync_AP_BCM) { /* For broadcom AP we write different default value */ |
91e39f09e staging: rtl8192u... |
2906 |
write_nic_byte(dev, rOFDM0_RxDetector3, 0x95); |
8fc8598e6 Staging: Added Re... |
2907 2908 2909 2910 |
reg_c38_State = RegC38_Fsync_AP_BCM; } } |
04d695d77 staging: rtl8192u... |
2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 |
} else { switch (priv->ieee80211->fsync_state) { case HW_Fsync: dm_EndHWFsync(dev); priv->ieee80211->fsync_state = Default_Fsync; break; case SW_Fsync: dm_EndSWFsync(dev); priv->ieee80211->fsync_state = Default_Fsync; break; case Default_Fsync: default: break; |
8fc8598e6 Staging: Added Re... |
2924 |
} |
04d695d77 staging: rtl8192u... |
2925 2926 2927 2928 |
if (priv->framesyncMonitor) { if (priv->ieee80211->state == IEEE80211_LINKED) { if (priv->undecorated_smoothed_pwdb <= RegC38_TH) { if (reg_c38_State != RegC38_NonFsync_Other_AP) { |
91e39f09e staging: rtl8192u... |
2929 |
write_nic_byte(dev, rOFDM0_RxDetector3, 0x90); |
8fc8598e6 Staging: Added Re... |
2930 2931 |
reg_c38_State = RegC38_NonFsync_Other_AP; |
8fc8598e6 Staging: Added Re... |
2932 |
} |
04d695d77 staging: rtl8192u... |
2933 2934 |
} else if (priv->undecorated_smoothed_pwdb >= (RegC38_TH+5)) { if (reg_c38_State) { |
8fc8598e6 Staging: Added Re... |
2935 2936 |
write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); reg_c38_State = RegC38_Default; |
04d695d77 staging: rtl8192u... |
2937 2938 |
/*DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x ", pHalData->framesync);*/ |
8fc8598e6 Staging: Added Re... |
2939 2940 |
} } |
04d695d77 staging: rtl8192u... |
2941 2942 |
} else { if (reg_c38_State) { |
8fc8598e6 Staging: Added Re... |
2943 2944 |
write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); reg_c38_State = RegC38_Default; |
04d695d77 staging: rtl8192u... |
2945 2946 |
/*DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x ", pHalData->framesync);*/ |
8fc8598e6 Staging: Added Re... |
2947 2948 2949 2950 |
} } } } |
04d695d77 staging: rtl8192u... |
2951 2952 |
if (priv->framesyncMonitor) { if (priv->reset_count != reset_cnt) { /* After silent reset, the reg_c38_State will be returned to default value */ |
8fc8598e6 Staging: Added Re... |
2953 2954 2955 |
write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); reg_c38_State = RegC38_Default; reset_cnt = priv->reset_count; |
04d695d77 staging: rtl8192u... |
2956 2957 |
/*DbgPrint("reg_c38_State = 0 for silent reset. ");*/ |
8fc8598e6 Staging: Added Re... |
2958 |
} |
04d695d77 staging: rtl8192u... |
2959 2960 |
} else { if (reg_c38_State) { |
8fc8598e6 Staging: Added Re... |
2961 2962 |
write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); reg_c38_State = RegC38_Default; |
04d695d77 staging: rtl8192u... |
2963 2964 |
/*DbgPrint("framesync no monitor, write 0xc38 = 0x%x ", pHalData->framesync);*/ |
8fc8598e6 Staging: Added Re... |
2965 2966 2967 |
} } } |
8fc8598e6 Staging: Added Re... |
2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 |
/*----------------------------------------------------------------------------- * Function: dm_shadow_init() * * Overview: Store all NIC MAC/BB register content. * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 05/29/2008 amy Create Version 0 porting from windows code. * *---------------------------------------------------------------------------*/ |
c541fa875 staging:rtl8192u:... |
2984 |
void dm_shadow_init(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
2985 2986 2987 2988 2989 |
{ u8 page; u16 offset; for (page = 0; page < 5; page++) |
04d695d77 staging: rtl8192u... |
2990 |
for (offset = 0; offset < 256; offset++) { |
b3d42bf18 staging: rtl8192u... |
2991 |
read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]); |
e1da1d573 staging: rtl8192u... |
2992 2993 |
/*DbgPrint("P-%d/O-%02x=%02x\r ", page, offset, DM_Shadow[page][offset]);*/ |
8fc8598e6 Staging: Added Re... |
2994 2995 2996 2997 |
} for (page = 8; page < 11; page++) for (offset = 0; offset < 256; offset++) |
b3d42bf18 staging: rtl8192u... |
2998 |
read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]); |
8fc8598e6 Staging: Added Re... |
2999 3000 3001 |
for (page = 12; page < 15; page++) for (offset = 0; offset < 256; offset++) |
b3d42bf18 staging: rtl8192u... |
3002 |
read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]); |
8fc8598e6 Staging: Added Re... |
3003 3004 3005 3006 3007 3008 3009 3010 |
} /* dm_shadow_init */ /*---------------------------Define function prototype------------------------*/ /*----------------------------------------------------------------------------- * Function: DM_DynamicTxPower() * * Overview: Detect Signal strength to control TX Registry |
e406322b4 Staging: rtl8192u... |
3011 |
Tx Power Control For Near/Far Range |
8fc8598e6 Staging: Added Re... |
3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 |
* * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 03/06/2008 Jacken Create Version 0. * *---------------------------------------------------------------------------*/ static void dm_init_dynamic_txpower(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
3027 3028 |
/* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */ priv->ieee80211->bdynamic_txpower_enable = true; /* Default to enable Tx Power Control */ |
8fc8598e6 Staging: Added Re... |
3029 3030 3031 3032 3033 3034 3035 3036 3037 |
priv->bLastDTPFlag_High = false; priv->bLastDTPFlag_Low = false; priv->bDynamicTxHighPower = false; priv->bDynamicTxLowPower = false; } static void dm_dynamic_txpower(struct net_device *dev) { struct r8192_priv *priv = ieee80211_priv(dev); |
04d695d77 staging: rtl8192u... |
3038 3039 3040 3041 |
unsigned int txhipower_threshhold = 0; unsigned int txlowpower_threshold = 0; if (priv->ieee80211->bdynamic_txpower_enable != true) { |
8fc8598e6 Staging: Added Re... |
3042 3043 3044 3045 |
priv->bDynamicTxHighPower = false; priv->bDynamicTxLowPower = false; return; } |
04d695d77 staging: rtl8192u... |
3046 3047 3048 |
/*printk("priv->ieee80211->current_network.unknown_cap_exist is %d , priv->ieee80211->current_network.broadcom_cap_exist is %d ", priv->ieee80211->current_network.unknown_cap_exist, priv->ieee80211->current_network.broadcom_cap_exist);*/ if ((priv->ieee80211->current_network.atheros_cap_exist) && (priv->ieee80211->mode == IEEE_G)) { |
8fc8598e6 Staging: Added Re... |
3049 3050 |
txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH; txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW; |
04d695d77 staging: rtl8192u... |
3051 |
} else { |
8fc8598e6 Staging: Added Re... |
3052 3053 3054 |
txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH; txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW; } |
04d695d77 staging: rtl8192u... |
3055 3056 3057 3058 |
/*printk("=======>%s(): txhipower_threshhold is %d, txlowpower_threshold is %d ", __func__, txhipower_threshhold, txlowpower_threshold);*/ RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld ", priv->undecorated_smoothed_pwdb); |
8fc8598e6 Staging: Added Re... |
3059 |
|
04d695d77 staging: rtl8192u... |
3060 3061 |
if (priv->ieee80211->state == IEEE80211_LINKED) { if (priv->undecorated_smoothed_pwdb >= txhipower_threshhold) { |
8fc8598e6 Staging: Added Re... |
3062 3063 |
priv->bDynamicTxHighPower = true; priv->bDynamicTxLowPower = false; |
04d695d77 staging: rtl8192u... |
3064 |
} else { |
e1da1d573 staging: rtl8192u... |
3065 |
/* high power state check */ |
c40753b5c staging: rtl8192u... |
3066 |
if (priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower) |
8fc8598e6 Staging: Added Re... |
3067 |
priv->bDynamicTxHighPower = false; |
04d695d77 staging: rtl8192u... |
3068 |
|
e1da1d573 staging: rtl8192u... |
3069 |
/* low power state check */ |
16da78083 staging: rtl8192u... |
3070 |
if (priv->undecorated_smoothed_pwdb < 35) |
8fc8598e6 Staging: Added Re... |
3071 |
priv->bDynamicTxLowPower = true; |
16da78083 staging: rtl8192u... |
3072 |
else if (priv->undecorated_smoothed_pwdb >= 40) |
8fc8598e6 Staging: Added Re... |
3073 |
priv->bDynamicTxLowPower = false; |
8fc8598e6 Staging: Added Re... |
3074 |
} |
04d695d77 staging: rtl8192u... |
3075 |
} else { |
e1da1d573 staging: rtl8192u... |
3076 |
/*pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;*/ |
8fc8598e6 Staging: Added Re... |
3077 3078 3079 |
priv->bDynamicTxHighPower = false; priv->bDynamicTxLowPower = false; } |
04d695d77 staging: rtl8192u... |
3080 3081 3082 3083 |
if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) || (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) { RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190() channel = %d ", priv->ieee80211->current_network.channel); |
8fc8598e6 Staging: Added Re... |
3084 3085 |
#if defined(RTL8190P) || defined(RTL8192E) |
04d695d77 staging: rtl8192u... |
3086 |
SetTxPowerLevel8190(Adapter, pHalData->CurrentChannel); |
8fc8598e6 Staging: Added Re... |
3087 |
#endif |
04d695d77 staging: rtl8192u... |
3088 |
rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel); |
e1da1d573 staging: rtl8192u... |
3089 |
/*pHalData->bStartTxCtrlByTPCNFR = FALSE; Clear th flag of Set TX Power from Sitesurvey*/ |
8fc8598e6 Staging: Added Re... |
3090 3091 3092 3093 3094 |
} priv->bLastDTPFlag_High = priv->bDynamicTxHighPower; priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower; } /* dm_dynamic_txpower */ |
e1da1d573 staging: rtl8192u... |
3095 |
/* added by vivi, for read tx rate and retrycount */ |
999d594b7 STAGING: rtl8192u... |
3096 |
static void dm_check_txrateandretrycount(struct net_device *dev) |
8fc8598e6 Staging: Added Re... |
3097 3098 |
{ struct r8192_priv *priv = ieee80211_priv(dev); |
999d594b7 STAGING: rtl8192u... |
3099 |
struct ieee80211_device *ieee = priv->ieee80211; |
e1da1d573 staging: rtl8192u... |
3100 3101 |
/* for 11n tx rate */ /*priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);*/ |
b3d42bf18 staging: rtl8192u... |
3102 |
read_nic_byte(dev, Current_Tx_Rate_Reg, &ieee->softmac_stats.CurrentShowTxate); |
e1da1d573 staging: rtl8192u... |
3103 3104 3105 3106 |
/*printk("=============>tx_rate_reg:%x ", ieee->softmac_stats.CurrentShowTxate);*/ /* for initial tx rate */ /*priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);*/ |
b3d42bf18 staging: rtl8192u... |
3107 |
read_nic_byte(dev, Initial_Tx_Rate_Reg, &ieee->softmac_stats.last_packet_rate); |
e1da1d573 staging: rtl8192u... |
3108 3109 |
/* for tx tx retry count */ /*priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);*/ |
b3d42bf18 staging: rtl8192u... |
3110 |
read_nic_dword(dev, Tx_Retry_Count_Reg, &ieee->softmac_stats.txretrycount); |
8fc8598e6 Staging: Added Re... |
3111 3112 3113 3114 |
} static void dm_send_rssi_tofw(struct net_device *dev) { |
8fc8598e6 Staging: Added Re... |
3115 |
struct r8192_priv *priv = ieee80211_priv(dev); |
e1da1d573 staging: rtl8192u... |
3116 3117 3118 3119 3120 |
/* * If we test chariot, we should stop the TX command ? * Because 92E will always silent reset when we send tx command. We use register * 0x1e0(byte) to notify driver. */ |
8fc8598e6 Staging: Added Re... |
3121 |
write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb); |
8fc8598e6 Staging: Added Re... |
3122 3123 3124 |
} /*---------------------------Define function prototype------------------------*/ |