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drivers/ata/pata_cmd64x.c
12.9 KB
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/* |
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* pata_cmd64x.c - CMD64x PATA for new ATA layer |
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* (C) 2005 Red Hat Inc |
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* Alan Cox <alan@lxorguk.ukuu.org.uk> |
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* (C) 2009-2010 Bartlomiej Zolnierkiewicz |
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* (C) 2012 MontaVista Software, LLC <source@mvista.com> |
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* * Based upon * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 * * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. * Note, this driver is not used at all on other systems because * there the "BIOS" has done all of the following already. * Due to massive hardware bugs, UltraDMA is only supported * on the 646U2 and not on the 646U. * * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) * Copyright (C) 1998 David S. Miller (davem@redhat.com) * * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> * * TODO * Testing work */ |
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#include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> |
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#include <linux/blkdev.h> #include <linux/delay.h> #include <scsi/scsi_host.h> #include <linux/libata.h> #define DRV_NAME "pata_cmd64x" |
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#define DRV_VERSION "0.2.18" |
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/* * CMD64x specific registers definition. */ |
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enum { CFR = 0x50, |
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CFR_INTR_CH0 = 0x04, |
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CNTRL = 0x51, CNTRL_CH0 = 0x04, CNTRL_CH1 = 0x08, |
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CMDTIM = 0x52, ARTTIM0 = 0x53, DRWTIM0 = 0x54, ARTTIM1 = 0x55, DRWTIM1 = 0x56, ARTTIM23 = 0x57, ARTTIM23_DIS_RA2 = 0x04, ARTTIM23_DIS_RA3 = 0x08, ARTTIM23_INTR_CH1 = 0x10, |
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DRWTIM2 = 0x58, BRST = 0x59, DRWTIM3 = 0x5b, BMIDECR0 = 0x70, MRDMODE = 0x71, MRDMODE_INTR_CH0 = 0x04, MRDMODE_INTR_CH1 = 0x08, |
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BMIDESR0 = 0x72, UDIDETCR0 = 0x73, DTPR0 = 0x74, BMIDECR1 = 0x78, BMIDECSR = 0x79, |
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UDIDETCR1 = 0x7B, DTPR1 = 0x7C }; |
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static int cmd648_cable_detect(struct ata_port *ap) |
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{ struct pci_dev *pdev = to_pci_dev(ap->host->dev); u8 r; /* Check cable detect bits */ pci_read_config_byte(pdev, BMIDECSR, &r); if (r & (1 << ap->port_no)) |
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return ATA_CBL_PATA80; return ATA_CBL_PATA40; |
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} /** |
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* cmd64x_set_timing - set PIO and MWDMA timing |
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* @ap: ATA interface * @adev: ATA device |
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* @mode: mode |
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* |
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* Called to do the PIO and MWDMA mode setup. |
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*/ |
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static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) |
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{ struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct ata_timing t; const unsigned long T = 1000000 / 33; const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; |
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u8 reg; |
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/* Port layout is not logical so use a table */ |
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const u8 arttim_port[2][2] = { |
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{ ARTTIM0, ARTTIM1 }, { ARTTIM23, ARTTIM23 } }; const u8 drwtim_port[2][2] = { { DRWTIM0, DRWTIM1 }, { DRWTIM2, DRWTIM3 } }; |
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int arttim = arttim_port[ap->port_no][adev->devno]; int drwtim = drwtim_port[ap->port_no][adev->devno]; |
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/* ata_timing_compute is smart and will produce timings for MWDMA that don't violate the drives PIO capabilities. */ if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { |
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printk(KERN_ERR DRV_NAME ": mode computation failed. "); return; } if (ap->port_no) { /* Slave has shared address setup */ struct ata_device *pair = ata_dev_pair(adev); |
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if (pair) { struct ata_timing tp; ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); } } |
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printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d. ", t.active, t.recover, t.setup); if (t.recover > 16) { t.active += t.recover - 16; t.recover = 16; } if (t.active > 16) t.active = 16; |
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/* Now convert the clocks into values we can actually stuff into the chip */ |
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if (t.recover == 16) t.recover = 0; else if (t.recover > 1) |
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t.recover--; else t.recover = 15; |
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if (t.setup > 4) t.setup = 0xC0; else t.setup = setup_data[t.setup]; |
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t.active &= 0x0F; /* 0 = 16 */ |
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/* Load setup timing */ pci_read_config_byte(pdev, arttim, ®); reg &= 0x3F; reg |= t.setup; pci_write_config_byte(pdev, arttim, reg); |
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/* Load active/recovery */ |
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pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); |
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} /** |
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* cmd64x_set_piomode - set initial PIO mode data * @ap: ATA interface * @adev: ATA device * * Used when configuring the devices ot set the PIO timings. All the * actual work is done by the PIO/MWDMA setting helper */ static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) { cmd64x_set_timing(ap, adev, adev->pio_mode); } /** |
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* cmd64x_set_dmamode - set initial DMA mode data * @ap: ATA interface * @adev: ATA device * * Called to do the DMA mode setup. */ |
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static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) { static const u8 udma_data[] = { |
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0x30, 0x20, 0x10, 0x20, 0x10, 0x00 |
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}; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); u8 regU, regD; int pciU = UDIDETCR0 + 8 * ap->port_no; int pciD = BMIDESR0 + 8 * ap->port_no; int shift = 2 * adev->devno; |
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pci_read_config_byte(pdev, pciD, ®D); pci_read_config_byte(pdev, pciU, ®U); |
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/* DMA bits off */ regD &= ~(0x20 << adev->devno); /* DMA control bits */ regU &= ~(0x30 << shift); /* DMA timing bits */ regU &= ~(0x05 << adev->devno); |
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if (adev->dma_mode >= XFER_UDMA_0) { |
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/* Merge the timing value */ |
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regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; |
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/* Merge the control bits */ regU |= 1 << adev->devno; /* UDMA on */ |
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if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */ |
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regU |= 4 << adev->devno; |
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} else { regU &= ~ (1 << adev->devno); /* UDMA off */ cmd64x_set_timing(ap, adev, adev->dma_mode); } |
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regD |= 0x20 << adev->devno; pci_write_config_byte(pdev, pciU, regU); pci_write_config_byte(pdev, pciD, regD); } /** |
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* cmd64x_sff_irq_check - check IDE interrupt * @ap: ATA interface * * Check IDE interrupt in CFR/ARTTIM23 registers. */ static bool cmd64x_sff_irq_check(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; int irq_reg = ap->port_no ? ARTTIM23 : CFR; u8 irq_stat; /* NOTE: reading the register should clear the interrupt */ pci_read_config_byte(pdev, irq_reg, &irq_stat); return irq_stat & irq_mask; } /** |
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* cmd64x_sff_irq_clear - clear IDE interrupt * @ap: ATA interface |
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* |
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* Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers. |
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*/ |
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static void cmd64x_sff_irq_clear(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); int irq_reg = ap->port_no ? ARTTIM23 : CFR; u8 irq_stat; |
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ata_bmdma_irq_clear(ap); |
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/* Reading the register should be enough to clear the interrupt */ pci_read_config_byte(pdev, irq_reg, &irq_stat); } /** |
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* cmd648_sff_irq_check - check IDE interrupt * @ap: ATA interface * * Check IDE interrupt in MRDMODE register. */ static bool cmd648_sff_irq_check(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); unsigned long base = pci_resource_start(pdev, 4); int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; u8 mrdmode = inb(base + 1); return mrdmode & irq_mask; } /** |
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* cmd648_sff_irq_clear - clear IDE interrupt * @ap: ATA interface |
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* |
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* Clear IDE interrupt in MRDMODE and DMA status registers. |
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*/ |
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static void cmd648_sff_irq_clear(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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unsigned long base = pci_resource_start(pdev, 4); int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; u8 mrdmode; |
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ata_bmdma_irq_clear(ap); |
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/* Clear this port's interrupt bit (leaving the other port alone) */ mrdmode = inb(base + 1); mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1); outb(mrdmode | irq_mask, base + 1); |
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} |
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/** |
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* cmd646r1_bmdma_stop - DMA stop callback |
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* @qc: Command in progress * |
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* Stub for now while investigating the r1 quirk in the old driver. |
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*/ |
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static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) |
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{ ata_bmdma_stop(qc); } |
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static struct scsi_host_template cmd64x_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static const struct ata_port_operations cmd64x_base_ops = { .inherits = &ata_bmdma_port_ops, |
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.set_piomode = cmd64x_set_piomode, .set_dmamode = cmd64x_set_dmamode, |
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}; |
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static struct ata_port_operations cmd64x_port_ops = { .inherits = &cmd64x_base_ops, |
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.sff_irq_check = cmd64x_sff_irq_check, |
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.sff_irq_clear = cmd64x_sff_irq_clear, |
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.cable_detect = ata_cable_40wire, |
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}; |
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static struct ata_port_operations cmd646r1_port_ops = { .inherits = &cmd64x_base_ops, |
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.sff_irq_check = cmd64x_sff_irq_check, |
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.sff_irq_clear = cmd64x_sff_irq_clear, |
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.bmdma_stop = cmd646r1_bmdma_stop, |
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.cable_detect = ata_cable_40wire, |
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}; |
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static struct ata_port_operations cmd646r3_port_ops = { .inherits = &cmd64x_base_ops, |
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.sff_irq_check = cmd648_sff_irq_check, |
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.sff_irq_clear = cmd648_sff_irq_clear, |
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.cable_detect = ata_cable_40wire, }; |
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static struct ata_port_operations cmd648_port_ops = { |
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.inherits = &cmd64x_base_ops, |
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.sff_irq_check = cmd648_sff_irq_check, |
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.sff_irq_clear = cmd648_sff_irq_clear, |
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.cable_detect = cmd648_cable_detect, |
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}; |
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static void cmd64x_fixup(struct pci_dev *pdev) { u8 mrdmode; pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); pci_read_config_byte(pdev, MRDMODE, &mrdmode); mrdmode &= ~0x30; /* IRQ set up */ mrdmode |= 0x02; /* Memory read line enable */ pci_write_config_byte(pdev, MRDMODE, mrdmode); /* PPC specific fixup copied from old driver */ #ifdef CONFIG_PPC pci_write_config_byte(pdev, UDIDETCR0, 0xF0); #endif } |
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static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) { |
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static const struct ata_port_info cmd_info[7] = { |
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{ /* CMD 643 - no UDMA */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
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.port_ops = &cmd64x_port_ops }, { /* CMD 646 with broken UDMA */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
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.port_ops = &cmd64x_port_ops }, |
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{ /* CMD 646U with broken UDMA */ .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .port_ops = &cmd646r3_port_ops }, { /* CMD 646U2 with working UDMA */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA2, |
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.port_ops = &cmd646r3_port_ops |
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}, { /* CMD 646 rev 1 */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
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.port_ops = &cmd646r1_port_ops }, { /* CMD 648 */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA4, |
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.port_ops = &cmd648_port_ops }, { /* CMD 649 */ |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &cmd648_port_ops } }; |
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const struct ata_port_info *ppi[] = { |
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&cmd_info[id->driver_data], &cmd_info[id->driver_data], NULL }; |
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u8 reg; |
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int rc; |
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struct pci_dev *bridge = pdev->bus->self; /* mobility split bridges don't report enabled ports correctly */ int port_ok = !(bridge && bridge->vendor == PCI_VENDOR_ID_MOBILITY_ELECTRONICS); /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */ int cntrl_ch0_ok = (id->driver_data != 0); |
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rc = pcim_enable_device(pdev); if (rc) return rc; |
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if (id->driver_data == 0) /* 643 */ |
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ata_pci_bmdma_clear_simplex(pdev); |
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if (pdev->device == PCI_DEVICE_ID_CMD_646) switch (pdev->revision) { /* UDMA works since rev 5 */ default: |
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ppi[0] = &cmd_info[3]; ppi[1] = &cmd_info[3]; |
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break; |
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/* Interrupts in MRDMODE since rev 3 */ |
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case 3: case 4: |
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ppi[0] = &cmd_info[2]; ppi[1] = &cmd_info[2]; |
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break; /* Rev 1 with other problems? */ case 1: |
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ppi[0] = &cmd_info[4]; ppi[1] = &cmd_info[4]; |
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/* FALL THRU */ /* Early revs have no CNTRL_CH0 */ case 2: case 0: |
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cntrl_ch0_ok = 0; |
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break; } |
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cmd64x_fixup(pdev); |
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/* check for enabled ports */ pci_read_config_byte(pdev, CNTRL, ®); if (!port_ok) |
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468 469 |
dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable "); |
9281b16ca
|
470 |
if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) { |
a52f514c9
|
471 472 |
dev_notice(&pdev->dev, "Primary port is disabled "); |
9281b16ca
|
473 |
ppi[0] = &ata_dummy_port_info; |
641589bff
|
474 |
|
9281b16ca
|
475 476 |
} if (port_ok && !(reg & CNTRL_CH1)) { |
a52f514c9
|
477 478 |
dev_notice(&pdev->dev, "Secondary port is disabled "); |
9281b16ca
|
479 480 |
ppi[1] = &ata_dummy_port_info; } |
1c5afdf7a
|
481 |
return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0); |
669a5db41
|
482 |
} |
58eb8cd56
|
483 |
#ifdef CONFIG_PM_SLEEP |
7f72a3791
|
484 485 |
static int cmd64x_reinit_one(struct pci_dev *pdev) { |
0a86e1c85
|
486 |
struct ata_host *host = pci_get_drvdata(pdev); |
f08048e94
|
487 488 489 490 491 |
int rc; rc = ata_pci_device_do_resume(pdev); if (rc) return rc; |
f4c6ae502
|
492 |
cmd64x_fixup(pdev); |
f08048e94
|
493 494 |
ata_host_resume(host); return 0; |
7f72a3791
|
495 |
} |
438ac6d5e
|
496 |
#endif |
7f72a3791
|
497 |
|
2d2744fc8
|
498 499 500 |
static const struct pci_device_id cmd64x[] = { { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, |
8a686bc98
|
501 502 |
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 }, { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 }, |
2d2744fc8
|
503 504 |
{ }, |
669a5db41
|
505 506 507 |
}; static struct pci_driver cmd64x_pci_driver = { |
2d2744fc8
|
508 |
.name = DRV_NAME, |
669a5db41
|
509 510 |
.id_table = cmd64x, .probe = cmd64x_init_one, |
7f72a3791
|
511 |
.remove = ata_pci_remove_one, |
58eb8cd56
|
512 |
#ifdef CONFIG_PM_SLEEP |
7f72a3791
|
513 514 |
.suspend = ata_pci_device_suspend, .resume = cmd64x_reinit_one, |
438ac6d5e
|
515 |
#endif |
669a5db41
|
516 |
}; |
2fc75da0c
|
517 |
module_pci_driver(cmd64x_pci_driver); |
669a5db41
|
518 |
|
669a5db41
|
519 520 521 522 523 |
MODULE_AUTHOR("Alan Cox"); MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, cmd64x); MODULE_VERSION(DRV_VERSION); |