# SPDX-License-Identifier: GPL-2.0

  config ARM
  	bool
  	default y

  	select ARCH_CLOCKSOURCE_DATA

  	select ARCH_HAS_DEBUG_VIRTUAL

  	select ARCH_HAS_DEVMEM_IS_ALLOWED

  	select ARCH_HAS_ELF_RANDOMIZE

  	select ARCH_HAS_SET_MEMORY

  	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  	select ARCH_HAS_STRICT_MODULE_RWX if MMU

  	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST

  	select ARCH_HAVE_CUSTOM_GPIO_H

  	select ARCH_HAS_GCOV_PROFILE_ALL

  	select ARCH_MIGHT_HAVE_PC_PARPORT

  	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7

  	select ARCH_SUPPORTS_ATOMIC_RMW

  	select ARCH_USE_BUILTIN_BSWAP

  	select ARCH_USE_CMPXCHG_LOCKREF

  	select ARCH_WANT_IPC_PARSE_VERSION

  	select BUILDTIME_EXTABLE_SORT if MMU

  	select CLONE_BACKWARDS

  	select CPU_PM if (SUSPEND || CPU_IDLE)

  	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS

  	select DMA_NOOP_OPS if !MMU

  	select EDAC_SUPPORT
  	select EDAC_ATOMIC_SCRUB

  	select GENERIC_ALLOCATOR

  	select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY

  	select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)

  	select GENERIC_CLOCKEVENTS_BROADCAST if SMP

  	select GENERIC_CPU_AUTOPROBE

  	select GENERIC_EARLY_IOREMAP

  	select GENERIC_IDLE_POLL_SETUP

  	select GENERIC_IRQ_PROBE
  	select GENERIC_IRQ_SHOW

  	select GENERIC_IRQ_SHOW_LEVEL

  	select GENERIC_PCI_IOMAP

  	select GENERIC_SCHED_CLOCK

  	select GENERIC_SMP_IDLE_THREAD
  	select GENERIC_STRNCPY_FROM_USER
  	select GENERIC_STRNLEN_USER

  	select HANDLE_DOMAIN_IRQ

  	select HARDIRQS_SW_RESEND

  	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)

  	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6

  	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU

  	select HAVE_ARCH_MMAP_RND_BITS if MMU

  	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)

  	select HAVE_ARCH_TRACEHOOK

  	select HAVE_ARM_SMCCC if CPU_V7

  	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32

  	select HAVE_CC_STACKPROTECTOR

  	select HAVE_CONTEXT_TRACKING

  	select HAVE_C_RECORDMCOUNT
  	select HAVE_DEBUG_KMEMLEAK
  	select HAVE_DMA_API_DEBUG

  	select HAVE_DMA_CONTIGUOUS if MMU

  	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU

  	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE

  	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU

  	select HAVE_EXIT_THREAD

  	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)

  	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)

  	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)

  	select HAVE_GCC_PLUGINS

  	select HAVE_GENERIC_DMA_COHERENT

  	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  	select HAVE_IDE if PCI || ISA || PCMCIA

  	select HAVE_IRQ_TIME_ACCOUNTING

  	select HAVE_KERNEL_GZIP

  	select HAVE_KERNEL_LZ4

  	select HAVE_KERNEL_LZMA

  	select HAVE_KERNEL_LZO

  	select HAVE_KERNEL_XZ

  	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M

  	select HAVE_KRETPROBES if (HAVE_KPROBES)
  	select HAVE_MEMBLOCK

  	select HAVE_MOD_ARCH_SPECIFIC

  	select HAVE_NMI

  	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)

  	select HAVE_OPTPROBES if !THUMB2_KERNEL

  	select HAVE_PERF_EVENTS

  	select HAVE_PERF_REGS
  	select HAVE_PERF_USER_STACK_DUMP

  	select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)

  	select HAVE_REGS_AND_STACK_ACCESS_API

  	select HAVE_SYSCALL_TRACEPOINTS

  	select HAVE_UID16

  	select HAVE_VIRT_CPU_ACCOUNTING_GEN

  	select IRQ_FORCED_THREADING

  	select MODULES_USE_ELF_REL

  	select NO_BOOTMEM

  	select OF_EARLY_FLATTREE if OF
  	select OF_RESERVED_MEM if OF

  	select OLD_SIGACTION
  	select OLD_SIGSUSPEND3

  	select PERF_USE_VMALLOC
  	select RTC_LIB
  	select SYS_SUPPORTS_APM_EMULATION

  	# Above selects are sorted alphabetically; please add new ones
  	# according to that.  Thanks.

  	help
  	  The ARM series is a line of low-power-consumption RISC chip designs

  	  licensed by ARM Ltd and targeted at embedded applications and

  	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer

  	  manufactured, but legacy ARM-based PC hardware remains popular in

  	  Europe.  There is an ARM Linux project with a web page at
  	  <http://www.arm.linux.org.uk/>.

  config ARM_HAS_SG_CHAIN

  	select ARCH_HAS_SG_CHAIN

  	bool

  config NEED_SG_DMA_LENGTH
  	bool
  
  config ARM_DMA_USE_IOMMU

  	bool

  	select ARM_HAS_SG_CHAIN
  	select NEED_SG_DMA_LENGTH

  if ARM_DMA_USE_IOMMU
  
  config ARM_DMA_IOMMU_ALIGNMENT
  	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
  	range 4 9
  	default 8
  	help
  	  DMA mapping framework by default aligns all buffers to the smallest
  	  PAGE_SIZE order which is greater than or equal to the requested buffer
  	  size. This works well for buffers up to a few hundreds kilobytes, but
  	  for larger buffers it just a waste of address space. Drivers which has
  	  relatively small addressing window (like 64Mib) might run out of
  	  virtual space with just a few allocations.
  
  	  With this parameter you can specify the maximum PAGE_SIZE order for
  	  DMA IOMMU buffers. Larger buffers will be aligned only to this
  	  specified order. The order is expressed as a power of two multiplied
  	  by the PAGE_SIZE.
  
  endif

  config MIGHT_HAVE_PCI
  	bool

  config SYS_SUPPORTS_APM_EMULATION
  	bool

  config HAVE_TCM
  	bool
  	select GENERIC_ALLOCATOR

  config HAVE_PROC_CPU
  	bool

  config NO_IOPORT_MAP

  	bool

  config EISA
  	bool
  	---help---
  	  The Extended Industry Standard Architecture (EISA) bus was
  	  developed as an open alternative to the IBM MicroChannel bus.
  
  	  The EISA bus provided some of the features of the IBM MicroChannel
  	  bus while maintaining backward compatibility with cards made for
  	  the older ISA bus.  The EISA bus saw limited use between 1988 and
  	  1995 when it was made obsolete by the PCI bus.
  
  	  Say Y here if you are building a kernel for an EISA-based machine.
  
  	  Otherwise, say N.
  
  config SBUS
  	bool

  config STACKTRACE_SUPPORT
  	bool
  	default y
  
  config LOCKDEP_SUPPORT
  	bool
  	default y

  config TRACE_IRQFLAGS_SUPPORT
  	bool

  	default !CPU_V7M

  config RWSEM_XCHGADD_ALGORITHM
  	bool

  	default y

  config ARCH_HAS_ILOG2_U32
  	bool

  
  config ARCH_HAS_ILOG2_U64
  	bool

  config ARCH_HAS_BANDGAP
  	bool

  config FIX_EARLYCON_MEM
  	def_bool y if MMU

  config GENERIC_HWEIGHT
  	bool
  	default y

  config GENERIC_CALIBRATE_DELAY
  	bool
  	default y

  config ARCH_MAY_HAVE_PC_FDC
  	bool

  config ZONE_DMA
  	bool

  config NEED_DMA_MAP_STATE
         def_bool y

  config ARCH_SUPPORTS_UPROBES
  	def_bool y

  config ARCH_HAS_DMA_SET_COHERENT_MASK
  	bool

  config GENERIC_ISA_DMA
  	bool

  config FIQ
  	bool

  config NEED_RET_TO_USER
  	bool

  config ARCH_MTD_XIP
  	bool

  config VECTORS_BASE
  	hex

  	default 0xffff0000 if MMU || CPU_HIGH_VECTOR

  	default DRAM_BASE if REMAP_VECTORS_TO_RAM
  	default 0x00000000
  	help

  	  The base address of exception vectors.  This must be two pages
  	  in size.

  config ARM_PATCH_PHYS_VIRT

  	bool "Patch physical to virtual translations at runtime" if EMBEDDED
  	default y

  	depends on !XIP_KERNEL && MMU

  	help

  	  Patch phys-to-virt and virt-to-phys translation functions at
  	  boot and module load time according to the position of the
  	  kernel in system memory.

  	  This can only be used with non-XIP MMU kernels where the base

  	  of physical memory is at a 16MB boundary.

  	  Only disable this option if you know that you do not require
  	  this feature (eg, building a kernel for a single machine) and
  	  you need to shrink the kernel to the minimal size.

  config NEED_MACH_IO_H
  	bool
  	help
  	  Select this when mach/io.h is required to provide special
  	  definitions for this platform.  The need for mach/io.h should
  	  be avoided when possible.

  config NEED_MACH_MEMORY_H

  	bool
  	help

  	  Select this when mach/memory.h is required to provide special
  	  definitions for this platform.  The need for mach/memory.h should
  	  be avoided when possible.

  config PHYS_OFFSET

  	hex "Physical address of main memory" if MMU

  	depends on !ARM_PATCH_PHYS_VIRT

  	default DRAM_BASE if !MMU

  	default 0x00000000 if ARCH_EBSA110 || \

  			ARCH_FOOTBRIDGE || \
  			ARCH_INTEGRATOR || \
  			ARCH_IOP13XX || \
  			ARCH_KS8695 || \

  			ARCH_REALVIEW

  	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
  	default 0x20000000 if ARCH_S5PV210

  	default 0xc0000000 if ARCH_SA1100

  	help

  	  Please provide the physical address corresponding to the
  	  location of main memory in your system.

  config GENERIC_BUG
  	def_bool y
  	depends on BUG

  config PGTABLE_LEVELS
  	int
  	default 3 if ARM_LPAE
  	default 2

  source "init/Kconfig"

  source "kernel/Kconfig.freezer"

  menu "System Type"

  config MMU
  	bool "MMU-based Paged Memory Management Support"
  	default y
  	help
  	  Select if you want MMU-based virtualised addressing space
  	  support by paged memory management. If unsure, say 'Y'.

  config ARCH_MMAP_RND_BITS_MIN
  	default 8
  
  config ARCH_MMAP_RND_BITS_MAX
  	default 14 if PAGE_OFFSET=0x40000000
  	default 15 if PAGE_OFFSET=0x80000000
  	default 16

  #
  # The "ARM system type" choice list is ordered alphabetically by option
  # text.  Please add new entries in the option alphabetic order.
  #

  choice
  	prompt "ARM system type"

  	default ARM_SINGLE_ARMV7M if !MMU

  	default ARCH_MULTIPLATFORM if MMU

  config ARCH_MULTIPLATFORM
  	bool "Allow multiple platforms to be selected"

  	depends on MMU

  	select ARM_HAS_SG_CHAIN

  	select ARM_PATCH_PHYS_VIRT
  	select AUTO_ZRELADDR

  	select TIMER_OF

  	select COMMON_CLK

  	select GENERIC_CLOCKEVENTS

  	select MIGHT_HAVE_PCI

  	select MULTI_IRQ_HANDLER

  	select PCI_DOMAINS if PCI

  	select SPARSE_IRQ
  	select USE_OF

  config ARM_SINGLE_ARMV7M
  	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
  	depends on !MMU

  	select ARM_NVIC

  	select AUTO_ZRELADDR

  	select TIMER_OF

  	select COMMON_CLK
  	select CPU_V7M
  	select GENERIC_CLOCKEVENTS
  	select NO_IOPORT_MAP
  	select SPARSE_IRQ
  	select USE_OF

  config ARCH_EBSA110
  	bool "EBSA-110"

  	select ARCH_USES_GETTIMEOFFSET

  	select CPU_SA110

  	select ISA

  	select NEED_MACH_IO_H

  	select NEED_MACH_MEMORY_H

  	select NO_IOPORT_MAP

  	help
  	  This is an evaluation board for the StrongARM processor available

  	  from Digital. It has limited hardware on-board, including an

  	  Ethernet interface, two PCMCIA sockets, two serial ports and a
  	  parallel port.

  config ARCH_EP93XX
  	bool "EP93xx-based"

  	select ARCH_HAS_HOLES_MEMORYMODEL

  	select ARM_AMBA

  	imply ARM_PATCH_PHYS_VIRT

  	select ARM_VIC

  	select AUTO_ZRELADDR

  	select CLKDEV_LOOKUP

  	select CLKSRC_MMIO

  	select CPU_ARM920T

  	select GENERIC_CLOCKEVENTS

  	select GPIOLIB

  	help
  	  This enables support for the Cirrus EP93xx series of CPUs.

  config ARCH_FOOTBRIDGE
  	bool "FootBridge"

  	select CPU_SA110

  	select FOOTBRIDGE

  	select GENERIC_CLOCKEVENTS

  	select HAVE_IDE

  	select NEED_MACH_IO_H if !MMU

  	select NEED_MACH_MEMORY_H

  	help
  	  Support for systems based on the DC21285 companion chip
  	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.

  config ARCH_NETX
  	bool "Hilscher NetX based"

  	select ARM_VIC

  	select CLKSRC_MMIO

  	select CPU_ARM926T

  	select GENERIC_CLOCKEVENTS

  	help

  	  This enables support for systems based on the Hilscher NetX Soc

  config ARCH_IOP13XX
  	bool "IOP13xx-based"
  	depends on MMU

  	select CPU_XSC3

  	select NEED_MACH_MEMORY_H

  	select NEED_RET_TO_USER

  	select PCI
  	select PLAT_IOP
  	select VMSPLIT_1G

  	select SPARSE_IRQ

  	help
  	  Support for Intel's IOP13XX (XScale) family of processors.

  config ARCH_IOP32X
  	bool "IOP32x-based"

  	depends on MMU

  	select CPU_XSCALE

  	select GPIO_IOP

  	select GPIOLIB

  	select NEED_RET_TO_USER

  	select PCI

  	select PLAT_IOP

  	help

  	  Support for Intel's 80219 and IOP32X (XScale) family of
  	  processors.
  
  config ARCH_IOP33X
  	bool "IOP33x-based"
  	depends on MMU

  	select CPU_XSCALE

  	select GPIO_IOP

  	select GPIOLIB

  	select NEED_RET_TO_USER

  	select PCI

  	select PLAT_IOP

  	help
  	  Support for Intel's IOP33X (XScale) family of processors.

  config ARCH_IXP4XX
  	bool "IXP4xx-based"

  	depends on MMU

  	select ARCH_HAS_DMA_SET_COHERENT_MASK

  	select ARCH_SUPPORTS_BIG_ENDIAN

  	select CLKSRC_MMIO

  	select CPU_XSCALE

  	select DMABOUNCE if PCI

  	select GENERIC_CLOCKEVENTS

  	select GPIOLIB

  	select MIGHT_HAVE_PCI

  	select NEED_MACH_IO_H

  	select USB_EHCI_BIG_ENDIAN_DESC

  	select USB_EHCI_BIG_ENDIAN_MMIO

  	help

  	  Support for Intel's IXP4XX (XScale) family of processors.

  config ARCH_DOVE
  	bool "Marvell Dove"

  	select CPU_PJ4

  	select GENERIC_CLOCKEVENTS

  	select GPIOLIB

  	select MIGHT_HAVE_PCI

  	select MULTI_IRQ_HANDLER

  	select MVEBU_MBUS

  	select PINCTRL
  	select PINCTRL_DOVE

  	select PLAT_ORION_LEGACY

  	select SPARSE_IRQ

  	select PM_GENERIC_DOMAINS if PM

  	help

  	  Support for the Marvell Dove SoC 88AP510

  
  config ARCH_KS8695
  	bool "Micrel/Kendin KS8695"

  	select CLKSRC_MMIO

  	select CPU_ARM922T

  	select GENERIC_CLOCKEVENTS

  	select GPIOLIB

  	select NEED_MACH_MEMORY_H

  	help
  	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
  	  System-on-Chip devices.

  config ARCH_W90X900
  	bool "Nuvoton W90X900 CPU"

  	select CLKDEV_LOOKUP

  	select CLKSRC_MMIO

  	select CPU_ARM926T

  	select GENERIC_CLOCKEVENTS

  	select GPIOLIB

  	help

  	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
  	  At present, the w90x900 has been renamed nuc900, regarding
  	  the ARM series product line, you can login the following
  	  link address to know more.
  
  	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
  		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>

  config ARCH_LPC32XX
  	bool "NXP LPC32XX"

  	select ARM_AMBA
  	select CLKDEV_LOOKUP

  	select CLKSRC_LPC32XX
  	select COMMON_CLK

  	select CPU_ARM926T
  	select GENERIC_CLOCKEVENTS

  	select GPIOLIB

  	select MULTI_IRQ_HANDLER
  	select SPARSE_IRQ

  	select USE_OF
  	help
  	  Support for the NXP LPC32XX family of processors

  config ARCH_PXA

  	bool "PXA2xx/PXA3xx-based"

  	depends on MMU

  	select ARCH_MTD_XIP

  	select ARM_CPU_SUSPEND if PM
  	select AUTO_ZRELADDR

  	select COMMON_CLK

  	select CLKDEV_LOOKUP

  	select CLKSRC_PXA

  	select CLKSRC_MMIO

  	select TIMER_OF

  	select CPU_XSCALE if !CPU_XSC3

  	select GENERIC_CLOCKEVENTS

  	select GPIO_PXA

  	select GPIOLIB

  	select HAVE_IDE

  	select IRQ_DOMAIN

  	select MULTI_IRQ_HANDLER

  	select PLAT_PXA
  	select SPARSE_IRQ

  	help

  	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.

  
  config ARCH_RPC
  	bool "RiscPC"

  	depends on MMU

  	select ARCH_ACORN

  	select ARCH_MAY_HAVE_PC_FDC

  	select ARCH_SPARSEMEM_ENABLE

  	select ARCH_USES_GETTIMEOFFSET

  	select CPU_SA110

  	select FIQ

  	select HAVE_IDE

  	select HAVE_PATA_PLATFORM
  	select ISA_DMA_API

  	select NEED_MACH_IO_H

  	select NEED_MACH_MEMORY_H

  	select NO_IOPORT_MAP

  	help
  	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
  	  CD-ROM interface, serial and parallel port, and the floppy drive.
  
  config ARCH_SA1100
  	bool "SA1100-based"

  	select ARCH_MTD_XIP

  	select ARCH_SPARSEMEM_ENABLE
  	select CLKDEV_LOOKUP
  	select CLKSRC_MMIO

  	select CLKSRC_PXA

  	select TIMER_OF if OF

  	select CPU_FREQ

  	select CPU_SA1100

  	select GENERIC_CLOCKEVENTS

  	select GPIOLIB

  	select HAVE_IDE

  	select IRQ_DOMAIN

  	select ISA

  	select MULTI_IRQ_HANDLER

  	select NEED_MACH_MEMORY_H

  	select SPARSE_IRQ

  	help
  	  Support for StrongARM 11x0 based boards.

  config ARCH_S3C24XX
  	bool "Samsung S3C24XX SoCs"

  	select ATAGS

  	select CLKDEV_LOOKUP

  	select CLKSRC_SAMSUNG_PWM

  	select GENERIC_CLOCKEVENTS

  	select GPIO_SAMSUNG

  	select GPIOLIB

  	select HAVE_S3C2410_I2C if I2C

  	select HAVE_S3C2410_WATCHDOG if WATCHDOG

  	select HAVE_S3C_RTC if RTC_CLASS

  	select MULTI_IRQ_HANDLER

  	select NEED_MACH_IO_H

  	select SAMSUNG_ATAGS

  	help

  	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
  	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
  	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
  	  Samsung SMDK2410 development board (and derivatives).

  config ARCH_DAVINCI
  	bool "TI DaVinci"

  	select ARCH_HAS_HOLES_MEMORYMODEL

  	select CLKDEV_LOOKUP

  	select CPU_ARM926T

  	select GENERIC_ALLOCATOR

  	select GENERIC_CLOCKEVENTS

  	select GENERIC_IRQ_CHIP

  	select GPIOLIB

  	select HAVE_IDE

  	select USE_OF

  	select ZONE_DMA

  	help
  	  Support for TI's DaVinci platform.

  config ARCH_OMAP1
  	bool "TI OMAP1"

  	depends on MMU

  	select ARCH_HAS_HOLES_MEMORYMODEL

  	select ARCH_OMAP

  	select CLKDEV_LOOKUP

  	select CLKSRC_MMIO

  	select GENERIC_CLOCKEVENTS

  	select GENERIC_IRQ_CHIP

  	select GPIOLIB

  	select HAVE_IDE
  	select IRQ_DOMAIN

  	select MULTI_IRQ_HANDLER

  	select NEED_MACH_IO_H if PCCARD
  	select NEED_MACH_MEMORY_H

  	select SPARSE_IRQ

  	help

  	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)

  endchoice

  menu "Multiple platform selection"
  	depends on ARCH_MULTIPLATFORM
  
  comment "CPU Core family selection"

  config ARCH_MULTI_V4
  	bool "ARMv4 based platforms (FA526)"
  	depends on !ARCH_MULTI_V6_V7
  	select ARCH_MULTI_V4_V5
  	select CPU_FA526

  config ARCH_MULTI_V4T
  	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"

  	depends on !ARCH_MULTI_V6_V7

  	select ARCH_MULTI_V4_V5

  	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
  		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
  		CPU_ARM925T || CPU_ARM940T)

  
  config ARCH_MULTI_V5
  	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"

  	depends on !ARCH_MULTI_V6_V7

  	select ARCH_MULTI_V4_V5

  	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \

  		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
  		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)

  
  config ARCH_MULTI_V4_V5
  	bool
  
  config ARCH_MULTI_V6

  	bool "ARMv6 based platforms (ARM11)"

  	select ARCH_MULTI_V6_V7

  	select CPU_V6K

  
  config ARCH_MULTI_V7

  	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"

  	default y
  	select ARCH_MULTI_V6_V7

  	select CPU_V7

  	select HAVE_SMP

  
  config ARCH_MULTI_V6_V7
  	bool

  	select MIGHT_HAVE_CACHE_L2X0

  
  config ARCH_MULTI_CPU_AUTO
  	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
  	select ARCH_MULTI_V5
  
  endmenu

  config ARCH_VIRT

  	bool "Dummy Virtual Machine"
  	depends on ARCH_MULTI_V7

  	select ARM_AMBA

  	select ARM_GIC

  	select ARM_GIC_V2M if PCI

  	select ARM_GIC_V3

  	select ARM_GIC_V3_ITS if PCI

  	select ARM_PSCI

  	select HAVE_ARM_ARCH_TIMER

  #
  # This is sorted alphabetically by mach-* pathname.  However, plat-*
  # Kconfigs may be included either alphabetically (according to the
  # plat- suffix) or along side the corresponding mach-* source.
  #

  source "arch/arm/mach-mvebu/Kconfig"

  source "arch/arm/mach-actions/Kconfig"

  source "arch/arm/mach-alpine/Kconfig"

  source "arch/arm/mach-artpec/Kconfig"

  source "arch/arm/mach-asm9260/Kconfig"

  source "arch/arm/mach-at91/Kconfig"

  source "arch/arm/mach-axxia/Kconfig"

  source "arch/arm/mach-bcm/Kconfig"

  source "arch/arm/mach-berlin/Kconfig"

  source "arch/arm/mach-clps711x/Kconfig"

  source "arch/arm/mach-cns3xxx/Kconfig"

  source "arch/arm/mach-davinci/Kconfig"

  source "arch/arm/mach-digicolor/Kconfig"

  source "arch/arm/mach-dove/Kconfig"

  source "arch/arm/mach-ep93xx/Kconfig"

  source "arch/arm/mach-footbridge/Kconfig"

  source "arch/arm/mach-gemini/Kconfig"

  source "arch/arm/mach-highbank/Kconfig"

  source "arch/arm/mach-hisi/Kconfig"

  source "arch/arm/mach-integrator/Kconfig"

  source "arch/arm/mach-iop32x/Kconfig"
  
  source "arch/arm/mach-iop33x/Kconfig"

  source "arch/arm/mach-iop13xx/Kconfig"

  source "arch/arm/mach-ixp4xx/Kconfig"

  source "arch/arm/mach-keystone/Kconfig"

  source "arch/arm/mach-ks8695/Kconfig"

  source "arch/arm/mach-meson/Kconfig"

  source "arch/arm/mach-moxart/Kconfig"

  source "arch/arm/mach-aspeed/Kconfig"

  source "arch/arm/mach-mv78xx0/Kconfig"

  source "arch/arm/mach-imx/Kconfig"

  source "arch/arm/mach-mediatek/Kconfig"

  source "arch/arm/mach-mxs/Kconfig"

  source "arch/arm/mach-netx/Kconfig"

  source "arch/arm/mach-nomadik/Kconfig"

  source "arch/arm/mach-nspire/Kconfig"

  source "arch/arm/plat-omap/Kconfig"
  
  source "arch/arm/mach-omap1/Kconfig"

  source "arch/arm/mach-omap2/Kconfig"

  source "arch/arm/mach-orion5x/Kconfig"

  source "arch/arm/mach-picoxcell/Kconfig"

  source "arch/arm/mach-pxa/Kconfig"
  source "arch/arm/plat-pxa/Kconfig"

  source "arch/arm/mach-mmp/Kconfig"

  source "arch/arm/mach-oxnas/Kconfig"

  source "arch/arm/mach-qcom/Kconfig"

  source "arch/arm/mach-realview/Kconfig"

  source "arch/arm/mach-rockchip/Kconfig"

  source "arch/arm/mach-sa1100/Kconfig"

  source "arch/arm/mach-socfpga/Kconfig"

  source "arch/arm/mach-spear/Kconfig"

  source "arch/arm/mach-sti/Kconfig"

  source "arch/arm/mach-stm32/Kconfig"

  source "arch/arm/mach-s3c24xx/Kconfig"

  source "arch/arm/mach-s3c64xx/Kconfig"

  source "arch/arm/mach-s5pv210/Kconfig"

  source "arch/arm/mach-exynos/Kconfig"

  source "arch/arm/plat-samsung/Kconfig"

  source "arch/arm/mach-shmobile/Kconfig"

  source "arch/arm/mach-sunxi/Kconfig"

  source "arch/arm/mach-prima2/Kconfig"

  source "arch/arm/mach-tango/Kconfig"

  source "arch/arm/mach-tegra/Kconfig"

  source "arch/arm/mach-u300/Kconfig"

  source "arch/arm/mach-uniphier/Kconfig"

  source "arch/arm/mach-ux500/Kconfig"

  
  source "arch/arm/mach-versatile/Kconfig"

  source "arch/arm/mach-vexpress/Kconfig"

  source "arch/arm/plat-versatile/Kconfig"

  source "arch/arm/mach-vt8500/Kconfig"

  source "arch/arm/mach-w90x900/Kconfig"

  source "arch/arm/mach-zx/Kconfig"

  source "arch/arm/mach-zynq/Kconfig"

  # ARMv7-M architecture
  config ARCH_EFM32
  	bool "Energy Micro efm32"
  	depends on ARM_SINGLE_ARMV7M

  	select GPIOLIB

  	help
  	  Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
  	  processors.
  
  config ARCH_LPC18XX
  	bool "NXP LPC18xx/LPC43xx"
  	depends on ARM_SINGLE_ARMV7M
  	select ARCH_HAS_RESET_CONTROLLER
  	select ARM_AMBA
  	select CLKSRC_LPC32XX
  	select PINCTRL
  	help
  	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
  	  high performance microcontrollers.

  config ARCH_MPS2

  	bool "ARM MPS2 platform"

  	depends on ARM_SINGLE_ARMV7M
  	select ARM_AMBA
  	select CLKSRC_MPS2
  	help
  	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
  	  with a range of available cores like Cortex-M3/M4/M7.
  
  	  Please, note that depends which Application Note is used memory map
  	  for the platform may vary, so adjustment of RAM base might be needed.

  # Definitions to make life easier
  config ARCH_ACORN
  	bool

  config PLAT_IOP
  	bool

  	select GENERIC_CLOCKEVENTS

  config PLAT_ORION
  	bool

  	select CLKSRC_MMIO

  	select COMMON_CLK

  	select GENERIC_IRQ_CHIP

  	select IRQ_DOMAIN

  config PLAT_ORION_LEGACY
  	bool
  	select PLAT_ORION

  config PLAT_PXA
  	bool

  config PLAT_VERSATILE
  	bool

  source "arch/arm/firmware/Kconfig"

  source arch/arm/mm/Kconfig

  config IWMMXT

  	bool "Enable iWMMXt support"
  	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
  	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B

  	help
  	  Enable support for iWMMXt context switching at run time if
  	  running on a CPU that supports it.

  config MULTI_IRQ_HANDLER
  	bool
  	help
  	  Allow each machine to specify it's own IRQ handler at run time.

  if !MMU
  source "arch/arm/Kconfig-nommu"
  endif

  config PJ4B_ERRATA_4742
  	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
  	depends on CPU_PJ4B && MACH_ARMADA_370
  	default y
  	help
  	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
  	  Event (WFE) IDLE states, a specific timing sensitivity exists between
  	  the retiring WFI/WFE instructions and the newly issued subsequent
  	  instructions.  This sensitivity can result in a CPU hang scenario.
  	  Workaround:
  	  The software must insert either a Data Synchronization Barrier (DSB)
  	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
  	  instruction

  config ARM_ERRATA_326103
  	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
  	depends on CPU_V6
  	help
  	  Executing a SWP instruction to read-only memory does not set bit 11
  	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
  	  treat the access as a read, preventing a COW from occurring and
  	  causing the faulting task to livelock.

  config ARM_ERRATA_411920
  	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"

  	depends on CPU_V6 || CPU_V6K

  	help
  	  Invalidation of the Instruction Cache operation can
  	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
  	  It does not affect the MPCore. This option enables the ARM Ltd.
  	  recommended workaround.

  config ARM_ERRATA_430973
  	bool "ARM errata: Stale prediction on replaced interworking branch"
  	depends on CPU_V7
  	help
  	  This option enables the workaround for the 430973 Cortex-A8

  	  r1p* erratum. If a code sequence containing an ARM/Thumb

  	  interworking branch is replaced with another code sequence at the
  	  same virtual address, whether due to self-modifying code or virtual
  	  to physical address re-mapping, Cortex-A8 does not recover from the
  	  stale interworking branch prediction. This results in Cortex-A8
  	  executing the new code sequence in the incorrect ARM or Thumb state.
  	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
  	  and also flushes the branch target cache at every context switch.
  	  Note that setting specific bits in the ACTLR register may not be
  	  available in non-secure mode.

  config ARM_ERRATA_458693
  	bool "ARM errata: Processor deadlock when a false hazard is created"
  	depends on CPU_V7

  	depends on !ARCH_MULTIPLATFORM

  	help
  	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
  	  erratum. For very specific sequences of memory operations, it is
  	  possible for a hazard condition intended for a cache line to instead
  	  be incorrectly associated with a different cache line. This false
  	  hazard might then cause a processor deadlock. The workaround enables
  	  the L1 caching of the NEON accesses and disables the PLD instruction
  	  in the ACTLR register. Note that setting specific bits in the ACTLR
  	  register may not be available in non-secure mode.

  config ARM_ERRATA_460075
  	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
  	depends on CPU_V7

  	depends on !ARCH_MULTIPLATFORM

  	help
  	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
  	  erratum. Any asynchronous access to the L2 cache may encounter a
  	  situation in which recent store transactions to the L2 cache are lost
  	  and overwritten with stale memory contents from external memory. The
  	  workaround disables the write-allocate mode for the L2 cache via the
  	  ACTLR register. Note that setting specific bits in the ACTLR register
  	  may not be available in non-secure mode.

  config ARM_ERRATA_742230
  	bool "ARM errata: DMB operation may be faulty"
  	depends on CPU_V7 && SMP

  	depends on !ARCH_MULTIPLATFORM

  	help
  	  This option enables the workaround for the 742230 Cortex-A9
  	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
  	  between two write operations may not ensure the correct visibility
  	  ordering of the two writes. This workaround sets a specific bit in
  	  the diagnostic register of the Cortex-A9 which causes the DMB
  	  instruction to behave as a DSB, ensuring the correct behaviour of
  	  the two writes.

  config ARM_ERRATA_742231
  	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
  	depends on CPU_V7 && SMP

  	depends on !ARCH_MULTIPLATFORM

  	help
  	  This option enables the workaround for the 742231 Cortex-A9
  	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
  	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
  	  accessing some data located in the same cache line, may get corrupted
  	  data due to bad handling of the address hazard when the line gets
  	  replaced from one of the CPUs at the same time as another CPU is
  	  accessing it. This workaround sets specific bits in the diagnostic
  	  register of the Cortex-A9 which reduces the linefill issuing
  	  capabilities of the processor.

  config ARM_ERRATA_643719
  	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
  	depends on CPU_V7 && SMP

  	default y

  	help
  	  This option enables the workaround for the 643719 Cortex-A9 (prior to
  	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
  	  register returns zero when it should return one. The workaround
  	  corrects this value, ensuring cache maintenance operations which use
  	  it behave as intended and avoiding data corruption.

  config ARM_ERRATA_720789
  	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"

  	depends on CPU_V7

  	help
  	  This option enables the workaround for the 720789 Cortex-A9 (prior to
  	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
  	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
  	  As a consequence of this erratum, some TLB entries which should be
  	  invalidated are not, resulting in an incoherency in the system page
  	  tables. The workaround changes the TLB flushing routines to invalidate
  	  entries regardless of the ASID.

  
  config ARM_ERRATA_743622
  	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
  	depends on CPU_V7

  	depends on !ARCH_MULTIPLATFORM

  	help
  	  This option enables the workaround for the 743622 Cortex-A9

  	  (r2p*) erratum. Under very rare conditions, a faulty

  	  optimisation in the Cortex-A9 Store Buffer may lead to data
  	  corruption. This workaround sets a specific bit in the diagnostic
  	  register of the Cortex-A9 which disables the Store Buffer
  	  optimisation, preventing the defect from occurring. This has no
  	  visible impact on the overall performance or power consumption of the
  	  processor.

  config ARM_ERRATA_751472
  	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"

  	depends on CPU_V7

  	depends on !ARCH_MULTIPLATFORM

  	help
  	  This option enables the workaround for the 751472 Cortex-A9 (prior
  	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
  	  completion of a following broadcasted operation if the second
  	  operation is received by a CPU before the ICIALLUIS has completed,
  	  potentially leading to corrupted entries in the cache or TLB.

  config ARM_ERRATA_754322
  	bool "ARM errata: possible faulty MMU translations following an ASID switch"
  	depends on CPU_V7
  	help
  	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
  	  r3p*) erratum. A speculative memory access may cause a page table walk
  	  which starts prior to an ASID switch but completes afterwards. This
  	  can populate the micro-TLB with a stale entry which may be hit with
  	  the new ASID. This workaround places two dsb instructions in the mm
  	  switching code so that no page table walks can cross the ASID switch.

  config ARM_ERRATA_754327
  	bool "ARM errata: no automatic Store Buffer drain"
  	depends on CPU_V7 && SMP
  	help
  	  This option enables the workaround for the 754327 Cortex-A9 (prior to
  	  r2p0) erratum. The Store Buffer does not have any automatic draining
  	  mechanism and therefore a livelock may occur if an external agent
  	  continuously polls a memory location waiting to observe an update.
  	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
  	  written polling loops from denying visibility of updates to memory.

  config ARM_ERRATA_364296
  	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"

  	depends on CPU_V6

  	help
  	  This options enables the workaround for the 364296 ARM1136
  	  r0p2 erratum (possible cache data corruption with
  	  hit-under-miss enabled). It sets the undocumented bit 31 in
  	  the auxiliary control register and the FI bit in the control
  	  register, thus disabling hit-under-miss without putting the
  	  processor into full low interrupt latency mode. ARM11MPCore
  	  is not affected.

  config ARM_ERRATA_764369
  	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
  	depends on CPU_V7 && SMP
  	help
  	  This option enables the workaround for erratum 764369
  	  affecting Cortex-A9 MPCore with two or more processors (all
  	  current revisions). Under certain timing circumstances, a data
  	  cache line maintenance operation by MVA targeting an Inner
  	  Shareable memory region may fail to proceed up to either the
  	  Point of Coherency or to the Point of Unification of the
  	  system. This workaround adds a DSB instruction before the
  	  relevant cache maintenance functions and sets a specific bit
  	  in the diagnostic control register of the SCU.

  config ARM_ERRATA_775420
         bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
         depends on CPU_V7
         help
  	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
  	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
  	 operation aborts with MMU exception, it might cause the processor
  	 to deadlock. This workaround puts DSB before executing ISB if
  	 an abort may occur on cache maintenance.

  config ARM_ERRATA_798181
  	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
  	depends on CPU_V7 && SMP
  	help
  	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
  	  adequately shooting down all use of the old entries. This
  	  option enables the Linux kernel workaround for this erratum
  	  which sends an IPI to the CPUs that are running the same ASID
  	  as the one being invalidated.

  config ARM_ERRATA_773022
  	bool "ARM errata: incorrect instructions may be executed from loop buffer"
  	depends on CPU_V7
  	help
  	  This option enables the workaround for the 773022 Cortex-A15
  	  (up to r0p4) erratum. In certain rare sequences of code, the
  	  loop buffer may deliver incorrect instructions. This
  	  workaround disables the loop buffer to avoid the erratum.

  config ARM_ERRATA_818325_852422
  	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
  	depends on CPU_V7
  	help
  	  This option enables the workaround for:
  	  - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
  	    instruction might deadlock.  Fixed in r0p1.
  	  - Cortex-A12 852422: Execution of a sequence of instructions might
  	    lead to either a data corruption or a CPU deadlock.  Not fixed in
  	    any Cortex-A12 cores yet.
  	  This workaround for all both errata involves setting bit[12] of the
  	  Feature Register. This bit disables an optimisation applied to a
  	  sequence of 2 instructions that use opposing condition codes.

  config ARM_ERRATA_821420
  	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
  	depends on CPU_V7
  	help
  	  This option enables the workaround for the 821420 Cortex-A12
  	  (all revs) erratum. In very rare timing conditions, a sequence
  	  of VMOV to Core registers instructions, for which the second
  	  one is in the shadow of a branch or abort, can lead to a
  	  deadlock when the VMOV instructions are issued out-of-order.

  config ARM_ERRATA_825619
  	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
  	depends on CPU_V7
  	help
  	  This option enables the workaround for the 825619 Cortex-A12
  	  (all revs) erratum. Within rare timing constraints, executing a
  	  DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
  	  and Device/Strongly-Ordered loads and stores might cause deadlock

  config ARM_ERRATA_814220
  	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
  	depends on CPU_V7
  	help
  	  The v7 ARM states that all cache and branch predictor maintenance operations
  	  that do not specify an address execute, relative to each other, in program order.
  	  However, because of this erratum, an L2 set/way cache maintenance operation can
  	  overtake an L1 set/way cache maintenance operation. This ERRATA only affected the
  	  Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.

  config ARM_ERRATA_852421
  	bool "ARM errata: A17: DMB ST might fail to create order between stores"
  	depends on CPU_V7
  	help
  	  This option enables the workaround for the 852421 Cortex-A17
  	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
  	  execution of a DMB ST instruction might fail to properly order
  	  stores from GroupA and stores from GroupB.

  config ARM_ERRATA_852423
  	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
  	depends on CPU_V7
  	help
  	  This option enables the workaround for:
  	  - Cortex-A17 852423: Execution of a sequence of instructions might
  	    lead to either a data corruption or a CPU deadlock.  Not fixed in
  	    any Cortex-A17 cores yet.
  	  This is identical to Cortex-A12 erratum 852422.  It is a separate
  	  config option from the A12 erratum due to the way errata are checked
  	  for and handled.

  endmenu
  
  source "arch/arm/common/Kconfig"

  menu "Bus support"

  config ISA
  	bool

  	help
  	  Find out whether you have ISA slots on your motherboard.  ISA is the
  	  name of a bus system, i.e. the way the CPU talks to the other stuff
  	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
  	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
  	  newer boards don't support it.  If you have ISA, say Y, otherwise N.

  # Select ISA DMA controller support

  config ISA_DMA
  	bool

  	select ISA_DMA_API

  # Select ISA DMA interface

  config ISA_DMA_API
  	bool

  config PCI

  	bool "PCI support" if MIGHT_HAVE_PCI

  	help
  	  Find out whether you have a PCI motherboard. PCI is the name of a
  	  bus system, i.e. the way the CPU talks to the other stuff inside
  	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
  	  VESA. If you have PCI, say Y, otherwise N.

  config PCI_DOMAINS
  	bool
  	depends on PCI

  config PCI_DOMAINS_GENERIC
  	def_bool PCI_DOMAINS

  config PCI_NANOENGINE
  	bool "BSE nanoEngine PCI support"
  	depends on SA1100_NANOENGINE
  	help
  	  Enable PCI on the BSE nanoEngine board.

  config PCI_SYSCALL
  	def_bool PCI

  config PCI_HOST_ITE8152
  	bool
  	depends on PCI && MACH_ARMCORE
  	default y
  	select DMABOUNCE

  source "drivers/pci/Kconfig"
  
  source "drivers/pcmcia/Kconfig"
  
  endmenu
  
  menu "Kernel Features"

  config HAVE_SMP
  	bool
  	help
  	  This option should be selected by machines which have an SMP-
  	  capable CPU.
  
  	  The only effect of this option is to make the SMP-related
  	  options available to the user for configuration.

  config SMP

  	bool "Symmetric Multi-Processing"

  	depends on CPU_V6K || CPU_V7

  	depends on GENERIC_CLOCKEVENTS

  	depends on HAVE_SMP

  	depends on MMU || ARM_MPU

  	select IRQ_WORK

  	help
  	  This enables support for systems with more than one CPU. If you have

  	  a system with only one CPU, say N. If you have a system with more
  	  than one CPU, say Y.

  	  If you say N here, the kernel will run on uni- and multiprocessor

  	  machines, but will use only one CPU of a multiprocessor machine. If

  	  you say Y here, the kernel will run on many, but not all,
  	  uniprocessor machines. On a uniprocessor machine, the kernel
  	  will run faster if you say N here.

  	  See also <file:Documentation/x86/i386/IO-APIC.txt>,

  	  <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at

  	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.

  
  	  If you don't know what to do here, say N.

  config SMP_ON_UP

  	bool "Allow booting SMP kernel on uniprocessor systems"

  	depends on SMP && !XIP_KERNEL && MMU

  	default y
  	help
  	  SMP kernels contain instructions which fail on non-SMP processors.
  	  Enabling this option allows the kernel to modify itself to make
  	  these instructions safe.  Disabling it allows about 1K of space
  	  savings.
  
  	  If you don't know what to do here, say Y.

  config ARM_CPU_TOPOLOGY
  	bool "Support cpu topology definition"
  	depends on SMP && CPU_V7
  	default y
  	help
  	  Support ARM cpu topology definition. The MPIDR register defines
  	  affinity between processors which is then used to describe the cpu
  	  topology of an ARM System.
  
  config SCHED_MC
  	bool "Multi-core scheduler support"
  	depends on ARM_CPU_TOPOLOGY
  	help
  	  Multi-core scheduler support improves the CPU scheduler's decision
  	  making when dealing with multi-core CPU chips at a cost of slightly
  	  increased overhead in some places. If unsure say N here.
  
  config SCHED_SMT
  	bool "SMT scheduler support"
  	depends on ARM_CPU_TOPOLOGY
  	help
  	  Improves the CPU scheduler's decision making when dealing with
  	  MultiThreading at a cost of slightly increased overhead in some
  	  places. If unsure say N here.

  config HAVE_ARM_SCU
  	bool

  	help
  	  This option enables support for the ARM system coherency unit

  config HAVE_ARM_ARCH_TIMER

  	bool "Architected timer support"
  	depends on CPU_V7

  	select ARM_ARCH_TIMER

  	select GENERIC_CLOCKEVENTS

  	help
  	  This option enables support for the ARM architected timer

  config HAVE_ARM_TWD
  	bool

  	select TIMER_OF if OF

  	help
  	  This options enables support for the ARM timer and watchdog unit

  config MCPM
  	bool "Multi-Cluster Power Management"
  	depends on CPU_V7 && SMP
  	help
  	  This option provides the common power management infrastructure
  	  for (multi-)cluster based systems, such as big.LITTLE based
  	  systems.

  config MCPM_QUAD_CLUSTER
  	bool
  	depends on MCPM
  	help
  	  To avoid wasting resources unnecessarily, MCPM only supports up
  	  to 2 clusters by default.
  	  Platforms with 3 or 4 clusters that use MCPM must select this
  	  option to allow the additional clusters to be managed.

  config BIG_LITTLE
  	bool "big.LITTLE support (Experimental)"
  	depends on CPU_V7 && SMP
  	select MCPM
  	help
  	  This option enables support selections for the big.LITTLE
  	  system architecture.
  
  config BL_SWITCHER
  	bool "big.LITTLE switcher support"

  	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC

  	select CPU_PM

  	help
  	  The big.LITTLE "switcher" provides the core functionality to
  	  transparently handle transition between a cluster of A15's
  	  and a cluster of A7's in a big.LITTLE system.

  config BL_SWITCHER_DUMMY_IF
  	tristate "Simple big.LITTLE switcher user interface"
  	depends on BL_SWITCHER && DEBUG_KERNEL
  	help
  	  This is a simple and dummy char dev interface to control
  	  the big.LITTLE switcher core code.  It is meant for
  	  debugging purposes only.

  choice
  	prompt "Memory split"

  	depends on MMU

  	default VMSPLIT_3G
  	help
  	  Select the desired split between kernel and user memory.
  
  	  If you are not absolutely sure what you are doing, leave this
  	  option alone!
  
  	config VMSPLIT_3G
  		bool "3G/1G user/kernel split"

  	config VMSPLIT_3G_OPT

  		depends on !ARM_LPAE