// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2017 NXP
 * Copyright 2020 Embedian, Inc.
 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "../freescale/imx8mq.dtsi"

/ {
	firmware {
		android {
			compatible = "android,firmware";
			/* default emmc node used for GSI */
			boot_devices = "soc@0/30800000.bus/30b40000.mmc";
			/* sd card node which used if androidboot.boot_device_root=mmcblk1 */
			boot_devices_mmcblk1 = "soc@0/30800000.bus/30b50000.mmc";
			/* emmc node which used if androidboot.boot_device_root=mmcblk0 */
			boot_devices_mmcblk0 = "soc@0/30800000.bus/30b40000.mmc";
			fstab {
				compatible = "android,fstab";
				system {
					compatible = "android,system";
					dev = "system";
					type = "ext4";
					mnt_flags = "noatime,errors=panic,ro,barrier=1,inode_readahead_blks=8";
					fsmgr_flags = "wait,slotselect,avb,avb_keys=/avb,logical,first_stage_mount";
				};
				system_ext {
					compatible = "android,system_ext";
					dev = "system_ext";
					type = "ext4";
					mnt_flags = "noatime,ro,errors=panic";
					fsmgr_flags = "wait,slotselect,avb,logical,first_stage_mount";
				};
				vendor {
					compatible = "android,vendor";
					dev = "vendor";
					type = "ext4";
					mnt_flags = "noatime,errors=panic,ro,barrier=1,inode_readahead_blks=8";
					fsmgr_flags = "wait,slotselect,avb,logical,first_stage_mount";
				};
				product {
					compatible = "android,product";
					dev = "product";
					type = "ext4";
					mnt_flags = "noatime,errors=panic,ro,barrier=1,inode_readahead_blks=8";
					fsmgr_flags = "wait,slotselect,avb,logical,first_stage_mount";
				};
				metadata {
					compatible = "android,metadata";
					dev = "/dev/block/by-name/metadata";
					type = "ext4";
					mnt_flags = "noatime,nosuid,nodev,discard,sync";
					fsmgr_flags = "wait,formattable,first_stage_mount,check";
				};
			};
			vbmeta {
				/*we need use FirstStageMountVBootV2 if we enable avb*/
				compatible = "android,vbmeta";
				/*parts means the partition witch can be mount in first stage*/
				parts = "vbmeta,dtbo,boot,system,vendor,product";
			};
		};
	};
};

/ {
	trusty {
		compatible = "android,trusty-smc-v1";
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		use-gicv3-workaround;
		trusty-irq {
			use-gicv3-workaround;
			compatible = "android,trusty-irq-v1";
			interrupt-ranges = < 0 15 0>;
			ipi-range = <8 15 8>;
		};
		trusty-virtio {
			compatible = "android,trusty-virtio-v1";
		};
		trusty-log {
			compatible = "android,trusty-log-v1";
		};
	};
};

/ {
	compatible = "embedian,imx8mq-smarc", "fsl,imx8mq";

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0 0xc0000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rpmsg_reserved: rpmsg@0xb8000000 {
			no-map;
			reg = <0 0xb8000000 0 0x400000>;
		};
	};

	resmem: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pcie1_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_usdhc2_vmmc: regulator-vsd-3v3 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2>;
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <20000>;
		enable-active-high;
	};

	buck2_reg: regulator-buck2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_buck2>;
		compatible = "regulator-gpio";
		regulator-name = "vdd_arm";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
		states = <1000000 0x0
			  900000 0x1>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_audio: audio_vdd {
		compatible = "regulator-fixed";
		regulator-name = "sgtl5000_supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_3p3v: 3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	epdev_on: epdev_on {
		compatible = "regulator-fixed";
		regulator-name = "epdev";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_5p0v: 5p0v {
		compatible = "regulator-fixed";
		regulator-name = "5P0V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	reg_1p8v: 1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	sound-sgtl5000 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "sgtl5000-audio";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&codec>;
			frame-master;
			bitclock-master;
		};
	};

	sound-hdmi {
		compatible = "fsl,imx8mq-evk-cdnhdmi",
				"fsl,imx-audio-cdnhdmi";
		model = "imx-audio-hdmi";
		audio-cpu = <&sai4>;
		protocol = <1>;
		hdmi-out;
		constraint-rate = <44100>,
				<88200>,
				<176400>,
				<32000>,
				<48000>,
				<96000>,
				<192000>;
		status = "disabled";
	};

	sound-hdmi-arc {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-hdmi-arc";
		spdif-controller = <&spdif2>;
		spdif-in;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		enable-gpios = <&gpio4 0 0>;    /* Backlight Enable */
		pwms = <&pwm1 0 1000000 0>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
		status = "disabled";
	};

	/* external oscillator of mcp2515 on SPI1.2 and SPI1.3 */
	clk25m: clock-25m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency  = <25000000>;
		clock-output-names = "clk25m";
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

&csi1_bridge {
	fsl,mipi-mode;
	fsl,two-8bit-sensor-mode;
	status = "okay";

	port {
		csi1_ep: endpoint {
			remote-endpoint = <&csi1_mipi_ep>;
		};
	};
};

&csi2_bridge {
	fsl,mipi-mode;
	fsl,two-8bit-sensor-mode;
	status = "okay";

	port {
		csi2_ep: endpoint {
			remote-endpoint = <&csi2_mipi_ep>;
		};
	};
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25M {
			opp-hz = /bits/ 64 <25000000>;
	};

		opp-100M {
			opp-hz = /bits/ 64 <100000000>;
	};

		/*
		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
		 */
		opp-166M {
			opp-hz = /bits/ 64 <166935483>;
	};

		opp-800M {
			opp-hz = /bits/ 64 <800000000>;
	};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <6>;
			at803x,eee-disabled;
		};
	};
};

&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	port {
		mipi1_sensor_ep: endpoint@0 {
			remote-endpoint = <&ov5640_mipi1_ep>;
			data-lanes = <1 2>;
			bus-type = <4>;
		};

		csi1_mipi_ep: endpoint@1 {
			remote-endpoint = <&csi1_ep>;
		};
	};
};

&mipi_csi_2 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	port {
		mipi2_sensor_ep: endpoint@0 {
			remote-endpoint = <&ov5640_mipi2_ep>;
			data-lanes = <1 2>;
			bus-type = <4>;
		};

		csi2_mipi_ep: endpoint@1 {
			remote-endpoint = <&csi2_ep>;
		};
	};
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&sai3 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&sai4 {
	assigned-clocks = <&clk IMX8MQ_CLK_SAI4>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
		<&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
		<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
		<&clk IMX8MQ_AUDIO_PLL2_OUT>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
	status = "okay";
};

&spdif2 {
	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@8 {
		compatible = "fsl,pfuze100";
		fsl,pfuze-support-disable-sw;
		reg = <0x8>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			sw3a_reg: sw3ab {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <975000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1675000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1625000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <3075000>;
				regulator-max-microvolt = <3625000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	cape_eeprom0: cape_eeprom@57 {
		compatible = "at,24c256";
		reg = <0x57>;
	};

	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		#sound-dai-cells = <0>;
		reg = <0x0a>;
		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
		clock-names = "mclk";
		VDDA-supply = <&reg_audio>;
		VDDIO-supply = <&reg_1p8v>;
		status = "okay";
	};

	s35390a: s35390a@30 {
		compatible = "sii,s35390a";
		reg = <0x30>;
		status = "okay";
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	dsi_lvds_bridge: sn65dsi84@2c {
		status = "disabled";
		reg = <0x2c>;
		compatible = "ti,sn65dsi84";
		enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
		interrupt-parent = <&gpio4>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;

		/* AUO G070VW01 7-inch 800x480 LVDS Display */
		sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
					0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
					0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
					0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
					0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
					0x3C 0x3D 0x3E 0xE0 0x0D>;

		sn65dsi84,values =    < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
					0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
					0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
					0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
					0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
					0x00 0x00 0x00 0x01 0x01>;

		/* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
		/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
					0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
					0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
					0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
					0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
					0x3C 0x3D 0x3E 0xE0 0x0D>;

		sn65dsi84,values =    < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
					0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
					0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
					0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
					0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
					0x00 0x00 0x00 0x01 0x01>;*/

		/* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
		/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
					0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
					0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
					0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
					0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
					0x3C 0x3D 0x3E 0xE0 0x0D>;

		sn65dsi84,values =    < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
					0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
					0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
					0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
					0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
					0x00 0x00 0x00 0x01 0x01>;*/
	};

	ov5640_mipi: ov5640_mipi@3c {
		compatible = "ovti,ov5640_mipi";
		reg = <0x3c>;
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi1>;
		clocks = <&clk IMX8MQ_CLK_CLKO2>;
		clock-names = "csi_mclk";
		assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
		assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
		assigned-clock-rates = <20000000>;
		csi_id = <0>;
		pwn-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;	/*GPIO0*/
		rst-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;	/*GPIO2*/
		mclk = <20000000>;
		mclk_source = <0>;
		port {
			ov5640_mipi1_ep: endpoint {
				remote-endpoint = <&mipi1_sensor_ep>;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	baseboard_eeprom: baseboard_eeprom@50 {
		compatible = "at,24c256";
		reg = <0x50>;
	};

};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	ov5640_mipi2: ov5640_mipi2@3c {
		compatible = "ovti,ov5640_mipi";
		reg = <0x3c>;
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi2>;
		clocks = <&clk IMX8MQ_CLK_CLKO2>;
		clock-names = "csi_mclk";
		assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
		assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
		assigned-clock-rates = <20000000>;
		csi_id = <1>;
		pwn-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;       /*GPIO1*/
		rst-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;       /*GPIO3*/
		mclk = <20000000>;
		mclk_source = <0>;
		port {
			ov5640_mipi2_ep: endpoint {
				remote-endpoint = <&mipi2_sensor_ep>;
			};
		};
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	epdev_on-supply = <&epdev_on>;
	reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>;
	assigned-clock-rates = <10000000>;
	assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>;
	status = "disabled";
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie1>;
	epdev_on-supply = <&epdev_on>;
	reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
		 <&pcie1_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>;
	assigned-clock-rates = <10000000>;
	assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>;
	status = "disabled";
};

&snvs_rtc {
	status = "disabled";
};

&pgc_gpu {
	power-supply = <&sw1a_reg>;
};

&pgc_vpu {
	power-supply = <&sw1c_reg>;
};

&snvs_pwrkey {
	status = "okay";
};

&qspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";

};

/* SER3 */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
	status = "okay";
};

/* SER2 */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
	fsl,uart-has-rtscts;        
	status = "okay";
};

/* SER1 */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
	status = "okay";
};

/* SER0 */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "peripheral";
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vqmmc-supply = <&sw4_reg>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
		   <&gpio1 0 GPIO_ACTIVE_LOW>,
		   <&gpio3 15 GPIO_ACTIVE_LOW>,
		   <&gpio3 17 GPIO_ACTIVE_LOW>;
	fsl,spi-num-chipselects = <4>;
	status = "okay";

	spidev@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <24000000>;
	};

	spidev@1 {
		compatible = "rohm,dh2228fv";
		reg = <1>;
		spi-max-frequency = <24000000>;
	};

	can1: can@2 {
		compatible = "microchip,mcp2515";
		reg = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can1>;
		interrupt-parent = <&gpio3>;
		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <10000000>;
		clocks = <&clk25m>;
		vdd-supply = <&reg_3p3v>;
		xceiver-supply = <&reg_5p0v>;
		status = "okay";
	};

	can2: can@3 {
		compatible = "microchip,mcp2515";
		reg = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can2>;
		interrupt-parent = <&gpio3>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <10000000>;
		clocks = <&clk25m>;
		vdd-supply = <&reg_3p3v>;
		xceiver-supply = <&reg_5p0v>;
		status = "okay";
	};
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19	/*RESET_OUT#*/
			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x41	/*FEC_IRQ#*/
			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x41	/*PCIE_WAKE#*/
			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x41	/*LID#*/
			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x41	/*SLEEP#*/
			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x41	/*CHARGING#*/
			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22		0x41	/*CHARGER_PRSNT#*/
			MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19	/*CARRIER_STBY#*/
			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21		0x41	/*BATLOW#*/
			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x41	/*USB0_EN_OC#*/
			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x41	/*USB2_EN_OC#*/
			MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13		0x41	/*USB3_EN_OC#*/
		>;
	};

	pinctrl_buck2: vddarmgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
		>;

	};

	pinctrl_ir_recv: ir-recv {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x4f
		>;
	};

	pinctrl_csi1_pwn: csi1_pwn_grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19
		>;
	};
	pinctrl_csi2_pwn: csi2_pwn_grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x19
		>;
	};

	pinctrl_csi_rst: csi_rst_grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2	0x59
		>;
	};

	pinctrl_csi1: csi1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x19	/*GPIO0*/
			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x19	/*GPIO2*/
			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2	0x59
		>;
	};
	pinctrl_csi2: csi2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x19	/*GPIO1*/
			MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21		0x19	/*GPIO3*/
			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2	0x59
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
		>;
	};

	pinctrl_i2c1_dsi_ts_int: dsi_ts_int {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7		0x19
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000067
			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000067
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x4000007f
		>;
	};

	pinctrl_i2c1_gpio: i2c1grp-gpio {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14		0x7f
			MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15		0x7f
		>;
	};

	pinctrl_i2c2_gpio: i2c2grp-gpio {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16		0x7f
			MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17		0x7f
		>;
	};

	pinctrl_i2c3_gpio: i2c3grp-gpio {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18		0x7f
			MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19		0x7f
		>;
	};

	pinctrl_i2c4_gpio: i2c4grp-gpio {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20		0x7f
			MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21		0x7f
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x16
		>;
	};

	pinctrl_pcie1: pcie1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B		0x76 /* open drain, pull up */
			MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x16
			MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x16
		>;
	};

	pinctrl_qspi: qspigrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82

		>;
	};

	pinctrl_reg_usdhc2: regusdhc2grpgpio {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
			MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
		>;
	};

	pinctrl_sai1_pcm: sai1grp_pcm {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK		0xd6
			MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0		0xd6
			MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1		0xd6
			MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2		0xd6
			MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3		0xd6
			MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4		0xd6
			MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5		0xd6
			MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6		0xd6
			MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7		0xd6
		>;
	};

	pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0		0xd6
			MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1		0xd6
			MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2		0xd6
			MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3		0xd6
			MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4		0xd6
			MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5		0xd6
			MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6		0xd6
			MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7		0xd6
		>;
	};

	pinctrl_sai1_dsd: sai1grp_dsd {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK		0xd6
			MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4		0xd6
			MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0		0xd6
			MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1		0xd6
			MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2		0xd6
			MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3		0xd6
			MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4		0xd6
			MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5		0xd6
			MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6		0xd6
			MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7		0xd6
		>;
	};

	pinctrl_sai5: sai5grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK	0xd6
			MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK	0xd6
			MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC	0xd6
			MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0	0xd6
			MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1    0xd6
			MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2    0xd6
			MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3    0xd6
		>;
	};

	pinctrl_spdif1: spdif1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
			MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
		>;
	};

	pinctrl_ss_sel: usb3ssgrp{
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x16
		>;
	};

	pinctrl_typec: typecgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x17059
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
		>;
        };

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_wdog: wdog1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT		0x06
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x16
			MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x16
			MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x16
			MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x16
			MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x16
			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x16
			MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x16
		>;
	};

	pinctrl_can1: can1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x16	/*CAN0_INT#*/
		>;
	};

	pinctrl_can2: can2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x16	/*CAN1_INT#*/
		>;
	};

	pinctrl_wifi_reset: wifiresetgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
		>;
	};

	pinctrl_lvds: lvdsgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x16
		>;
	};

	pinctrl_hdmi: hdmigrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x16
		>;
	};
};

&vpu {
	status = "okay";
};

&vpu_v4l2 {
	status = "okay";
};

&gpu3d {
	status = "okay";
};

&irqsteer {
	status = "okay";
};

&tmu {
	throttle-cfgs {
		throttle_devfreq: devfreq {
			throttle,max_state = <2>;
			#cooling-cells = <2>;
		};
	};
};

&cpu_thermal {
	trips {
		cpu_alert1: trip1 {
			temperature = <82000>;
			hysteresis = <2000>;
			type = "passive";
		};
		cpu_alert2: trip2 {
			temperature = <86000>;
			hysteresis = <2000>;
			type = "passive";
		};
	};
	cooling-maps {
		map0 {
			trip = <&cpu_alert1>;
			cooling-device =
				<&throttle_devfreq 0 1>;
		};
		map1 {
			trip = <&cpu_alert2>;
			cooling-device =
				<&throttle_devfreq 0 2>;
		};
	};
};