fsl-smarcimx8mq-common.dtsi 32.2 KB
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/*
 * Copyright 2017 NXP
 * Copyright 2018 Embedian, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include "../freescale/fsl-imx8mq.dtsi"

/ {
	compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq";

        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;

                m4_reserved: m4@0x80000000 {
                        no-map;
                        reg = <0 0x80000000 0 0x1000000>;
                };

        };

	aliases { 
		spi0 = &ecspi1; 
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "VSD_3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

                reg_audio: audio_vdd {
                        compatible = "regulator-fixed";
                        regulator-name = "sgtl5000_supply";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };

                reg_3p3v: 3p3v {
                        compatible = "regulator-fixed";
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };

                reg_5p0v: 5p0v {
                        compatible = "regulator-fixed";
                        regulator-name = "5P0V";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        regulator-always-on;
                };

                reg_1p8v: 1p8v {
                        compatible = "regulator-fixed";
                        regulator-name = "1P8V";
                        regulator-min-microvolt = <1800000>;
                        regulator-max-microvolt = <1800000>;
                        regulator-always-on;
                };

		reg_gpio_dvfs: regulator-gpio {
			compatible = "regulator-gpio";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_dvfs>;
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <1000000>;
			regulator-name = "gpio_dvfs";
			regulator-type = "voltage";
			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
			states = <900000 0x1 1000000 0x0>;
		};
	};

	sound-sgtl5000 {
		compatible = "fsl,imx-audio-sgtl5000", 
			     "smarc,imx8mq-audio-sgtl5000";
		model = "imx8mq-audio-sgtl5000";
		ssi-controller = <&sai2>;
		audio-codec = <&codec>;
                audio-routing =
                        "MIC_IN", "Mic Jack",
                        "Mic Jack", "Mic Bias",
                        "Headphone Jack", "HP_OUT";
		fsl,no-audmux;
	};

	sound-hdmi {
		compatible = "fsl,imx-audio-cdnhdmi";
		model = "imx-audio-hdmi";
		audio-cpu = <&sai4>;
		protocol = <1>;
	};

	sound-hdmi-arc {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-hdmi-arc";
		spdif-controller = <&spdif2>;
		spdif-in;
	};

        backlight: backlight {
                compatible = "pwm-backlight";
		enable-gpios = <&gpio4 0 0>;	/* Backlight Enable */ 
                pwms = <&pwm1 0 1000000 0>;
                brightness-levels = < 0  1  2  3  4  5  6  7  8  9
                                     10 11 12 13 14 15 16 17 18 19
                                     20 21 22 23 24 25 26 27 28 29
                                     30 31 32 33 34 35 36 37 38 39
                                     40 41 42 43 44 45 46 47 48 49
                                     50 51 52 53 54 55 56 57 58 59
                                     60 61 62 63 64 65 66 67 68 69
                                     70 71 72 73 74 75 76 77 78 79
                                     80 81 82 83 84 85 86 87 88 89
                                     90 91 92 93 94 95 96 97 98 99
                                    100>;
                default-brightness-level = <80>;
                status = "disabled";
        };

        /* external oscillator of mcp2515 on SPI1.0 and SPI1.1 */
        can_osc: can_osc {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency  = <25000000>;
        };
};



&clk {
	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
	assigned-clock-rates = <786432000>, <722534400>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	smarcimx8mq {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19	/*RESET_OUT#*/
				MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19	/*FEC_IRQ#*/
				MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19	/*PCIE_WAKE#*/
                                MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9              	0x19   	/*LID#*/
                                MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10             	0x19   	/*SLEEP#*/
                                MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1              	0x19   	/*CHARGING#*/
                                MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12             	0x19   	/*CHARGER_PRSNT#*/
                                MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2              	0x19   	/*CARRIER_STBY#*/
                                MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8             	0x19   	/*BATLOW#*/
                                MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10            	0x41    /*USB0_EN_OC#*/
                                MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11            	0x41    /*USB1_EN_OC#*/
                                MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12            	0x41    /*USB2_EN_OC#*/
                                MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13            	0x41    /*USB3_EN_OC#*/
			>;
		};

		pinctrl_csi1: csi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x19	/*GPIO0*/
				MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x19	/*GPIO2*/
				MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2	0x59
			>;
		};
		pinctrl_csi2: csi2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x19	/*GPIO1*/
				MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21		0x19	/*GPIO3*/
				MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2	0x59
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
				MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
			>;
		};

                pinctrl_i2c4: i2c4grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                  0x4000007f
                                MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                  0x4000007f
                        >;
                };

		pinctrl_pcie0: pcie0grp {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3	0x16
			>;
		};

		pinctrl_pcie1: pcie1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x16
			>;
		};

		pinctrl_dvfs: dvfsgrp {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
			>;
		};

		pinctrl_qspi: qspigrp {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
				MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
				MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
				MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
				MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
				MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82

			>;
		};

		pinctrl_typec: typecgrp {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15	0x16
				MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3	0x17059
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
				MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
			>;
		};

                pinctrl_uart2: uart2grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x49
                                MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
				MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11             0x19
				MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10            	0x19
                        >;
                };

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
				MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
			>;
		};

                pinctrl_uart4: uart4grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX           	0x49
                                MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX           	0x49
                                MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B        0x49
                                MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B         0x49
                        >;
                };

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_sai1: sai1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK		0xd6
				MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC		0xd6
				MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC		0xd6
				MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK		0xd6
				MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0		0xd6
				MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1		0xd6
				MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2		0xd6
				MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3		0xd6
				MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4		0xd6
				MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5		0xd6
				MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6		0xd6
				MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7		0xd6
			>;
		};

		pinctrl_sai2: sai2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
                                MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
			>;
		};

                pinctrl_sai3: sai3grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
                                MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
                                MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0    	0xd6
                               	MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0    	0xd6
                        >;
                };

		pinctrl_sai5: sai5grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK	0xd6
				MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK	0xd6
				MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC	0xd6
				MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0	0xd6
				MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1    0xd6
				MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2    0xd6
				MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3    0xd6
			>;
		};

		pinctrl_spdif1: spdif1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
				MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
			>;
		};

		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
			>;
		};

                pinctrl_pwm1: pwm1grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT  	0x06
                        >;
                };

                pinctrl_ecspi1: ecspi1grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x16
                                MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x16
                                MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x16
                                MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9              	0x16
                                MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0              	0x16
                                MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15              	0x16
                                MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17              	0x16
                        >;
                };
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <6>;
			at803x,led-act-blind-workaround;
			at803x,eee-disabled;
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pfuze100@08 {
		compatible = "fsl,pfuze100";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			sw3a_reg: sw3ab {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
                               	regulator-always-on;
			};
		};
	};

        s35390a: s35390a@30 {
                compatible = "s35390a";
                reg = <0x30>;
        };

        cape_eeprom0: cape_eeprom@57 {
                compatible = "at,24c256";
                reg = <0x57>;
        };

        codec: sgtl5000@0a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
        	assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
                        	<&clk IMX8MQ_CLK_SAI2_DIV>;
        	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
        	assigned-clock-rates = <0>, <24576000>;
                clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
                clock-names = "mclk";
                VDDA-supply = <&reg_audio>;
                VDDIO-supply = <&reg_1p8v>;
        };
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

        dsi_lvds_bridge: sn65dsi84@2c {
		status = "disabled";
                reg = <0x2c>;
                compatible = "ti,sn65dsi84";
                enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
               	interrupt-parent = <&gpio4>;
             	interrupts = <4 IRQ_TYPE_EDGE_FALLING>;

		/* AUO G070VW01 7-inch 800x480 LVDS Display */
               	sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
                                        0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
                                        0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
                                        0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
                                        0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
                                        0x3C 0x3D 0x3E 0xE0 0x0D>;

                sn65dsi84,values =    < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
                                        0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
                                        0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
                                        0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
                                        0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
                                        0x00 0x00 0x00 0x01 0x01>;

		/* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
		/*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
                                        0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
                                        0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
                                        0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
                                        0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
                                        0x3C 0x3D 0x3E 0xE0 0x0D>;

                sn65dsi84,values =    < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
                                        0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
                                        0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
                                        0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
                                        0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
                                        0x00 0x00 0x00 0x01 0x01>;*/

		/* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
                /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
                                        0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
                                        0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
                                        0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
                                        0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
                                        0x3C 0x3D 0x3E 0xE0 0x0D>;

                sn65dsi84,values =    < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
                                        0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
                                        0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
                                        0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
                                        0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
                                        0x00 0x00 0x00 0x01 0x01>;*/
        };

        ov5640_mipi: ov5640_mipi@3c {
                compatible = "ovti,ov5640_mipi";
                reg = <0x3c>;
                status = "okay";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_csi1>;
                clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
                clock-names = "csi_mclk";
                assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
                                  <&clk IMX8MQ_CLK_CLKO2_DIV>;
                assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
                assigned-clock-rates = <0>, <20000000>;
                csi_id = <0>;
                pwn-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;	/*GPIO0*/
                rst-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;	/*GPIO2*/
                mclk = <20000000>;
                mclk_source = <0>;
                port {
                        ov5640_mipi1_ep: endpoint {
                                remote-endpoint = <&mipi1_sensor_ep>;
                        };
                };
        };
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

        baseboard_eeprom: baseboard_eeprom@50 {
                compatible = "at,24c256";
                reg = <0x50>;
        };
};

&i2c4 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c4>;
        status = "okay";

        ov5640_mipi2: ov5640_mipi2@3c {
                compatible = "ovti,ov5640_mipi";
                reg = <0x3c>;
                status = "disabled";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_csi2>;
                clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
                clock-names = "csi_mclk";
                assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
                                  <&clk IMX8MQ_CLK_CLKO2_DIV>;
                assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
                assigned-clock-rates = <0>, <20000000>;
                csi_id = <0>;
                pwn-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;	/*GPIO1*/
                rst-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;	/*GPIO3*/
                mclk = <20000000>;
                mclk_source = <0>;
                port {
                        ov5640_mipi2_ep: endpoint {
                                remote-endpoint = <&mipi2_sensor_ep>;
                        };
                };
        };
};

&pcie0{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
	ext_osc = <1>;
	status = "okay";
};

&pcie1{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie1>;
	reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
	ext_osc = <1>;
	status = "okay";
};

/* SER3 */
&uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
        assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
        assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
        status = "okay";
};

/* SER2 */
&uart2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart2>;
        assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
        assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
	cts-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
	rts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
        fsl,uart-has-rtscts;
        status = "okay";
};

/* SER1 */
&uart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart3>;
        assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
        assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
        status = "okay";
};

/* SER0 */
&uart4 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart4>;
        assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>;
        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
       	fsl,uart-has-rtscts;
        status = "okay";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";
};

/* eMMC */
&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
        bus-width = <4>;
        cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
        vmmc-supply = <&reg_usdhc2_vmmc>;
        status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	status = "okay";
	dr_mode = "host";
};

&usb3_phy1 {
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	status = "okay";
	dr_mode = "host";
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};

&sai3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai3>;
        assigned-clocks = <&clk IMX8MQ_CLK_SAI3_SRC>,
                        <&clk IMX8MQ_CLK_SAI3_DIV>;
        assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
        assigned-clock-rates = <0>, <24576000>;
        status = "okay";
};

&sai4 {
	assigned-clocks = <&clk IMX8MQ_CLK_SAI4_SRC>,
			<&clk IMX8MQ_CLK_SAI4_DIV>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <0>, <24576000>;
	status = "okay";
};

&spdif2 {
	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2_SRC>,
			<&clk IMX8MQ_CLK_SPDIF2_DIV>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <0>, <24576000>;
	status = "okay";
};

&gpu_pd {
	power-supply = <&sw1a_reg>;
};

&vpu_pd {
	power-supply = <&sw1c_reg>;
};

&gpu {
	status = "okay";
};

&vpu {
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&mu {
	status = "okay";
};

&rpmsg{
	/*
	 * 64K for one rpmsg instance:
	 * --0xb8000000~0xb800ffff: pingpong
	 */
	vdev-nums = <1>;
	reg = <0x0 0xb8000000 0x0 0x10000>;
	status = "okay";
};

&A53_0 {
	operating-points = <
		/* kHz    uV */
		1500000 1000000
		1300000 1000000
		1000000 900000
		800000  900000
	>;
};

&csi1_bridge {
	fsl,mipi-mode;
	fsl,two-8bit-sensor-mode;
	status = "okay";

	port {
		csi1_ep: endpoint {
			remote-endpoint = <&csi1_mipi_ep>;
		};
	};
};

&csi2_bridge {
	fsl,mipi-mode;
	fsl,two-8bit-sensor-mode;
	status = "okay";

	port {
		csi2_ep: endpoint {
			remote-endpoint = <&csi2_mipi_ep>;
		};
	};
};

&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	port {
		mipi1_sensor_ep: endpoint1 {
			remote-endpoint = <&ov5640_mipi1_ep>;
			data-lanes = <1 2>;
		};

		csi1_mipi_ep: endpoint2 {
			remote-endpoint = <&csi1_ep>;
		};
	};
};

&mipi_csi_2 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	port {
		mipi2_sensor_ep: endpoint1 {
			remote-endpoint = <&ov5640_mipi2_ep>;
			data-lanes = <1 2 3 4>;
		};

		csi2_mipi_ep: endpoint2 {
			remote-endpoint = <&csi2_ep>;
		};
	};
};

&mipi_dsi {
        status = "disabled";
        assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
                          <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
                          <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
                          <&clk IMX8MQ_VIDEO_PLL1>;
        assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
                                 <&clk IMX8MQ_SYS1_PLL_266M>,
                                 <&clk IMX8MQ_CLK_25M>;
        assigned-clock-rates = <24000000>,
                               <266000000>,
                               <0>,
                               <599999999>;
};

&mipi_dsi_bridge {
        status = "disabled";

        panel@0 {
                reg = <0>;
                status = "okay";
		/* AUO G070VW01 800x480 LVDS Display */
               	compatible = "auo,g070vw01";
		/* AUO G185XW01 1366x768 LVDS Display */
		/*compatible = "auo,g185xw01";*/
		/* AUO G240HW01 1920x1080 LVDS Display */
		/*compatible = "auo,g240hw01";*/
                backlight = <&backlight>;
	        enable-gpios = <&gpio4 1 0>;    /* Enable LCD_VDD_EN pin */
                dsi-lanes = <4>;
		/* AUO G070VW01 800x480 LVDS Display */
               	panel-width-mm  = <152>;	
                panel-height-mm = <91>;
		/* AUO G185XW01 1366x768 LVDS Display */
		/*panel-width-mm  = <410>;
                panel-height-mm = <230>;*/
		/* AUO G240HW01 1920x1080 LVDS Display */
                /*panel-width-mm  = <531>;
                panel-height-mm = <299>;*/

		delay,prepare = <120>;

                port {
                        panel_in: endpoint {
                                remote-endpoint = <&mipi_dsi_bridge_out>;
                        };
                };
        };

        port@1 {
                mipi_dsi_bridge_out: endpoint {
                        remote-endpoint = <&panel_in>;
                };
        };
};

&ecspi1 {
        #address-cells = <1>;
        #size-cells = <0>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio5 9 0>, <&gpio1 0 0>, <&gpio3 15 0>, <&gpio3 17 0>;
        fsl,spi-num-chipselects = <4>;
        status = "okay";

        spidev@0 {
                compatible = "rohm,dh2228fv";
                reg = <0>;
                spi-max-frequency = <24000000>;
                };

        spidev@1 {
                compatible = "rohm,dh2228fv";
                reg = <1>;
                spi-max-frequency = <24000000>;
                };

       	can1: can@2 {
                compatible = "microchip,mcp2515";
                reg = <2>;
                spi-max-frequency = <16000000>;
                clocks = <&can_osc>;
                interrupt-parent = <&gpio3>;
                interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
                vdd-supply = <&reg_3p3v>;
                xceiver-supply = <&reg_5p0v>;
        };

        can2: can@3 {
                compatible = "microchip,mcp2515";
                reg = <3>;
                spi-max-frequency = <16000000>;
                clocks = <&can_osc>;
                interrupt-parent = <&gpio3>;
                interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
                vdd-supply = <&reg_3p3v>;
                xceiver-supply = <&reg_5p0v>;
        };
};

&pwm1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm1>;
};

&snvs_rtc {
        status = "disabled";
};