MLK-21292 ARM64: dts: imx8mm: introduce inamte linux

Introduce inmate linux support for jailhouse, we need to benchmark inmate OS, so choose linux. The clock/pin are preconfigured by 1st root cell linux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Ye Li <ye.li@nxp.com>

MLK-21292 ARM64: dts: imx8mm: introduce inamte linux
Introduce inmate linux support for jailhouse, we need to benchmark inmate OS, so choose linux. The clock/pin are preconfigured by 1st root cell linux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Ye Li <ye.li@nxp.com>
Peng Fan
1 parent 4bdcef27c2
Showing 3 changed files with 275 additions and 2 deletions Side-by-side Diff
arch/arm64/boot/dts/freescale/Makefile
arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-inmate.dts
arch/arm64/boot/dts/freescale/fsl-imx8mm-evk-root.dts
@@ -126,6 +126,7 @@
 				 fsl-imx8mm-ddr4-val.dtb \
 				 fsl-imx8mm-evk-rm67191.dtb \
 				 fsl-imx8mm-evk-root.dtb \
+				 fsl-imx8mm-evk-inmate.dtb \
 				 fsl-imx8mm-evk-revb.dtb \
 				 fsl-imx8mm-evk-revb-rm67191.dtb \
 				 fsl-imx8mm-ddr4-evk-rm67191.dtb \
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8mm.dtsi"
+
+/ {
+	model = "Freescale i.MX8MM EVK";
+	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
+	interrupt-parent = <&gic>;
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8333333>;
+	};
+
+	clocks {
+		clk_dummy: clock@7 {
+			compatible = "fixed-clock";
+			reg = <7>;
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "clk_dummy";
+		};
+
+		/* The clocks are configured by 1st OS */
+		clk_200m: clock@8 {
+			compatible = "fixed-clock";
+			reg = <8>;
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			clock-output-names = "200m";
+		};
+		clk_266m: clock@9 {
+			compatible = "fixed-clock";
+			reg = <9>;
+			#clock-cells = <0>;
+			clock-frequency = <266000000>;
+			clock-output-names = "266m";
+		};
+		clk_80m: clock@10 {
+			compatible = "fixed-clock";
+			reg = <10>;
+			#clock-cells = <0>;
+			clock-frequency = <80000000>;
+			clock-output-names = "80m";
+		};
+	};
+
+	display-subsystem {
+		/delete-property/ compatible;
+	};
+
+	pci@bb800000 {
+		compatible = "pci-host-ecam-generic";
+		device_type = "pci";
+		bus-range = <0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
+		reg = <0x0 0xbb800000 0x0 0x100000>;
+		ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
+	};
+};
+
+/delete-node/ &{/memory@40000000};
+/delete-node/ &{/reserved-memory};
+/delete-node/ &{/busfreq};
+/delete-node/ &ddr_pmu0;
+
+&hsio_pd {
+	status = "disabled";
+};
+
+&pcie0_pd {
+	status = "disabled";
+};
+
+&usb_otg1_pd {
+	status = "disabled";
+};
+
+&usb_otg2_pd {
+	status = "disabled";
+};
+
+&gpumix_pd {
+	status = "disabled";
+};
+
+&vpumix_pd {
+	status = "disabled";
+};
+
+&vpu_g1_pd {
+	status = "disabled";
+};
+
+&vpu_g2_pd {
+	status = "disabled";
+};
+
+&vpu_h1_pd {
+	status = "disabled";
+};
+
+&dispmix_pd {
+	status = "disabled";
+};
+
+&mipi_pd {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+&gpio2 {
+	status = "disabled";
+};
+&gpio3 {
+	status = "disabled";
+};
+&gpio4 {
+	status = "disabled";
+};
+&gpio5 {
+	status = "disabled";
+};
+
+/delete-node/ &tmu;
+/delete-node/ &{/thermal-zones};
+/delete-node/ &iomuxc;
+
+&gpr {
+	/delete-property/ compatible;
+};
+
+/delete-node/ &anatop;
+/delete-node/ &snvs;
+
+&clk {
+	/delete-property/ compatible;
+};
+
+&src {
+	/delete-property/ compatible;
+};
+
+/delete-node/ &system_counter;
+
+/delete-node/ &imx_rpmsg;
+/delete-node/ &ocotp;
+
+&dispmix_gpr {
+	/delete-property/ compatible;
+};
+
+&sdma1 {
+	status = "disabled";
+};
+
+&sdma2 {
+	status = "disabled";
+};
+
+&sdma3 {
+	status = "disabled";
+};
+
+/delete-node/ &{/imx_ion};
+/delete-node/ &pcie0;
+/delete-node/ &crypto;
+/delete-node/ &caam_sm;
+/delete-node/ &caam_snvs;
+/delete-node/ &irq_sec_vio;
+
+/delete-node/ &{/cpus/cpu@0};
+/delete-node/ &{/cpus/cpu@1};
+/delete-node/ &{/pmu};
+
+&gic {
+	reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+	      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+};
+
+&uart4 {
+	clocks = <&osc_24m>,
+		<&osc_24m>;
+	clock-names = "ipg", "per";
+	/delete-property/ dmas;
+	/delete-property/ dmas-names;
+	status = "okay";
+};
+
+&usdhc3 {
+	clocks = <&clk_dummy>,
+		<&clk_266m>,
+		<&clk_200m>;
+	/delete-property/assigned-clocks;
+	/delete-property/assigned-clock-rates;
+	clock-names = "ipg", "ahb", "per";
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
@@ -26,6 +26,35 @@
 	/*arm,psci-suspend-param = <0x0>;*/
 };
  
+&clk {
+	init-on-array = <IMX8MM_CLK_AHB_CG IMX8MM_CLK_DRAM_CORE
+			 IMX8MM_CLK_NOC_CG IMX8MM_CLK_NOC_APB_CG
+			 IMX8MM_CLK_USB_BUS_CG
+			 IMX8MM_CLK_MAIN_AXI_CG IMX8MM_CLK_AUDIO_AHB_CG
+			 IMX8MM_CLK_DRAM_APB_DIV IMX8MM_CLK_A53_DIV
+			 IMX8MM_ARM_PLL_OUT IMX8MM_CLK_DISP_AXI_CG
+			 IMX8MM_CLK_DISP_APB_CG
+			 IMX8MM_CLK_NAND_USDHC_BUS_CG
+			 IMX8MM_CLK_USDHC3_ROOT
+			 IMX8MM_CLK_UART4_ROOT>;
+};
+
+&iomuxc {
+	imx8mq-evk {
+		/*
+		 * Used for the 2nd Linux.
+		 * TODO: M4 may use these pins.
+		 */
+		pinctrl_uart4: uart4grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
+				MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
+			>;
+		};
+
+	};
+};
+
 &{/busfreq} {
 	/* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */
 	status = "disabled";
  
  
@@ -58,9 +87,28 @@
 		reg = <0 0xb7c00000 0x0 0x00400000>;
 	};
  
-	inmate_reserved: inmate@0xb3c00000 {
+	/* 512MB */
+	inmate_reserved: inmate@0x93c00000 {
 		no-map;
-		reg = <0 0xb3c00000 0x0 0x04000000>;
+		reg = <0 0x93c00000 0x0 0x24000000>;
 	};
+};
+
+&uart2 {
+	/* uart2 is used by the 2nd OS, so configure pin and clk */
+	pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>;
+	assigned-clocks = <&clk IMX8MM_CLK_UART4_SRC>;
+	assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
+};
+
+&usdhc3 {
+	status = "disabled";
+};
+
+&usdhc2 {
+	/* sdhc3 is used by 2nd linux, configure the pin */
+	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 };
...	...	@@ -126,6 +126,7 @@
126	126	fsl-imx8mm-ddr4-val.dtb \
127	127	fsl-imx8mm-evk-rm67191.dtb \
128	128	fsl-imx8mm-evk-root.dtb \
	129	+ fsl-imx8mm-evk-inmate.dtb \
129	130	fsl-imx8mm-evk-revb.dtb \
130	131	fsl-imx8mm-evk-revb-rm67191.dtb \
131	132	fsl-imx8mm-ddr4-evk-rm67191.dtb \
	1	+/*
	2	+ * Copyright 2019 NXP
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ */
	14	+
	15	+/dts-v1/;
	16	+
	17	+#include "fsl-imx8mm.dtsi"
	18	+
	19	+/ {
	20	+ model = "Freescale i.MX8MM EVK";
	21	+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
	22	+ interrupt-parent = <&gic>;
	23	+
	24	+ timer {
	25	+ compatible = "arm,armv8-timer";
	26	+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
	27	+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
	28	+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
	29	+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
	30	+ clock-frequency = <8333333>;
	31	+ };
	32	+
	33	+ clocks {
	34	+ clk_dummy: clock@7 {
	35	+ compatible = "fixed-clock";
	36	+ reg = <7>;
	37	+ #clock-cells = <0>;
	38	+ clock-frequency = <0>;
	39	+ clock-output-names = "clk_dummy";
	40	+ };
	41	+
	42	+ /* The clocks are configured by 1st OS */
	43	+ clk_200m: clock@8 {
	44	+ compatible = "fixed-clock";
	45	+ reg = <8>;
	46	+ #clock-cells = <0>;
	47	+ clock-frequency = <200000000>;
	48	+ clock-output-names = "200m";
	49	+ };
	50	+ clk_266m: clock@9 {
	51	+ compatible = "fixed-clock";
	52	+ reg = <9>;
	53	+ #clock-cells = <0>;
	54	+ clock-frequency = <266000000>;
	55	+ clock-output-names = "266m";
	56	+ };
	57	+ clk_80m: clock@10 {
	58	+ compatible = "fixed-clock";
	59	+ reg = <10>;
	60	+ #clock-cells = <0>;
	61	+ clock-frequency = <80000000>;
	62	+ clock-output-names = "80m";
	63	+ };
	64	+ };
	65	+
	66	+ display-subsystem {
	67	+ /delete-property/ compatible;
	68	+ };
	69	+
	70	+ pci@bb800000 {
	71	+ compatible = "pci-host-ecam-generic";
	72	+ device_type = "pci";
	73	+ bus-range = <0 0>;
	74	+ #address-cells = <3>;
	75	+ #size-cells = <2>;
	76	+ #interrupt-cells = <1>;
	77	+ interrupt-map-mask = <0 0 0 7>;
	78	+ interrupt-map = <0 0 0 1 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
	79	+ reg = <0x0 0xbb800000 0x0 0x100000>;
	80	+ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
	81	+ };
	82	+};
	83	+
	84	+/delete-node/ &{/memory@40000000};
	85	+/delete-node/ &{/reserved-memory};
	86	+/delete-node/ &{/busfreq};
	87	+/delete-node/ &ddr_pmu0;
	88	+
	89	+&hsio_pd {
	90	+ status = "disabled";
	91	+};
	92	+
	93	+&pcie0_pd {
	94	+ status = "disabled";
	95	+};
	96	+
	97	+&usb_otg1_pd {
	98	+ status = "disabled";
	99	+};
	100	+
	101	+&usb_otg2_pd {
	102	+ status = "disabled";
	103	+};
	104	+
	105	+&gpumix_pd {
	106	+ status = "disabled";
	107	+};
	108	+
	109	+&vpumix_pd {
	110	+ status = "disabled";
	111	+};
	112	+
	113	+&vpu_g1_pd {
	114	+ status = "disabled";
	115	+};
	116	+
	117	+&vpu_g2_pd {
	118	+ status = "disabled";
	119	+};
	120	+
	121	+&vpu_h1_pd {
	122	+ status = "disabled";
	123	+};
	124	+
	125	+&dispmix_pd {
	126	+ status = "disabled";
	127	+};
	128	+
	129	+&mipi_pd {
	130	+ status = "disabled";
	131	+};
	132	+
	133	+&gpio1 {
	134	+ status = "disabled";
	135	+};
	136	+&gpio2 {
	137	+ status = "disabled";
	138	+};
	139	+&gpio3 {
	140	+ status = "disabled";
	141	+};
	142	+&gpio4 {
	143	+ status = "disabled";
	144	+};
	145	+&gpio5 {
	146	+ status = "disabled";
	147	+};
	148	+
	149	+/delete-node/ &tmu;
	150	+/delete-node/ &{/thermal-zones};
	151	+/delete-node/ &iomuxc;
	152	+
	153	+&gpr {
	154	+ /delete-property/ compatible;
	155	+};
	156	+
	157	+/delete-node/ &anatop;
	158	+/delete-node/ &snvs;
	159	+
	160	+&clk {
	161	+ /delete-property/ compatible;
	162	+};
	163	+
	164	+&src {
	165	+ /delete-property/ compatible;
	166	+};
	167	+
	168	+/delete-node/ &system_counter;
	169	+
	170	+/delete-node/ &imx_rpmsg;
	171	+/delete-node/ &ocotp;
	172	+
	173	+&dispmix_gpr {
	174	+ /delete-property/ compatible;
	175	+};
	176	+
	177	+&sdma1 {
	178	+ status = "disabled";
	179	+};
	180	+
	181	+&sdma2 {
	182	+ status = "disabled";
	183	+};
	184	+
	185	+&sdma3 {
	186	+ status = "disabled";
	187	+};
	188	+
	189	+/delete-node/ &{/imx_ion};
	190	+/delete-node/ &pcie0;
	191	+/delete-node/ &crypto;
	192	+/delete-node/ &caam_sm;
	193	+/delete-node/ &caam_snvs;
	194	+/delete-node/ &irq_sec_vio;
	195	+
	196	+/delete-node/ &{/cpus/cpu@0};
	197	+/delete-node/ &{/cpus/cpu@1};
	198	+/delete-node/ &{/pmu};
	199	+
	200	+&gic {
	201	+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
	202	+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
	203	+};
	204	+
	205	+&uart4 {
	206	+ clocks = <&osc_24m>,
	207	+ <&osc_24m>;
	208	+ clock-names = "ipg", "per";
	209	+ /delete-property/ dmas;
	210	+ /delete-property/ dmas-names;
	211	+ status = "okay";
	212	+};
	213	+
	214	+&usdhc3 {
	215	+ clocks = <&clk_dummy>,
	216	+ <&clk_266m>,
	217	+ <&clk_200m>;
	218	+ /delete-property/assigned-clocks;
	219	+ /delete-property/assigned-clock-rates;
	220	+ clock-names = "ipg", "ahb", "per";
	221	+ bus-width = <8>;
	222	+ non-removable;
	223	+ status = "okay";
	224	+};
...	...	@@ -26,6 +26,35 @@
26	26	/arm,psci-suspend-param = <0x0>;/
27	27	};
28	28
	29	+&clk {
	30	+ init-on-array = <IMX8MM_CLK_AHB_CG IMX8MM_CLK_DRAM_CORE
	31	+ IMX8MM_CLK_NOC_CG IMX8MM_CLK_NOC_APB_CG
	32	+ IMX8MM_CLK_USB_BUS_CG
	33	+ IMX8MM_CLK_MAIN_AXI_CG IMX8MM_CLK_AUDIO_AHB_CG
	34	+ IMX8MM_CLK_DRAM_APB_DIV IMX8MM_CLK_A53_DIV
	35	+ IMX8MM_ARM_PLL_OUT IMX8MM_CLK_DISP_AXI_CG
	36	+ IMX8MM_CLK_DISP_APB_CG
	37	+ IMX8MM_CLK_NAND_USDHC_BUS_CG
	38	+ IMX8MM_CLK_USDHC3_ROOT
	39	+ IMX8MM_CLK_UART4_ROOT>;
	40	+};
	41	+
	42	+&iomuxc {
	43	+ imx8mq-evk {
	44	+ /*
	45	+ * Used for the 2nd Linux.
	46	+ * TODO: M4 may use these pins.
	47	+ */
	48	+ pinctrl_uart4: uart4grp {
	49	+ fsl,pins = <
	50	+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
	51	+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
	52	+ >;
	53	+ };
	54	+
	55	+ };
	56	+};
	57	+
29	58	&{/busfreq} {
30	59	/* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */
31	60	status = "disabled";
32	61
33	62
...	...	@@ -58,9 +87,28 @@
58	87	reg = <0 0xb7c00000 0x0 0x00400000>;
59	88	};
60	89
61		- inmate_reserved: inmate@0xb3c00000 {
	90	+ /* 512MB */
	91	+ inmate_reserved: inmate@0x93c00000 {
62	92	no-map;
63		- reg = <0 0xb3c00000 0x0 0x04000000>;
	93	+ reg = <0 0x93c00000 0x0 0x24000000>;
64	94	};
	95	+};
	96	+
	97	+&uart2 {
	98	+ /* uart2 is used by the 2nd OS, so configure pin and clk */
	99	+ pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>;
	100	+ assigned-clocks = <&clk IMX8MM_CLK_UART4_SRC>;
	101	+ assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
	102	+};
	103	+
	104	+&usdhc3 {
	105	+ status = "disabled";
	106	+};
	107	+
	108	+&usdhc2 {
	109	+ /* sdhc3 is used by 2nd linux, configure the pin */
	110	+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	111	+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	112	+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
65	113	};