add real-time avb device tree

Eric Lee
1 parent 114eab7cc7
Showing 4 changed files with 127 additions and 0 deletions Side-by-side Diff
arch/arm64/boot/dts/embedian/Makefile
arch/arm64/boot/dts/embedian/imx8mm-smarc-avb.dts
arch/arm64/boot/dts/embedian/imx8mp-pitx-avb.dts
arch/arm64/boot/dts/embedian/imx8mp-smarc-avb.dts
 # SPDX-License-Identifier: GPL-2.0
  
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-smarc.dtb \
+			imx8mp-pitx-avb.dtb \
 			imx8mp-pitx-rs485.dtb \
 			imx8mp-pitx-lvds-rs485.dtb \
 			imx8mp-pitx.dtb \
 			imx8mp-pitx-lvds.dtb \
+			imx8mp-smarc-avb.dtb \
 			imx8mp-smarc-hdmi.dtb \
 			imx8mp-smarc-lvds.dtb \
 			imx8mp-smarc-m7.dtb \
@@ -21,6 +23,7 @@
 			imx8mq-smarc-m4-lcdif-lvds.dtb \
 			imx8mq-smarc-m4-dual-display.dtb \
 			imx8mm-smarc.dtb \
+			imx8mm-smarc-avb.dtb \
 			imx8mm-smarc-m4.dtb \
 			imx8qm-smarc.dtb \
 			imx8qm-smarc-dp.dtb \
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020-2021 NXP
+ * Copyright 2023 Embedian
+ */
+
+/dts-v1/;
+
+#include "imx8mm-smarc.dts"
+
+/* AVB HW timer*/
+&gpt1 {
+	compatible = "fsl,avb-gpt";
+	timer-channel = <1>; /* Use output compare channel 1*/
+	prescale = <1>;
+	domain = <0>;
+
+	clocks = <&clk IMX8MM_CLK_GPT1_ROOT>,
+		 <&clk IMX8MM_CLK_GPT1_ROOT>, <&clk IMX8MM_AUDIO_PLL1>;
+	clock-names = "ipg", "per", "audio_pll";
+
+	/* Make the GPT clk root derive from the audio PLL */
+	assigned-clocks = <&clk IMX8MM_CLK_GPT1>;
+	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <0>;
+
+	/* Enble SW sampling for media clock recovery on port 0 */
+	sw-recovery = <0>;
+
+	status = "okay";
+};
+
+&fec1 {
+	fsl,rx-phy-delay-100-ns = <670>;
+	fsl,tx-phy-delay-100-ns = <670>;
+	fsl,rx-phy-delay-1000-ns = <0>;
+	fsl,tx-phy-delay-1000-ns = <0>;
+};
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2023 Embedian
+ */
+
+/dts-v1/;
+
+#include "imx8mp-pitx-common.dtsi"
+
+/* AVB HW timer*/
+&gpt1 {
+	compatible = "fsl,avb-gpt";
+	timer-channel = <1>; /* Use output compare channel 1*/
+	rec-channel = <1 0 1>; // capture channel, eth port, ENET TC id
+	prescale = <1>;
+	domain = <0>;
+
+	clocks = <&clk IMX8MP_CLK_GPT1_ROOT>,
+		 <&clk IMX8MP_CLK_GPT1_ROOT>,
+		 <&clk IMX8MP_AUDIO_PLL1>;
+	clock-names = "ipg", "per", "audio_pll";
+
+	/* Make the GPT clk root derive from the audio PLL*/
+	assigned-clocks = <&clk IMX8MP_CLK_GPT1>;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <0>;
+
+	gpt1_capin1_sel = <&gpr 0x4 2>;
+
+	status = "okay";
+};
+
+&fec {
+	fsl,rx-phy-delay-100-ns = <670>;
+	fsl,tx-phy-delay-100-ns = <670>;
+	fsl,rx-phy-delay-1000-ns = <0>;
+	fsl,tx-phy-delay-1000-ns = <0>;
+};
+
+&ethphy0 {
+	eee-broken-100tx;
+};
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2023 Embedian
+ */
+
+/dts-v1/;
+
+#include "imx8mp-smarc-common.dtsi"
+
+/* AVB HW timer*/
+&gpt1 {
+	compatible = "fsl,avb-gpt";
+	timer-channel = <1>; /* Use output compare channel 1*/
+	rec-channel = <1 0 1>; // capture channel, eth port, ENET TC id
+	prescale = <1>;
+	domain = <0>;
+
+	clocks = <&clk IMX8MP_CLK_GPT1_ROOT>,
+		 <&clk IMX8MP_CLK_GPT1_ROOT>,
+		 <&clk IMX8MP_AUDIO_PLL1>;
+	clock-names = "ipg", "per", "audio_pll";
+
+	/* Make the GPT clk root derive from the audio PLL*/
+	assigned-clocks = <&clk IMX8MP_CLK_GPT1>;
+	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <0>;
+
+	gpt1_capin1_sel = <&gpr 0x4 2>;
+
+	status = "okay";
+};
+
+&fec {
+	fsl,rx-phy-delay-100-ns = <670>;
+	fsl,tx-phy-delay-100-ns = <670>;
+	fsl,rx-phy-delay-1000-ns = <0>;
+	fsl,tx-phy-delay-1000-ns = <0>;
+};
+
+&ethphy0 {
+	eee-broken-100tx;
+};
1	1	# SPDX-License-Identifier: GPL-2.0
2	2
3	3	dtb-$(CONFIG_ARCH_MXC) += imx8mp-smarc.dtb \
	4	+ imx8mp-pitx-avb.dtb \
4	5	imx8mp-pitx-rs485.dtb \
5	6	imx8mp-pitx-lvds-rs485.dtb \
6	7	imx8mp-pitx.dtb \
7	8	imx8mp-pitx-lvds.dtb \
	9	+ imx8mp-smarc-avb.dtb \
8	10	imx8mp-smarc-hdmi.dtb \
9	11	imx8mp-smarc-lvds.dtb \
10	12	imx8mp-smarc-m7.dtb \
...	...	@@ -21,6 +23,7 @@
21	23	imx8mq-smarc-m4-lcdif-lvds.dtb \
22	24	imx8mq-smarc-m4-dual-display.dtb \
23	25	imx8mm-smarc.dtb \
	26	+ imx8mm-smarc-avb.dtb \
24	27	imx8mm-smarc-m4.dtb \
25	28	imx8qm-smarc.dtb \
26	29	imx8qm-smarc-dp.dtb \
	1	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	+/*
	3	+ * Copyright 2020-2021 NXP
	4	+ * Copyright 2023 Embedian
	5	+ */
	6	+
	7	+/dts-v1/;
	8	+
	9	+#include "imx8mm-smarc.dts"
	10	+
	11	+/* AVB HW timer*/
	12	+&gpt1 {
	13	+ compatible = "fsl,avb-gpt";
	14	+ timer-channel = <1>; /* Use output compare channel 1*/
	15	+ prescale = <1>;
	16	+ domain = <0>;
	17	+
	18	+ clocks = <&clk IMX8MM_CLK_GPT1_ROOT>,
	19	+ <&clk IMX8MM_CLK_GPT1_ROOT>, <&clk IMX8MM_AUDIO_PLL1>;
	20	+ clock-names = "ipg", "per", "audio_pll";
	21	+
	22	+ /* Make the GPT clk root derive from the audio PLL */
	23	+ assigned-clocks = <&clk IMX8MM_CLK_GPT1>;
	24	+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	25	+ assigned-clock-rates = <0>;
	26	+
	27	+ /* Enble SW sampling for media clock recovery on port 0 */
	28	+ sw-recovery = <0>;
	29	+
	30	+ status = "okay";
	31	+};
	32	+
	33	+&fec1 {
	34	+ fsl,rx-phy-delay-100-ns = <670>;
	35	+ fsl,tx-phy-delay-100-ns = <670>;
	36	+ fsl,rx-phy-delay-1000-ns = <0>;
	37	+ fsl,tx-phy-delay-1000-ns = <0>;
	38	+};
	1	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	+/*
	3	+ * Copyright 2019 NXP
	4	+ * Copyright 2023 Embedian
	5	+ */
	6	+
	7	+/dts-v1/;
	8	+
	9	+#include "imx8mp-pitx-common.dtsi"
	10	+
	11	+/* AVB HW timer*/
	12	+&gpt1 {
	13	+ compatible = "fsl,avb-gpt";
	14	+ timer-channel = <1>; /* Use output compare channel 1*/
	15	+ rec-channel = <1 0 1>; // capture channel, eth port, ENET TC id
	16	+ prescale = <1>;
	17	+ domain = <0>;
	18	+
	19	+ clocks = <&clk IMX8MP_CLK_GPT1_ROOT>,
	20	+ <&clk IMX8MP_CLK_GPT1_ROOT>,
	21	+ <&clk IMX8MP_AUDIO_PLL1>;
	22	+ clock-names = "ipg", "per", "audio_pll";
	23	+
	24	+ /* Make the GPT clk root derive from the audio PLL*/
	25	+ assigned-clocks = <&clk IMX8MP_CLK_GPT1>;
	26	+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
	27	+ assigned-clock-rates = <0>;
	28	+
	29	+ gpt1_capin1_sel = <&gpr 0x4 2>;
	30	+
	31	+ status = "okay";
	32	+};
	33	+
	34	+&fec {
	35	+ fsl,rx-phy-delay-100-ns = <670>;
	36	+ fsl,tx-phy-delay-100-ns = <670>;
	37	+ fsl,rx-phy-delay-1000-ns = <0>;
	38	+ fsl,tx-phy-delay-1000-ns = <0>;
	39	+};
	40	+
	41	+&ethphy0 {
	42	+ eee-broken-100tx;
	43	+};