From 04e5497cfc82d6181bcfbec7ade5fb973b488cd0 Mon Sep 17 00:00:00 2001
From: Eric Lee <eric.lee@embedian.com>
Date: Sat, 27 May 2023 13:59:53 +0800
Subject: [PATCH] add real-time avb device tree
---
arch/arm64/boot/dts/embedian/Makefile | 3 ++
arch/arm64/boot/dts/embedian/imx8mm-smarc-avb.dts | 38 ++++++++++++++++++++
arch/arm64/boot/dts/embedian/imx8mp-pitx-avb.dts | 43 +++++++++++++++++++++++
arch/arm64/boot/dts/embedian/imx8mp-smarc-avb.dts | 43 +++++++++++++++++++++++
4 files changed, 127 insertions(+)
create mode 100644 arch/arm64/boot/dts/embedian/imx8mm-smarc-avb.dts
create mode 100644 arch/arm64/boot/dts/embedian/imx8mp-pitx-avb.dts
create mode 100644 arch/arm64/boot/dts/embedian/imx8mp-smarc-avb.dts
diff --git a/arch/arm64/boot/dts/embedian/Makefile b/arch/arm64/boot/dts/embedian/Makefile
index e632d82..5596d70 100644
--- a/arch/arm64/boot/dts/embedian/Makefile
+++ b/arch/arm64/boot/dts/embedian/Makefile
@@ -1,10 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MXC) += imx8mp-smarc.dtb \
+ imx8mp-pitx-avb.dtb \
imx8mp-pitx-rs485.dtb \
imx8mp-pitx-lvds-rs485.dtb \
imx8mp-pitx.dtb \
imx8mp-pitx-lvds.dtb \
+ imx8mp-smarc-avb.dtb \
imx8mp-smarc-hdmi.dtb \
imx8mp-smarc-lvds.dtb \
imx8mp-smarc-m7.dtb \
@@ -21,6 +23,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-smarc.dtb \
imx8mq-smarc-m4-lcdif-lvds.dtb \
imx8mq-smarc-m4-dual-display.dtb \
imx8mm-smarc.dtb \
+ imx8mm-smarc-avb.dtb \
imx8mm-smarc-m4.dtb \
imx8qm-smarc.dtb \
imx8qm-smarc-dp.dtb \
diff --git a/arch/arm64/boot/dts/embedian/imx8mm-smarc-avb.dts b/arch/arm64/boot/dts/embedian/imx8mm-smarc-avb.dts
new file mode 100644
index 0000000..8bcb4c9
--- /dev/null
+++ b/arch/arm64/boot/dts/embedian/imx8mm-smarc-avb.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020-2021 NXP
+ * Copyright 2023 Embedian
+ */
+
+/dts-v1/;
+
+#include "imx8mm-smarc.dts"
+
+/* AVB HW timer*/
+&gpt1 {
+ compatible = "fsl,avb-gpt";
+ timer-channel = <1>; /* Use output compare channel 1*/
+ prescale = <1>;
+ domain = <0>;
+
+ clocks = <&clk IMX8MM_CLK_GPT1_ROOT>,
+ <&clk IMX8MM_CLK_GPT1_ROOT>, <&clk IMX8MM_AUDIO_PLL1>;
+ clock-names = "ipg", "per", "audio_pll";
+
+ /* Make the GPT clk root derive from the audio PLL */
+ assigned-clocks = <&clk IMX8MM_CLK_GPT1>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>;
+
+ /* Enble SW sampling for media clock recovery on port 0 */
+ sw-recovery = <0>;
+
+ status = "okay";
+};
+
+&fec1 {
+ fsl,rx-phy-delay-100-ns = <670>;
+ fsl,tx-phy-delay-100-ns = <670>;
+ fsl,rx-phy-delay-1000-ns = <0>;
+ fsl,tx-phy-delay-1000-ns = <0>;
+};
diff --git a/arch/arm64/boot/dts/embedian/imx8mp-pitx-avb.dts b/arch/arm64/boot/dts/embedian/imx8mp-pitx-avb.dts
new file mode 100644
index 0000000..070b507
--- /dev/null
+++ b/arch/arm64/boot/dts/embedian/imx8mp-pitx-avb.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2023 Embedian
+ */
+
+/dts-v1/;
+
+#include "imx8mp-pitx-common.dtsi"
+
+/* AVB HW timer*/
+&gpt1 {
+ compatible = "fsl,avb-gpt";
+ timer-channel = <1>; /* Use output compare channel 1*/
+ rec-channel = <1 0 1>; // capture channel, eth port, ENET TC id
+ prescale = <1>;
+ domain = <0>;
+
+ clocks = <&clk IMX8MP_CLK_GPT1_ROOT>,
+ <&clk IMX8MP_CLK_GPT1_ROOT>,
+ <&clk IMX8MP_AUDIO_PLL1>;
+ clock-names = "ipg", "per", "audio_pll";
+
+ /* Make the GPT clk root derive from the audio PLL*/
+ assigned-clocks = <&clk IMX8MP_CLK_GPT1>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>;
+
+ gpt1_capin1_sel = <&gpr 0x4 2>;
+
+ status = "okay";
+};
+
+&fec {
+ fsl,rx-phy-delay-100-ns = <670>;
+ fsl,tx-phy-delay-100-ns = <670>;
+ fsl,rx-phy-delay-1000-ns = <0>;
+ fsl,tx-phy-delay-1000-ns = <0>;
+};
+
+ðphy0 {
+ eee-broken-100tx;
+};
diff --git a/arch/arm64/boot/dts/embedian/imx8mp-smarc-avb.dts b/arch/arm64/boot/dts/embedian/imx8mp-smarc-avb.dts
new file mode 100644
index 0000000..1e9d72c
--- /dev/null
+++ b/arch/arm64/boot/dts/embedian/imx8mp-smarc-avb.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2023 Embedian
+ */
+
+/dts-v1/;
+
+#include "imx8mp-smarc-common.dtsi"
+
+/* AVB HW timer*/
+&gpt1 {
+ compatible = "fsl,avb-gpt";
+ timer-channel = <1>; /* Use output compare channel 1*/
+ rec-channel = <1 0 1>; // capture channel, eth port, ENET TC id
+ prescale = <1>;
+ domain = <0>;
+
+ clocks = <&clk IMX8MP_CLK_GPT1_ROOT>,
+ <&clk IMX8MP_CLK_GPT1_ROOT>,
+ <&clk IMX8MP_AUDIO_PLL1>;
+ clock-names = "ipg", "per", "audio_pll";
+
+ /* Make the GPT clk root derive from the audio PLL*/
+ assigned-clocks = <&clk IMX8MP_CLK_GPT1>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>;
+
+ gpt1_capin1_sel = <&gpr 0x4 2>;
+
+ status = "okay";
+};
+
+&fec {
+ fsl,rx-phy-delay-100-ns = <670>;
+ fsl,tx-phy-delay-100-ns = <670>;
+ fsl,rx-phy-delay-1000-ns = <0>;
+ fsl,tx-phy-delay-1000-ns = <0>;
+};
+
+ðphy0 {
+ eee-broken-100tx;
+};
--
1.9.1