Commit 1e6655478ffa22618e5c3b99a0cdc260f3840c97

Authored by Eric Lee
1 parent af60382906

Fix Support for LVDS diaplay

Showing 6 changed files with 71 additions and 69 deletions Side-by-side Diff

arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-common.dtsi
... ... @@ -185,14 +185,14 @@
185 185 pinctrl_hog: hoggrp {
186 186 fsl,pins = <
187 187 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /*RESET_OUT#*/
188   - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /*FEC_IRQ#*/
189   - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /*PCIE_WAKE#*/
190   - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x41 /*LID#*/
191   - MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 /*SLEEP#*/
192   - MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 /*CHARGING#*/
193   - MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 /*CHARGER_PRSNT#*/
  188 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 /*FEC_IRQ#*/
  189 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x41 /*PCIE_WAKE#*/
  190 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x41 /*LID#*/
  191 + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 /*SLEEP#*/
  192 + MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 /*CHARGING#*/
  193 + MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 /*CHARGER_PRSNT#*/
194 194 MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /*CARRIER_STBY#*/
195   - MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 /*BATLOW#*/
  195 + MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 /*BATLOW#*/
196 196 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x41 /*USB0_EN_OC#*/
197 197 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x41 /*USB2_EN_OC#*/
198 198 MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x41 /*USB3_EN_OC#*/
... ... @@ -724,7 +724,7 @@
724 724 0x00 0x00 0x00 0x01 0x01>;*/
725 725  
726 726 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
727   - /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
  727 + /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
728 728 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
729 729 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
730 730 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
... ... @@ -897,7 +897,7 @@
897 897  
898 898 &usb_dwc3_0 {
899 899 status = "okay";
900   - dr_mode = "peripheral";
  900 + dr_mode = "host";
901 901 };
902 902  
903 903 &usb3_phy1 {
... ... @@ -959,7 +959,6 @@
959 959 };
960 960  
961 961 &gpu {
962   - gpu-noc-priority = <0x80000600>;
963 962 status = "okay";
964 963 };
965 964  
... ... @@ -978,14 +977,15 @@
978 977 status = "okay";
979 978 };
980 979  
981   -&rpmsg{
982   - /*
983   - * 64K for one rpmsg instance:
984   - * --0x98000000~0x9800ffff: pingpong
985   - */
986   - vdev-nums = <1>;
987   - reg = <0x0 0x98000000 0x0 0x10000>;
988   - status = "okay";
  980 +&resmem {
  981 + /* cma region is provided by kernel command line as cma=<size>M */
  982 + /delete-node/ linux,cma;
  983 +
  984 + /delete-node/ rpmsg@0x98000000;
  985 + rpmsg_reserved: rpmsg@0x40000000 {
  986 + no-map;
  987 + reg = <0 0x40000000 0 0x400000>;
  988 + };
989 989 };
990 990  
991 991 &A53_0 {
992 992  
... ... @@ -1102,25 +1102,10 @@
1102 1102 };
1103 1103 };
1104 1104  
1105   -&mipi_dsi {
1106   - status = "disabled";
1107   - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1108   - <&clk IMX8MQ_CLK_DSI_CORE>,
1109   - <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1110   - <&clk IMX8MQ_VIDEO_PLL1>;
1111   - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
1112   - <&clk IMX8MQ_SYS1_PLL_266M>,
1113   - <&clk IMX8MQ_CLK_25M>;
1114   - assigned-clock-rates = <24000000>,
1115   - <266000000>,
1116   - <0>,
1117   - <599999999>;
1118   -};
1119   -
1120 1105 &mipi_dsi_bridge {
1121 1106 status = "disabled";
1122 1107  
1123   - panel@0 {
  1108 + panel@0 {
1124 1109 reg = <0>;
1125 1110 status = "okay";
1126 1111 /* AUO G070VW01 800x480 LVDS Display */
1127 1112  
1128 1113  
1129 1114  
1130 1115  
1131 1116  
... ... @@ -1128,28 +1113,28 @@
1128 1113 /* AUO G185XW01 1366x768 LVDS Display */
1129 1114 /*compatible = "auo,g185xw01";*/
1130 1115 /* AUO G240HW01 1920x1080 LVDS Display */
1131   - /*compatible = "auo,g240hw01";*/
1132   - backlight = <&backlight>;
1133   - enable-gpios = <&gpio4 1 0>; /* Enable LCD_VDD_EN pin */
1134   - dsi-lanes = <4>;
  1116 + /*compatible = "auo,g240hw01";*/
  1117 + backlight = <&backlight>;
  1118 + enable-gpios = <&gpio4 1 0>; /* Enable LCD_VDD_EN pin */
  1119 + dsi-lanes = <4>;
1135 1120 /* AUO G070VW01 800x480 LVDS Display */
1136 1121 panel-width-mm = <152>;
1137 1122 panel-height-mm = <91>;
1138 1123 /* AUO G185XW01 1366x768 LVDS Display */
1139   - /*panel-width-mm = <410>;
  1124 + /*panel-width-mm = <410>;
1140 1125 panel-height-mm = <230>;*/
1141 1126 /* AUO G240HW01 1920x1080 LVDS Display */
1142   - /*panel-width-mm = <531>;
  1127 + /*panel-width-mm = <531>;
1143 1128 panel-height-mm = <299>;*/
1144 1129  
1145   - delay,prepare = <120>;
  1130 + delay,prepare = <120>;
1146 1131  
1147   - port {
  1132 + port {
1148 1133 panel_in: endpoint {
1149 1134 remote-endpoint = <&mipi_dsi_bridge_out>;
1150 1135 };
1151 1136 };
1152   - };
  1137 + };
1153 1138  
1154 1139 port@1 {
1155 1140 mipi_dsi_bridge_out: endpoint {
... ... @@ -1182,8 +1167,8 @@
1182 1167 can1: can@2 {
1183 1168 compatible = "microchip,mcp2515";
1184 1169 reg = <2>;
1185   - interrupt-parent = <&gpio3>;
1186   - interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
  1170 + interrupt-parent = <&gpio3>;
  1171 + interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
1187 1172 spi-max-frequency = <12000000>;
1188 1173 clocks = <&can_osc>;
1189 1174 vdd-supply = <&reg_3p3v>;
... ... @@ -1193,8 +1178,8 @@
1193 1178 can2: can@3 {
1194 1179 compatible = "microchip,mcp2515";
1195 1180 reg = <3>;
1196   - interrupt-parent = <&gpio3>;
1197   - interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
  1181 + interrupt-parent = <&gpio3>;
  1182 + interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
1198 1183 spi-max-frequency = <12000000>;
1199 1184 clocks = <&can_osc>;
1200 1185 vdd-supply = <&reg_3p3v>;
... ... @@ -1205,6 +1190,10 @@
1205 1190 &pwm1 {
1206 1191 pinctrl-names = "default";
1207 1192 pinctrl-0 = <&pinctrl_pwm1>;
  1193 +};
  1194 +
  1195 +&snvs_rtc {
  1196 + status = "disabled";
1208 1197 };
1209 1198  
1210 1199 &crypto {
arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-dcss-lvds.dtsi
... ... @@ -13,6 +13,12 @@
13 13 * GNU General Public License for more details.
14 14 */
15 15  
  16 +/ {
  17 + sound-hdmi {
  18 + status = "disabled";
  19 + };
  20 +};
  21 +
16 22 &hdmi {
17 23 status = "disabled";
18 24 };
... ... @@ -22,22 +28,26 @@
22 28 disp-dev = "mipi_disp";
23 29 enable-gpios = <&gpio4 1 0>; /* Enable LCD_VDD_EN pin */
24 30  
25   - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
26   - <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
27   - <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
28   - <&clk IMX8MQ_CLK_DC_PIXEL>,
29   - <&clk IMX8MQ_CLK_DUMMY>,
30   - <&clk IMX8MQ_CLK_DISP_DTRC>;
31   - clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
32   - assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
33   - <&clk IMX8MQ_CLK_DISP_AXI>,
34   - <&clk IMX8MQ_CLK_DISP_RTRM>;
35   - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
36   - <&clk IMX8MQ_SYS1_PLL_800M>,
37   - <&clk IMX8MQ_SYS1_PLL_800M>;
38   - assigned-clock-rates = <594000000>,
39   - <800000000>,
40   - <400000000>;
  31 + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
  32 + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
  33 + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
  34 + <&clk IMX8MQ_CLK_DC_PIXEL>,
  35 + <&clk IMX8MQ_CLK_DISP_DTRC>,
  36 + <&clk IMX8MQ_VIDEO_PLL1>,
  37 + <&clk IMX8MQ_CLK_27M>,
  38 + <&clk IMX8MQ_CLK_25M>;
  39 + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll",
  40 + "pll_src1", "pll_src2";
  41 +
  42 + assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
  43 + <&clk IMX8MQ_CLK_DISP_AXI>,
  44 + <&clk IMX8MQ_CLK_DISP_RTRM>;
  45 + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
  46 + <&clk IMX8MQ_SYS1_PLL_800M>,
  47 + <&clk IMX8MQ_SYS1_PLL_800M>;
  48 + assigned-clock-rates = <594000000>,
  49 + <800000000>,
  50 + <400000000>;
41 51  
42 52 dcss_disp0: port@0 {
43 53 reg = <0>;
arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-lcdif-lvds.dtsi
... ... @@ -56,6 +56,7 @@
56 56 as_bridge;
57 57 sync-pol = <1>;
58 58 pwr-delay = <10>;
  59 + /delete-property/ no_clk_reset;
59 60  
60 61 port@1 {
61 62 mipi_dsi_in: endpoint {
... ... @@ -66,6 +67,7 @@
66 67  
67 68 &mipi_dsi_bridge {
68 69 status = "okay";
  70 + /delete-property/ no_clk_reset;
69 71 };
70 72  
71 73 &pwm1 {
drivers/gpu/drm/mxsfb/mxsfb_drv.c
... ... @@ -50,7 +50,7 @@
50 50 /* Maximum Video PLL frequency */
51 51 #define MAX_PLL_FREQ 1200000000
52 52 /* Mininum pixel clock in Hz */
53   -#define MIN_PIX_CLK 74250000
  53 +#define MIN_PIX_CLK 31500000
54 54 enum mxsfb_devtype {
55 55 MXSFB_V3,
56 56 MXSFB_V4,
drivers/gpu/drm/panel/panel-simple.c
... ... @@ -1238,7 +1238,7 @@
1238 1238 /*
1239 1239 * The panel spec recommends one second delay
1240 1240 * to the below items. However, it's a bit too
1241   - * long in pratical. Based on tests, it turns
  1241 + * long in practice. Based on tests, it turns
1242 1242 * out 100 milliseconds is fine.
1243 1243 */
1244 1244 .prepare = 100,
... ... @@ -2369,7 +2369,7 @@
2369 2369 };
2370 2370  
2371 2371 static const struct drm_display_mode auo_g070vw01_mode = {
2372   - .clock = 29500,
  2372 + .clock = 31500,
2373 2373 .hdisplay = 800,
2374 2374 .hsync_start = 800 + 40,
2375 2375 .hsync_end = 800 + 40 + 128,
... ... @@ -2392,6 +2392,7 @@
2392 2392 .height = 91,
2393 2393 },
2394 2394 .bus_flags = DRM_BUS_FLAG_DE_LOW,
  2395 +
2395 2396 },
2396 2397 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST,
2397 2398 .format = MIPI_DSI_FMT_RGB888,
2398 2399  
... ... @@ -2399,11 +2400,11 @@
2399 2400 };
2400 2401  
2401 2402 static const struct drm_display_mode auo_g185xw01_mode = {
2402   - .clock = 85000,
  2403 + .clock = 74250,
2403 2404 .hdisplay = 1368,
2404 2405 .hsync_start = 1368 + 72,
2405 2406 .hsync_end = 1368 + 72 + 144,
2406   - .htotal = 1366 + 72 + 144 + 216,
  2407 + .htotal = 1368 + 72 + 144 + 216,
2407 2408 .vdisplay = 768,
2408 2409 .vsync_start = 768 + 1,
2409 2410 .vsync_end = 768 + 1 + 3,
drivers/gpu/imx/dcss/dcss-dtg.c
... ... @@ -92,7 +92,7 @@
92 92 /* Maximum Video PLL frequency */
93 93 #define MAX_PLL_FREQ 1200000000
94 94 /* Mininum pixel clock in kHz */
95   -#define MIN_PIX_CLK 74250
  95 +#define MIN_PIX_CLK 31500
96 96  
97 97 static struct dcss_debug_reg dtg_debug_reg[] = {
98 98 DCSS_DBG_REG(DCSS_DTG_TC_CONTROL_STATUS),