Commit 4b5e2a69f6a52f0ce1513ee88810a6d5c00965bb

Authored by Eric Lee
1 parent 5bd5fe20de

Fix SD interface driven strength

Showing 1 changed file with 1 additions and 3 deletions Inline Diff

arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-common.dtsi
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * Copyright 2018-2019 Variscite Ltd. 3 * Copyright 2018-2019 Variscite Ltd.
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 /dts-v1/; 16 /dts-v1/;
17 17
18 #include "../freescale/fsl-imx8mq.dtsi" 18 #include "../freescale/fsl-imx8mq.dtsi"
19 19
20 / { 20 / {
21 compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq"; 21 compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq";
22 22
23 regulators { 23 regulators {
24 compatible = "simple-bus"; 24 compatible = "simple-bus";
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <0>; 26 #size-cells = <0>;
27 27
28 reg_usdhc2_vmmc: usdhc2_vmmc { 28 reg_usdhc2_vmmc: usdhc2_vmmc {
29 compatible = "regulator-fixed"; 29 compatible = "regulator-fixed";
30 regulator-name = "VSD_3V3"; 30 regulator-name = "VSD_3V3";
31 regulator-min-microvolt = <3300000>; 31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>;
33 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 33 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
34 off-on-delay = <20000>; 34 off-on-delay = <20000>;
35 enable-active-high; 35 enable-active-high;
36 }; 36 };
37 37
38 reg_audio: audio_vdd { 38 reg_audio: audio_vdd {
39 compatible = "regulator-fixed"; 39 compatible = "regulator-fixed";
40 regulator-name = "sgtl5000_supply"; 40 regulator-name = "sgtl5000_supply";
41 regulator-min-microvolt = <3300000>; 41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>;
43 regulator-always-on; 43 regulator-always-on;
44 }; 44 };
45 45
46 reg_3p3v: 3p3v { 46 reg_3p3v: 3p3v {
47 compatible = "regulator-fixed"; 47 compatible = "regulator-fixed";
48 regulator-name = "3P3V"; 48 regulator-name = "3P3V";
49 regulator-min-microvolt = <3300000>; 49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>; 50 regulator-max-microvolt = <3300000>;
51 regulator-always-on; 51 regulator-always-on;
52 }; 52 };
53 53
54 reg_5p0v: 5p0v { 54 reg_5p0v: 5p0v {
55 compatible = "regulator-fixed"; 55 compatible = "regulator-fixed";
56 regulator-name = "5P0V"; 56 regulator-name = "5P0V";
57 regulator-min-microvolt = <5000000>; 57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>; 58 regulator-max-microvolt = <5000000>;
59 regulator-always-on; 59 regulator-always-on;
60 }; 60 };
61 61
62 reg_1p8v: 1p8v { 62 reg_1p8v: 1p8v {
63 compatible = "regulator-fixed"; 63 compatible = "regulator-fixed";
64 regulator-name = "1P8V"; 64 regulator-name = "1P8V";
65 regulator-min-microvolt = <1800000>; 65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>; 66 regulator-max-microvolt = <1800000>;
67 regulator-always-on; 67 regulator-always-on;
68 }; 68 };
69 69
70 reg_gpio_dvfs: regulator-gpio { 70 reg_gpio_dvfs: regulator-gpio {
71 compatible = "regulator-gpio"; 71 compatible = "regulator-gpio";
72 pinctrl-names = "default"; 72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_dvfs>; 73 pinctrl-0 = <&pinctrl_dvfs>;
74 regulator-min-microvolt = <900000>; 74 regulator-min-microvolt = <900000>;
75 regulator-max-microvolt = <1000000>; 75 regulator-max-microvolt = <1000000>;
76 regulator-name = "gpio_dvfs"; 76 regulator-name = "gpio_dvfs";
77 regulator-type = "voltage"; 77 regulator-type = "voltage";
78 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 78 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
79 states = <900000 0x1 1000000 0x0>; 79 states = <900000 0x1 1000000 0x0>;
80 }; 80 };
81 }; 81 };
82 82
83 sound-sgtl5000 { 83 sound-sgtl5000 {
84 compatible = "fsl,imx-audio-sgtl5000", 84 compatible = "fsl,imx-audio-sgtl5000",
85 "smarc,imx8mq-audio-sgtl5000"; 85 "smarc,imx8mq-audio-sgtl5000";
86 model = "imx8mq-audio-sgtl5000"; 86 model = "imx8mq-audio-sgtl5000";
87 ssi-controller = <&sai2>; 87 ssi-controller = <&sai2>;
88 audio-codec = <&codec>; 88 audio-codec = <&codec>;
89 audio-routing = 89 audio-routing =
90 "MIC_IN", "Mic Jack", 90 "MIC_IN", "Mic Jack",
91 "Mic Jack", "Mic Bias", 91 "Mic Jack", "Mic Bias",
92 "Headphone Jack", "HP_OUT"; 92 "Headphone Jack", "HP_OUT";
93 fsl,no-audmux; 93 fsl,no-audmux;
94 }; 94 };
95 95
96 sound-hdmi { 96 sound-hdmi {
97 compatible = "fsl,imx8mq-evk-cdnhdmi", 97 compatible = "fsl,imx8mq-evk-cdnhdmi",
98 "fsl,imx-audio-cdnhdmi"; 98 "fsl,imx-audio-cdnhdmi";
99 model = "imx-audio-hdmi"; 99 model = "imx-audio-hdmi";
100 audio-cpu = <&sai4>; 100 audio-cpu = <&sai4>;
101 protocol = <1>; 101 protocol = <1>;
102 hdmi-out; 102 hdmi-out;
103 constraint-rate = <44100>, 103 constraint-rate = <44100>,
104 <88200>, 104 <88200>,
105 <176400>, 105 <176400>,
106 <32000>, 106 <32000>,
107 <48000>, 107 <48000>,
108 <96000>, 108 <96000>,
109 <192000>; 109 <192000>;
110 status = "disabled"; 110 status = "disabled";
111 }; 111 };
112 112
113 sound-hdmi-arc { 113 sound-hdmi-arc {
114 compatible = "fsl,imx-audio-spdif"; 114 compatible = "fsl,imx-audio-spdif";
115 model = "imx-hdmi-arc"; 115 model = "imx-hdmi-arc";
116 spdif-controller = <&spdif2>; 116 spdif-controller = <&spdif2>;
117 spdif-in; 117 spdif-in;
118 status = "disabled"; 118 status = "disabled";
119 }; 119 };
120 120
121 backlight: backlight { 121 backlight: backlight {
122 compatible = "pwm-backlight"; 122 compatible = "pwm-backlight";
123 enable-gpios = <&gpio4 0 0>; /* Backlight Enable */ 123 enable-gpios = <&gpio4 0 0>; /* Backlight Enable */
124 pwms = <&pwm1 0 1000000 0>; 124 pwms = <&pwm1 0 1000000 0>;
125 brightness-levels = < 0 1 2 3 4 5 6 7 8 9 125 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
126 10 11 12 13 14 15 16 17 18 19 126 10 11 12 13 14 15 16 17 18 19
127 20 21 22 23 24 25 26 27 28 29 127 20 21 22 23 24 25 26 27 28 29
128 30 31 32 33 34 35 36 37 38 39 128 30 31 32 33 34 35 36 37 38 39
129 40 41 42 43 44 45 46 47 48 49 129 40 41 42 43 44 45 46 47 48 49
130 50 51 52 53 54 55 56 57 58 59 130 50 51 52 53 54 55 56 57 58 59
131 60 61 62 63 64 65 66 67 68 69 131 60 61 62 63 64 65 66 67 68 69
132 70 71 72 73 74 75 76 77 78 79 132 70 71 72 73 74 75 76 77 78 79
133 80 81 82 83 84 85 86 87 88 89 133 80 81 82 83 84 85 86 87 88 89
134 90 91 92 93 94 95 96 97 98 99 134 90 91 92 93 94 95 96 97 98 99
135 100>; 135 100>;
136 default-brightness-level = <80>; 136 default-brightness-level = <80>;
137 status = "disabled"; 137 status = "disabled";
138 }; 138 };
139 139
140 /* external oscillator of mcp2515 on SPI1.0 and SPI1.1 */ 140 /* external oscillator of mcp2515 on SPI1.0 and SPI1.1 */
141 can_osc: can_osc { 141 can_osc: can_osc {
142 compatible = "fixed-clock"; 142 compatible = "fixed-clock";
143 #clock-cells = <0>; 143 #clock-cells = <0>;
144 clock-frequency = <25000000>; 144 clock-frequency = <25000000>;
145 }; 145 };
146 }; 146 };
147 147
148 &clk { 148 &clk {
149 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; 149 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
150 assigned-clock-rates = <786432000>, <722534400>; 150 assigned-clock-rates = <786432000>, <722534400>;
151 }; 151 };
152 152
153 &iomuxc { 153 &iomuxc {
154 pinctrl-names = "default"; 154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_hog>; 155 pinctrl-0 = <&pinctrl_hog>;
156 156
157 smarcimx8mq { 157 smarcimx8mq {
158 pinctrl_hog: hoggrp { 158 pinctrl_hog: hoggrp {
159 fsl,pins = < 159 fsl,pins = <
160 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /*RESET_OUT#*/ 160 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /*RESET_OUT#*/
161 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 /*FEC_IRQ#*/ 161 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 /*FEC_IRQ#*/
162 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x41 /*PCIE_WAKE#*/ 162 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x41 /*PCIE_WAKE#*/
163 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x41 /*LID#*/ 163 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x41 /*LID#*/
164 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 /*SLEEP#*/ 164 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 /*SLEEP#*/
165 MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 /*CHARGING#*/ 165 MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 /*CHARGING#*/
166 MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 /*CHARGER_PRSNT#*/ 166 MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 /*CHARGER_PRSNT#*/
167 MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /*CARRIER_STBY#*/ 167 MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /*CARRIER_STBY#*/
168 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 /*BATLOW#*/ 168 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 /*BATLOW#*/
169 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x41 /*USB0_EN_OC#*/ 169 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x41 /*USB0_EN_OC#*/
170 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x41 /*USB2_EN_OC#*/ 170 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x41 /*USB2_EN_OC#*/
171 MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x41 /*USB3_EN_OC#*/ 171 MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x41 /*USB3_EN_OC#*/
172 >; 172 >;
173 }; 173 };
174 174
175 pinctrl_csi1: csi1grp { 175 pinctrl_csi1: csi1grp {
176 fsl,pins = < 176 fsl,pins = <
177 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /*GPIO0*/ 177 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /*GPIO0*/
178 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /*GPIO2*/ 178 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /*GPIO2*/
179 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 179 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
180 >; 180 >;
181 }; 181 };
182 182
183 pinctrl_csi2: csi2grp { 183 pinctrl_csi2: csi2grp {
184 fsl,pins = < 184 fsl,pins = <
185 MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /*GPIO1*/ 185 MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /*GPIO1*/
186 MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /*GPIO3*/ 186 MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /*GPIO3*/
187 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 187 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
188 >; 188 >;
189 }; 189 };
190 190
191 pinctrl_fec1: fec1grp { 191 pinctrl_fec1: fec1grp {
192 fsl,pins = < 192 fsl,pins = <
193 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 193 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
194 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 194 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
195 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 195 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
196 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 196 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
197 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 197 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
198 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 198 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
199 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 199 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
200 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 200 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
201 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 201 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
202 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 202 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
203 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 203 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
204 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 204 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
205 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 205 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
206 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 206 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
207 >; 207 >;
208 }; 208 };
209 209
210 pinctrl_i2c1: i2c1grp { 210 pinctrl_i2c1: i2c1grp {
211 fsl,pins = < 211 fsl,pins = <
212 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 212 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
213 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 213 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
214 >; 214 >;
215 }; 215 };
216 216
217 pinctrl_i2c2: i2c2grp { 217 pinctrl_i2c2: i2c2grp {
218 fsl,pins = < 218 fsl,pins = <
219 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 219 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
220 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 220 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
221 >; 221 >;
222 }; 222 };
223 223
224 pinctrl_i2c3: i2c3grp { 224 pinctrl_i2c3: i2c3grp {
225 fsl,pins = < 225 fsl,pins = <
226 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f 226 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
227 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f 227 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
228 >; 228 >;
229 }; 229 };
230 230
231 pinctrl_i2c4: i2c4grp { 231 pinctrl_i2c4: i2c4grp {
232 fsl,pins = < 232 fsl,pins = <
233 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f 233 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
234 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f 234 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
235 >; 235 >;
236 }; 236 };
237 237
238 pinctrl_pcie0: pcie0grp { 238 pinctrl_pcie0: pcie0grp {
239 fsl,pins = < 239 fsl,pins = <
240 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16 240 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16
241 >; 241 >;
242 }; 242 };
243 243
244 pinctrl_pcie1: pcie1grp { 244 pinctrl_pcie1: pcie1grp {
245 fsl,pins = < 245 fsl,pins = <
246 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16 246 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16
247 >; 247 >;
248 }; 248 };
249 249
250 pinctrl_dvfs: dvfsgrp { 250 pinctrl_dvfs: dvfsgrp {
251 fsl,pins = < 251 fsl,pins = <
252 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 252 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
253 >; 253 >;
254 }; 254 };
255 255
256 pinctrl_typec: typecgrp { 256 pinctrl_typec: typecgrp {
257 fsl,pins = < 257 fsl,pins = <
258 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 258 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
259 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 259 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
260 >; 260 >;
261 }; 261 };
262 262
263 pinctrl_qspi: qspigrp { 263 pinctrl_qspi: qspigrp {
264 fsl,pins = < 264 fsl,pins = <
265 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 265 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
266 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 266 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
267 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 267 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
268 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 268 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
269 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 269 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
270 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 270 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
271 271
272 >; 272 >;
273 }; 273 };
274 274
275 pinctrl_uart1: uart1grp { 275 pinctrl_uart1: uart1grp {
276 fsl,pins = < 276 fsl,pins = <
277 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 277 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
278 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 278 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
279 >; 279 >;
280 }; 280 };
281 281
282 pinctrl_uart2: uart2grp { 282 pinctrl_uart2: uart2grp {
283 fsl,pins = < 283 fsl,pins = <
284 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 284 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
285 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 285 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
286 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 286 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
287 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 287 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
288 >; 288 >;
289 }; 289 };
290 290
291 pinctrl_uart3: uart3grp { 291 pinctrl_uart3: uart3grp {
292 fsl,pins = < 292 fsl,pins = <
293 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 293 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
294 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 294 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
295 >; 295 >;
296 }; 296 };
297 297
298 pinctrl_uart4: uart4grp { 298 pinctrl_uart4: uart4grp {
299 fsl,pins = < 299 fsl,pins = <
300 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 300 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
301 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 301 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
302 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 302 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
303 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 303 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
304 >; 304 >;
305 }; 305 };
306 306
307 pinctrl_usdhc1: usdhc1grp { 307 pinctrl_usdhc1: usdhc1grp {
308 fsl,pins = < 308 fsl,pins = <
309 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 309 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
310 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 310 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
311 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 311 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
312 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 312 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
313 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 313 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
314 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 314 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
315 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 315 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
316 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 316 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
317 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 317 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
318 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 318 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
319 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 319 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
320 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 320 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
321 >; 321 >;
322 }; 322 };
323 323
324 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 324 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
325 fsl,pins = < 325 fsl,pins = <
326 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 326 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
327 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 327 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
328 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 328 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
329 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 329 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
330 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 330 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
331 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 331 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
332 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 332 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
333 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 333 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
334 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 334 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
335 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 335 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
336 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 336 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
337 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 337 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
338 >; 338 >;
339 }; 339 };
340 340
341 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 341 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
342 fsl,pins = < 342 fsl,pins = <
343 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 343 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
344 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 344 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
345 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 345 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
346 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 346 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
347 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 347 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
348 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 348 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
349 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 349 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
350 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 350 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
351 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 351 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
352 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 352 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
353 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 353 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
354 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 354 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
355 >; 355 >;
356 }; 356 };
357 357
358 pinctrl_usdhc2_gpio: usdhc2grpgpio { 358 pinctrl_usdhc2_gpio: usdhc2grpgpio {
359 fsl,pins = < 359 fsl,pins = <
360 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 360 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
361 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 361 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
362 >; 362 >;
363 }; 363 };
364 364
365 pinctrl_usdhc2: usdhc2grp { 365 pinctrl_usdhc2: usdhc2grp {
366 fsl,pins = < 366 fsl,pins = <
367 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 367 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
368 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 368 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
369 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 369 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
370 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 370 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
371 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 371 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
372 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 372 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
373 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 373 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
374 >; 374 >;
375 }; 375 };
376 376
377 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 377 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
378 fsl,pins = < 378 fsl,pins = <
379 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 379 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
380 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 380 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
381 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 381 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
382 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 382 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
383 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 383 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
384 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 384 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
385 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 385 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
386 >; 386 >;
387 }; 387 };
388 388
389 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 389 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
390 fsl,pins = < 390 fsl,pins = <
391 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 391 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
392 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf 392 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
393 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf 393 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
394 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf 394 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
395 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf 395 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
396 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf 396 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
397 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 397 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
398 >; 398 >;
399 }; 399 };
400 400
401 pinctrl_sai1_pcm: sai1grp_pcm { 401 pinctrl_sai1_pcm: sai1grp_pcm {
402 fsl,pins = < 402 fsl,pins = <
403 MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 403 MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
404 MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 404 MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
405 MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 405 MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
406 MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 406 MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
407 MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 407 MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
408 MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 408 MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
409 MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 409 MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
410 MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 410 MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
411 MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 411 MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
412 MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 412 MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
413 MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 413 MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
414 MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 414 MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
415 >; 415 >;
416 }; 416 };
417 417
418 pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m { 418 pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m {
419 fsl,pins = < 419 fsl,pins = <
420 MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 420 MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6
421 MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 421 MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
422 MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 422 MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
423 MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 423 MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
424 MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 424 MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
425 MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 425 MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
426 MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 426 MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
427 MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 427 MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
428 MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 428 MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
429 MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 429 MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
430 MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 430 MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
431 MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 431 MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
432 >; 432 >;
433 }; 433 };
434 434
435 pinctrl_sai1_dsd: sai1grp_dsd { 435 pinctrl_sai1_dsd: sai1grp_dsd {
436 fsl,pins = < 436 fsl,pins = <
437 MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 437 MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
438 MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 438 MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
439 MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 439 MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6
440 MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 440 MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
441 MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 441 MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
442 MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 442 MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
443 MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 443 MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
444 MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 444 MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
445 MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 445 MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
446 MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 446 MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
447 MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 447 MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
448 MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 448 MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
449 >; 449 >;
450 }; 450 };
451 451
452 pinctrl_sai2: sai2grp { 452 pinctrl_sai2: sai2grp {
453 fsl,pins = < 453 fsl,pins = <
454 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 454 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
455 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 455 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
456 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 456 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
457 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 457 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
458 MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 458 MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
459 >; 459 >;
460 }; 460 };
461 461
462 pinctrl_sai3: sai3grp { 462 pinctrl_sai3: sai3grp {
463 fsl,pins = < 463 fsl,pins = <
464 MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 464 MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
465 MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 465 MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
466 MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 466 MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
467 MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 467 MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
468 >; 468 >;
469 }; 469 };
470 470
471 pinctrl_sai5: sai5grp { 471 pinctrl_sai5: sai5grp {
472 fsl,pins = < 472 fsl,pins = <
473 MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 473 MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
474 MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 474 MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
475 MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 475 MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
476 MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 476 MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
477 MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 477 MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6
478 MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 478 MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6
479 MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 479 MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6
480 >; 480 >;
481 }; 481 };
482 482
483 pinctrl_spdif1: spdif1grp { 483 pinctrl_spdif1: spdif1grp {
484 fsl,pins = < 484 fsl,pins = <
485 MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 485 MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
486 MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 486 MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
487 >; 487 >;
488 }; 488 };
489 489
490 pinctrl_wdog: wdoggrp { 490 pinctrl_wdog: wdoggrp {
491 fsl,pins = < 491 fsl,pins = <
492 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 492 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
493 >; 493 >;
494 }; 494 };
495 495
496 pinctrl_pwm1: pwm1grp { 496 pinctrl_pwm1: pwm1grp {
497 fsl,pins = < 497 fsl,pins = <
498 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06 498 MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06
499 >; 499 >;
500 }; 500 };
501 501
502 pinctrl_ecspi1: ecspi1grp { 502 pinctrl_ecspi1: ecspi1grp {
503 fsl,pins = < 503 fsl,pins = <
504 MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x16 504 MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x16
505 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x16 505 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x16
506 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x16 506 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x16
507 MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x16 507 MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x16
508 MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x16 508 MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x16
509 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 509 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
510 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16 510 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
511 >; 511 >;
512 }; 512 };
513 513
514 pinctrl_lvds: lvdsgrp { 514 pinctrl_lvds: lvdsgrp {
515 fsl,pins = < 515 fsl,pins = <
516 MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x16 516 MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x16
517 >; 517 >;
518 }; 518 };
519 }; 519 };
520 }; 520 };
521 521
522 &fec1 { 522 &fec1 {
523 pinctrl-names = "default"; 523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_fec1>; 524 pinctrl-0 = <&pinctrl_fec1>;
525 phy-mode = "rgmii-id"; 525 phy-mode = "rgmii-id";
526 phy-handle = <&ethphy0>; 526 phy-handle = <&ethphy0>;
527 fsl,magic-packet; 527 fsl,magic-packet;
528 status = "okay"; 528 status = "okay";
529 529
530 mdio { 530 mdio {
531 #address-cells = <1>; 531 #address-cells = <1>;
532 #size-cells = <0>; 532 #size-cells = <0>;
533 533
534 ethphy0: ethernet-phy@0 { 534 ethphy0: ethernet-phy@0 {
535 compatible = "ethernet-phy-ieee802.3-c22"; 535 compatible = "ethernet-phy-ieee802.3-c22";
536 reg = <6>; 536 reg = <6>;
537 at803x,led-act-blind-workaround; 537 at803x,led-act-blind-workaround;
538 at803x,eee-disabled; 538 at803x,eee-disabled;
539 }; 539 };
540 }; 540 };
541 }; 541 };
542 542
543 &i2c1 { 543 &i2c1 {
544 clock-frequency = <100000>; 544 clock-frequency = <100000>;
545 pinctrl-names = "default"; 545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_i2c1>; 546 pinctrl-0 = <&pinctrl_i2c1>;
547 status = "okay"; 547 status = "okay";
548 548
549 pmic: pfuze100@08 { 549 pmic: pfuze100@08 {
550 compatible = "fsl,pfuze100"; 550 compatible = "fsl,pfuze100";
551 reg = <0x08>; 551 reg = <0x08>;
552 552
553 regulators { 553 regulators {
554 sw1a_reg: sw1ab { 554 sw1a_reg: sw1ab {
555 regulator-min-microvolt = <300000>; 555 regulator-min-microvolt = <300000>;
556 regulator-max-microvolt = <1875000>; 556 regulator-max-microvolt = <1875000>;
557 }; 557 };
558 558
559 sw1c_reg: sw1c { 559 sw1c_reg: sw1c {
560 regulator-min-microvolt = <300000>; 560 regulator-min-microvolt = <300000>;
561 regulator-max-microvolt = <1875000>; 561 regulator-max-microvolt = <1875000>;
562 }; 562 };
563 563
564 sw2_reg: sw2 { 564 sw2_reg: sw2 {
565 regulator-min-microvolt = <800000>; 565 regulator-min-microvolt = <800000>;
566 regulator-max-microvolt = <3300000>; 566 regulator-max-microvolt = <3300000>;
567 regulator-always-on; 567 regulator-always-on;
568 }; 568 };
569 569
570 sw3a_reg: sw3ab { 570 sw3a_reg: sw3ab {
571 regulator-min-microvolt = <400000>; 571 regulator-min-microvolt = <400000>;
572 regulator-max-microvolt = <1975000>; 572 regulator-max-microvolt = <1975000>;
573 regulator-always-on; 573 regulator-always-on;
574 }; 574 };
575 575
576 sw4_reg: sw4 { 576 sw4_reg: sw4 {
577 regulator-min-microvolt = <800000>; 577 regulator-min-microvolt = <800000>;
578 regulator-max-microvolt = <3300000>; 578 regulator-max-microvolt = <3300000>;
579 regulator-always-on; 579 regulator-always-on;
580 }; 580 };
581 581
582 swbst_reg: swbst { 582 swbst_reg: swbst {
583 regulator-min-microvolt = <5000000>; 583 regulator-min-microvolt = <5000000>;
584 regulator-max-microvolt = <5150000>; 584 regulator-max-microvolt = <5150000>;
585 }; 585 };
586 586
587 snvs_reg: vsnvs { 587 snvs_reg: vsnvs {
588 regulator-min-microvolt = <1000000>; 588 regulator-min-microvolt = <1000000>;
589 regulator-max-microvolt = <3000000>; 589 regulator-max-microvolt = <3000000>;
590 regulator-always-on; 590 regulator-always-on;
591 }; 591 };
592 592
593 vref_reg: vrefddr { 593 vref_reg: vrefddr {
594 regulator-always-on; 594 regulator-always-on;
595 }; 595 };
596 596
597 vgen1_reg: vgen1 { 597 vgen1_reg: vgen1 {
598 regulator-min-microvolt = <800000>; 598 regulator-min-microvolt = <800000>;
599 regulator-max-microvolt = <1550000>; 599 regulator-max-microvolt = <1550000>;
600 }; 600 };
601 601
602 vgen2_reg: vgen2 { 602 vgen2_reg: vgen2 {
603 regulator-min-microvolt = <800000>; 603 regulator-min-microvolt = <800000>;
604 regulator-max-microvolt = <1550000>; 604 regulator-max-microvolt = <1550000>;
605 regulator-always-on; 605 regulator-always-on;
606 }; 606 };
607 607
608 vgen3_reg: vgen3 { 608 vgen3_reg: vgen3 {
609 regulator-min-microvolt = <1800000>; 609 regulator-min-microvolt = <1800000>;
610 regulator-max-microvolt = <3300000>; 610 regulator-max-microvolt = <3300000>;
611 regulator-always-on; 611 regulator-always-on;
612 }; 612 };
613 613
614 vgen4_reg: vgen4 { 614 vgen4_reg: vgen4 {
615 regulator-min-microvolt = <1800000>; 615 regulator-min-microvolt = <1800000>;
616 regulator-max-microvolt = <3300000>; 616 regulator-max-microvolt = <3300000>;
617 regulator-always-on; 617 regulator-always-on;
618 }; 618 };
619 619
620 vgen5_reg: vgen5 { 620 vgen5_reg: vgen5 {
621 regulator-min-microvolt = <1800000>; 621 regulator-min-microvolt = <1800000>;
622 regulator-max-microvolt = <3300000>; 622 regulator-max-microvolt = <3300000>;
623 regulator-always-on; 623 regulator-always-on;
624 }; 624 };
625 625
626 vgen6_reg: vgen6 { 626 vgen6_reg: vgen6 {
627 regulator-min-microvolt = <1800000>; 627 regulator-min-microvolt = <1800000>;
628 regulator-max-microvolt = <3300000>; 628 regulator-max-microvolt = <3300000>;
629 }; 629 };
630 }; 630 };
631 }; 631 };
632 632
633 s35390a: s35390a@30 { 633 s35390a: s35390a@30 {
634 compatible = "s35390a"; 634 compatible = "s35390a";
635 reg = <0x30>; 635 reg = <0x30>;
636 }; 636 };
637 637
638 cape_eeprom0: cape_eeprom@57 { 638 cape_eeprom0: cape_eeprom@57 {
639 compatible = "at,24c256"; 639 compatible = "at,24c256";
640 reg = <0x57>; 640 reg = <0x57>;
641 }; 641 };
642 642
643 codec: sgtl5000@0a { 643 codec: sgtl5000@0a {
644 compatible = "fsl,sgtl5000"; 644 compatible = "fsl,sgtl5000";
645 reg = <0x0a>; 645 reg = <0x0a>;
646 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 646 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
647 clock-names = "mclk"; 647 clock-names = "mclk";
648 VDDA-supply = <&reg_audio>; 648 VDDA-supply = <&reg_audio>;
649 VDDIO-supply = <&reg_1p8v>; 649 VDDIO-supply = <&reg_1p8v>;
650 status = "okay"; 650 status = "okay";
651 }; 651 };
652 }; 652 };
653 653
654 &i2c2 { 654 &i2c2 {
655 clock-frequency = <100000>; 655 clock-frequency = <100000>;
656 pinctrl-names = "default"; 656 pinctrl-names = "default";
657 pinctrl-0 = <&pinctrl_i2c2>; 657 pinctrl-0 = <&pinctrl_i2c2>;
658 status = "okay"; 658 status = "okay";
659 659
660 dsi_lvds_bridge: sn65dsi84@2c { 660 dsi_lvds_bridge: sn65dsi84@2c {
661 status = "disabled"; 661 status = "disabled";
662 reg = <0x2c>; 662 reg = <0x2c>;
663 compatible = "ti,sn65dsi84"; 663 compatible = "ti,sn65dsi84";
664 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 664 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
665 interrupt-parent = <&gpio4>; 665 interrupt-parent = <&gpio4>;
666 interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 666 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
667 667
668 /* AUO G070VW01 7-inch 800x480 LVDS Display */ 668 /* AUO G070VW01 7-inch 800x480 LVDS Display */
669 sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 669 sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
670 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 670 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
671 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 671 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
672 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 672 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
673 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 673 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
674 0x3C 0x3D 0x3E 0xE0 0x0D>; 674 0x3C 0x3D 0x3E 0xE0 0x0D>;
675 675
676 sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00 676 sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00
677 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00 677 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00
678 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 678 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
679 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 679 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00
680 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 680 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00
681 0x00 0x00 0x00 0x01 0x01>; 681 0x00 0x00 0x00 0x01 0x01>;
682 682
683 /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */ 683 /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */
684 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 684 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
685 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 685 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
686 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 686 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
687 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 687 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
688 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 688 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
689 0x3C 0x3D 0x3E 0xE0 0x0D>; 689 0x3C 0x3D 0x3E 0xE0 0x0D>;
690 690
691 sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00 691 sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00
692 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00 692 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00
693 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 693 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00
694 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00 694 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00
695 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 695 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00
696 0x00 0x00 0x00 0x01 0x01>;*/ 696 0x00 0x00 0x00 0x01 0x01>;*/
697 697
698 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */ 698 /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */
699 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 699 /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13
700 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 700 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23
701 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 701 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
702 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 702 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
703 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 703 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B
704 0x3C 0x3D 0x3E 0xE0 0x0D>; 704 0x3C 0x3D 0x3E 0xE0 0x0D>;
705 705
706 sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00 706 sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00
707 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00 707 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00
708 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00 708 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00
709 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00 709 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00
710 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00 710 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00
711 0x00 0x00 0x00 0x01 0x01>;*/ 711 0x00 0x00 0x00 0x01 0x01>;*/
712 }; 712 };
713 713
714 ov5640_mipi: ov5640_mipi@3c { 714 ov5640_mipi: ov5640_mipi@3c {
715 compatible = "ovti,ov5640_mipi"; 715 compatible = "ovti,ov5640_mipi";
716 reg = <0x3c>; 716 reg = <0x3c>;
717 status = "okay"; 717 status = "okay";
718 pinctrl-names = "default"; 718 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_csi1>; 719 pinctrl-0 = <&pinctrl_csi1>;
720 clocks = <&clk IMX8MQ_CLK_CLKO2>; 720 clocks = <&clk IMX8MQ_CLK_CLKO2>;
721 clock-names = "csi_mclk"; 721 clock-names = "csi_mclk";
722 assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; 722 assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
723 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; 723 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
724 assigned-clock-rates = <20000000>; 724 assigned-clock-rates = <20000000>;
725 csi_id = <0>; 725 csi_id = <0>;
726 pwn-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /*GPIO0*/ 726 pwn-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /*GPIO0*/
727 rst-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; /*GPIO2*/ 727 rst-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; /*GPIO2*/
728 mclk = <20000000>; 728 mclk = <20000000>;
729 mclk_source = <0>; 729 mclk_source = <0>;
730 port { 730 port {
731 ov5640_mipi1_ep: endpoint { 731 ov5640_mipi1_ep: endpoint {
732 remote-endpoint = <&mipi1_sensor_ep>; 732 remote-endpoint = <&mipi1_sensor_ep>;
733 }; 733 };
734 }; 734 };
735 }; 735 };
736 }; 736 };
737 737
738 &i2c3 { 738 &i2c3 {
739 clock-frequency = <100000>; 739 clock-frequency = <100000>;
740 pinctrl-names = "default"; 740 pinctrl-names = "default";
741 pinctrl-0 = <&pinctrl_i2c3>; 741 pinctrl-0 = <&pinctrl_i2c3>;
742 status = "okay"; 742 status = "okay";
743 743
744 baseboard_eeprom: baseboard_eeprom@50 { 744 baseboard_eeprom: baseboard_eeprom@50 {
745 compatible = "at,24c256"; 745 compatible = "at,24c256";
746 reg = <0x50>; 746 reg = <0x50>;
747 }; 747 };
748 }; 748 };
749 749
750 &i2c4 { 750 &i2c4 {
751 clock-frequency = <100000>; 751 clock-frequency = <100000>;
752 pinctrl-names = "default"; 752 pinctrl-names = "default";
753 pinctrl-0 = <&pinctrl_i2c4>; 753 pinctrl-0 = <&pinctrl_i2c4>;
754 status = "okay"; 754 status = "okay";
755 755
756 ov5640_mipi2: ov5640_mipi2@3c { 756 ov5640_mipi2: ov5640_mipi2@3c {
757 compatible = "ovti,ov5640_mipi"; 757 compatible = "ovti,ov5640_mipi";
758 reg = <0x3c>; 758 reg = <0x3c>;
759 status = "okay"; 759 status = "okay";
760 pinctrl-names = "default"; 760 pinctrl-names = "default";
761 pinctrl-0 = <&pinctrl_csi2>; 761 pinctrl-0 = <&pinctrl_csi2>;
762 clocks = <&clk IMX8MQ_CLK_CLKO2>; 762 clocks = <&clk IMX8MQ_CLK_CLKO2>;
763 clock-names = "csi_mclk"; 763 clock-names = "csi_mclk";
764 assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; 764 assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
765 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; 765 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
766 assigned-clock-rates = <20000000>; 766 assigned-clock-rates = <20000000>;
767 csi_id = <1>; 767 csi_id = <1>;
768 pwn-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; /*GPIO1*/ 768 pwn-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; /*GPIO1*/
769 rst-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; /*GPIO3*/ 769 rst-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; /*GPIO3*/
770 mclk = <20000000>; 770 mclk = <20000000>;
771 mclk_source = <0>; 771 mclk_source = <0>;
772 port { 772 port {
773 ov5640_mipi2_ep: endpoint { 773 ov5640_mipi2_ep: endpoint {
774 remote-endpoint = <&mipi2_sensor_ep>; 774 remote-endpoint = <&mipi2_sensor_ep>;
775 }; 775 };
776 }; 776 };
777 }; 777 };
778 }; 778 };
779 779
780 &pcie0 { 780 &pcie0 {
781 pinctrl-names = "default"; 781 pinctrl-names = "default";
782 pinctrl-0 = <&pinctrl_pcie0>; 782 pinctrl-0 = <&pinctrl_pcie0>;
783 reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; 783 reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
784 ext_osc = <1>; 784 ext_osc = <1>;
785 status = "okay"; 785 status = "okay";
786 }; 786 };
787 787
788 &pcie1 { 788 &pcie1 {
789 pinctrl-names = "default"; 789 pinctrl-names = "default";
790 pinctrl-0 = <&pinctrl_pcie1>; 790 pinctrl-0 = <&pinctrl_pcie1>;
791 reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; 791 reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
792 ext_osc = <1>; 792 ext_osc = <1>;
793 status = "okay"; 793 status = "okay";
794 }; 794 };
795 795
796 /* SER3 */ 796 /* SER3 */
797 &uart1 { 797 &uart1 {
798 pinctrl-names = "default"; 798 pinctrl-names = "default";
799 pinctrl-0 = <&pinctrl_uart1>; 799 pinctrl-0 = <&pinctrl_uart1>;
800 assigned-clocks = <&clk IMX8MQ_CLK_UART1>; 800 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
801 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 801 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
802 status = "okay"; 802 status = "okay";
803 }; 803 };
804 804
805 /* SER2 */ 805 /* SER2 */
806 &uart2 { 806 &uart2 {
807 pinctrl-names = "default"; 807 pinctrl-names = "default";
808 pinctrl-0 = <&pinctrl_uart2>; 808 pinctrl-0 = <&pinctrl_uart2>;
809 assigned-clocks = <&clk IMX8MQ_CLK_UART2>; 809 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
810 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 810 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
811 fsl,uart-has-rtscts; 811 fsl,uart-has-rtscts;
812 status = "okay"; 812 status = "okay";
813 }; 813 };
814 814
815 /* SER1 */ 815 /* SER1 */
816 &uart3 { 816 &uart3 {
817 pinctrl-names = "default"; 817 pinctrl-names = "default";
818 pinctrl-0 = <&pinctrl_uart3>; 818 pinctrl-0 = <&pinctrl_uart3>;
819 assigned-clocks = <&clk IMX8MQ_CLK_UART3>; 819 assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
820 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 820 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
821 status = "okay"; 821 status = "okay";
822 }; 822 };
823 823
824 /* SER0 */ 824 /* SER0 */
825 &uart4 { 825 &uart4 {
826 pinctrl-names = "default"; 826 pinctrl-names = "default";
827 pinctrl-0 = <&pinctrl_uart4>; 827 pinctrl-0 = <&pinctrl_uart4>;
828 assigned-clocks = <&clk IMX8MQ_CLK_UART4>; 828 assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
829 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 829 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
830 fsl,uart-has-rtscts; 830 fsl,uart-has-rtscts;
831 status = "okay"; 831 status = "okay";
832 }; 832 };
833 833
834 &qspi { 834 &qspi {
835 pinctrl-names = "default"; 835 pinctrl-names = "default";
836 pinctrl-0 = <&pinctrl_qspi>; 836 pinctrl-0 = <&pinctrl_qspi>;
837 status = "okay"; 837 status = "okay";
838 }; 838 };
839 839
840 /* eMMC */ 840 /* eMMC */
841 &usdhc1 { 841 &usdhc1 {
842 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 842 pinctrl-names = "default", "state_100mhz", "state_200mhz";
843 pinctrl-0 = <&pinctrl_usdhc1>; 843 pinctrl-0 = <&pinctrl_usdhc1>;
844 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 844 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
845 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 845 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
846 bus-width = <8>; 846 bus-width = <8>;
847 non-removable; 847 non-removable;
848 status = "okay"; 848 status = "okay";
849 }; 849 };
850 850
851 &usdhc2 { 851 &usdhc2 {
852 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 852 pinctrl-names = "default";
853 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 853 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
854 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
855 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
856 bus-width = <4>; 854 bus-width = <4>;
857 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 855 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
858 vmmc-supply = <&reg_usdhc2_vmmc>; 856 vmmc-supply = <&reg_usdhc2_vmmc>;
859 status = "okay"; 857 status = "okay";
860 }; 858 };
861 859
862 &usb3_phy0 { 860 &usb3_phy0 {
863 status = "okay"; 861 status = "okay";
864 }; 862 };
865 863
866 &usb3_0 { 864 &usb3_0 {
867 status = "okay"; 865 status = "okay";
868 }; 866 };
869 867
870 &usb_dwc3_0 { 868 &usb_dwc3_0 {
871 status = "okay"; 869 status = "okay";
872 dr_mode = "host"; 870 dr_mode = "host";
873 }; 871 };
874 872
875 &usb3_phy1 { 873 &usb3_phy1 {
876 status = "okay"; 874 status = "okay";
877 }; 875 };
878 876
879 &usb3_1 { 877 &usb3_1 {
880 status = "okay"; 878 status = "okay";
881 }; 879 };
882 880
883 &usb_dwc3_1 { 881 &usb_dwc3_1 {
884 status = "okay"; 882 status = "okay";
885 dr_mode = "host"; 883 dr_mode = "host";
886 }; 884 };
887 885
888 &sai2 { 886 &sai2 {
889 pinctrl-names = "default"; 887 pinctrl-names = "default";
890 pinctrl-0 = <&pinctrl_sai2>; 888 pinctrl-0 = <&pinctrl_sai2>;
891 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 889 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
892 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 890 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
893 assigned-clock-rates = <24576000>; 891 assigned-clock-rates = <24576000>;
894 status = "okay"; 892 status = "okay";
895 }; 893 };
896 894
897 &sai3 { 895 &sai3 {
898 pinctrl-names = "default"; 896 pinctrl-names = "default";
899 pinctrl-0 = <&pinctrl_sai3>; 897 pinctrl-0 = <&pinctrl_sai3>;
900 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; 898 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
901 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 899 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
902 assigned-clock-rates = <24576000>; 900 assigned-clock-rates = <24576000>;
903 status = "okay"; 901 status = "okay";
904 }; 902 };
905 903
906 &sai4 { 904 &sai4 {
907 assigned-clocks = <&clk IMX8MQ_CLK_SAI4>; 905 assigned-clocks = <&clk IMX8MQ_CLK_SAI4>;
908 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 906 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
909 assigned-clock-rates = <24576000>; 907 assigned-clock-rates = <24576000>;
910 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>, 908 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
911 <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, 909 <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
912 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, 910 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
913 <&clk IMX8MQ_AUDIO_PLL2_OUT>; 911 <&clk IMX8MQ_AUDIO_PLL2_OUT>;
914 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 912 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
915 status = "okay"; 913 status = "okay";
916 }; 914 };
917 915
918 &spdif2 { 916 &spdif2 {
919 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; 917 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
920 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 918 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
921 assigned-clock-rates = <24576000>; 919 assigned-clock-rates = <24576000>;
922 status = "okay"; 920 status = "okay";
923 }; 921 };
924 922
925 &gpu_pd { 923 &gpu_pd {
926 power-supply = <&sw1a_reg>; 924 power-supply = <&sw1a_reg>;
927 }; 925 };
928 926
929 &vpu_pd { 927 &vpu_pd {
930 power-supply = <&sw1c_reg>; 928 power-supply = <&sw1c_reg>;
931 }; 929 };
932 930
933 &gpu { 931 &gpu {
934 status = "okay"; 932 status = "okay";
935 }; 933 };
936 934
937 &vpu { 935 &vpu {
938 status = "okay"; 936 status = "okay";
939 }; 937 };
940 938
941 &wdog1 { 939 &wdog1 {
942 pinctrl-names = "default"; 940 pinctrl-names = "default";
943 pinctrl-0 = <&pinctrl_wdog>; 941 pinctrl-0 = <&pinctrl_wdog>;
944 fsl,ext-reset-output; 942 fsl,ext-reset-output;
945 status = "okay"; 943 status = "okay";
946 }; 944 };
947 945
948 &mu { 946 &mu {
949 status = "okay"; 947 status = "okay";
950 }; 948 };
951 949
952 &resmem { 950 &resmem {
953 /* cma region is provided by kernel command line as cma=<size>M */ 951 /* cma region is provided by kernel command line as cma=<size>M */
954 /delete-node/ linux,cma; 952 /delete-node/ linux,cma;
955 953
956 /delete-node/ rpmsg@0xb8000000; 954 /delete-node/ rpmsg@0xb8000000;
957 rpmsg_reserved: rpmsg@0x40000000 { 955 rpmsg_reserved: rpmsg@0x40000000 {
958 no-map; 956 no-map;
959 reg = <0 0x40000000 0 0x400000>; 957 reg = <0 0x40000000 0 0x400000>;
960 }; 958 };
961 }; 959 };
962 960
963 &A53_0 { 961 &A53_0 {
964 operating-points = < 962 operating-points = <
965 /* kHz uV */ 963 /* kHz uV */
966 1500000 1000000 964 1500000 1000000
967 1300000 1000000 965 1300000 1000000
968 1000000 900000 966 1000000 900000
969 800000 900000 967 800000 900000
970 >; 968 >;
971 dc-supply = <&reg_gpio_dvfs>; 969 dc-supply = <&reg_gpio_dvfs>;
972 }; 970 };
973 971
974 &csi1_bridge { 972 &csi1_bridge {
975 fsl,mipi-mode; 973 fsl,mipi-mode;
976 fsl,two-8bit-sensor-mode; 974 fsl,two-8bit-sensor-mode;
977 status = "okay"; 975 status = "okay";
978 976
979 port { 977 port {
980 csi1_ep: endpoint { 978 csi1_ep: endpoint {
981 remote-endpoint = <&csi1_mipi_ep>; 979 remote-endpoint = <&csi1_mipi_ep>;
982 }; 980 };
983 }; 981 };
984 }; 982 };
985 983
986 &csi2_bridge { 984 &csi2_bridge {
987 fsl,mipi-mode; 985 fsl,mipi-mode;
988 fsl,two-8bit-sensor-mode; 986 fsl,two-8bit-sensor-mode;
989 status = "okay"; 987 status = "okay";
990 988
991 port { 989 port {
992 csi2_ep: endpoint { 990 csi2_ep: endpoint {
993 remote-endpoint = <&csi2_mipi_ep>; 991 remote-endpoint = <&csi2_mipi_ep>;
994 }; 992 };
995 }; 993 };
996 }; 994 };
997 995
998 &mipi_csi_1 { 996 &mipi_csi_1 {
999 #address-cells = <1>; 997 #address-cells = <1>;
1000 #size-cells = <0>; 998 #size-cells = <0>;
1001 status = "okay"; 999 status = "okay";
1002 port { 1000 port {
1003 mipi1_sensor_ep: endpoint1 { 1001 mipi1_sensor_ep: endpoint1 {
1004 remote-endpoint = <&ov5640_mipi1_ep>; 1002 remote-endpoint = <&ov5640_mipi1_ep>;
1005 data-lanes = <1 2>; 1003 data-lanes = <1 2>;
1006 }; 1004 };
1007 1005
1008 csi1_mipi_ep: endpoint2 { 1006 csi1_mipi_ep: endpoint2 {
1009 remote-endpoint = <&csi1_ep>; 1007 remote-endpoint = <&csi1_ep>;
1010 }; 1008 };
1011 }; 1009 };
1012 }; 1010 };
1013 1011
1014 &mipi_csi_2 { 1012 &mipi_csi_2 {
1015 #address-cells = <1>; 1013 #address-cells = <1>;
1016 #size-cells = <0>; 1014 #size-cells = <0>;
1017 status = "okay"; 1015 status = "okay";
1018 port { 1016 port {
1019 mipi2_sensor_ep: endpoint1 { 1017 mipi2_sensor_ep: endpoint1 {
1020 remote-endpoint = <&ov5640_mipi2_ep>; 1018 remote-endpoint = <&ov5640_mipi2_ep>;
1021 data-lanes = <1 2 3 4>; 1019 data-lanes = <1 2 3 4>;
1022 }; 1020 };
1023 1021
1024 csi2_mipi_ep: endpoint2 { 1022 csi2_mipi_ep: endpoint2 {
1025 remote-endpoint = <&csi2_ep>; 1023 remote-endpoint = <&csi2_ep>;
1026 }; 1024 };
1027 }; 1025 };
1028 }; 1026 };
1029 1027
1030 &mipi_dsi_bridge { 1028 &mipi_dsi_bridge {
1031 status = "disabled"; 1029 status = "disabled";
1032 1030
1033 panel@0 { 1031 panel@0 {
1034 reg = <0>; 1032 reg = <0>;
1035 status = "okay"; 1033 status = "okay";
1036 /* AUO G070VW01 800x480 LVDS Display */ 1034 /* AUO G070VW01 800x480 LVDS Display */
1037 compatible = "auo,g070vw01"; 1035 compatible = "auo,g070vw01";
1038 /* AUO G185XW01 1366x768 LVDS Display */ 1036 /* AUO G185XW01 1366x768 LVDS Display */
1039 /*compatible = "auo,g185xw01";*/ 1037 /*compatible = "auo,g185xw01";*/
1040 /* AUO G240HW01 1920x1080 LVDS Display */ 1038 /* AUO G240HW01 1920x1080 LVDS Display */
1041 /*compatible = "auo,g240hw01";*/ 1039 /*compatible = "auo,g240hw01";*/
1042 backlight = <&backlight>; 1040 backlight = <&backlight>;
1043 enable-gpios = <&gpio4 1 0>; /* Enable LCD_VDD_EN pin */ 1041 enable-gpios = <&gpio4 1 0>; /* Enable LCD_VDD_EN pin */
1044 dsi-lanes = <4>; 1042 dsi-lanes = <4>;
1045 /* AUO G070VW01 800x480 LVDS Display */ 1043 /* AUO G070VW01 800x480 LVDS Display */
1046 panel-width-mm = <152>; 1044 panel-width-mm = <152>;
1047 panel-height-mm = <91>; 1045 panel-height-mm = <91>;
1048 /* AUO G185XW01 1366x768 LVDS Display */ 1046 /* AUO G185XW01 1366x768 LVDS Display */
1049 /*panel-width-mm = <410>; 1047 /*panel-width-mm = <410>;
1050 panel-height-mm = <230>;*/ 1048 panel-height-mm = <230>;*/
1051 /* AUO G240HW01 1920x1080 LVDS Display */ 1049 /* AUO G240HW01 1920x1080 LVDS Display */
1052 /*panel-width-mm = <531>; 1050 /*panel-width-mm = <531>;
1053 panel-height-mm = <299>;*/ 1051 panel-height-mm = <299>;*/
1054 1052
1055 delay,prepare = <120>; 1053 delay,prepare = <120>;
1056 1054
1057 port { 1055 port {
1058 panel_in: endpoint { 1056 panel_in: endpoint {
1059 remote-endpoint = <&mipi_dsi_bridge_out>; 1057 remote-endpoint = <&mipi_dsi_bridge_out>;
1060 }; 1058 };
1061 }; 1059 };
1062 }; 1060 };
1063 1061
1064 port@1 { 1062 port@1 {
1065 mipi_dsi_bridge_out: endpoint { 1063 mipi_dsi_bridge_out: endpoint {
1066 remote-endpoint = <&panel_in>; 1064 remote-endpoint = <&panel_in>;
1067 }; 1065 };
1068 }; 1066 };
1069 }; 1067 };
1070 1068
1071 &ecspi1 { 1069 &ecspi1 {
1072 #address-cells = <1>; 1070 #address-cells = <1>;
1073 #size-cells = <0>; 1071 #size-cells = <0>;
1074 pinctrl-names = "default"; 1072 pinctrl-names = "default";
1075 pinctrl-0 = <&pinctrl_ecspi1>; 1073 pinctrl-0 = <&pinctrl_ecspi1>;
1076 cs-gpios = <&gpio5 9 0>, <&gpio1 0 0>, <&gpio3 15 0>, <&gpio3 17 0>; 1074 cs-gpios = <&gpio5 9 0>, <&gpio1 0 0>, <&gpio3 15 0>, <&gpio3 17 0>;
1077 fsl,spi-num-chipselects = <4>; 1075 fsl,spi-num-chipselects = <4>;
1078 status = "okay"; 1076 status = "okay";
1079 1077
1080 spidev@0 { 1078 spidev@0 {
1081 compatible = "rohm,dh2228fv"; 1079 compatible = "rohm,dh2228fv";
1082 reg = <0>; 1080 reg = <0>;
1083 spi-max-frequency = <24000000>; 1081 spi-max-frequency = <24000000>;
1084 }; 1082 };
1085 1083
1086 spidev@1 { 1084 spidev@1 {
1087 compatible = "rohm,dh2228fv"; 1085 compatible = "rohm,dh2228fv";
1088 reg = <1>; 1086 reg = <1>;
1089 spi-max-frequency = <24000000>; 1087 spi-max-frequency = <24000000>;
1090 }; 1088 };
1091 1089
1092 can1: can@2 { 1090 can1: can@2 {
1093 compatible = "microchip,mcp2515"; 1091 compatible = "microchip,mcp2515";
1094 reg = <2>; 1092 reg = <2>;
1095 interrupt-parent = <&gpio3>; 1093 interrupt-parent = <&gpio3>;
1096 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 1094 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
1097 spi-max-frequency = <12000000>; 1095 spi-max-frequency = <12000000>;
1098 clocks = <&can_osc>; 1096 clocks = <&can_osc>;
1099 vdd-supply = <&reg_3p3v>; 1097 vdd-supply = <&reg_3p3v>;
1100 xceiver-supply = <&reg_5p0v>; 1098 xceiver-supply = <&reg_5p0v>;
1101 }; 1099 };
1102 1100
1103 can2: can@3 { 1101 can2: can@3 {
1104 compatible = "microchip,mcp2515"; 1102 compatible = "microchip,mcp2515";
1105 reg = <3>; 1103 reg = <3>;
1106 interrupt-parent = <&gpio3>; 1104 interrupt-parent = <&gpio3>;
1107 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 1105 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
1108 spi-max-frequency = <12000000>; 1106 spi-max-frequency = <12000000>;
1109 clocks = <&can_osc>; 1107 clocks = <&can_osc>;
1110 vdd-supply = <&reg_3p3v>; 1108 vdd-supply = <&reg_3p3v>;
1111 xceiver-supply = <&reg_5p0v>; 1109 xceiver-supply = <&reg_5p0v>;
1112 }; 1110 };
1113 }; 1111 };
1114 1112
1115 &pwm1 { 1113 &pwm1 {
1116 pinctrl-names = "default"; 1114 pinctrl-names = "default";
1117 pinctrl-0 = <&pinctrl_pwm1>; 1115 pinctrl-0 = <&pinctrl_pwm1>;
1118 }; 1116 };
1119 1117
1120 &snvs_rtc { 1118 &snvs_rtc {
1121 status = "disabled"; 1119 status = "disabled";
1122 }; 1120 };
1123 1121