Eric Lee / smarc-fsl-linux-kernel

Commit 508996b6a0ef0c7aa7701995d137e71c56180752

Authored by Linus Torvalds 14 years ago

3 parents 619297855a 1c389795c1 58cbe2476a

Exists in master and in 39 other branches

Merge branches 'irq-fixes-for-linus' and 'sched-fixes-for-linus' of git://git.ke…

…rnel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'irq-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  genirq: Fix incorrect unlock in __setup_irq()
  cris: Use generic show_interrupts()
  genirq: show_interrupts: Check desc->name before printing it blindly
  cris: Use accessor functions to set IRQ_PER_CPU flag
  cris: Fix irq conversion fallout

* 'sched-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  sched, kernel-doc: Fix runqueue_is_locked() description

Showing 6 changed files Inline Diff

arch/cris/Kconfig
arch/cris/arch-v10/kernel/irq.c
arch/cris/arch-v32/kernel/irq.c
arch/cris/kernel/irq.c
kernel/irq/manage.c
kernel/irq/proc.c

arch/cris/Kconfig

Diff comments View file @ 508996b

 config MMU
 	bool
 	default y
 config ZONE_DMA
 	bool
 	default y
 config RWSEM_GENERIC_SPINLOCK
 	bool
 	default y
 config RWSEM_XCHGADD_ALGORITHM
 	bool
 config GENERIC_CMOS_UPDATE
 	def_bool y
 config ARCH_USES_GETTIMEOFFSET
 	def_bool n
 config GENERIC_IOMAP
        bool
        default y
 config ARCH_HAS_ILOG2_U32
 	bool
 	default n
 config ARCH_HAS_ILOG2_U64
 	bool
 	default n
 config GENERIC_FIND_NEXT_BIT
 	bool
 	default y
 config GENERIC_HWEIGHT
 	bool
 	default y
 config GENERIC_CALIBRATE_DELAY
 	bool
 	default y
 config NO_IOPORT
 	def_bool y
 config FORCE_MAX_ZONEORDER
 	int
 	default 6
 config CRIS
 	bool
 	default y
 	select HAVE_IDE
 	select HAVE_GENERIC_HARDIRQS
 	select GENERIC_HARDIRQS_NO_DEPRECATED
+	select GENERIC_IRQ_SHOW
 config HZ
 	int
 	default 100
 source "init/Kconfig"
 source "kernel/Kconfig.freezer"
 menu "General setup"
 source "fs/Kconfig.binfmt"
 config ETRAX_CMDLINE
 	string "Kernel command line"
 	default "root=/dev/mtdblock3"
 	help
 	  Pass additional commands to the kernel.
 config ETRAX_WATCHDOG
 	bool "Enable ETRAX watchdog"
 	help
 	  Enable the built-in watchdog timer support on ETRAX based embedded
 	  network computers.
 config ETRAX_WATCHDOG_NICE_DOGGY
 	bool "Disable watchdog during Oops printouts"
 	depends on ETRAX_WATCHDOG
 	help
 	  By enabling this you make sure that the watchdog does not bite while
 	  printing oopses. Recommended for development systems but not for
 	  production releases.
 config ETRAX_FAST_TIMER
        bool "Enable ETRAX fast timer API"
        help
          This options enables the API to a fast timer implementation using
 	 timer1 to get sub jiffie resolution timers (primarily one-shot
 	 timers).
 	 This is needed if CONFIG_ETRAX_SERIAL_FAST_TIMER is enabled.
 config ETRAX_KMALLOCED_MODULES
 	bool "Enable module allocation with kmalloc"
 	help
 	  Enable module allocation with kmalloc instead of vmalloc.
 config OOM_REBOOT
        bool "Enable reboot at out of memory"
 source "kernel/Kconfig.preempt"
 source mm/Kconfig
 endmenu
 menu "Hardware setup"
 choice
 	prompt "Processor type"
 	default ETRAX100LX
 config ETRAX100LX
 	bool "ETRAX-100LX-v1"
 	select ARCH_USES_GETTIMEOFFSET
 	help
 	  Support version 1 of the ETRAX 100LX.
 config ETRAX100LX_V2
 	bool "ETRAX-100LX-v2"
 	select ARCH_USES_GETTIMEOFFSET
 	help
 	  Support version 2 of the ETRAX 100LX.
 config SVINTO_SIM
 	bool "ETRAX-100LX-for-xsim-simulator"
 	select ARCH_USES_GETTIMEOFFSET
 	help
 	  Support the xsim ETRAX Simulator.
 config ETRAXFS
 	bool "ETRAX-FS-V32"
 	help
 	  Support CRIS V32.
 config CRIS_MACH_ARTPEC3
         bool "ARTPEC-3"
         help
           Support Axis ARTPEC-3.
 endchoice
 config ETRAX_VCS_SIM
 	bool "VCS Simulator"
 	help
 	  Setup hardware to be run in the VCS simulator.
 config ETRAX_ARCH_V10
        bool
        default y if ETRAX100LX || ETRAX100LX_V2
        default n if !(ETRAX100LX || ETRAX100LX_V2)
 config ETRAX_ARCH_V32
        bool
        default y if (ETRAXFS || CRIS_MACH_ARTPEC3)
        default n if !(ETRAXFS || CRIS_MACH_ARTPEC3)
 config ETRAX_DRAM_SIZE
 	int "DRAM size (dec, in MB)"
 	default "8"
 	help
 	  Size of DRAM (decimal in MB) typically 2, 8 or 16.
 config ETRAX_VMEM_SIZE
        int "Video memory size (dec, in MB)"
        depends on ETRAX_ARCH_V32 && !ETRAXFS
        default 8 if !ETRAXFS
        help
 	Size of Video accessible memory (decimal, in MB).
 config ETRAX_FLASH_BUSWIDTH
 	int "Buswidth of NOR flash in bytes"
 	default "2"
 	help
 	  Width in bytes of the NOR Flash bus (1, 2 or 4). Is usually 2.
 config ETRAX_NANDFLASH_BUSWIDTH
 	int "Buswidth of NAND flash in bytes"
 	default "1"
 	help
 	  Width in bytes of the NAND flash (1 or 2).
 config ETRAX_FLASH1_SIZE
        int "FLASH1 size (dec, in MB. 0 = Unknown)"
        default "0"
 choice
 	prompt "Product debug-port"
 	default ETRAX_DEBUG_PORT0
 config ETRAX_DEBUG_PORT0
 	bool "Serial-0"
 	help
 	  Choose a serial port for the ETRAX debug console.  Default to
 	  port 0.
 config ETRAX_DEBUG_PORT1
 	bool "Serial-1"
 	help
 	  Use serial port 1 for the console.
 config ETRAX_DEBUG_PORT2
 	bool "Serial-2"
 	help
 	  Use serial port 2 for the console.
 config ETRAX_DEBUG_PORT3
 	bool "Serial-3"
 	help
 	  Use serial port 3 for the console.
 config ETRAX_DEBUG_PORT_NULL
 	bool "disabled"
 	help
 	  Disable serial-port debugging.
 endchoice
 choice
 	prompt "Kernel GDB port"
 	depends on ETRAX_KGDB
 	default ETRAX_KGDB_PORT0
 	help
 	  Choose a serial port for kernel debugging.  NOTE: This port should
 	  not be enabled under Drivers for built-in interfaces (as it has its
 	  own initialization code) and should not be the same as the debug port.
 config ETRAX_KGDB_PORT0
 	bool "Serial-0"
 	help
 	  Use serial port 0 for kernel debugging.
 config ETRAX_KGDB_PORT1
 	bool "Serial-1"
 	help
 	  Use serial port 1 for kernel debugging.
 config ETRAX_KGDB_PORT2
 	bool "Serial-2"
 	help
 	  Use serial port 2 for kernel debugging.
 config ETRAX_KGDB_PORT3
 	bool "Serial-3"
 	help
 	  Use serial port 3 for kernel debugging.
 endchoice
 source arch/cris/arch-v10/Kconfig
 source arch/cris/arch-v32/Kconfig
 endmenu
 source "net/Kconfig"
 # bring in ETRAX built-in drivers
 menu "Drivers for built-in interfaces"
 source arch/cris/arch-v10/drivers/Kconfig
 source arch/cris/arch-v32/drivers/Kconfig
 config ETRAX_AXISFLASHMAP
 	bool "Axis flash-map support"
 	select MTD
 	select MTD_CFI
 	select MTD_CFI_AMDSTD
 	select MTD_JEDECPROBE if ETRAX_ARCH_V32
 	select MTD_CHAR
 	select MTD_BLOCK
 	select MTD_PARTITIONS
 	select MTD_CONCAT
 	select MTD_COMPLEX_MAPPINGS
 	help
 	  This option enables MTD mapping of flash devices.  Needed to use
 	  flash memories.  If unsure, say Y.
 config ETRAX_RTC
 	bool "Real Time Clock support"
 	depends on ETRAX_I2C
 	help
 	  Enables drivers for the Real-Time Clock battery-backed chips on
 	  some products. The kernel reads the time when booting, and
 	  the date can be set using ioctl(fd, RTC_SET_TIME, &rt) with rt a
 	  rtc_time struct (see <file:include/asm-cris/rtc.h>) on the /dev/rtc
 	  device.  You can check the time with cat /proc/rtc, but
 	  normal time reading should be done using libc function time and
 	  friends.
 choice
 	prompt "RTC chip"
 	depends on ETRAX_RTC
 	default ETRAX_PCF8563 if ETRAX_ARCH_V32
 	default ETRAX_DS1302 if ETRAX_ARCH_V10
 config ETRAX_DS1302
 	depends on ETRAX_ARCH_V10
 	bool "DS1302"
 	help
 	  Enables the driver for the DS1302 Real-Time Clock battery-backed
 	  chip on some products.
 config ETRAX_PCF8563
 	bool "PCF8563"
 	help
 	  Enables the driver for the PCF8563 Real-Time Clock battery-backed
 	  chip on some products.
 endchoice
 config ETRAX_SYNCHRONOUS_SERIAL
 	bool "Synchronous serial-port support"
 	help
 	  Select this to enable the synchronous serial port driver.
 config ETRAX_SYNCHRONOUS_SERIAL_PORT0
 	bool "Synchronous serial port 0 enabled"
 	depends on ETRAX_SYNCHRONOUS_SERIAL
 	help
 	  Enabled synchronous serial port 0.
 config ETRAX_SYNCHRONOUS_SERIAL0_DMA
 	bool "Enable DMA on synchronous serial port 0."
 	depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0
 	help
 	  A synchronous serial port can run in manual or DMA mode.
 	  Selecting this option will make it run in DMA mode.
 config ETRAX_SYNCHRONOUS_SERIAL_PORT1
 	bool "Synchronous serial port 1 enabled"
 	depends on ETRAX_SYNCHRONOUS_SERIAL && (ETRAXFS || ETRAX_ARCH_V10)
 	help
 	  Enabled synchronous serial port 1.
 config ETRAX_SYNCHRONOUS_SERIAL1_DMA
 	bool "Enable DMA on synchronous serial port 1."
 	depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1
 	help
 	  A synchronous serial port can run in manual or DMA mode.
 	  Selecting this option will make it run in DMA mode.
 choice
 	prompt "Network LED behavior"
 	depends on ETRAX_ETHERNET
 	default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
 config ETRAX_NETWORK_LED_ON_WHEN_LINK
 	bool "LED_on_when_link"
 	help
 	  Selecting LED_on_when_link will light the LED when there is a
 	  connection and will flash off when there is activity.
 	  Selecting LED_on_when_activity will light the LED only when
 	  there is activity.
 	  This setting will also affect the behaviour of other activity LEDs
 	  e.g. Bluetooth.
 config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
 	bool "LED_on_when_activity"
 	help
 	  Selecting LED_on_when_link will light the LED when there is a
 	  connection and will flash off when there is activity.
 	  Selecting LED_on_when_activity will light the LED only when
 	  there is activity.
 	  This setting will also affect the behaviour of other activity LEDs
 	  e.g. Bluetooth.
 endchoice
 choice
 	prompt "Ser0 DMA out channel"
 	depends on ETRAX_SERIAL_PORT0
 	default ETRAX_SERIAL_PORT0_DMA6_OUT if ETRAX_ARCH_V32
 	default ETRAX_SERIAL_PORT0_NO_DMA_OUT if ETRAX_ARCH_V10
 config ETRAX_SERIAL_PORT0_NO_DMA_OUT
 	bool "Ser0 uses no DMA for output"
 	help
 	  Do not use DMA for ser0 output.
 config ETRAX_SERIAL_PORT0_DMA6_OUT
 	bool "Ser0 uses DMA6 for output"
 	depends on ETRAXFS
 	help
 	  Enables the DMA6 output channel for ser0 (ttyS0).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when transmitting data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 config ETRAX_SERIAL_PORT0_DMA0_OUT
 	bool "Ser0 uses DMA0 for output"
 	depends on CRIS_MACH_ARTPEC3
 	help
 	  Enables the DMA0 output channel for ser0 (ttyS0).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when transmitting data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 endchoice
 choice
 	prompt "Ser0 DMA in channel "
 	depends on ETRAX_SERIAL_PORT0
 	default ETRAX_SERIAL_PORT0_NO_DMA_IN if ETRAX_ARCH_V32
 	default ETRAX_SERIAL_PORT0_DMA7_IN if ETRAX_ARCH_V10
 	help
 	  What DMA channel to use for ser0.
 config ETRAX_SERIAL_PORT0_NO_DMA_IN
 	bool "Ser0 uses no DMA for input"
 	help
 	  Do not use DMA for ser0 input.
 config ETRAX_SERIAL_PORT0_DMA7_IN
 	bool "Ser0 uses DMA7 for input"
 	depends on ETRAXFS
 	help
 	  Enables the DMA7 input channel for ser0 (ttyS0).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when receiving data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 config ETRAX_SERIAL_PORT0_DMA1_IN
 	bool "Ser0 uses DMA1 for input"
 	depends on CRIS_MACH_ARTPEC3
 	help
 	  Enables the DMA1 input channel for ser0 (ttyS0).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when receiving data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 endchoice
 choice
 	prompt "Ser1 DMA in channel "
 	depends on ETRAX_SERIAL_PORT1
 	default ETRAX_SERIAL_PORT1_NO_DMA_IN if ETRAX_ARCH_V32
 	default ETRAX_SERIAL_PORT1_DMA9_IN if ETRAX_ARCH_V10
 	help
 	  What DMA channel to use for ser1.
 config ETRAX_SERIAL_PORT1_NO_DMA_IN
 	bool "Ser1 uses no DMA for input"
 	help
 	  Do not use DMA for ser1 input.
 config ETRAX_SERIAL_PORT1_DMA5_IN
 	bool "Ser1 uses DMA5 for input"
 	depends on ETRAX_ARCH_V32
 	help
 	  Enables the DMA5 input channel for ser1 (ttyS1).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when receiving data.
 	  Normally you want this on, unless you use the DMA channel for
 	  something else.
 config ETRAX_SERIAL_PORT1_DMA9_IN
 	depends on ETRAX_ARCH_V10
 	bool "Ser1 uses DMA9 for input"
 endchoice
 choice
 	prompt "Ser1 DMA out channel"
 	depends on ETRAX_SERIAL_PORT1
 	default ETRAX_SERIAL_PORT1_NO_DMA_OUT if ETRAX_ARCH_V32
 	default ETRAX_SERIAL_PORT1_DMA8_OUT if ETRAX_ARCH_V10
 	help
 	  What DMA channel to use for ser1.
 config ETRAX_SERIAL_PORT1_NO_DMA_OUT
 	bool "Ser1 uses no DMA for output"
 	help
 	  Do not use DMA for ser1 output.
 config ETRAX_SERIAL_PORT1_DMA8_OUT
 	depends on ETRAX_ARCH_V10
 	bool "Ser1 uses DMA8 for output"
 config ETRAX_SERIAL_PORT1_DMA4_OUT
 	depends on ETRAX_ARCH_V32
 	bool "Ser1 uses DMA4 for output"
 	help
 	  Enables the DMA4 output channel for ser1 (ttyS1).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when transmitting data.
 	  Normally you want this on, unless you use the DMA channel for
 	  something else.
 endchoice
 choice
 	prompt "Ser2 DMA out channel"
 	depends on ETRAX_SERIAL_PORT2
 	default ETRAX_SERIAL_PORT2_NO_DMA_OUT if ETRAX_ARCH_V32
 	default ETRAX_SERIAL_PORT2_DMA2_OUT if ETRAX_ARCH_V10
 config ETRAX_SERIAL_PORT2_NO_DMA_OUT
 	bool "Ser2 uses no DMA for output"
 	help
 	  Do not use DMA for ser2 output.
 config ETRAX_SERIAL_PORT2_DMA2_OUT
 	bool "Ser2 uses DMA2 for output"
 	depends on ETRAXFS || ETRAX_ARCH_V10
 	help
 	  Enables the DMA2 output channel for ser2 (ttyS2).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when transmitting data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 config ETRAX_SERIAL_PORT2_DMA6_OUT
 	bool "Ser2 uses DMA6 for output"
 	depends on CRIS_MACH_ARTPEC3
 	help
 	  Enables the DMA6 output channel for ser2 (ttyS2).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when transmitting data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 endchoice
 choice
 	prompt "Ser2 DMA in channel"
 	depends on ETRAX_SERIAL_PORT2
 	default ETRAX_SERIAL_PORT2_NO_DMA_IN if ETRAX_ARCH_V32
 	default ETRAX_SERIAL_PORT2_DMA3_IN if ETRAX_ARCH_V10
 	help
 	  What DMA channel to use for ser2.
 config ETRAX_SERIAL_PORT2_NO_DMA_IN
 	bool "Ser2 uses no DMA for input"
 	help
 	  Do not use DMA for ser2 input.
 config ETRAX_SERIAL_PORT2_DMA3_IN
 	bool "Ser2 uses DMA3 for input"
 	depends on ETRAXFS || ETRAX_ARCH_V10
 	help
 	  Enables the DMA3 input channel for ser2 (ttyS2).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when receiving data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 config ETRAX_SERIAL_PORT2_DMA7_IN
 	bool "Ser2 uses DMA7 for input"
 	depends on CRIS_MACH_ARTPEC3
 	help
 	  Enables the DMA7 input channel for ser2 (ttyS2).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when receiving data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 endchoice
 choice
 	prompt "Ser3 DMA in channel"
 	depends on ETRAX_SERIAL_PORT3
 	default ETRAX_SERIAL_PORT3_NO_DMA_IN if ETRAX_ARCH_V32
 	default ETRAX_SERIAL_PORT3_DMA5_IN if ETRAX_ARCH_V10
 	help
 	  What DMA channel to use for ser3.
 config ETRAX_SERIAL_PORT3_NO_DMA_IN
 	bool "Ser3 uses no DMA for input"
 	help
 	  Do not use DMA for ser3 input.
 config ETRAX_SERIAL_PORT3_DMA5_IN
 	depends on ETRAX_ARCH_V10
 	bool "DMA 5"
 config ETRAX_SERIAL_PORT3_DMA9_IN
 	bool "Ser3 uses DMA9 for input"
 	depends on ETRAXFS
 	help
 	  Enables the DMA9 input channel for ser3 (ttyS3).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when receiving data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 config ETRAX_SERIAL_PORT3_DMA3_IN
 	bool "Ser3 uses DMA3 for input"
 	depends on CRIS_MACH_ARTPEC3
 	help
 	  Enables the DMA3 input channel for ser3 (ttyS3).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when receiving data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 endchoice
 choice
 	prompt "Ser3 DMA out channel"
 	depends on ETRAX_SERIAL_PORT3
 	default ETRAX_SERIAL_PORT3_NO_DMA_OUT if ETRAX_ARCH_V32
 	default ETRAX_SERIAL_PORT3_DMA4_OUT if ETRAX_ARCH_V10
 config ETRAX_SERIAL_PORT3_NO_DMA_OUT
 	bool "Ser3 uses no DMA for output"
 	help
 	  Do not use DMA for ser3 output.
 config ETRAX_SERIAL_PORT3_DMA4_OUT
 	depends on ETRAX_ARCH_V10
 	bool "DMA 4"
 config ETRAX_SERIAL_PORT3_DMA8_OUT
 	bool "Ser3 uses DMA8 for output"
 	depends on ETRAXFS
 	help
 	  Enables the DMA8 output channel for ser3 (ttyS3).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when transmitting data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 config ETRAX_SERIAL_PORT3_DMA2_OUT
 	bool "Ser3 uses DMA2 for output"
 	depends on CRIS_MACH_ARTPEC3
 	help
 	  Enables the DMA2 output channel for ser3 (ttyS3).
 	  If you do not enable DMA, an interrupt for each character will be
 	  used when transmitting data.
 	  Normally you want to use DMA, unless you use the DMA channel for
 	  something else.
 endchoice
 endmenu
 source "drivers/base/Kconfig"
 # standard linux drivers
 source "drivers/mtd/Kconfig"
 source "drivers/parport/Kconfig"
 source "drivers/pnp/Kconfig"
 source "drivers/block/Kconfig"
 source "drivers/ide/Kconfig"
 source "drivers/net/Kconfig"
 source "drivers/i2c/Kconfig"
 source "drivers/rtc/Kconfig"
 #
 # input before char - char/joystick depends on it. As does USB.
 #
 source "drivers/input/Kconfig"
 source "drivers/char/Kconfig"
 source "fs/Kconfig"
 source "drivers/usb/Kconfig"
 source "drivers/uwb/Kconfig"
 source "drivers/staging/Kconfig"
 source "arch/cris/Kconfig.debug"
 source "security/Kconfig"
 source "crypto/Kconfig"
 source "lib/Kconfig"

arch/cris/arch-v10/kernel/irq.c

Diff comments View file @ 508996b

1	/*	1	/*
2	* linux/arch/cris/kernel/irq.c	2	* linux/arch/cris/kernel/irq.c
3	*	3	*
4	* Copyright (c) 2000-2002 Axis Communications AB	4	* Copyright (c) 2000-2002 Axis Communications AB
5	*	5	*
6	* Authors: Bjorn Wesen (bjornw@axis.com)	6	* Authors: Bjorn Wesen (bjornw@axis.com)
7	*	7	*
8	* This file contains the interrupt vectors and some	8	* This file contains the interrupt vectors and some
9	* helper functions	9	* helper functions
10	*	10	*
11	*/	11	*/
12		12
13	#include <asm/irq.h>	13	#include <asm/irq.h>
14	#include <asm/current.h>	14	#include <asm/current.h>
15	#include <linux/irq.h>	15	#include <linux/irq.h>
16	#include <linux/interrupt.h>	16	#include <linux/interrupt.h>
17	#include <linux/kernel.h>	17	#include <linux/kernel.h>
18	#include <linux/init.h>	18	#include <linux/init.h>
19		19
20	#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));	20	#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
21	#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));	21	#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
22		22
23	/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is	23	/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
24	* global just so that the kernel gdb can use it.	24	* global just so that the kernel gdb can use it.
25	*/	25	*/
26		26
27	void	27	void
28	set_int_vector(int n, irqvectptr addr)	28	set_int_vector(int n, irqvectptr addr)
29	{	29	{
30	etrax_irv->v[n + 0x20] = (irqvectptr)addr;	30	etrax_irv->v[n + 0x20] = (irqvectptr)addr;
31	}	31	}
32		32
33	/* the breakpoint vector is obviously not made just like the normal irq handlers	33	/* the breakpoint vector is obviously not made just like the normal irq handlers
34	* but needs to contain _code_ to jump to addr.	34	* but needs to contain _code_ to jump to addr.
35	*	35	*
36	* the BREAK n instruction jumps to IBR + n * 8	36	* the BREAK n instruction jumps to IBR + n * 8
37	*/	37	*/
38		38
39	void	39	void
40	set_break_vector(int n, irqvectptr addr)	40	set_break_vector(int n, irqvectptr addr)
41	{	41	{
42	unsigned short jinstr = (unsigned short )&etrax_irv->v[n*2];	42	unsigned short jinstr = (unsigned short )&etrax_irv->v[n*2];
43	unsigned long jaddr = (unsigned long )(jinstr + 1);	43	unsigned long jaddr = (unsigned long )(jinstr + 1);
44		44
45	/* if you don't know what this does, do not touch it! */	45	/* if you don't know what this does, do not touch it! */
46		46
47	*jinstr = 0x0d3f;	47	*jinstr = 0x0d3f;
48	*jaddr = (unsigned long)addr;	48	*jaddr = (unsigned long)addr;
49		49
50	/* 00000026 <clrlop+1a> 3f0d82000000 jump 0x82 */	50	/* 00000026 <clrlop+1a> 3f0d82000000 jump 0x82 */
51	}	51	}
52		52
53	/*	53	/*
54	* This builds up the IRQ handler stubs using some ugly macros in irq.h	54	* This builds up the IRQ handler stubs using some ugly macros in irq.h
55	*	55	*
56	* These macros create the low-level assembly IRQ routines that do all	56	* These macros create the low-level assembly IRQ routines that do all
57	* the operations that are needed. They are also written to be fast - and to	57	* the operations that are needed. They are also written to be fast - and to
58	* disable interrupts as little as humanly possible.	58	* disable interrupts as little as humanly possible.
59	*	59	*
60	*/	60	*/
61		61
62	/* IRQ0 and 1 are special traps */	62	/* IRQ0 and 1 are special traps */
63	void hwbreakpoint(void);	63	void hwbreakpoint(void);
64	void IRQ1_interrupt(void);	64	void IRQ1_interrupt(void);
65	BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */	65	BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */
66	BUILD_IRQ(3, 0x08)	66	BUILD_IRQ(3, 0x08)
67	BUILD_IRQ(4, 0x10)	67	BUILD_IRQ(4, 0x10)
68	BUILD_IRQ(5, 0x20)	68	BUILD_IRQ(5, 0x20)
69	BUILD_IRQ(6, 0x40)	69	BUILD_IRQ(6, 0x40)
70	BUILD_IRQ(7, 0x80)	70	BUILD_IRQ(7, 0x80)
71	BUILD_IRQ(8, 0x100)	71	BUILD_IRQ(8, 0x100)
72	BUILD_IRQ(9, 0x200)	72	BUILD_IRQ(9, 0x200)
73	BUILD_IRQ(10, 0x400)	73	BUILD_IRQ(10, 0x400)
74	BUILD_IRQ(11, 0x800)	74	BUILD_IRQ(11, 0x800)
75	BUILD_IRQ(12, 0x1000)	75	BUILD_IRQ(12, 0x1000)
76	BUILD_IRQ(13, 0x2000)	76	BUILD_IRQ(13, 0x2000)
77	void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */	77	void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */
78	void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */	78	void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */
79	BUILD_IRQ(16, 0x10000 \| 0x20000) /* ethernet tx interrupt needs to block rx */	79	BUILD_IRQ(16, 0x10000 \| 0x20000) /* ethernet tx interrupt needs to block rx */
80	BUILD_IRQ(17, 0x20000 \| 0x10000) /* ...and vice versa */	80	BUILD_IRQ(17, 0x20000 \| 0x10000) /* ...and vice versa */
81	BUILD_IRQ(18, 0x40000)	81	BUILD_IRQ(18, 0x40000)
82	BUILD_IRQ(19, 0x80000)	82	BUILD_IRQ(19, 0x80000)
83	BUILD_IRQ(20, 0x100000)	83	BUILD_IRQ(20, 0x100000)
84	BUILD_IRQ(21, 0x200000)	84	BUILD_IRQ(21, 0x200000)
85	BUILD_IRQ(22, 0x400000)	85	BUILD_IRQ(22, 0x400000)
86	BUILD_IRQ(23, 0x800000)	86	BUILD_IRQ(23, 0x800000)
87	BUILD_IRQ(24, 0x1000000)	87	BUILD_IRQ(24, 0x1000000)
88	BUILD_IRQ(25, 0x2000000)	88	BUILD_IRQ(25, 0x2000000)
89	/* IRQ 26-30 are reserved */	89	/* IRQ 26-30 are reserved */
90	BUILD_IRQ(31, 0x80000000)	90	BUILD_IRQ(31, 0x80000000)
91		91
92	/*	92	/*
93	* Pointers to the low-level handlers	93	* Pointers to the low-level handlers
94	*/	94	*/
95		95
96	static void (*interrupt[NR_IRQS])(void) = {	96	static void (*interrupt[NR_IRQS])(void) = {
97	NULL, NULL, IRQ2_interrupt, IRQ3_interrupt,	97	NULL, NULL, IRQ2_interrupt, IRQ3_interrupt,
98	IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt,	98	IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt,
99	IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt,	99	IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt,
100	IRQ12_interrupt, IRQ13_interrupt, NULL, NULL,	100	IRQ12_interrupt, IRQ13_interrupt, NULL, NULL,
101	IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt,	101	IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt,
102	IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt,	102	IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt,
103	IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL,	103	IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL,
104	IRQ31_interrupt	104	IRQ31_interrupt
105	};	105	};
106		106
107	static void enable_crisv10_irq(struct irq_data *data)	107	static void enable_crisv10_irq(struct irq_data *data)
108	{	108	{
109	crisv10_unmask_irq(data->irq);	109	crisv10_unmask_irq(data->irq);
110	}	110	}
111		111
112	static void disable_crisv10_irq(struct irq_data *data)	112	static void disable_crisv10_irq(struct irq_data *data)
113	{	113	{
114	crisv10_mask_irq(data->irq);	114	crisv10_mask_irq(data->irq);
115	}	115	}
116		116
117	static struct irq_chip crisv10_irq_type = {	117	static struct irq_chip crisv10_irq_type = {
118	.name = "CRISv10",	118	.name = "CRISv10",
119	.irq_shutdown = disable_crisv10_irq,	119	.irq_shutdown = disable_crisv10_irq,
120	.irq_enable = enable_crisv10_irq,	120	.irq_enable = enable_crisv10_irq,
121	.irq_disable = disable_crisv10_irq,	121	.irq_disable = disable_crisv10_irq,
122	};	122	};
123		123
124	void weird_irq(void);	124	void weird_irq(void);
125	void system_call(void); /* from entry.S */	125	void system_call(void); /* from entry.S */
126	void do_sigtrap(void); /* from entry.S */	126	void do_sigtrap(void); /* from entry.S */
127	void gdb_handle_breakpoint(void); /* from entry.S */	127	void gdb_handle_breakpoint(void); /* from entry.S */
128		128
129	extern void do_IRQ(int irq, struct pt_regs * regs);	129	extern void do_IRQ(int irq, struct pt_regs * regs);
130		130
131	/* Handle multiple IRQs */	131	/* Handle multiple IRQs */
132	void do_multiple_IRQ(struct pt_regs* regs)	132	void do_multiple_IRQ(struct pt_regs* regs)
133	{	133	{
134	int bit;	134	int bit;
135	unsigned masked;	135	unsigned masked;
136	unsigned mask;	136	unsigned mask;
137	unsigned ethmask = 0;	137	unsigned ethmask = 0;
138		138
139	/* Get interrupts to mask and handle */	139	/* Get interrupts to mask and handle */
140	mask = masked = *R_VECT_MASK_RD;	140	mask = masked = *R_VECT_MASK_RD;
141		141
142	/* Never mask timer IRQ */	142	/* Never mask timer IRQ */
143	mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));	143	mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));
144		144
145	/*	145	/*
146	* If either ethernet interrupt (rx or tx) is active then block	146	* If either ethernet interrupt (rx or tx) is active then block
147	* the other one too. Unblock afterwards also.	147	* the other one too. Unblock afterwards also.
148	*/	148	*/
149	if (mask &	149	if (mask &
150	(IO_STATE(R_VECT_MASK_RD, dma0, active) \|	150	(IO_STATE(R_VECT_MASK_RD, dma0, active) \|
151	IO_STATE(R_VECT_MASK_RD, dma1, active))) {	151	IO_STATE(R_VECT_MASK_RD, dma1, active))) {
152	ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) \|	152	ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) \|
153	IO_MASK(R_VECT_MASK_RD, dma1));	153	IO_MASK(R_VECT_MASK_RD, dma1));
154	}	154	}
155		155
156	/* Block them */	156	/* Block them */
157	*R_VECT_MASK_CLR = (mask \| ethmask);	157	*R_VECT_MASK_CLR = (mask \| ethmask);
158		158
159	/* An extra irq_enter here to prevent softIRQs to run after	159	/* An extra irq_enter here to prevent softIRQs to run after
160	* each do_IRQ. This will decrease the interrupt latency.	160	* each do_IRQ. This will decrease the interrupt latency.
161	*/	161	*/
162	irq_enter();	162	irq_enter();
163		163
164	/* Handle all IRQs */	164	/* Handle all IRQs */
165	for (bit = 2; bit < 32; bit++) {	165	for (bit = 2; bit < 32; bit++) {
166	if (masked & (1 << bit)) {	166	if (masked & (1 << bit)) {
167	do_IRQ(bit, regs);	167	do_IRQ(bit, regs);
168	}	168	}
169	}	169	}
170		170
171	/* This irq_exit() will trigger the soft IRQs. */	171	/* This irq_exit() will trigger the soft IRQs. */
172	irq_exit();	172	irq_exit();
173		173
174	/* Unblock the IRQs again */	174	/* Unblock the IRQs again */
175	*R_VECT_MASK_SET = (masked \| ethmask);	175	*R_VECT_MASK_SET = (masked \| ethmask);
176	}	176	}
177		177
178	/* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and	178	/* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and
179	setting the irq vector table.	179	setting the irq vector table.
180	*/	180	*/
181		181
182	void __init	182	void __init
183	init_IRQ(void)	183	init_IRQ(void)
184	{	184	{
185	int i;	185	int i;
186		186
187	/* clear all interrupt masks */	187	/* clear all interrupt masks */
188		188
189	#ifndef CONFIG_SVINTO_SIM	189	#ifndef CONFIG_SVINTO_SIM
190	*R_IRQ_MASK0_CLR = 0xffffffff;	190	*R_IRQ_MASK0_CLR = 0xffffffff;
191	*R_IRQ_MASK1_CLR = 0xffffffff;	191	*R_IRQ_MASK1_CLR = 0xffffffff;
192	*R_IRQ_MASK2_CLR = 0xffffffff;	192	*R_IRQ_MASK2_CLR = 0xffffffff;
193	#endif	193	#endif
194		194
195	*R_VECT_MASK_CLR = 0xffffffff;	195	*R_VECT_MASK_CLR = 0xffffffff;
196		196
197	for (i = 0; i < 256; i++)	197	for (i = 0; i < 256; i++)
198	etrax_irv->v[i] = weird_irq;	198	etrax_irv->v[i] = weird_irq;
199		199
200	/* Initialize IRQ handler descriptors. */	200	/* Initialize IRQ handler descriptors. */
201	for(i = 2; i < NR_IRQS; i++) {	201	for(i = 2; i < NR_IRQS; i++) {
202	set_irq_desc_and_handler(i, &crisv10_irq_type,	202	irq_set_chip_and_handler(i, &crisv10_irq_type,
203	handle_simple_irq);	203	handle_simple_irq);
204	set_int_vector(i, interrupt[i]);	204	set_int_vector(i, interrupt[i]);
205	}	205	}
206		206
207	/* the entries in the break vector contain actual code to be	207	/* the entries in the break vector contain actual code to be
208	executed by the associated break handler, rather than just a jump	208	executed by the associated break handler, rather than just a jump
209	address. therefore we need to setup a default breakpoint handler	209	address. therefore we need to setup a default breakpoint handler
210	for all breakpoints */	210	for all breakpoints */
211		211
212	for (i = 0; i < 16; i++)	212	for (i = 0; i < 16; i++)
213	set_break_vector(i, do_sigtrap);	213	set_break_vector(i, do_sigtrap);
214		214
215	/* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */	215	/* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
216		216
217	set_int_vector(15, multiple_interrupt);	217	set_int_vector(15, multiple_interrupt);
218		218
219	/* 0 and 1 which are special breakpoint/NMI traps */	219	/* 0 and 1 which are special breakpoint/NMI traps */
220		220
221	set_int_vector(0, hwbreakpoint);	221	set_int_vector(0, hwbreakpoint);
222	set_int_vector(1, IRQ1_interrupt);	222	set_int_vector(1, IRQ1_interrupt);
223		223
224	/* and irq 14 which is the mmu bus fault handler */	224	/* and irq 14 which is the mmu bus fault handler */
225		225
226	set_int_vector(14, mmu_bus_fault);	226	set_int_vector(14, mmu_bus_fault);
227		227
228	/* setup the system-call trap, which is reached by BREAK 13 */	228	/* setup the system-call trap, which is reached by BREAK 13 */
229		229
230	set_break_vector(13, system_call);	230	set_break_vector(13, system_call);
231		231
232	/* setup a breakpoint handler for debugging used for both user and	232	/* setup a breakpoint handler for debugging used for both user and
233	kernel mode debugging (which is why it is not inside an ifdef	233	kernel mode debugging (which is why it is not inside an ifdef
234	CONFIG_ETRAX_KGDB) */	234	CONFIG_ETRAX_KGDB) */
235	set_break_vector(8, gdb_handle_breakpoint);	235	set_break_vector(8, gdb_handle_breakpoint);
236		236
237	#ifdef CONFIG_ETRAX_KGDB	237	#ifdef CONFIG_ETRAX_KGDB
238	/* setup kgdb if its enabled, and break into the debugger */	238	/* setup kgdb if its enabled, and break into the debugger */
239	kgdb_init();	239	kgdb_init();
240	breakpoint();	240	breakpoint();
241	#endif	241	#endif
242	}	242	}
243		243

arch/cris/arch-v32/kernel/irq.c

Diff comments View file @ 508996b

1	/*	1	/*
2	* Copyright (C) 2003, Axis Communications AB.	2	* Copyright (C) 2003, Axis Communications AB.
3	*/	3	*/
4		4
5	#include <asm/irq.h>	5	#include <asm/irq.h>
6	#include <linux/irq.h>	6	#include <linux/irq.h>
7	#include <linux/interrupt.h>	7	#include <linux/interrupt.h>
8	#include <linux/smp.h>	8	#include <linux/smp.h>
9	#include <linux/kernel.h>	9	#include <linux/kernel.h>
10	#include <linux/errno.h>	10	#include <linux/errno.h>
11	#include <linux/init.h>	11	#include <linux/init.h>
12	#include <linux/profile.h>	12	#include <linux/profile.h>
13	#include <linux/proc_fs.h>	13	#include <linux/proc_fs.h>
14	#include <linux/seq_file.h>	14	#include <linux/seq_file.h>
15	#include <linux/threads.h>	15	#include <linux/threads.h>
16	#include <linux/spinlock.h>	16	#include <linux/spinlock.h>
17	#include <linux/kernel_stat.h>	17	#include <linux/kernel_stat.h>
18	#include <hwregs/reg_map.h>	18	#include <hwregs/reg_map.h>
19	#include <hwregs/reg_rdwr.h>	19	#include <hwregs/reg_rdwr.h>
20	#include <hwregs/intr_vect.h>	20	#include <hwregs/intr_vect.h>
21	#include <hwregs/intr_vect_defs.h>	21	#include <hwregs/intr_vect_defs.h>
22		22
23	#define CPU_FIXED -1	23	#define CPU_FIXED -1
24		24
25	/* IRQ masks (refer to comment for crisv32_do_multiple) */	25	/* IRQ masks (refer to comment for crisv32_do_multiple) */
26	#if TIMER0_INTR_VECT - FIRST_IRQ < 32	26	#if TIMER0_INTR_VECT - FIRST_IRQ < 32
27	#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))	27	#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
28	#undef TIMER_VECT1	28	#undef TIMER_VECT1
29	#else	29	#else
30	#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))	30	#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
31	#define TIMER_VECT1	31	#define TIMER_VECT1
32	#endif	32	#endif
33	#ifdef CONFIG_ETRAX_KGDB	33	#ifdef CONFIG_ETRAX_KGDB
34	#if defined(CONFIG_ETRAX_KGDB_PORT0)	34	#if defined(CONFIG_ETRAX_KGDB_PORT0)
35	#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))	35	#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
36	#elif defined(CONFIG_ETRAX_KGDB_PORT1)	36	#elif defined(CONFIG_ETRAX_KGDB_PORT1)
37	#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))	37	#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
38	#elif defined(CONFIG_ETRAX_KGB_PORT2)	38	#elif defined(CONFIG_ETRAX_KGB_PORT2)
39	#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))	39	#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
40	#elif defined(CONFIG_ETRAX_KGDB_PORT3)	40	#elif defined(CONFIG_ETRAX_KGDB_PORT3)
41	#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))	41	#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
42	#endif	42	#endif
43	#endif	43	#endif
44		44
45	DEFINE_SPINLOCK(irq_lock);	45	DEFINE_SPINLOCK(irq_lock);
46		46
47	struct cris_irq_allocation	47	struct cris_irq_allocation
48	{	48	{
49	int cpu; /* The CPU to which the IRQ is currently allocated. */	49	int cpu; /* The CPU to which the IRQ is currently allocated. */
50	cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */	50	cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
51	};	51	};
52		52
53	struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =	53	struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
54	{ [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };	54	{ [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };
55		55
56	static unsigned long irq_regs[NR_CPUS] =	56	static unsigned long irq_regs[NR_CPUS] =
57	{	57	{
58	regi_irq,	58	regi_irq,
59	#ifdef CONFIG_SMP	59	#ifdef CONFIG_SMP
60	regi_irq2,	60	regi_irq2,
61	#endif	61	#endif
62	};	62	};
63		63
64	#if NR_REAL_IRQS > 32	64	#if NR_REAL_IRQS > 32
65	#define NBR_REGS 2	65	#define NBR_REGS 2
66	#else	66	#else
67	#define NBR_REGS 1	67	#define NBR_REGS 1
68	#endif	68	#endif
69		69
70	unsigned long cpu_irq_counters[NR_CPUS];	70	unsigned long cpu_irq_counters[NR_CPUS];
71	unsigned long irq_counters[NR_REAL_IRQS];	71	unsigned long irq_counters[NR_REAL_IRQS];
72		72
73	/* From irq.c. */	73	/* From irq.c. */
74	extern void weird_irq(void);	74	extern void weird_irq(void);
75		75
76	/* From entry.S. */	76	/* From entry.S. */
77	extern void system_call(void);	77	extern void system_call(void);
78	extern void nmi_interrupt(void);	78	extern void nmi_interrupt(void);
79	extern void multiple_interrupt(void);	79	extern void multiple_interrupt(void);
80	extern void gdb_handle_exception(void);	80	extern void gdb_handle_exception(void);
81	extern void i_mmu_refill(void);	81	extern void i_mmu_refill(void);
82	extern void i_mmu_invalid(void);	82	extern void i_mmu_invalid(void);
83	extern void i_mmu_access(void);	83	extern void i_mmu_access(void);
84	extern void i_mmu_execute(void);	84	extern void i_mmu_execute(void);
85	extern void d_mmu_refill(void);	85	extern void d_mmu_refill(void);
86	extern void d_mmu_invalid(void);	86	extern void d_mmu_invalid(void);
87	extern void d_mmu_access(void);	87	extern void d_mmu_access(void);
88	extern void d_mmu_write(void);	88	extern void d_mmu_write(void);
89		89
90	/* From kgdb.c. */	90	/* From kgdb.c. */
91	extern void kgdb_init(void);	91	extern void kgdb_init(void);
92	extern void breakpoint(void);	92	extern void breakpoint(void);
93		93
94	/* From traps.c. */	94	/* From traps.c. */
95	extern void breakh_BUG(void);	95	extern void breakh_BUG(void);
96		96
97	/*	97	/*
98	* Build the IRQ handler stubs using macros from irq.h.	98	* Build the IRQ handler stubs using macros from irq.h.
99	*/	99	*/
100	#ifdef CONFIG_CRIS_MACH_ARTPEC3	100	#ifdef CONFIG_CRIS_MACH_ARTPEC3
101	BUILD_TIMER_IRQ(0x31, 0)	101	BUILD_TIMER_IRQ(0x31, 0)
102	#else	102	#else
103	BUILD_IRQ(0x31)	103	BUILD_IRQ(0x31)
104	#endif	104	#endif
105	BUILD_IRQ(0x32)	105	BUILD_IRQ(0x32)
106	BUILD_IRQ(0x33)	106	BUILD_IRQ(0x33)
107	BUILD_IRQ(0x34)	107	BUILD_IRQ(0x34)
108	BUILD_IRQ(0x35)	108	BUILD_IRQ(0x35)
109	BUILD_IRQ(0x36)	109	BUILD_IRQ(0x36)
110	BUILD_IRQ(0x37)	110	BUILD_IRQ(0x37)
111	BUILD_IRQ(0x38)	111	BUILD_IRQ(0x38)
112	BUILD_IRQ(0x39)	112	BUILD_IRQ(0x39)
113	BUILD_IRQ(0x3a)	113	BUILD_IRQ(0x3a)
114	BUILD_IRQ(0x3b)	114	BUILD_IRQ(0x3b)
115	BUILD_IRQ(0x3c)	115	BUILD_IRQ(0x3c)
116	BUILD_IRQ(0x3d)	116	BUILD_IRQ(0x3d)
117	BUILD_IRQ(0x3e)	117	BUILD_IRQ(0x3e)
118	BUILD_IRQ(0x3f)	118	BUILD_IRQ(0x3f)
119	BUILD_IRQ(0x40)	119	BUILD_IRQ(0x40)
120	BUILD_IRQ(0x41)	120	BUILD_IRQ(0x41)
121	BUILD_IRQ(0x42)	121	BUILD_IRQ(0x42)
122	BUILD_IRQ(0x43)	122	BUILD_IRQ(0x43)
123	BUILD_IRQ(0x44)	123	BUILD_IRQ(0x44)
124	BUILD_IRQ(0x45)	124	BUILD_IRQ(0x45)
125	BUILD_IRQ(0x46)	125	BUILD_IRQ(0x46)
126	BUILD_IRQ(0x47)	126	BUILD_IRQ(0x47)
127	BUILD_IRQ(0x48)	127	BUILD_IRQ(0x48)
128	BUILD_IRQ(0x49)	128	BUILD_IRQ(0x49)
129	BUILD_IRQ(0x4a)	129	BUILD_IRQ(0x4a)
130	#ifdef CONFIG_ETRAXFS	130	#ifdef CONFIG_ETRAXFS
131	BUILD_TIMER_IRQ(0x4b, 0)	131	BUILD_TIMER_IRQ(0x4b, 0)
132	#else	132	#else
133	BUILD_IRQ(0x4b)	133	BUILD_IRQ(0x4b)
134	#endif	134	#endif
135	BUILD_IRQ(0x4c)	135	BUILD_IRQ(0x4c)
136	BUILD_IRQ(0x4d)	136	BUILD_IRQ(0x4d)
137	BUILD_IRQ(0x4e)	137	BUILD_IRQ(0x4e)
138	BUILD_IRQ(0x4f)	138	BUILD_IRQ(0x4f)
139	BUILD_IRQ(0x50)	139	BUILD_IRQ(0x50)
140	#if MACH_IRQS > 32	140	#if MACH_IRQS > 32
141	BUILD_IRQ(0x51)	141	BUILD_IRQ(0x51)
142	BUILD_IRQ(0x52)	142	BUILD_IRQ(0x52)
143	BUILD_IRQ(0x53)	143	BUILD_IRQ(0x53)
144	BUILD_IRQ(0x54)	144	BUILD_IRQ(0x54)
145	BUILD_IRQ(0x55)	145	BUILD_IRQ(0x55)
146	BUILD_IRQ(0x56)	146	BUILD_IRQ(0x56)
147	BUILD_IRQ(0x57)	147	BUILD_IRQ(0x57)
148	BUILD_IRQ(0x58)	148	BUILD_IRQ(0x58)
149	BUILD_IRQ(0x59)	149	BUILD_IRQ(0x59)
150	BUILD_IRQ(0x5a)	150	BUILD_IRQ(0x5a)
151	BUILD_IRQ(0x5b)	151	BUILD_IRQ(0x5b)
152	BUILD_IRQ(0x5c)	152	BUILD_IRQ(0x5c)
153	BUILD_IRQ(0x5d)	153	BUILD_IRQ(0x5d)
154	BUILD_IRQ(0x5e)	154	BUILD_IRQ(0x5e)
155	BUILD_IRQ(0x5f)	155	BUILD_IRQ(0x5f)
156	BUILD_IRQ(0x60)	156	BUILD_IRQ(0x60)
157	BUILD_IRQ(0x61)	157	BUILD_IRQ(0x61)
158	BUILD_IRQ(0x62)	158	BUILD_IRQ(0x62)
159	BUILD_IRQ(0x63)	159	BUILD_IRQ(0x63)
160	BUILD_IRQ(0x64)	160	BUILD_IRQ(0x64)
161	BUILD_IRQ(0x65)	161	BUILD_IRQ(0x65)
162	BUILD_IRQ(0x66)	162	BUILD_IRQ(0x66)
163	BUILD_IRQ(0x67)	163	BUILD_IRQ(0x67)
164	BUILD_IRQ(0x68)	164	BUILD_IRQ(0x68)
165	BUILD_IRQ(0x69)	165	BUILD_IRQ(0x69)
166	BUILD_IRQ(0x6a)	166	BUILD_IRQ(0x6a)
167	BUILD_IRQ(0x6b)	167	BUILD_IRQ(0x6b)
168	BUILD_IRQ(0x6c)	168	BUILD_IRQ(0x6c)
169	BUILD_IRQ(0x6d)	169	BUILD_IRQ(0x6d)
170	BUILD_IRQ(0x6e)	170	BUILD_IRQ(0x6e)
171	BUILD_IRQ(0x6f)	171	BUILD_IRQ(0x6f)
172	BUILD_IRQ(0x70)	172	BUILD_IRQ(0x70)
173	#endif	173	#endif
174		174
175	/* Pointers to the low-level handlers. */	175	/* Pointers to the low-level handlers. */
176	static void (*interrupt[MACH_IRQS])(void) = {	176	static void (*interrupt[MACH_IRQS])(void) = {
177	IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,	177	IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
178	IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,	178	IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
179	IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,	179	IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
180	IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,	180	IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
181	IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,	181	IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
182	IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,	182	IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
183	IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,	183	IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
184	IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,	184	IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
185	IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,	185	IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
186	IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,	186	IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
187	IRQ0x4f_interrupt, IRQ0x50_interrupt,	187	IRQ0x4f_interrupt, IRQ0x50_interrupt,
188	#if MACH_IRQS > 32	188	#if MACH_IRQS > 32
189	IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,	189	IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,
190	IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,	190	IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,
191	IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,	191	IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,
192	IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,	192	IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,
193	IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,	193	IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,
194	IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,	194	IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,
195	IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,	195	IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,
196	IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,	196	IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,
197	IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,	197	IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,
198	IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,	198	IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,
199	IRQ0x6f_interrupt, IRQ0x70_interrupt,	199	IRQ0x6f_interrupt, IRQ0x70_interrupt,
200	#endif	200	#endif
201	};	201	};
202		202
203	void	203	void
204	block_irq(int irq, int cpu)	204	block_irq(int irq, int cpu)
205	{	205	{
206	int intr_mask;	206	int intr_mask;
207	unsigned long flags;	207	unsigned long flags;
208		208
209	spin_lock_irqsave(&irq_lock, flags);	209	spin_lock_irqsave(&irq_lock, flags);
210	/* Remember, 1 let thru, 0 block. */	210	/* Remember, 1 let thru, 0 block. */
211	if (irq - FIRST_IRQ < 32) {	211	if (irq - FIRST_IRQ < 32) {
212	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],	212	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
213	rw_mask, 0);	213	rw_mask, 0);
214	intr_mask &= ~(1 << (irq - FIRST_IRQ));	214	intr_mask &= ~(1 << (irq - FIRST_IRQ));
215	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,	215	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
216	0, intr_mask);	216	0, intr_mask);
217	} else {	217	} else {
218	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],	218	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
219	rw_mask, 1);	219	rw_mask, 1);
220	intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));	220	intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
221	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,	221	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
222	1, intr_mask);	222	1, intr_mask);
223	}	223	}
224	spin_unlock_irqrestore(&irq_lock, flags);	224	spin_unlock_irqrestore(&irq_lock, flags);
225	}	225	}
226		226
227	void	227	void
228	unblock_irq(int irq, int cpu)	228	unblock_irq(int irq, int cpu)
229	{	229	{
230	int intr_mask;	230	int intr_mask;
231	unsigned long flags;	231	unsigned long flags;
232		232
233	spin_lock_irqsave(&irq_lock, flags);	233	spin_lock_irqsave(&irq_lock, flags);
234	/* Remember, 1 let thru, 0 block. */	234	/* Remember, 1 let thru, 0 block. */
235	if (irq - FIRST_IRQ < 32) {	235	if (irq - FIRST_IRQ < 32) {
236	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],	236	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
237	rw_mask, 0);	237	rw_mask, 0);
238	intr_mask \|= (1 << (irq - FIRST_IRQ));	238	intr_mask \|= (1 << (irq - FIRST_IRQ));
239	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,	239	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
240	0, intr_mask);	240	0, intr_mask);
241	} else {	241	} else {
242	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],	242	intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
243	rw_mask, 1);	243	rw_mask, 1);
244	intr_mask \|= (1 << (irq - FIRST_IRQ - 32));	244	intr_mask \|= (1 << (irq - FIRST_IRQ - 32));
245	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,	245	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
246	1, intr_mask);	246	1, intr_mask);
247	}	247	}
248	spin_unlock_irqrestore(&irq_lock, flags);	248	spin_unlock_irqrestore(&irq_lock, flags);
249	}	249	}
250		250
251	/* Find out which CPU the irq should be allocated to. */	251	/* Find out which CPU the irq should be allocated to. */
252	static int irq_cpu(int irq)	252	static int irq_cpu(int irq)
253	{	253	{
254	int cpu;	254	int cpu;
255	unsigned long flags;	255	unsigned long flags;
256		256
257	spin_lock_irqsave(&irq_lock, flags);	257	spin_lock_irqsave(&irq_lock, flags);
258	cpu = irq_allocations[irq - FIRST_IRQ].cpu;	258	cpu = irq_allocations[irq - FIRST_IRQ].cpu;
259		259
260	/* Fixed interrupts stay on the local CPU. */	260	/* Fixed interrupts stay on the local CPU. */
261	if (cpu == CPU_FIXED)	261	if (cpu == CPU_FIXED)
262	{	262	{
263	spin_unlock_irqrestore(&irq_lock, flags);	263	spin_unlock_irqrestore(&irq_lock, flags);
264	return smp_processor_id();	264	return smp_processor_id();
265	}	265	}
266		266
267		267
268	/* Let the interrupt stay if possible */	268	/* Let the interrupt stay if possible */
269	if (cpu_isset(cpu, irq_allocations[irq - FIRST_IRQ].mask))	269	if (cpu_isset(cpu, irq_allocations[irq - FIRST_IRQ].mask))
270	goto out;	270	goto out;
271		271
272	/* IRQ must be moved to another CPU. */	272	/* IRQ must be moved to another CPU. */
273	cpu = first_cpu(irq_allocations[irq - FIRST_IRQ].mask);	273	cpu = first_cpu(irq_allocations[irq - FIRST_IRQ].mask);
274	irq_allocations[irq - FIRST_IRQ].cpu = cpu;	274	irq_allocations[irq - FIRST_IRQ].cpu = cpu;
275	out:	275	out:
276	spin_unlock_irqrestore(&irq_lock, flags);	276	spin_unlock_irqrestore(&irq_lock, flags);
277	return cpu;	277	return cpu;
278	}	278	}
279		279
280	void crisv32_mask_irq(int irq)	280	void crisv32_mask_irq(int irq)
281	{	281	{
282	int cpu;	282	int cpu;
283		283
284	for (cpu = 0; cpu < NR_CPUS; cpu++)	284	for (cpu = 0; cpu < NR_CPUS; cpu++)
285	block_irq(irq, cpu);	285	block_irq(irq, cpu);
286	}	286	}
287		287
288	void crisv32_unmask_irq(int irq)	288	void crisv32_unmask_irq(int irq)
289	{	289	{
290	unblock_irq(irq, irq_cpu(irq));	290	unblock_irq(irq, irq_cpu(irq));
291	}	291	}
292		292
293		293
294	static void enable_crisv32_irq(struct irq_data *data)	294	static void enable_crisv32_irq(struct irq_data *data)
295	{	295	{
296	crisv32_unmask_irq(data->irq);	296	crisv32_unmask_irq(data->irq);
297	}	297	}
298		298
299	static void disable_crisv32_irq(struct irq_data *data)	299	static void disable_crisv32_irq(struct irq_data *data)
300	{	300	{
301	crisv32_mask_irq(data->irq);	301	crisv32_mask_irq(data->irq);
302	}	302	}
303		303
304	static int set_affinity_crisv32_irq(struct irq_data *data,	304	static int set_affinity_crisv32_irq(struct irq_data *data,
305	const struct cpumask *dest, bool force)	305	const struct cpumask *dest, bool force)
306	{	306	{
307	unsigned long flags;	307	unsigned long flags;
308		308
309	spin_lock_irqsave(&irq_lock, flags);	309	spin_lock_irqsave(&irq_lock, flags);
310	irq_allocations[data->irq - FIRST_IRQ].mask = *dest;	310	irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
311	spin_unlock_irqrestore(&irq_lock, flags);	311	spin_unlock_irqrestore(&irq_lock, flags);
312	return 0;	312	return 0;
313	}	313	}
314		314
315	static struct irq_chip crisv32_irq_type = {	315	static struct irq_chip crisv32_irq_type = {
316	.name = "CRISv32",	316	.name = "CRISv32",
317	.irq_shutdown = disable_crisv32_irq,	317	.irq_shutdown = disable_crisv32_irq,
318	.irq_enable = enable_crisv32_irq,	318	.irq_enable = enable_crisv32_irq,
319	.irq_disable = disable_crisv32_irq,	319	.irq_disable = disable_crisv32_irq,
320	.irq_set_affinity = set_affinity_crisv32_irq,	320	.irq_set_affinity = set_affinity_crisv32_irq,
321	};	321	};
322		322
323	void	323	void
324	set_exception_vector(int n, irqvectptr addr)	324	set_exception_vector(int n, irqvectptr addr)
325	{	325	{
326	etrax_irv->v[n] = (irqvectptr) addr;	326	etrax_irv->v[n] = (irqvectptr) addr;
327	}	327	}
328		328
329	extern void do_IRQ(int irq, struct pt_regs * regs);	329	extern void do_IRQ(int irq, struct pt_regs * regs);
330		330
331	void	331	void
332	crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)	332	crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
333	{	333	{
334	/* Interrupts that may not be moved to another CPU and	334	/* Interrupts that may not be moved to another CPU and
335	* are IRQF_DISABLED may skip blocking. This is currently	335	* are IRQF_DISABLED may skip blocking. This is currently
336	* only valid for the timer IRQ and the IPI and is used	336	* only valid for the timer IRQ and the IPI and is used
337	* for the timer interrupt to avoid watchdog starvation.	337	* for the timer interrupt to avoid watchdog starvation.
338	*/	338	*/
339	if (!block) {	339	if (!block) {
340	do_IRQ(irq, regs);	340	do_IRQ(irq, regs);
341	return;	341	return;
342	}	342	}
343		343
344	block_irq(irq, smp_processor_id());	344	block_irq(irq, smp_processor_id());
345	do_IRQ(irq, regs);	345	do_IRQ(irq, regs);
346		346
347	unblock_irq(irq, irq_cpu(irq));	347	unblock_irq(irq, irq_cpu(irq));
348	}	348	}
349		349
350	/* If multiple interrupts occur simultaneously we get a multiple	350	/* If multiple interrupts occur simultaneously we get a multiple
351	* interrupt from the CPU and software has to sort out which	351	* interrupt from the CPU and software has to sort out which
352	* interrupts that happened. There are two special cases here:	352	* interrupts that happened. There are two special cases here:
353	*	353	*
354	* 1. Timer interrupts may never be blocked because of the	354	* 1. Timer interrupts may never be blocked because of the
355	* watchdog (refer to comment in include/asr/arch/irq.h)	355	* watchdog (refer to comment in include/asr/arch/irq.h)
356	* 2. GDB serial port IRQs are unhandled here and will be handled	356	* 2. GDB serial port IRQs are unhandled here and will be handled
357	* as a single IRQ when it strikes again because the GDB	357	* as a single IRQ when it strikes again because the GDB
358	* stubb wants to save the registers in its own fashion.	358	* stubb wants to save the registers in its own fashion.
359	*/	359	*/
360	void	360	void
361	crisv32_do_multiple(struct pt_regs* regs)	361	crisv32_do_multiple(struct pt_regs* regs)
362	{	362	{
363	int cpu;	363	int cpu;
364	int mask;	364	int mask;
365	int masked[NBR_REGS];	365	int masked[NBR_REGS];
366	int bit;	366	int bit;
367	int i;	367	int i;
368		368
369	cpu = smp_processor_id();	369	cpu = smp_processor_id();
370		370
371	/* An extra irq_enter here to prevent softIRQs to run after	371	/* An extra irq_enter here to prevent softIRQs to run after
372	* each do_IRQ. This will decrease the interrupt latency.	372	* each do_IRQ. This will decrease the interrupt latency.
373	*/	373	*/
374	irq_enter();	374	irq_enter();
375		375
376	for (i = 0; i < NBR_REGS; i++) {	376	for (i = 0; i < NBR_REGS; i++) {
377	/* Get which IRQs that happend. */	377	/* Get which IRQs that happend. */
378	masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],	378	masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
379	r_masked_vect, i);	379	r_masked_vect, i);
380		380
381	/* Calculate new IRQ mask with these IRQs disabled. */	381	/* Calculate new IRQ mask with these IRQs disabled. */
382	mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);	382	mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
383	mask &= ~masked[i];	383	mask &= ~masked[i];
384		384
385	/* Timer IRQ is never masked */	385	/* Timer IRQ is never masked */
386	#ifdef TIMER_VECT1	386	#ifdef TIMER_VECT1
387	if ((i == 1) && (masked[0] & TIMER_MASK))	387	if ((i == 1) && (masked[0] & TIMER_MASK))
388	mask \|= TIMER_MASK;	388	mask \|= TIMER_MASK;
389	#else	389	#else
390	if ((i == 0) && (masked[0] & TIMER_MASK))	390	if ((i == 0) && (masked[0] & TIMER_MASK))
391	mask \|= TIMER_MASK;	391	mask \|= TIMER_MASK;
392	#endif	392	#endif
393	/* Block all the IRQs */	393	/* Block all the IRQs */
394	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);	394	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
395		395
396	/* Check for timer IRQ and handle it special. */	396	/* Check for timer IRQ and handle it special. */
397	#ifdef TIMER_VECT1	397	#ifdef TIMER_VECT1
398	if ((i == 1) && (masked[i] & TIMER_MASK)) {	398	if ((i == 1) && (masked[i] & TIMER_MASK)) {
399	masked[i] &= ~TIMER_MASK;	399	masked[i] &= ~TIMER_MASK;
400	do_IRQ(TIMER0_INTR_VECT, regs);	400	do_IRQ(TIMER0_INTR_VECT, regs);
401	}	401	}
402	#else	402	#else
403	if ((i == 0) && (masked[i] & TIMER_MASK)) {	403	if ((i == 0) && (masked[i] & TIMER_MASK)) {
404	masked[i] &= ~TIMER_MASK;	404	masked[i] &= ~TIMER_MASK;
405	do_IRQ(TIMER0_INTR_VECT, regs);	405	do_IRQ(TIMER0_INTR_VECT, regs);
406	}	406	}
407	#endif	407	#endif
408	}	408	}
409		409
410	#ifdef IGNORE_MASK	410	#ifdef IGNORE_MASK
411	/* Remove IRQs that can't be handled as multiple. */	411	/* Remove IRQs that can't be handled as multiple. */
412	masked[0] &= ~IGNORE_MASK;	412	masked[0] &= ~IGNORE_MASK;
413	#endif	413	#endif
414		414
415	/* Handle the rest of the IRQs. */	415	/* Handle the rest of the IRQs. */
416	for (i = 0; i < NBR_REGS; i++) {	416	for (i = 0; i < NBR_REGS; i++) {
417	for (bit = 0; bit < 32; bit++) {	417	for (bit = 0; bit < 32; bit++) {
418	if (masked[i] & (1 << bit))	418	if (masked[i] & (1 << bit))
419	do_IRQ(bit + FIRST_IRQ + i*32, regs);	419	do_IRQ(bit + FIRST_IRQ + i*32, regs);
420	}	420	}
421	}	421	}
422		422
423	/* Unblock all the IRQs. */	423	/* Unblock all the IRQs. */
424	for (i = 0; i < NBR_REGS; i++) {	424	for (i = 0; i < NBR_REGS; i++) {
425	mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);	425	mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
426	mask \|= masked[i];	426	mask \|= masked[i];
427	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);	427	REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
428	}	428	}
429		429
430	/* This irq_exit() will trigger the soft IRQs. */	430	/* This irq_exit() will trigger the soft IRQs. */
431	irq_exit();	431	irq_exit();
432	}	432	}
433		433
434	/*	434	/*
435	* This is called by start_kernel. It fixes the IRQ masks and setup the	435	* This is called by start_kernel. It fixes the IRQ masks and setup the
436	* interrupt vector table to point to bad_interrupt pointers.	436	* interrupt vector table to point to bad_interrupt pointers.
437	*/	437	*/
438	void __init	438	void __init
439	init_IRQ(void)	439	init_IRQ(void)
440	{	440	{
441	int i;	441	int i;
442	int j;	442	int j;
443	reg_intr_vect_rw_mask vect_mask = {0};	443	reg_intr_vect_rw_mask vect_mask = {0};
444		444
445	/* Clear all interrupts masks. */	445	/* Clear all interrupts masks. */
446	for (i = 0; i < NBR_REGS; i++)	446	for (i = 0; i < NBR_REGS; i++)
447	REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);	447	REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);
448		448
449	for (i = 0; i < 256; i++)	449	for (i = 0; i < 256; i++)
450	etrax_irv->v[i] = weird_irq;	450	etrax_irv->v[i] = weird_irq;
451		451
452	/* Point all IRQ's to bad handlers. */	452	/* Point all IRQ's to bad handlers. */
453	for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {	453	for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
454	set_irq_chip_and_handler(j, &crisv32_irq_type,	454	irq_set_chip_and_handler(j, &crisv32_irq_type,
455	handle_simple_irq);	455	handle_simple_irq);
456	set_exception_vector(i, interrupt[j]);	456	set_exception_vector(i, interrupt[j]);
457	}	457	}
458		458
459	/* Mark Timer and IPI IRQs as CPU local */	459	/* Mark Timer and IPI IRQs as CPU local */
460	irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;	460	irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
461	irq_desc[TIMER0_INTR_VECT].status \|= IRQ_PER_CPU;	461	irq_set_status_flags(TIMER0_INTR_VECT, IRQ_PER_CPU);
462	irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;	462	irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
463	irq_desc[IPI_INTR_VECT].status \|= IRQ_PER_CPU;	463	irq_set_status_flags(IPI_INTR_VECT, IRQ_PER_CPU);
464		464
465	set_exception_vector(0x00, nmi_interrupt);	465	set_exception_vector(0x00, nmi_interrupt);
466	set_exception_vector(0x30, multiple_interrupt);	466	set_exception_vector(0x30, multiple_interrupt);
467		467
468	/* Set up handler for various MMU bus faults. */	468	/* Set up handler for various MMU bus faults. */
469	set_exception_vector(0x04, i_mmu_refill);	469	set_exception_vector(0x04, i_mmu_refill);
470	set_exception_vector(0x05, i_mmu_invalid);	470	set_exception_vector(0x05, i_mmu_invalid);
471	set_exception_vector(0x06, i_mmu_access);	471	set_exception_vector(0x06, i_mmu_access);
472	set_exception_vector(0x07, i_mmu_execute);	472	set_exception_vector(0x07, i_mmu_execute);
473	set_exception_vector(0x08, d_mmu_refill);	473	set_exception_vector(0x08, d_mmu_refill);
474	set_exception_vector(0x09, d_mmu_invalid);	474	set_exception_vector(0x09, d_mmu_invalid);
475	set_exception_vector(0x0a, d_mmu_access);	475	set_exception_vector(0x0a, d_mmu_access);
476	set_exception_vector(0x0b, d_mmu_write);	476	set_exception_vector(0x0b, d_mmu_write);
477		477
478	#ifdef CONFIG_BUG	478	#ifdef CONFIG_BUG
479	/* Break 14 handler, used to implement cheap BUG(). */	479	/* Break 14 handler, used to implement cheap BUG(). */
480	set_exception_vector(0x1e, breakh_BUG);	480	set_exception_vector(0x1e, breakh_BUG);
481	#endif	481	#endif
482		482
483	/* The system-call trap is reached by "break 13". */	483	/* The system-call trap is reached by "break 13". */
484	set_exception_vector(0x1d, system_call);	484	set_exception_vector(0x1d, system_call);
485		485
486	/* Exception handlers for debugging, both user-mode and kernel-mode. */	486	/* Exception handlers for debugging, both user-mode and kernel-mode. */
487		487
488	/* Break 8. */	488	/* Break 8. */
489	set_exception_vector(0x18, gdb_handle_exception);	489	set_exception_vector(0x18, gdb_handle_exception);
490	/* Hardware single step. */	490	/* Hardware single step. */
491	set_exception_vector(0x3, gdb_handle_exception);	491	set_exception_vector(0x3, gdb_handle_exception);
492	/* Hardware breakpoint. */	492	/* Hardware breakpoint. */
493	set_exception_vector(0xc, gdb_handle_exception);	493	set_exception_vector(0xc, gdb_handle_exception);
494		494
495	#ifdef CONFIG_ETRAX_KGDB	495	#ifdef CONFIG_ETRAX_KGDB
496	kgdb_init();	496	kgdb_init();
497	/* Everything is set up; now trap the kernel. */	497	/* Everything is set up; now trap the kernel. */
498	breakpoint();	498	breakpoint();
499	#endif	499	#endif
500	}	500	}
501		501
502		502

arch/cris/kernel/irq.c

Diff comments View file @ 508996b

 /*
  *
  *	linux/arch/cris/kernel/irq.c
  *
  *      Copyright (c) 2000,2007 Axis Communications AB
  *
  *      Authors: Bjorn Wesen (bjornw@axis.com)
  *
  * This file contains the code used by various IRQ handling routines:
  * asking for different IRQs should be done through these routines
  * instead of just grabbing them. Thus setups with different IRQ numbers
  * shouldn't result in any weird surprises, and installing new handlers
  * should be easier.
  *
  */
 /*
  * IRQs are in fact implemented a bit like signal handlers for the kernel.
  * Naturally it's not a 1:1 relation, but there are similarities.
  */
 #include <linux/module.h>
 #include <linux/ptrace.h>
 #include <linux/irq.h>
 #include <linux/kernel_stat.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/timex.h>
 #include <linux/random.h>
 #include <linux/init.h>
 #include <linux/seq_file.h>
 #include <linux/errno.h>
 #include <linux/spinlock.h>
 #include <asm/io.h>
-int show_interrupts(struct seq_file *p, void *v)
-{
-	int i = *(loff_t *) v, j;
-	struct irqaction * action;
-	unsigned long flags;
-	if (i == 0) {
-		seq_printf(p, "           ");
-		for_each_online_cpu(j)
-			seq_printf(p, "CPU%d       ",j);
-		seq_putc(p, '\n');
-	}
-	if (i < NR_IRQS) {
-		raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-		action = irq_desc[i].action;
-		if (!action)
-			goto skip;
-		seq_printf(p, "%3d: ",i);
-#ifndef CONFIG_SMP
-		seq_printf(p, "%10u ", kstat_irqs(i));
-#else
-		for_each_online_cpu(j)
-			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-#endif
-		seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
-		seq_printf(p, "  %s", action->name);
-		for (action=action->next; action; action = action->next)
-			seq_printf(p, ", %s", action->name);
-		seq_putc(p, '\n');
-skip:
-		raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-	}
-	return 0;
-}
 /* called by the assembler IRQ entry functions defined in irq.h
  * to dispatch the interrupts to registered handlers
  * interrupts are disabled upon entry - depending on if the
  * interrupt was registered with IRQF_DISABLED or not, interrupts
  * are re-enabled or not.
  */
 asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
 {
 	unsigned long sp;
 	struct pt_regs *old_regs = set_irq_regs(regs);
 	irq_enter();
 	sp = rdsp();
 	if (unlikely((sp & (PAGE_SIZE - 1)) < (PAGE_SIZE/8))) {
 		printk("do_IRQ: stack overflow: %lX\n", sp);
 		show_stack(NULL, (unsigned long *)sp);
 	}
 	generic_handle_irq(irq);
 	irq_exit();
 	set_irq_regs(old_regs);
 }
 void weird_irq(void)
 {
 	local_irq_disable();
 	printk("weird irq\n");
 	while(1);
 }

kernel/irq/manage.c

Diff comments View file @ 508996b

 /*
  * linux/kernel/irq/manage.c
  *
  * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
  * Copyright (C) 2005-2006 Thomas Gleixner
  *
  * This file contains driver APIs to the irq subsystem.
  */
 #include <linux/irq.h>
 #include <linux/kthread.h>
 #include <linux/module.h>
 #include <linux/random.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
 #include <linux/sched.h>
 #include "internals.h"
 #ifdef CONFIG_IRQ_FORCED_THREADING
 __read_mostly bool force_irqthreads;
 static int __init setup_forced_irqthreads(char *arg)
 {
 	force_irqthreads = true;
 	return 0;
 }
 early_param("threadirqs", setup_forced_irqthreads);
 #endif
 /**
  *	synchronize_irq - wait for pending IRQ handlers (on other CPUs)
  *	@irq: interrupt number to wait for
  *
  *	This function waits for any pending IRQ handlers for this interrupt
  *	to complete before returning. If you use this function while
  *	holding a resource the IRQ handler may need you will deadlock.
  *
  *	This function may be called - with care - from IRQ context.
  */
 void synchronize_irq(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	unsigned int state;
 	if (!desc)
 		return;
 	do {
 		unsigned long flags;
 		/*
 		 * Wait until we're out of the critical section.  This might
 		 * give the wrong answer due to the lack of memory barriers.
 		 */
 		while (desc->istate & IRQS_INPROGRESS)
 			cpu_relax();
 		/* Ok, that indicated we're done: double-check carefully. */
 		raw_spin_lock_irqsave(&desc->lock, flags);
 		state = desc->istate;
 		raw_spin_unlock_irqrestore(&desc->lock, flags);
 		/* Oops, that failed? */
 	} while (state & IRQS_INPROGRESS);
 	/*
 	 * We made sure that no hardirq handler is running. Now verify
 	 * that no threaded handlers are active.
 	 */
 	wait_event(desc->wait_for_threads, !atomic_read(&desc->threads_active));
 }
 EXPORT_SYMBOL(synchronize_irq);
 #ifdef CONFIG_SMP
 cpumask_var_t irq_default_affinity;
 /**
  *	irq_can_set_affinity - Check if the affinity of a given irq can be set
  *	@irq:		Interrupt to check
  *
  */
 int irq_can_set_affinity(unsigned int irq)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	if (!desc || !irqd_can_balance(&desc->irq_data) ||
 	    !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity)
 		return 0;
 	return 1;
 }
 /**
  *	irq_set_thread_affinity - Notify irq threads to adjust affinity
  *	@desc:		irq descriptor which has affitnity changed
  *
  *	We just set IRQTF_AFFINITY and delegate the affinity setting
  *	to the interrupt thread itself. We can not call
  *	set_cpus_allowed_ptr() here as we hold desc->lock and this
  *	code can be called from hard interrupt context.
  */
 void irq_set_thread_affinity(struct irq_desc *desc)
 {
 	struct irqaction *action = desc->action;
 	while (action) {
 		if (action->thread)
 			set_bit(IRQTF_AFFINITY, &action->thread_flags);
 		action = action->next;
 	}
 }
 #ifdef CONFIG_GENERIC_PENDING_IRQ
 static inline bool irq_can_move_pcntxt(struct irq_desc *desc)
 {
 	return irq_settings_can_move_pcntxt(desc);
 }
 static inline bool irq_move_pending(struct irq_desc *desc)
 {
 	return irqd_is_setaffinity_pending(&desc->irq_data);
 }
 static inline void
 irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask)
 {
 	cpumask_copy(desc->pending_mask, mask);
 }
 static inline void
 irq_get_pending(struct cpumask *mask, struct irq_desc *desc)
 {
 	cpumask_copy(mask, desc->pending_mask);
 }
 #else
 static inline bool irq_can_move_pcntxt(struct irq_desc *desc) { return true; }
 static inline bool irq_move_pending(struct irq_desc *desc) { return false; }
 static inline void
 irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) { }
 static inline void
 irq_get_pending(struct cpumask *mask, struct irq_desc *desc) { }
 #endif
 /**
  *	irq_set_affinity - Set the irq affinity of a given irq
  *	@irq:		Interrupt to set affinity
  *	@cpumask:	cpumask
  *
  */
 int irq_set_affinity(unsigned int irq, const struct cpumask *mask)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	struct irq_chip *chip = desc->irq_data.chip;
 	unsigned long flags;
 	int ret = 0;
 	if (!chip->irq_set_affinity)
 		return -EINVAL;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	if (irq_can_move_pcntxt(desc)) {
 		ret = chip->irq_set_affinity(&desc->irq_data, mask, false);
 		switch (ret) {
 		case IRQ_SET_MASK_OK:
 			cpumask_copy(desc->irq_data.affinity, mask);
 		case IRQ_SET_MASK_OK_NOCOPY:
 			irq_set_thread_affinity(desc);
 			ret = 0;
 		}
 	} else {
 		irqd_set_move_pending(&desc->irq_data);
 		irq_copy_pending(desc, mask);
 	}
 	if (desc->affinity_notify) {
 		kref_get(&desc->affinity_notify->kref);
 		schedule_work(&desc->affinity_notify->work);
 	}
 	irq_compat_set_affinity(desc);
 	irqd_set(&desc->irq_data, IRQD_AFFINITY_SET);
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	return ret;
 }
 int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
 	if (!desc)
 		return -EINVAL;
 	desc->affinity_hint = m;
 	irq_put_desc_unlock(desc, flags);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(irq_set_affinity_hint);
 static void irq_affinity_notify(struct work_struct *work)
 {
 	struct irq_affinity_notify *notify =
 		container_of(work, struct irq_affinity_notify, work);
 	struct irq_desc *desc = irq_to_desc(notify->irq);
 	cpumask_var_t cpumask;
 	unsigned long flags;
 	if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL))
 		goto out;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	if (irq_move_pending(desc))
 		irq_get_pending(cpumask, desc);
 	else
 		cpumask_copy(cpumask, desc->irq_data.affinity);
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	notify->notify(notify, cpumask);
 	free_cpumask_var(cpumask);
 out:
 	kref_put(&notify->kref, notify->release);
 }
 /**
  *	irq_set_affinity_notifier - control notification of IRQ affinity changes
  *	@irq:		Interrupt for which to enable/disable notification
  *	@notify:	Context for notification, or %NULL to disable
  *			notification.  Function pointers must be initialised;
  *			the other fields will be initialised by this function.
  *
  *	Must be called in process context.  Notification may only be enabled
  *	after the IRQ is allocated and must be disabled before the IRQ is
  *	freed using free_irq().
  */
 int
 irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	struct irq_affinity_notify *old_notify;
 	unsigned long flags;
 	/* The release function is promised process context */
 	might_sleep();
 	if (!desc)
 		return -EINVAL;
 	/* Complete initialisation of *notify */
 	if (notify) {
 		notify->irq = irq;
 		kref_init(&notify->kref);
 		INIT_WORK(&notify->work, irq_affinity_notify);
 	}
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	old_notify = desc->affinity_notify;
 	desc->affinity_notify = notify;
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	if (old_notify)
 		kref_put(&old_notify->kref, old_notify->release);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(irq_set_affinity_notifier);
 #ifndef CONFIG_AUTO_IRQ_AFFINITY
 /*
  * Generic version of the affinity autoselector.
  */
 static int
 setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct cpumask *set = irq_default_affinity;
 	int ret;
 	/* Excludes PER_CPU and NO_BALANCE interrupts */
 	if (!irq_can_set_affinity(irq))
 		return 0;
 	/*
 	 * Preserve an userspace affinity setup, but make sure that
 	 * one of the targets is online.
 	 */
 	if (irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) {
 		if (cpumask_intersects(desc->irq_data.affinity,
 				       cpu_online_mask))
 			set = desc->irq_data.affinity;
 		else {
 			irq_compat_clr_affinity(desc);
 			irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET);
 		}
 	}
 	cpumask_and(mask, cpu_online_mask, set);
 	ret = chip->irq_set_affinity(&desc->irq_data, mask, false);
 	switch (ret) {
 	case IRQ_SET_MASK_OK:
 		cpumask_copy(desc->irq_data.affinity, mask);
 	case IRQ_SET_MASK_OK_NOCOPY:
 		irq_set_thread_affinity(desc);
 	}
 	return 0;
 }
 #else
 static inline int
 setup_affinity(unsigned int irq, struct irq_desc *d, struct cpumask *mask)
 {
 	return irq_select_affinity(irq);
 }
 #endif
 /*
  * Called when affinity is set via /proc/irq
  */
 int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	unsigned long flags;
 	int ret;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	ret = setup_affinity(irq, desc, mask);
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	return ret;
 }
 #else
 static inline int
 setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask)
 {
 	return 0;
 }
 #endif
 void __disable_irq(struct irq_desc *desc, unsigned int irq, bool suspend)
 {
 	if (suspend) {
 		if (!desc->action || (desc->action->flags & IRQF_NO_SUSPEND))
 			return;
 		desc->istate |= IRQS_SUSPENDED;
 	}
 	if (!desc->depth++)
 		irq_disable(desc);
 }
 static int __disable_irq_nosync(unsigned int irq)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
 	if (!desc)
 		return -EINVAL;
 	__disable_irq(desc, irq, false);
 	irq_put_desc_busunlock(desc, flags);
 	return 0;
 }
 /**
  *	disable_irq_nosync - disable an irq without waiting
  *	@irq: Interrupt to disable
  *
  *	Disable the selected interrupt line.  Disables and Enables are
  *	nested.
  *	Unlike disable_irq(), this function does not ensure existing
  *	instances of the IRQ handler have completed before returning.
  *
  *	This function may be called from IRQ context.
  */
 void disable_irq_nosync(unsigned int irq)
 {
 	__disable_irq_nosync(irq);
 }
 EXPORT_SYMBOL(disable_irq_nosync);
 /**
  *	disable_irq - disable an irq and wait for completion
  *	@irq: Interrupt to disable
  *
  *	Disable the selected interrupt line.  Enables and Disables are
  *	nested.
  *	This function waits for any pending IRQ handlers for this interrupt
  *	to complete before returning. If you use this function while
  *	holding a resource the IRQ handler may need you will deadlock.
  *
  *	This function may be called - with care - from IRQ context.
  */
 void disable_irq(unsigned int irq)
 {
 	if (!__disable_irq_nosync(irq))
 		synchronize_irq(irq);
 }
 EXPORT_SYMBOL(disable_irq);
 void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume)
 {
 	if (resume) {
 		if (!(desc->istate & IRQS_SUSPENDED)) {
 			if (!desc->action)
 				return;
 			if (!(desc->action->flags & IRQF_FORCE_RESUME))
 				return;
 			/* Pretend that it got disabled ! */
 			desc->depth++;
 		}
 		desc->istate &= ~IRQS_SUSPENDED;
 	}
 	switch (desc->depth) {
 	case 0:
  err_out:
 		WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", irq);
 		break;
 	case 1: {
 		if (desc->istate & IRQS_SUSPENDED)
 			goto err_out;
 		/* Prevent probing on this irq: */
 		irq_settings_set_noprobe(desc);
 		irq_enable(desc);
 		check_irq_resend(desc, irq);
 		/* fall-through */
 	}
 	default:
 		desc->depth--;
 	}
 }
 /**
  *	enable_irq - enable handling of an irq
  *	@irq: Interrupt to enable
  *
  *	Undoes the effect of one call to disable_irq().  If this
  *	matches the last disable, processing of interrupts on this
  *	IRQ line is re-enabled.
  *
  *	This function may be called from IRQ context only when
  *	desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL !
  */
 void enable_irq(unsigned int irq)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
 	if (!desc)
 		return;
 	if (WARN(!desc->irq_data.chip,
 		 KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq))
 		goto out;
 	__enable_irq(desc, irq, false);
 out:
 	irq_put_desc_busunlock(desc, flags);
 }
 EXPORT_SYMBOL(enable_irq);
 static int set_irq_wake_real(unsigned int irq, unsigned int on)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	int ret = -ENXIO;
 	if (desc->irq_data.chip->irq_set_wake)
 		ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on);
 	return ret;
 }
 /**
  *	irq_set_irq_wake - control irq power management wakeup
  *	@irq:	interrupt to control
  *	@on:	enable/disable power management wakeup
  *
  *	Enable/disable power management wakeup mode, which is
  *	disabled by default.  Enables and disables must match,
  *	just as they match for non-wakeup mode support.
  *
  *	Wakeup mode lets this IRQ wake the system from sleep
  *	states like "suspend to RAM".
  */
 int irq_set_irq_wake(unsigned int irq, unsigned int on)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
 	int ret = 0;
 	/* wakeup-capable irqs can be shared between drivers that
 	 * don't need to have the same sleep mode behaviors.
 	 */
 	if (on) {
 		if (desc->wake_depth++ == 0) {
 			ret = set_irq_wake_real(irq, on);
 			if (ret)
 				desc->wake_depth = 0;
 			else
 				irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE);
 		}
 	} else {
 		if (desc->wake_depth == 0) {
 			WARN(1, "Unbalanced IRQ %d wake disable\n", irq);
 		} else if (--desc->wake_depth == 0) {
 			ret = set_irq_wake_real(irq, on);
 			if (ret)
 				desc->wake_depth = 1;
 			else
 				irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE);
 		}
 	}
 	irq_put_desc_busunlock(desc, flags);
 	return ret;
 }
 EXPORT_SYMBOL(irq_set_irq_wake);
 /*
  * Internal function that tells the architecture code whether a
  * particular irq has been exclusively allocated or is available
  * for driver use.
  */
 int can_request_irq(unsigned int irq, unsigned long irqflags)
 {
 	unsigned long flags;
 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
 	int canrequest = 0;
 	if (!desc)
 		return 0;
 	if (irq_settings_can_request(desc)) {
 		if (desc->action)
 			if (irqflags & desc->action->flags & IRQF_SHARED)
 				canrequest =1;
 	}
 	irq_put_desc_unlock(desc, flags);
 	return canrequest;
 }
 int __irq_set_trigger(struct irq_desc *desc, unsigned int irq,
 		      unsigned long flags)
 {
 	struct irq_chip *chip = desc->irq_data.chip;
 	int ret, unmask = 0;
 	if (!chip || !chip->irq_set_type) {
 		/*
 		 * IRQF_TRIGGER_* but the PIC does not support multiple
 		 * flow-types?
 		 */
 		pr_debug("No set_type function for IRQ %d (%s)\n", irq,
 				chip ? (chip->name ? : "unknown") : "unknown");
 		return 0;
 	}
 	flags &= IRQ_TYPE_SENSE_MASK;
 	if (chip->flags & IRQCHIP_SET_TYPE_MASKED) {
 		if (!(desc->istate & IRQS_MASKED))
 			mask_irq(desc);
 		if (!(desc->istate & IRQS_DISABLED))
 			unmask = 1;
 	}
 	/* caller masked out all except trigger mode flags */
 	ret = chip->irq_set_type(&desc->irq_data, flags);
 	switch (ret) {
 	case IRQ_SET_MASK_OK:
 		irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK);
 		irqd_set(&desc->irq_data, flags);
 	case IRQ_SET_MASK_OK_NOCOPY:
 		flags = irqd_get_trigger_type(&desc->irq_data);
 		irq_settings_set_trigger_mask(desc, flags);
 		irqd_clear(&desc->irq_data, IRQD_LEVEL);
 		irq_settings_clr_level(desc);
 		if (flags & IRQ_TYPE_LEVEL_MASK) {
 			irq_settings_set_level(desc);
 			irqd_set(&desc->irq_data, IRQD_LEVEL);
 		}
 		if (chip != desc->irq_data.chip)
 			irq_chip_set_defaults(desc->irq_data.chip);
 		ret = 0;
 		break;
 	default:
 		pr_err("setting trigger mode %lu for irq %u failed (%pF)\n",
 		       flags, irq, chip->irq_set_type);
 	}
 	if (unmask)
 		unmask_irq(desc);
 	return ret;
 }
 /*
  * Default primary interrupt handler for threaded interrupts. Is
  * assigned as primary handler when request_threaded_irq is called
  * with handler == NULL. Useful for oneshot interrupts.
  */
 static irqreturn_t irq_default_primary_handler(int irq, void *dev_id)
 {
 	return IRQ_WAKE_THREAD;
 }
 /*
  * Primary handler for nested threaded interrupts. Should never be
  * called.
  */
 static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id)
 {
 	WARN(1, "Primary handler called for nested irq %d\n", irq);
 	return IRQ_NONE;
 }
 static int irq_wait_for_interrupt(struct irqaction *action)
 {
 	while (!kthread_should_stop()) {
 		set_current_state(TASK_INTERRUPTIBLE);
 		if (test_and_clear_bit(IRQTF_RUNTHREAD,
 				       &action->thread_flags)) {
 			__set_current_state(TASK_RUNNING);
 			return 0;
 		}
 		schedule();
 	}
 	return -1;
 }
 /*
  * Oneshot interrupts keep the irq line masked until the threaded
  * handler finished. unmask if the interrupt has not been disabled and
  * is marked MASKED.
  */
 static void irq_finalize_oneshot(struct irq_desc *desc,
 				 struct irqaction *action, bool force)
 {
 	if (!(desc->istate & IRQS_ONESHOT))
 		return;
 again:
 	chip_bus_lock(desc);
 	raw_spin_lock_irq(&desc->lock);
 	/*
 	 * Implausible though it may be we need to protect us against
 	 * the following scenario:
 	 *
 	 * The thread is faster done than the hard interrupt handler
 	 * on the other CPU. If we unmask the irq line then the
 	 * interrupt can come in again and masks the line, leaves due
 	 * to IRQS_INPROGRESS and the irq line is masked forever.
 	 *
 	 * This also serializes the state of shared oneshot handlers
 	 * versus "desc->threads_onehsot |= action->thread_mask;" in
 	 * irq_wake_thread(). See the comment there which explains the
 	 * serialization.
 	 */
 	if (unlikely(desc->istate & IRQS_INPROGRESS)) {
 		raw_spin_unlock_irq(&desc->lock);
 		chip_bus_sync_unlock(desc);
 		cpu_relax();
 		goto again;
 	}
 	/*
 	 * Now check again, whether the thread should run. Otherwise
 	 * we would clear the threads_oneshot bit of this thread which
 	 * was just set.
 	 */
 	if (!force && test_bit(IRQTF_RUNTHREAD, &action->thread_flags))
 		goto out_unlock;
 	desc->threads_oneshot &= ~action->thread_mask;
 	if (!desc->threads_oneshot && !(desc->istate & IRQS_DISABLED) &&
 	    (desc->istate & IRQS_MASKED)) {
 		irq_compat_clr_masked(desc);
 		desc->istate &= ~IRQS_MASKED;
 		desc->irq_data.chip->irq_unmask(&desc->irq_data);
 	}
 out_unlock:
 	raw_spin_unlock_irq(&desc->lock);
 	chip_bus_sync_unlock(desc);
 }
 #ifdef CONFIG_SMP
 /*
  * Check whether we need to chasnge the affinity of the interrupt thread.
  */
 static void
 irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action)
 {
 	cpumask_var_t mask;
 	if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags))
 		return;
 	/*
 	 * In case we are out of memory we set IRQTF_AFFINITY again and
 	 * try again next time
 	 */
 	if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
 		set_bit(IRQTF_AFFINITY, &action->thread_flags);
 		return;
 	}
 	raw_spin_lock_irq(&desc->lock);
 	cpumask_copy(mask, desc->irq_data.affinity);
 	raw_spin_unlock_irq(&desc->lock);
 	set_cpus_allowed_ptr(current, mask);
 	free_cpumask_var(mask);
 }
 #else
 static inline void
 irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { }
 #endif
 /*
  * Interrupts which are not explicitely requested as threaded
  * interrupts rely on the implicit bh/preempt disable of the hard irq
  * context. So we need to disable bh here to avoid deadlocks and other
  * side effects.
  */
 static void
 irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action)
 {
 	local_bh_disable();
 	action->thread_fn(action->irq, action->dev_id);
 	irq_finalize_oneshot(desc, action, false);
 	local_bh_enable();
 }
 /*
  * Interrupts explicitely requested as threaded interupts want to be
  * preemtible - many of them need to sleep and wait for slow busses to
  * complete.
  */
 static void irq_thread_fn(struct irq_desc *desc, struct irqaction *action)
 {
 	action->thread_fn(action->irq, action->dev_id);
 	irq_finalize_oneshot(desc, action, false);
 }
 /*
  * Interrupt handler thread
  */
 static int irq_thread(void *data)
 {
 	static const struct sched_param param = {
 		.sched_priority = MAX_USER_RT_PRIO/2,
 	};
 	struct irqaction *action = data;
 	struct irq_desc *desc = irq_to_desc(action->irq);
 	void (*handler_fn)(struct irq_desc *desc, struct irqaction *action);
 	int wake;
 	if (force_irqthreads & test_bit(IRQTF_FORCED_THREAD,
 					&action->thread_flags))
 		handler_fn = irq_forced_thread_fn;
 	else
 		handler_fn = irq_thread_fn;
 	sched_setscheduler(current, SCHED_FIFO, &param);
 	current->irqaction = action;
 	while (!irq_wait_for_interrupt(action)) {
 		irq_thread_check_affinity(desc, action);
 		atomic_inc(&desc->threads_active);
 		raw_spin_lock_irq(&desc->lock);
 		if (unlikely(desc->istate & IRQS_DISABLED)) {
 			/*
 			 * CHECKME: We might need a dedicated
 			 * IRQ_THREAD_PENDING flag here, which
 			 * retriggers the thread in check_irq_resend()
 			 * but AFAICT IRQS_PENDING should be fine as it
 			 * retriggers the interrupt itself --- tglx
 			 */
 			irq_compat_set_pending(desc);
 			desc->istate |= IRQS_PENDING;
 			raw_spin_unlock_irq(&desc->lock);
 		} else {
 			raw_spin_unlock_irq(&desc->lock);
 			handler_fn(desc, action);
 		}
 		wake = atomic_dec_and_test(&desc->threads_active);
 		if (wake && waitqueue_active(&desc->wait_for_threads))
 			wake_up(&desc->wait_for_threads);
 	}
 	/* Prevent a stale desc->threads_oneshot */
 	irq_finalize_oneshot(desc, action, true);
 	/*
 	 * Clear irqaction. Otherwise exit_irq_thread() would make
 	 * fuzz about an active irq thread going into nirvana.
 	 */
 	current->irqaction = NULL;
 	return 0;
 }
 /*
  * Called from do_exit()
  */
 void exit_irq_thread(void)
 {
 	struct task_struct *tsk = current;
 	struct irq_desc *desc;
 	if (!tsk->irqaction)
 		return;
 	printk(KERN_ERR
 	       "exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n",
 	       tsk->comm ? tsk->comm : "", tsk->pid, tsk->irqaction->irq);
 	desc = irq_to_desc(tsk->irqaction->irq);
 	/*
 	 * Prevent a stale desc->threads_oneshot. Must be called
 	 * before setting the IRQTF_DIED flag.
 	 */
 	irq_finalize_oneshot(desc, tsk->irqaction, true);
 	/*
 	 * Set the THREAD DIED flag to prevent further wakeups of the
 	 * soon to be gone threaded handler.
 	 */
 	set_bit(IRQTF_DIED, &tsk->irqaction->flags);
 }
 static void irq_setup_forced_threading(struct irqaction *new)
 {
 	if (!force_irqthreads)
 		return;
 	if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT))
 		return;
 	new->flags |= IRQF_ONESHOT;
 	if (!new->thread_fn) {
 		set_bit(IRQTF_FORCED_THREAD, &new->thread_flags);
 		new->thread_fn = new->handler;
 		new->handler = irq_default_primary_handler;
 	}
 }
 /*
  * Internal function to register an irqaction - typically used to
  * allocate special interrupts that are part of the architecture.
  */
 static int
 __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
 {
 	struct irqaction *old, **old_ptr;
 	const char *old_name = NULL;
 	unsigned long flags, thread_mask = 0;
 	int ret, nested, shared = 0;
 	cpumask_var_t mask;
 	if (!desc)
 		return -EINVAL;
 	if (desc->irq_data.chip == &no_irq_chip)
 		return -ENOSYS;
 	/*
 	 * Some drivers like serial.c use request_irq() heavily,
 	 * so we have to be careful not to interfere with a
 	 * running system.
 	 */
 	if (new->flags & IRQF_SAMPLE_RANDOM) {
 		/*
 		 * This function might sleep, we want to call it first,
 		 * outside of the atomic block.
 		 * Yes, this might clear the entropy pool if the wrong
 		 * driver is attempted to be loaded, without actually
 		 * installing a new handler, but is this really a problem,
 		 * only the sysadmin is able to do this.
 		 */
 		rand_initialize_irq(irq);
 	}
 	/*
 	 * Check whether the interrupt nests into another interrupt
 	 * thread.
 	 */
 	nested = irq_settings_is_nested_thread(desc);
 	if (nested) {
 		if (!new->thread_fn)
 			return -EINVAL;
 		/*
 		 * Replace the primary handler which was provided from
 		 * the driver for non nested interrupt handling by the
 		 * dummy function which warns when called.
 		 */
 		new->handler = irq_nested_primary_handler;
 	} else {
 		irq_setup_forced_threading(new);
 	}
 	/*
 	 * Create a handler thread when a thread function is supplied
 	 * and the interrupt does not nest into another interrupt
 	 * thread.
 	 */
 	if (new->thread_fn && !nested) {
 		struct task_struct *t;
 		t = kthread_create(irq_thread, new, "irq/%d-%s", irq,
 				   new->name);
 		if (IS_ERR(t))
 			return PTR_ERR(t);
 		/*
 		 * We keep the reference to the task struct even if
 		 * the thread dies to avoid that the interrupt code
 		 * references an already freed task_struct.
 		 */
 		get_task_struct(t);
 		new->thread = t;
 	}
 	if (!alloc_cpumask_var(&mask, GFP_KERNEL)) {
 		ret = -ENOMEM;
 		goto out_thread;
 	}
 	/*
 	 * The following block of code has to be executed atomically
 	 */
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	old_ptr = &desc->action;
 	old = *old_ptr;
 	if (old) {
 		/*
 		 * Can't share interrupts unless both agree to and are
 		 * the same type (level, edge, polarity). So both flag
 		 * fields must have IRQF_SHARED set and the bits which
 		 * set the trigger type must match. Also all must
 		 * agree on ONESHOT.
 		 */
 		if (!((old->flags & new->flags) & IRQF_SHARED) ||
 		    ((old->flags ^ new->flags) & IRQF_TRIGGER_MASK) ||
 		    ((old->flags ^ new->flags) & IRQF_ONESHOT)) {
 			old_name = old->name;
 			goto mismatch;
 		}
 		/* All handlers must agree on per-cpuness */
 		if ((old->flags & IRQF_PERCPU) !=
 		    (new->flags & IRQF_PERCPU))
 			goto mismatch;
 		/* add new interrupt at end of irq queue */
 		do {
 			thread_mask |= old->thread_mask;
 			old_ptr = &old->next;
 			old = *old_ptr;
 		} while (old);
 		shared = 1;
 	}
 	/*
 	 * Setup the thread mask for this irqaction. Unlikely to have
 	 * 32 resp 64 irqs sharing one line, but who knows.
 	 */
 	if (new->flags & IRQF_ONESHOT && thread_mask == ~0UL) {
 		ret = -EBUSY;
 		goto out_mask;
 	}
 	new->thread_mask = 1 << ffz(thread_mask);
 	if (!shared) {
 		irq_chip_set_defaults(desc->irq_data.chip);
 		init_waitqueue_head(&desc->wait_for_threads);
 		/* Setup the type (level, edge polarity) if configured: */
 		if (new->flags & IRQF_TRIGGER_MASK) {
 			ret = __irq_set_trigger(desc, irq,
 					new->flags & IRQF_TRIGGER_MASK);
 			if (ret)
 				goto out_mask;
 		}
 		desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \
 				  IRQS_INPROGRESS | IRQS_ONESHOT | \
 				  IRQS_WAITING);
 		if (new->flags & IRQF_PERCPU) {
 			irqd_set(&desc->irq_data, IRQD_PER_CPU);
 			irq_settings_set_per_cpu(desc);
 		}
 		if (new->flags & IRQF_ONESHOT)
 			desc->istate |= IRQS_ONESHOT;
 		if (irq_settings_can_autoenable(desc))
 			irq_startup(desc);
 		else
 			/* Undo nested disables: */
 			desc->depth = 1;
 		/* Exclude IRQ from balancing if requested */
 		if (new->flags & IRQF_NOBALANCING) {
 			irq_settings_set_no_balancing(desc);
 			irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
 		}
 		/* Set default affinity mask once everything is setup */
 		setup_affinity(irq, desc, mask);
 	} else if (new->flags & IRQF_TRIGGER_MASK) {
 		unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK;
 		unsigned int omsk = irq_settings_get_trigger_mask(desc);
 		if (nmsk != omsk)
 			/* hope the handler works with current  trigger mode */
 			pr_warning("IRQ %d uses trigger mode %u; requested %u\n",
 				   irq, nmsk, omsk);
 	}
 	new->irq = irq;
 	*old_ptr = new;
 	/* Reset broken irq detection when installing new handler */
 	desc->irq_count = 0;
 	desc->irqs_unhandled = 0;
 	/*
 	 * Check whether we disabled the irq via the spurious handler
 	 * before. Reenable it and give it another chance.
 	 */
 	if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) {
 		desc->istate &= ~IRQS_SPURIOUS_DISABLED;
 		__enable_irq(desc, irq, false);
 	}
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	/*
 	 * Strictly no need to wake it up, but hung_task complains
 	 * when no hard interrupt wakes the thread up.
 	 */
 	if (new->thread)
 		wake_up_process(new->thread);
 	register_irq_proc(irq, desc);
 	new->dir = NULL;
 	register_handler_proc(irq, new);
 	return 0;
 mismatch:
 #ifdef CONFIG_DEBUG_SHIRQ
 	if (!(new->flags & IRQF_PROBE_SHARED)) {
 		printk(KERN_ERR "IRQ handler type mismatch for IRQ %d\n", irq);
 		if (old_name)
 			printk(KERN_ERR "current handler: %s\n", old_name);
 		dump_stack();
 	}
 #endif
 	ret = -EBUSY;
 out_mask:
+	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	free_cpumask_var(mask);
 out_thread:
-	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	if (new->thread) {
 		struct task_struct *t = new->thread;
 		new->thread = NULL;
 		if (likely(!test_bit(IRQTF_DIED, &new->thread_flags)))
 			kthread_stop(t);
 		put_task_struct(t);
 	}
 	return ret;
 }
 /**
  *	setup_irq - setup an interrupt
  *	@irq: Interrupt line to setup
  *	@act: irqaction for the interrupt
  *
  * Used to statically setup interrupts in the early boot process.
  */
 int setup_irq(unsigned int irq, struct irqaction *act)
 {
 	int retval;
 	struct irq_desc *desc = irq_to_desc(irq);
 	chip_bus_lock(desc);
 	retval = __setup_irq(irq, desc, act);
 	chip_bus_sync_unlock(desc);
 	return retval;
 }
 EXPORT_SYMBOL_GPL(setup_irq);
  /*
  * Internal function to unregister an irqaction - used to free
  * regular and special interrupts that are part of the architecture.
  */
 static struct irqaction *__free_irq(unsigned int irq, void *dev_id)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	struct irqaction *action, **action_ptr;
 	unsigned long flags;
 	WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq);
 	if (!desc)
 		return NULL;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	/*
 	 * There can be multiple actions per IRQ descriptor, find the right
 	 * one based on the dev_id:
 	 */
 	action_ptr = &desc->action;
 	for (;;) {
 		action = *action_ptr;
 		if (!action) {
 			WARN(1, "Trying to free already-free IRQ %d\n", irq);
 			raw_spin_unlock_irqrestore(&desc->lock, flags);
 			return NULL;
 		}
 		if (action->dev_id == dev_id)
 			break;
 		action_ptr = &action->next;
 	}
 	/* Found it - now remove it from the list of entries: */
 	*action_ptr = action->next;
 	/* Currently used only by UML, might disappear one day: */
 #ifdef CONFIG_IRQ_RELEASE_METHOD
 	if (desc->irq_data.chip->release)
 		desc->irq_data.chip->release(irq, dev_id);
 #endif
 	/* If this was the last handler, shut down the IRQ line: */
 	if (!desc->action)
 		irq_shutdown(desc);
 #ifdef CONFIG_SMP
 	/* make sure affinity_hint is cleaned up */
 	if (WARN_ON_ONCE(desc->affinity_hint))
 		desc->affinity_hint = NULL;
 #endif
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	unregister_handler_proc(irq, action);
 	/* Make sure it's not being used on another CPU: */
 	synchronize_irq(irq);
 #ifdef CONFIG_DEBUG_SHIRQ
 	/*
 	 * It's a shared IRQ -- the driver ought to be prepared for an IRQ
 	 * event to happen even now it's being freed, so let's make sure that
 	 * is so by doing an extra call to the handler ....
 	 *
 	 * ( We do this after actually deregistering it, to make sure that a
 	 *   'real' IRQ doesn't run in * parallel with our fake. )
 	 */
 	if (action->flags & IRQF_SHARED) {
 		local_irq_save(flags);
 		action->handler(irq, dev_id);
 		local_irq_restore(flags);
 	}
 #endif
 	if (action->thread) {
 		if (!test_bit(IRQTF_DIED, &action->thread_flags))
 			kthread_stop(action->thread);
 		put_task_struct(action->thread);
 	}
 	return action;
 }
 /**
  *	remove_irq - free an interrupt
  *	@irq: Interrupt line to free
  *	@act: irqaction for the interrupt
  *
  * Used to remove interrupts statically setup by the early boot process.
  */
 void remove_irq(unsigned int irq, struct irqaction *act)
 {
 	__free_irq(irq, act->dev_id);
 }
 EXPORT_SYMBOL_GPL(remove_irq);
 /**
  *	free_irq - free an interrupt allocated with request_irq
  *	@irq: Interrupt line to free
  *	@dev_id: Device identity to free
  *
  *	Remove an interrupt handler. The handler is removed and if the
  *	interrupt line is no longer in use by any driver it is disabled.
  *	On a shared IRQ the caller must ensure the interrupt is disabled
  *	on the card it drives before calling this function. The function
  *	does not return until any executing interrupts for this IRQ
  *	have completed.
  *
  *	This function must not be called from interrupt context.
  */
 void free_irq(unsigned int irq, void *dev_id)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	if (!desc)
 		return;
 #ifdef CONFIG_SMP
 	if (WARN_ON(desc->affinity_notify))
 		desc->affinity_notify = NULL;
 #endif
 	chip_bus_lock(desc);
 	kfree(__free_irq(irq, dev_id));
 	chip_bus_sync_unlock(desc);
 }
 EXPORT_SYMBOL(free_irq);
 /**
  *	request_threaded_irq - allocate an interrupt line
  *	@irq: Interrupt line to allocate
  *	@handler: Function to be called when the IRQ occurs.
  *		  Primary handler for threaded interrupts
  *		  If NULL and thread_fn != NULL the default
  *		  primary handler is installed
  *	@thread_fn: Function called from the irq handler thread
  *		    If NULL, no irq thread is created
  *	@irqflags: Interrupt type flags
  *	@devname: An ascii name for the claiming device
  *	@dev_id: A cookie passed back to the handler function
  *
  *	This call allocates interrupt resources and enables the
  *	interrupt line and IRQ handling. From the point this
  *	call is made your handler function may be invoked. Since
  *	your handler function must clear any interrupt the board
  *	raises, you must take care both to initialise your hardware
  *	and to set up the interrupt handler in the right order.
  *
  *	If you want to set up a threaded irq handler for your device
  *	then you need to supply @handler and @thread_fn. @handler ist
  *	still called in hard interrupt context and has to check
  *	whether the interrupt originates from the device. If yes it
  *	needs to disable the interrupt on the device and return
  *	IRQ_WAKE_THREAD which will wake up the handler thread and run
  *	@thread_fn. This split handler design is necessary to support
  *	shared interrupts.
  *
  *	Dev_id must be globally unique. Normally the address of the
  *	device data structure is used as the cookie. Since the handler
  *	receives this value it makes sense to use it.
  *
  *	If your interrupt is shared you must pass a non NULL dev_id
  *	as this is required when freeing the interrupt.
  *
  *	Flags:
  *
  *	IRQF_SHARED		Interrupt is shared
  *	IRQF_SAMPLE_RANDOM	The interrupt can be used for entropy
  *	IRQF_TRIGGER_*		Specify active edge(s) or level
  *
  */
 int request_threaded_irq(unsigned int irq, irq_handler_t handler,
 			 irq_handler_t thread_fn, unsigned long irqflags,
 			 const char *devname, void *dev_id)
 {
 	struct irqaction *action;
 	struct irq_desc *desc;
 	int retval;
 	/*
 	 * Sanity-check: shared interrupts must pass in a real dev-ID,
 	 * otherwise we'll have trouble later trying to figure out
 	 * which interrupt is which (messes up the interrupt freeing
 	 * logic etc).
 	 */
 	if ((irqflags & IRQF_SHARED) && !dev_id)
 		return -EINVAL;
 	desc = irq_to_desc(irq);
 	if (!desc)
 		return -EINVAL;
 	if (!irq_settings_can_request(desc))
 		return -EINVAL;
 	if (!handler) {
 		if (!thread_fn)
 			return -EINVAL;
 		handler = irq_default_primary_handler;
 	}
 	action = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
 	if (!action)
 		return -ENOMEM;
 	action->handler = handler;
 	action->thread_fn = thread_fn;
 	action->flags = irqflags;
 	action->name = devname;
 	action->dev_id = dev_id;
 	chip_bus_lock(desc);
 	retval = __setup_irq(irq, desc, action);
 	chip_bus_sync_unlock(desc);
 	if (retval)
 		kfree(action);
 #ifdef CONFIG_DEBUG_SHIRQ_FIXME
 	if (!retval && (irqflags & IRQF_SHARED)) {
 		/*
 		 * It's a shared IRQ -- the driver ought to be prepared for it
 		 * to happen immediately, so let's make sure....
 		 * We disable the irq to make sure that a 'real' IRQ doesn't
 		 * run in parallel with our fake.
 		 */
 		unsigned long flags;
 		disable_irq(irq);
 		local_irq_save(flags);
 		handler(irq, dev_id);
 		local_irq_restore(flags);
 		enable_irq(irq);
 	}
 #endif
 	return retval;
 }
 EXPORT_SYMBOL(request_threaded_irq);
 /**
  *	request_any_context_irq - allocate an interrupt line
  *	@irq: Interrupt line to allocate
  *	@handler: Function to be called when the IRQ occurs.
  *		  Threaded handler for threaded interrupts.
  *	@flags: Interrupt type flags
  *	@name: An ascii name for the claiming device
  *	@dev_id: A cookie passed back to the handler function
  *
  *	This call allocates interrupt resources and enables the
  *	interrupt line and IRQ handling. It selects either a
  *	hardirq or threaded handling method depending on the
  *	context.
  *
  *	On failure, it returns a negative value. On success,
  *	it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.
  */
 int request_any_context_irq(unsigned int irq, irq_handler_t handler,
 			    unsigned long flags, const char *name, void *dev_id)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	int ret;
 	if (!desc)
 		return -EINVAL;
 	if (irq_settings_is_nested_thread(desc)) {
 		ret = request_threaded_irq(irq, NULL, handler,
 					   flags, name, dev_id);
 		return !ret ? IRQC_IS_NESTED : ret;
 	}
 	ret = request_irq(irq, handler, flags, name, dev_id);
 	return !ret ? IRQC_IS_HARDIRQ : ret;
 }
 EXPORT_SYMBOL_GPL(request_any_context_irq);

kernel/irq/proc.c

Diff comments View file @ 508996b

 /*
  * linux/kernel/irq/proc.c
  *
  * Copyright (C) 1992, 1998-2004 Linus Torvalds, Ingo Molnar
  *
  * This file contains the /proc/irq/ handling code.
  */
 #include <linux/irq.h>
 #include <linux/gfp.h>
 #include <linux/proc_fs.h>
 #include <linux/seq_file.h>
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include "internals.h"
 static struct proc_dir_entry *root_irq_dir;
 #ifdef CONFIG_SMP
 static int irq_affinity_proc_show(struct seq_file *m, void *v)
 {
 	struct irq_desc *desc = irq_to_desc((long)m->private);
 	const struct cpumask *mask = desc->irq_data.affinity;
 #ifdef CONFIG_GENERIC_PENDING_IRQ
 	if (irqd_is_setaffinity_pending(&desc->irq_data))
 		mask = desc->pending_mask;
 #endif
 	seq_cpumask(m, mask);
 	seq_putc(m, '\n');
 	return 0;
 }
 static int irq_affinity_hint_proc_show(struct seq_file *m, void *v)
 {
 	struct irq_desc *desc = irq_to_desc((long)m->private);
 	unsigned long flags;
 	cpumask_var_t mask;
 	if (!zalloc_cpumask_var(&mask, GFP_KERNEL))
 		return -ENOMEM;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	if (desc->affinity_hint)
 		cpumask_copy(mask, desc->affinity_hint);
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	seq_cpumask(m, mask);
 	seq_putc(m, '\n');
 	free_cpumask_var(mask);
 	return 0;
 }
 #ifndef is_affinity_mask_valid
 #define is_affinity_mask_valid(val) 1
 #endif
 int no_irq_affinity;
 static ssize_t irq_affinity_proc_write(struct file *file,
 		const char __user *buffer, size_t count, loff_t *pos)
 {
 	unsigned int irq = (int)(long)PDE(file->f_path.dentry->d_inode)->data;
 	cpumask_var_t new_value;
 	int err;
 	if (!irq_can_set_affinity(irq) || no_irq_affinity)
 		return -EIO;
 	if (!alloc_cpumask_var(&new_value, GFP_KERNEL))
 		return -ENOMEM;
 	err = cpumask_parse_user(buffer, count, new_value);
 	if (err)
 		goto free_cpumask;
 	if (!is_affinity_mask_valid(new_value)) {
 		err = -EINVAL;
 		goto free_cpumask;
 	}
 	/*
 	 * Do not allow disabling IRQs completely - it's a too easy
 	 * way to make the system unusable accidentally :-) At least
 	 * one online CPU still has to be targeted.
 	 */
 	if (!cpumask_intersects(new_value, cpu_online_mask)) {
 		/* Special case for empty set - allow the architecture
 		   code to set default SMP affinity. */
 		err = irq_select_affinity_usr(irq, new_value) ? -EINVAL : count;
 	} else {
 		irq_set_affinity(irq, new_value);
 		err = count;
 	}
 free_cpumask:
 	free_cpumask_var(new_value);
 	return err;
 }
 static int irq_affinity_proc_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, irq_affinity_proc_show, PDE(inode)->data);
 }
 static int irq_affinity_hint_proc_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, irq_affinity_hint_proc_show, PDE(inode)->data);
 }
 static const struct file_operations irq_affinity_proc_fops = {
 	.open		= irq_affinity_proc_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 	.write		= irq_affinity_proc_write,
 };
 static const struct file_operations irq_affinity_hint_proc_fops = {
 	.open		= irq_affinity_hint_proc_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 };
 static int default_affinity_show(struct seq_file *m, void *v)
 {
 	seq_cpumask(m, irq_default_affinity);
 	seq_putc(m, '\n');
 	return 0;
 }
 static ssize_t default_affinity_write(struct file *file,
 		const char __user *buffer, size_t count, loff_t *ppos)
 {
 	cpumask_var_t new_value;
 	int err;
 	if (!alloc_cpumask_var(&new_value, GFP_KERNEL))
 		return -ENOMEM;
 	err = cpumask_parse_user(buffer, count, new_value);
 	if (err)
 		goto out;
 	if (!is_affinity_mask_valid(new_value)) {
 		err = -EINVAL;
 		goto out;
 	}
 	/*
 	 * Do not allow disabling IRQs completely - it's a too easy
 	 * way to make the system unusable accidentally :-) At least
 	 * one online CPU still has to be targeted.
 	 */
 	if (!cpumask_intersects(new_value, cpu_online_mask)) {
 		err = -EINVAL;
 		goto out;
 	}
 	cpumask_copy(irq_default_affinity, new_value);
 	err = count;
 out:
 	free_cpumask_var(new_value);
 	return err;
 }
 static int default_affinity_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, default_affinity_show, PDE(inode)->data);
 }
 static const struct file_operations default_affinity_proc_fops = {
 	.open		= default_affinity_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 	.write		= default_affinity_write,
 };
 static int irq_node_proc_show(struct seq_file *m, void *v)
 {
 	struct irq_desc *desc = irq_to_desc((long) m->private);
 	seq_printf(m, "%d\n", desc->irq_data.node);
 	return 0;
 }
 static int irq_node_proc_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, irq_node_proc_show, PDE(inode)->data);
 }
 static const struct file_operations irq_node_proc_fops = {
 	.open		= irq_node_proc_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 };
 #endif
 static int irq_spurious_proc_show(struct seq_file *m, void *v)
 {
 	struct irq_desc *desc = irq_to_desc((long) m->private);
 	seq_printf(m, "count %u\n" "unhandled %u\n" "last_unhandled %u ms\n",
 		   desc->irq_count, desc->irqs_unhandled,
 		   jiffies_to_msecs(desc->last_unhandled));
 	return 0;
 }
 static int irq_spurious_proc_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, irq_spurious_proc_show, PDE(inode)->data);
 }
 static const struct file_operations irq_spurious_proc_fops = {
 	.open		= irq_spurious_proc_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 };
 #define MAX_NAMELEN 128
 static int name_unique(unsigned int irq, struct irqaction *new_action)
 {
 	struct irq_desc *desc = irq_to_desc(irq);
 	struct irqaction *action;
 	unsigned long flags;
 	int ret = 1;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	for (action = desc->action ; action; action = action->next) {
 		if ((action != new_action) && action->name &&
 				!strcmp(new_action->name, action->name)) {
 			ret = 0;
 			break;
 		}
 	}
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	return ret;
 }
 void register_handler_proc(unsigned int irq, struct irqaction *action)
 {
 	char name [MAX_NAMELEN];
 	struct irq_desc *desc = irq_to_desc(irq);
 	if (!desc->dir || action->dir || !action->name ||
 					!name_unique(irq, action))
 		return;
 	memset(name, 0, MAX_NAMELEN);
 	snprintf(name, MAX_NAMELEN, "%s", action->name);
 	/* create /proc/irq/1234/handler/ */
 	action->dir = proc_mkdir(name, desc->dir);
 }
 #undef MAX_NAMELEN
 #define MAX_NAMELEN 10
 void register_irq_proc(unsigned int irq, struct irq_desc *desc)
 {
 	char name [MAX_NAMELEN];
 	if (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip) || desc->dir)
 		return;
 	memset(name, 0, MAX_NAMELEN);
 	sprintf(name, "%d", irq);
 	/* create /proc/irq/1234 */
 	desc->dir = proc_mkdir(name, root_irq_dir);
 	if (!desc->dir)
 		return;
 #ifdef CONFIG_SMP
 	/* create /proc/irq/<irq>/smp_affinity */
 	proc_create_data("smp_affinity", 0600, desc->dir,
 			 &irq_affinity_proc_fops, (void *)(long)irq);
 	/* create /proc/irq/<irq>/affinity_hint */
 	proc_create_data("affinity_hint", 0400, desc->dir,
 			 &irq_affinity_hint_proc_fops, (void *)(long)irq);
 	proc_create_data("node", 0444, desc->dir,
 			 &irq_node_proc_fops, (void *)(long)irq);
 #endif
 	proc_create_data("spurious", 0444, desc->dir,
 			 &irq_spurious_proc_fops, (void *)(long)irq);
 }
 void unregister_irq_proc(unsigned int irq, struct irq_desc *desc)
 {
 	char name [MAX_NAMELEN];
 	if (!root_irq_dir || !desc->dir)
 		return;
 #ifdef CONFIG_SMP
 	remove_proc_entry("smp_affinity", desc->dir);
 	remove_proc_entry("affinity_hint", desc->dir);
 	remove_proc_entry("node", desc->dir);
 #endif
 	remove_proc_entry("spurious", desc->dir);
 	memset(name, 0, MAX_NAMELEN);
 	sprintf(name, "%u", irq);
 	remove_proc_entry(name, root_irq_dir);
 }
 #undef MAX_NAMELEN
 void unregister_handler_proc(unsigned int irq, struct irqaction *action)
 {
 	if (action->dir) {
 		struct irq_desc *desc = irq_to_desc(irq);
 		remove_proc_entry(action->dir->name, desc->dir);
 	}
 }
 static void register_default_affinity_proc(void)
 {
 #ifdef CONFIG_SMP
 	proc_create("irq/default_smp_affinity", 0600, NULL,
 		    &default_affinity_proc_fops);
 #endif
 }
 void init_irq_proc(void)
 {
 	unsigned int irq;
 	struct irq_desc *desc;
 	/* create /proc/irq */
 	root_irq_dir = proc_mkdir("irq", NULL);
 	if (!root_irq_dir)
 		return;
 	register_default_affinity_proc();
 	/*
 	 * Create entries for all existing IRQs.
 	 */
 	for_each_irq_desc(irq, desc) {
 		if (!desc)
 			continue;
 		register_irq_proc(irq, desc);
 	}
 }
 #ifdef CONFIG_GENERIC_IRQ_SHOW
 int __weak arch_show_interrupts(struct seq_file *p, int prec)
 {
 	return 0;
 }
 int show_interrupts(struct seq_file *p, void *v)
 {
 	static int prec;
 	unsigned long flags, any_count = 0;
 	int i = *(loff_t *) v, j;
 	struct irqaction *action;
 	struct irq_desc *desc;
 	if (i > nr_irqs)
 		return 0;
 	if (i == nr_irqs)
 		return arch_show_interrupts(p, prec);
 	/* print header and calculate the width of the first column */
 	if (i == 0) {
 		for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
 			j *= 10;
 		seq_printf(p, "%*s", prec + 8, "");
 		for_each_online_cpu(j)
 			seq_printf(p, "CPU%-8d", j);
 		seq_putc(p, '\n');
 	}
 	desc = irq_to_desc(i);
 	if (!desc)
 		return 0;
 	raw_spin_lock_irqsave(&desc->lock, flags);
 	for_each_online_cpu(j)
 		any_count |= kstat_irqs_cpu(i, j);
 	action = desc->action;
 	if (!action && !any_count)
 		goto out;
 	seq_printf(p, "%*d: ", prec, i);
 	for_each_online_cpu(j)
 		seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
 	seq_printf(p, " %8s", desc->irq_data.chip->name);
-	seq_printf(p, "-%-8s", desc->name);
+	if (desc->name)
+		seq_printf(p, "-%-8s", desc->name);
 	if (action) {
 		seq_printf(p, "  %s", action->name);
 		while ((action = action->next) != NULL)
 			seq_printf(p, ", %s", action->name);
 	}
 	seq_putc(p, '\n');
 out:
 	raw_spin_unlock_irqrestore(&desc->lock, flags);
 	return 0;
 }
 #endif