Commit 6cf4d0fadc2fec864634b2b614ff625a59a45db7
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Blackfin: coreb: add gpl module license
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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arch/blackfin/mach-bf561/coreb.c
| 1 | /* Load firmware into Core B on a BF561 | 1 | /* Load firmware into Core B on a BF561 |
| 2 | * | 2 | * |
| 3 | * Copyright 2004-2009 Analog Devices Inc. | 3 | * Copyright 2004-2009 Analog Devices Inc. |
| 4 | * Licensed under the GPL-2 or later. | 4 | * Licensed under the GPL-2 or later. |
| 5 | */ | 5 | */ |
| 6 | 6 | ||
| 7 | /* The Core B reset func requires code in the application that is loaded into | 7 | /* The Core B reset func requires code in the application that is loaded into |
| 8 | * Core B. In order to reset, the application needs to install an interrupt | 8 | * Core B. In order to reset, the application needs to install an interrupt |
| 9 | * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and | 9 | * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and |
| 10 | * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core | 10 | * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core |
| 11 | * B to stall when Supplemental Interrupt 0 is set, and will reset PC to | 11 | * B to stall when Supplemental Interrupt 0 is set, and will reset PC to |
| 12 | * 0xff600000 when COREB_SRAM_INIT is cleared. | 12 | * 0xff600000 when COREB_SRAM_INIT is cleared. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #include <linux/device.h> | 15 | #include <linux/device.h> |
| 16 | #include <linux/fs.h> | 16 | #include <linux/fs.h> |
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/miscdevice.h> | 18 | #include <linux/miscdevice.h> |
| 19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
| 20 | 20 | ||
| 21 | #define CMD_COREB_START 2 | 21 | #define CMD_COREB_START 2 |
| 22 | #define CMD_COREB_STOP 3 | 22 | #define CMD_COREB_STOP 3 |
| 23 | #define CMD_COREB_RESET 4 | 23 | #define CMD_COREB_RESET 4 |
| 24 | 24 | ||
| 25 | static long | 25 | static long |
| 26 | coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | 26 | coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 27 | { | 27 | { |
| 28 | int ret = 0; | 28 | int ret = 0; |
| 29 | 29 | ||
| 30 | switch (cmd) { | 30 | switch (cmd) { |
| 31 | case CMD_COREB_START: | 31 | case CMD_COREB_START: |
| 32 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); | 32 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); |
| 33 | break; | 33 | break; |
| 34 | case CMD_COREB_STOP: | 34 | case CMD_COREB_STOP: |
| 35 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); | 35 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); |
| 36 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); | 36 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); |
| 37 | break; | 37 | break; |
| 38 | case CMD_COREB_RESET: | 38 | case CMD_COREB_RESET: |
| 39 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); | 39 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); |
| 40 | break; | 40 | break; |
| 41 | default: | 41 | default: |
| 42 | ret = -EINVAL; | 42 | ret = -EINVAL; |
| 43 | break; | 43 | break; |
| 44 | } | 44 | } |
| 45 | 45 | ||
| 46 | CSYNC(); | 46 | CSYNC(); |
| 47 | 47 | ||
| 48 | return ret; | 48 | return ret; |
| 49 | } | 49 | } |
| 50 | 50 | ||
| 51 | static const struct file_operations coreb_fops = { | 51 | static const struct file_operations coreb_fops = { |
| 52 | .owner = THIS_MODULE, | 52 | .owner = THIS_MODULE, |
| 53 | .unlocked_ioctl = coreb_ioctl, | 53 | .unlocked_ioctl = coreb_ioctl, |
| 54 | }; | 54 | }; |
| 55 | 55 | ||
| 56 | static struct miscdevice coreb_dev = { | 56 | static struct miscdevice coreb_dev = { |
| 57 | .minor = MISC_DYNAMIC_MINOR, | 57 | .minor = MISC_DYNAMIC_MINOR, |
| 58 | .name = "coreb", | 58 | .name = "coreb", |
| 59 | .fops = &coreb_fops, | 59 | .fops = &coreb_fops, |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | static int __init bf561_coreb_init(void) | 62 | static int __init bf561_coreb_init(void) |
| 63 | { | 63 | { |
| 64 | return misc_register(&coreb_dev); | 64 | return misc_register(&coreb_dev); |
| 65 | } | 65 | } |
| 66 | module_init(bf561_coreb_init); | 66 | module_init(bf561_coreb_init); |
| 67 | 67 | ||
| 68 | static void __exit bf561_coreb_exit(void) | 68 | static void __exit bf561_coreb_exit(void) |
| 69 | { | 69 | { |
| 70 | misc_deregister(&coreb_dev); | 70 | misc_deregister(&coreb_dev); |
| 71 | } | 71 | } |
| 72 | module_exit(bf561_coreb_exit); | 72 | module_exit(bf561_coreb_exit); |
| 73 | 73 | ||
| 74 | MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); | 74 | MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); |
| 75 | MODULE_DESCRIPTION("BF561 Core B Support"); | 75 | MODULE_DESCRIPTION("BF561 Core B Support"); |
| 76 | MODULE_LICENSE("GPL"); | ||
| 76 | 77 |