Commit 71a19f7e0d1d107830edd1d878ff56c8bc65a4da

Authored by Eric Lee
1 parent 82e694ff81

make change to hardware revision 00E0

Showing 4 changed files with 13 additions and 8 deletions Side-by-side Diff

arch/arm/boot/dts/imx7d-smarcfimx7.dts
... ... @@ -263,14 +263,14 @@
263 263 #address-cells = <1>;
264 264 #size-cells = <0>;
265 265  
266   - ethphy0: ethernet-phy@6 {
  266 + ethphy0: ethernet-phy@1 {
267 267 compatible = "ethernet-phy-ieee802.3-c22";
268   - reg = <0x6>;
  268 + reg = <0x1>;
269 269 };
270 270  
271   - ethphy1: ethernet-phy@7 {
  271 + ethphy1: ethernet-phy@2 {
272 272 compatible = "ethernet-phy-ieee802.3-c22";
273   - reg = <0x7>;
  273 + reg = <0x2>;
274 274 };
275 275 };
276 276 };
arch/arm/boot/dts/imx7s-smarcfimx7.dts
... ... @@ -254,9 +254,9 @@
254 254 #address-cells = <1>;
255 255 #size-cells = <0>;
256 256  
257   - ethphy0: ethernet-phy@6 {
  257 + ethphy0: ethernet-phy@1 {
258 258 compatible = "ethernet-phy-ieee802.3-c22";
259   - reg = <0x6>;
  259 + reg = <0x1>;
260 260 };
261 261 };
262 262 };
arch/arm/configs/smarcfimx7_defconfig
... ... @@ -1597,7 +1597,7 @@
1597 1597 # CONFIG_NATIONAL_PHY is not set
1598 1598 # CONFIG_NXP_TJA110X_PHY is not set
1599 1599 # CONFIG_QSEMI_PHY is not set
1600   -# CONFIG_REALTEK_PHY is not set
  1600 +CONFIG_REALTEK_PHY=y
1601 1601 # CONFIG_ROCKCHIP_PHY is not set
1602 1602 # CONFIG_SMSC_PHY is not set
1603 1603 # CONFIG_STE10XP is not set
... ... @@ -4133,7 +4133,7 @@
4133 4133 CONFIG_FSL_EDMA=y
4134 4134 # CONFIG_FSL_EDMA_V3 is not set
4135 4135 # CONFIG_IMX_DMA is not set
4136   -CONFIG_IMX_SDMA=y
  4136 +CONFIG_IMX_SDMA=m
4137 4137 # CONFIG_INTEL_IDMA64 is not set
4138 4138 CONFIG_MXS_DMA=y
4139 4139 CONFIG_MXC_PXP_V2=y
drivers/net/phy/realtek.c
... ... @@ -102,6 +102,11 @@
102 102 if (ret < 0)
103 103 return ret;
104 104  
  105 + /* Set green LED for Link, yellow LED for Active */
  106 + phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd04);
  107 + phy_write(phydev, 0x10, 0x617f);
  108 + phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
  109 +
105 110 phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
106 111 reg = phy_read(phydev, 0x11);
107 112