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Commit 89434421d86a69af1868b65c5adbb3abda5af54f

Authored by Wey-Yi Guy
1 parent 86cb3b4e08

iwlagn: remove incorrect define 

Remove unused and incorrect EEPROM define

Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>

Showing 1 changed file with 0 additions and 1 deletions Inline Diff

drivers/net/wireless/iwlwifi/iwl-eeprom.h
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1 /****************************************************************************** 1 /******************************************************************************
2 * 2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license. 4 * redistributing this file, you may do so under either license.
5 * 5 *
6 * GPL LICENSE SUMMARY 6 * GPL LICENSE SUMMARY
7 * 7 *
8 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as 11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, but 14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details. 17 * General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA 22 * USA
23 * 23 *
24 * The full GNU General Public License is included in this distribution 24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL. 25 * in the file called LICENSE.GPL.
26 * 26 *
27 * Contact Information: 27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com> 28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * 30 *
31 * BSD LICENSE 31 * BSD LICENSE
32 * 32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. 33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved. 34 * All rights reserved.
35 * 35 *
36 * Redistribution and use in source and binary forms, with or without 36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions 37 * modification, are permitted provided that the following conditions
38 * are met: 38 * are met:
39 * 39 *
40 * * Redistributions of source code must retain the above copyright 40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer. 41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright 42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in 43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the 44 * the documentation and/or other materials provided with the
45 * distribution. 45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its 46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived 47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission. 48 * from this software without specific prior written permission.
49 * 49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/ 61 *****************************************************************************/
62 62
63 #ifndef __iwl_eeprom_h__ 63 #ifndef __iwl_eeprom_h__
64 #define __iwl_eeprom_h__ 64 #define __iwl_eeprom_h__
65 65
66 #include <net/mac80211.h> 66 #include <net/mac80211.h>
67 67
68 struct iwl_priv; 68 struct iwl_priv;
69 69
70 /* 70 /*
71 * EEPROM access time values: 71 * EEPROM access time values:
72 * 72 *
73 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. 73 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
74 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). 74 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
75 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. 75 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
76 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. 76 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
77 */ 77 */
78 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 78 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
79 79
80 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ 80 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
81 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 81 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
82 82
83 83
84 /* 84 /*
85 * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags. 85 * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
86 * 86 *
87 * IBSS and/or AP operation is allowed *only* on those channels with 87 * IBSS and/or AP operation is allowed *only* on those channels with
88 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because 88 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
89 * RADAR detection is not supported by the 4965 driver, but is a 89 * RADAR detection is not supported by the 4965 driver, but is a
90 * requirement for establishing a new network for legal operation on channels 90 * requirement for establishing a new network for legal operation on channels
91 * requiring RADAR detection or restricting ACTIVE scanning. 91 * requiring RADAR detection or restricting ACTIVE scanning.
92 * 92 *
93 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels. 93 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
94 * It only indicates that 20 MHz channel use is supported; HT40 channel 94 * It only indicates that 20 MHz channel use is supported; HT40 channel
95 * usage is indicated by a separate set of regulatory flags for each 95 * usage is indicated by a separate set of regulatory flags for each
96 * HT40 channel pair. 96 * HT40 channel pair.
97 * 97 *
98 * NOTE: Using a channel inappropriately will result in a uCode error! 98 * NOTE: Using a channel inappropriately will result in a uCode error!
99 */ 99 */
100 #define IWL_NUM_TX_CALIB_GROUPS 5 100 #define IWL_NUM_TX_CALIB_GROUPS 5
101 enum { 101 enum {
102 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ 102 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
103 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ 103 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
104 /* Bit 2 Reserved */ 104 /* Bit 2 Reserved */
105 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ 105 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
106 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ 106 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
107 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ 107 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
108 /* Bit 6 Reserved (was Narrow Channel) */ 108 /* Bit 6 Reserved (was Narrow Channel) */
109 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ 109 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
110 }; 110 };
111 111
112 /* SKU Capabilities */ 112 /* SKU Capabilities */
113 #define EEPROM_SKU_CAP_BAND_24GHZ (1 << 4) 113 #define EEPROM_SKU_CAP_BAND_24GHZ (1 << 4)
114 #define EEPROM_SKU_CAP_BAND_52GHZ (1 << 5) 114 #define EEPROM_SKU_CAP_BAND_52GHZ (1 << 5)
115 #define EEPROM_SKU_CAP_11N_ENABLE (1 << 6) 115 #define EEPROM_SKU_CAP_11N_ENABLE (1 << 6)
116 #define EEPROM_SKU_CAP_AMT_ENABLE (1 << 7) 116 #define EEPROM_SKU_CAP_AMT_ENABLE (1 << 7)
117 #define EEPROM_SKU_CAP_IPAN_ENABLE (1 << 8) 117 #define EEPROM_SKU_CAP_IPAN_ENABLE (1 << 8)
118 118
119 /* *regulatory* channel data format in eeprom, one for each channel. 119 /* *regulatory* channel data format in eeprom, one for each channel.
120 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */ 120 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
121 struct iwl_eeprom_channel { 121 struct iwl_eeprom_channel {
122 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ 122 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
123 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ 123 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
124 } __packed; 124 } __packed;
125 125
126 enum iwl_eeprom_enhanced_txpwr_flags { 126 enum iwl_eeprom_enhanced_txpwr_flags {
127 IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0), 127 IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0),
128 IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1), 128 IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1),
129 IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2), 129 IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2),
130 IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3), 130 IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3),
131 IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4), 131 IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4),
132 IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5), 132 IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5),
133 IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6), 133 IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6),
134 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7), 134 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7),
135 }; 135 };
136 136
137 /** 137 /**
138 * iwl_eeprom_enhanced_txpwr structure 138 * iwl_eeprom_enhanced_txpwr structure
139 * This structure presents the enhanced regulatory tx power limit layout 139 * This structure presents the enhanced regulatory tx power limit layout
140 * in eeprom image 140 * in eeprom image
141 * Enhanced regulatory tx power portion of eeprom image can be broken down 141 * Enhanced regulatory tx power portion of eeprom image can be broken down
142 * into individual structures; each one is 8 bytes in size and contain the 142 * into individual structures; each one is 8 bytes in size and contain the
143 * following information 143 * following information
144 * @flags: entry flags 144 * @flags: entry flags
145 * @channel: channel number 145 * @channel: channel number
146 * @chain_a_max_pwr: chain a max power in 1/2 dBm 146 * @chain_a_max_pwr: chain a max power in 1/2 dBm
147 * @chain_b_max_pwr: chain b max power in 1/2 dBm 147 * @chain_b_max_pwr: chain b max power in 1/2 dBm
148 * @chain_c_max_pwr: chain c max power in 1/2 dBm 148 * @chain_c_max_pwr: chain c max power in 1/2 dBm
149 * @delta_20_in_40: 20-in-40 deltas (hi/lo) 149 * @delta_20_in_40: 20-in-40 deltas (hi/lo)
150 * @mimo2_max_pwr: mimo2 max power in 1/2 dBm 150 * @mimo2_max_pwr: mimo2 max power in 1/2 dBm
151 * @mimo3_max_pwr: mimo3 max power in 1/2 dBm 151 * @mimo3_max_pwr: mimo3 max power in 1/2 dBm
152 * 152 *
153 */ 153 */
154 struct iwl_eeprom_enhanced_txpwr { 154 struct iwl_eeprom_enhanced_txpwr {
155 u8 flags; 155 u8 flags;
156 u8 channel; 156 u8 channel;
157 s8 chain_a_max; 157 s8 chain_a_max;
158 s8 chain_b_max; 158 s8 chain_b_max;
159 s8 chain_c_max; 159 s8 chain_c_max;
160 u8 delta_20_in_40; 160 u8 delta_20_in_40;
161 s8 mimo2_max; 161 s8 mimo2_max;
162 s8 mimo3_max; 162 s8 mimo3_max;
163 } __packed; 163 } __packed;
164 164
165 /* calibration */ 165 /* calibration */
166 #define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION) 166 #define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
167 #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL) 167 #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL)
168 168
169 /* temperature */ 169 /* temperature */
170 #define EEPROM_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL) 170 #define EEPROM_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL)
171 171
172 /* agn links */ 172 /* agn links */
173 #define EEPROM_LINK_HOST (2*0x64) 173 #define EEPROM_LINK_HOST (2*0x64)
174 #define EEPROM_LINK_GENERAL (2*0x65) 174 #define EEPROM_LINK_GENERAL (2*0x65)
175 #define EEPROM_LINK_REGULATORY (2*0x66) 175 #define EEPROM_LINK_REGULATORY (2*0x66)
176 #define EEPROM_LINK_CALIBRATION (2*0x67) 176 #define EEPROM_LINK_CALIBRATION (2*0x67)
177 #define EEPROM_LINK_PROCESS_ADJST (2*0x68) 177 #define EEPROM_LINK_PROCESS_ADJST (2*0x68)
178 #define EEPROM_LINK_OTHERS (2*0x69) 178 #define EEPROM_LINK_OTHERS (2*0x69)
179 #define EEPROM_LINK_TXP_LIMIT (2*0x6a) 179 #define EEPROM_LINK_TXP_LIMIT (2*0x6a)
180 #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b) 180 #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b)
181 181
182 /* agn regulatory - indirect access */ 182 /* agn regulatory - indirect access */
183 #define EEPROM_REG_BAND_1_CHANNELS ((0x08)\ 183 #define EEPROM_REG_BAND_1_CHANNELS ((0x08)\
184 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 28 bytes */ 184 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 28 bytes */
185 #define EEPROM_REG_BAND_2_CHANNELS ((0x26)\ 185 #define EEPROM_REG_BAND_2_CHANNELS ((0x26)\
186 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 26 bytes */ 186 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 26 bytes */
187 #define EEPROM_REG_BAND_3_CHANNELS ((0x42)\ 187 #define EEPROM_REG_BAND_3_CHANNELS ((0x42)\
188 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */ 188 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */
189 #define EEPROM_REG_BAND_4_CHANNELS ((0x5C)\ 189 #define EEPROM_REG_BAND_4_CHANNELS ((0x5C)\
190 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */ 190 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */
191 #define EEPROM_REG_BAND_5_CHANNELS ((0x74)\ 191 #define EEPROM_REG_BAND_5_CHANNELS ((0x74)\
192 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 12 bytes */ 192 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 12 bytes */
193 #define EEPROM_REG_BAND_24_HT40_CHANNELS ((0x82)\ 193 #define EEPROM_REG_BAND_24_HT40_CHANNELS ((0x82)\
194 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */ 194 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */
195 #define EEPROM_REG_BAND_52_HT40_CHANNELS ((0x92)\ 195 #define EEPROM_REG_BAND_52_HT40_CHANNELS ((0x92)\
196 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */ 196 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */
197 197
198 /* 6000 regulatory - indirect access */ 198 /* 6000 regulatory - indirect access */
199 #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS ((0x80)\ 199 #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS ((0x80)\
200 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */ 200 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */
201 201
202 /* 5000 Specific */ 202 /* 5000 Specific */
203 #define EEPROM_5000_TX_POWER_VERSION (4) 203 #define EEPROM_5000_TX_POWER_VERSION (4)
204 #define EEPROM_5000_EEPROM_VERSION (0x11A) 204 #define EEPROM_5000_EEPROM_VERSION (0x11A)
205 205
206 /* 5050 Specific */ 206 /* 5050 Specific */
207 #define EEPROM_5050_TX_POWER_VERSION (4) 207 #define EEPROM_5050_TX_POWER_VERSION (4)
208 #define EEPROM_5050_EEPROM_VERSION (0x21E) 208 #define EEPROM_5050_EEPROM_VERSION (0x21E)
209 209
210 /* 1000 Specific */ 210 /* 1000 Specific */
211 #define EEPROM_1000_TX_POWER_VERSION (4) 211 #define EEPROM_1000_TX_POWER_VERSION (4)
212 #define EEPROM_1000_EEPROM_VERSION (0x15C) 212 #define EEPROM_1000_EEPROM_VERSION (0x15C)
213 213
214 /* 6x00 Specific */ 214 /* 6x00 Specific */
215 #define EEPROM_6000_TX_POWER_VERSION (4) 215 #define EEPROM_6000_TX_POWER_VERSION (4)
216 #define EEPROM_6000_EEPROM_VERSION (0x423) 216 #define EEPROM_6000_EEPROM_VERSION (0x423)
217 217
218 /* 6x50 Specific */ 218 /* 6x50 Specific */
219 #define EEPROM_6050_TX_POWER_VERSION (4) 219 #define EEPROM_6050_TX_POWER_VERSION (4)
220 #define EEPROM_6050_EEPROM_VERSION (0x532) 220 #define EEPROM_6050_EEPROM_VERSION (0x532)
221 221
222 /* 6150 Specific */ 222 /* 6150 Specific */
223 #define EEPROM_6150_TX_POWER_VERSION (6) 223 #define EEPROM_6150_TX_POWER_VERSION (6)
224 #define EEPROM_6150_EEPROM_VERSION (0x553) 224 #define EEPROM_6150_EEPROM_VERSION (0x553)
225 225
226 /* 6x05 Specific */ 226 /* 6x05 Specific */
227 #define EEPROM_6005_TX_POWER_VERSION (6) 227 #define EEPROM_6005_TX_POWER_VERSION (6)
228 #define EEPROM_6005_EEPROM_VERSION (0x709) 228 #define EEPROM_6005_EEPROM_VERSION (0x709)
229 229
230 /* 6x30 Specific */ 230 /* 6x30 Specific */
231 #define EEPROM_6030_TX_POWER_VERSION (6) 231 #define EEPROM_6030_TX_POWER_VERSION (6)
232 #define EEPROM_6030_EEPROM_VERSION (0x709) 232 #define EEPROM_6030_EEPROM_VERSION (0x709)
233 233
234 /* 2x00 Specific */ 234 /* 2x00 Specific */
235 #define EEPROM_2000_TX_POWER_VERSION (6) 235 #define EEPROM_2000_TX_POWER_VERSION (6)
236 #define EEPROM_2000_EEPROM_VERSION (0x805) 236 #define EEPROM_2000_EEPROM_VERSION (0x805)
237 237
238 /* 6x35 Specific */ 238 /* 6x35 Specific */
239 #define EEPROM_6035_TX_POWER_VERSION (6) 239 #define EEPROM_6035_TX_POWER_VERSION (6)
240 #define EEPROM_6035_EEPROM_VERSION (0x753) 240 #define EEPROM_6035_EEPROM_VERSION (0x753)
241 241
242 242
243 /* OTP */ 243 /* OTP */
244 /* lower blocks contain EEPROM image and calibration data */ 244 /* lower blocks contain EEPROM image and calibration data */
245 #define OTP_LOW_IMAGE_SIZE (2 * 512 * sizeof(u16)) /* 2 KB */ 245 #define OTP_LOW_IMAGE_SIZE (2 * 512 * sizeof(u16)) /* 2 KB */
246 /* high blocks contain PAPD data */ 246 /* high blocks contain PAPD data */
247 #define OTP_HIGH_IMAGE_SIZE_6x00 (6 * 512 * sizeof(u16)) /* 6 KB */ 247 #define OTP_HIGH_IMAGE_SIZE_6x00 (6 * 512 * sizeof(u16)) /* 6 KB */
248 #define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */ 248 #define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */
249 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */ 249 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
250 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */ 250 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
251 #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */ 251 #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
252 #define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */ 252 #define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
253 253
254 /* 2.4 GHz */ 254 /* 2.4 GHz */
255 extern const u8 iwl_eeprom_band_1[14]; 255 extern const u8 iwl_eeprom_band_1[14];
256 256
257 #define ADDRESS_MSK 0x0000FFFF 257 #define ADDRESS_MSK 0x0000FFFF
258 #define INDIRECT_TYPE_MSK 0x000F0000 258 #define INDIRECT_TYPE_MSK 0x000F0000
259 #define INDIRECT_HOST 0x00010000 259 #define INDIRECT_HOST 0x00010000
260 #define INDIRECT_GENERAL 0x00020000 260 #define INDIRECT_GENERAL 0x00020000
261 #define INDIRECT_REGULATORY 0x00030000 261 #define INDIRECT_REGULATORY 0x00030000
262 #define INDIRECT_CALIBRATION 0x00040000 262 #define INDIRECT_CALIBRATION 0x00040000
263 #define INDIRECT_PROCESS_ADJST 0x00050000 263 #define INDIRECT_PROCESS_ADJST 0x00050000
264 #define INDIRECT_OTHERS 0x00060000 264 #define INDIRECT_OTHERS 0x00060000
265 #define INDIRECT_TXP_LIMIT 0x00070000 265 #define INDIRECT_TXP_LIMIT 0x00070000
266 #define INDIRECT_TXP_LIMIT_SIZE 0x00080000 266 #define INDIRECT_TXP_LIMIT_SIZE 0x00080000
267 #define INDIRECT_ADDRESS 0x00100000 267 #define INDIRECT_ADDRESS 0x00100000
268 268
269 /* General */ 269 /* General */
270 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ 270 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
271 #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */ 271 #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
272 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ 272 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
273 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ 273 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
274 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ 274 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
275 #define EEPROM_VERSION (2*0x44) /* 2 bytes */ 275 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
276 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ 276 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
277 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ 277 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
278 #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
279 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ 278 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
280 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ 279 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
281 280
282 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */ 281 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */
283 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ 282 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
284 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 283 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
285 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 284 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
286 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 285 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
287 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 286 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
288 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 287 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
289 288
290 #define EEPROM_RF_CONFIG_TYPE_MAX 0x3 289 #define EEPROM_RF_CONFIG_TYPE_MAX 0x3
291 290
292 #define EEPROM_REGULATORY_BAND_NO_HT40 (0) 291 #define EEPROM_REGULATORY_BAND_NO_HT40 (0)
293 292
294 struct iwl_eeprom_ops { 293 struct iwl_eeprom_ops {
295 const u32 regulatory_bands[7]; 294 const u32 regulatory_bands[7];
296 const u8* (*query_addr) (const struct iwl_priv *priv, size_t offset); 295 const u8* (*query_addr) (const struct iwl_priv *priv, size_t offset);
297 void (*update_enhanced_txpower) (struct iwl_priv *priv); 296 void (*update_enhanced_txpower) (struct iwl_priv *priv);
298 }; 297 };
299 298
300 299
301 int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev); 300 int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev);
302 void iwl_eeprom_free(struct iwl_priv *priv); 301 void iwl_eeprom_free(struct iwl_priv *priv);
303 int iwl_eeprom_check_version(struct iwl_priv *priv); 302 int iwl_eeprom_check_version(struct iwl_priv *priv);
304 int iwl_eeprom_check_sku(struct iwl_priv *priv); 303 int iwl_eeprom_check_sku(struct iwl_priv *priv);
305 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset); 304 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset);
306 int iwlcore_eeprom_verify_signature(struct iwl_priv *priv); 305 int iwlcore_eeprom_verify_signature(struct iwl_priv *priv);
307 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset); 306 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset);
308 int iwl_init_channel_map(struct iwl_priv *priv); 307 int iwl_init_channel_map(struct iwl_priv *priv);
309 void iwl_free_channel_map(struct iwl_priv *priv); 308 void iwl_free_channel_map(struct iwl_priv *priv);
310 const struct iwl_channel_info *iwl_get_channel_info( 309 const struct iwl_channel_info *iwl_get_channel_info(
311 const struct iwl_priv *priv, 310 const struct iwl_priv *priv,
312 enum ieee80211_band band, u16 channel); 311 enum ieee80211_band band, u16 channel);
313 void iwl_rf_config(struct iwl_priv *priv); 312 void iwl_rf_config(struct iwl_priv *priv);
314 313
315 #endif /* __iwl_eeprom_h__ */ 314 #endif /* __iwl_eeprom_h__ */
316 315