Commit 9f06cf38eca57e279b4c78e465e19f10c2f78174

Authored by Paul Mundt

Merge branch 'sh/pm-runtime' into sh-latest

Conflicts:
	arch/sh/kernel/cpu/sh4a/clock-sh7723.c

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 13 changed files Side-by-side Diff

arch/sh/include/asm/device.h
... ... @@ -14,16 +14,7 @@
14 14  
15 15 void plat_early_device_setup(void);
16 16  
17   -#define PDEV_ARCHDATA_FLAG_INIT 0
18   -#define PDEV_ARCHDATA_FLAG_IDLE 1
19   -#define PDEV_ARCHDATA_FLAG_SUSP 2
20   -
21 17 struct pdev_archdata {
22 18 int hwblk_id;
23   -#ifdef CONFIG_PM_RUNTIME
24   - unsigned long flags;
25   - struct list_head entry;
26   - struct mutex mutex;
27   -#endif
28 19 };
arch/sh/include/asm/hwblk.h
... ... @@ -44,6 +44,9 @@
44 44 int nr_hwblks;
45 45 };
46 46  
  47 +#if !defined(CONFIG_CPU_SUBTYPE_SH7722) && \
  48 + !defined(CONFIG_CPU_SUBTYPE_SH7723) && \
  49 + !defined(CONFIG_CPU_SUBTYPE_SH7724)
47 50 /* Should be defined by processor-specific code */
48 51 int arch_hwblk_init(void);
49 52 int arch_hwblk_sleep_mode(void);
... ... @@ -66,6 +69,8 @@
66 69 }
67 70  
68 71 int sh_hwblk_clk_register(struct clk *clks, int nr);
69   -
  72 +#else
  73 +#define hwblk_init() 0
  74 +#endif
70 75 #endif /* __ASM_SH_HWBLK_H */
arch/sh/kernel/cpu/Makefile
... ... @@ -18,5 +18,8 @@
18 18 obj-$(CONFIG_SH_ADC) += adc.o
19 19 obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20 20  
21   -obj-y += irq/ init.o clock.o fpu.o hwblk.o proc.o
  21 +obj-y += irq/ init.o clock.o fpu.o proc.o
  22 +ifneq ($(CONFIG_CPU_SUBTYPE_SH7722)$(CONFIG_CPU_SUBTYPE_SH7723)$(CONFIG_CPU_SUBTYPE_SH7724),y)
  23 +obj-y += hwblk.o
  24 +endif
arch/sh/kernel/cpu/sh4a/Makefile
... ... @@ -27,9 +27,9 @@
27 27 clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
28 28 clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
29 29 clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30   -clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o
31   -clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o
32   -clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o hwblk-sh7724.o
  30 +clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
  31 +clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
  32 +clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
33 33 clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34 34 clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35 35  
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
... ... @@ -22,8 +22,8 @@
22 22 #include <linux/kernel.h>
23 23 #include <linux/io.h>
24 24 #include <linux/clkdev.h>
  25 +#include <linux/sh_clk.h>
25 26 #include <asm/clock.h>
26   -#include <asm/hwblk.h>
27 27 #include <cpu/sh7722.h>
28 28  
29 29 /* SH7722 registers */
... ... @@ -33,6 +33,9 @@
33 33 #define SCLKBCR 0xa415000c
34 34 #define IRDACLKCR 0xa4150018
35 35 #define PLLCR 0xa4150024
  36 +#define MSTPCR0 0xa4150030
  37 +#define MSTPCR1 0xa4150034
  38 +#define MSTPCR2 0xa4150038
36 39 #define DLLFRQ 0xa4150050
37 40  
38 41 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
39 42  
40 43  
... ... @@ -148,31 +151,31 @@
148 151 };
149 152  
150 153 static struct clk mstp_clks[HWBLK_NR] = {
151   - SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
152   - SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
153   - SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
154   - SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
155   - SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
156   - SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
157   - SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
158   - SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
159   - SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
  154 + [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
  155 + [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
  156 + [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
  157 + [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
  158 + [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
  159 + [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
  160 + [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
  161 + [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
  162 + [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
160 163  
161   - SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
162   - SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
  164 + [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
  165 + [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
163 166  
164   - SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
165   - SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
166   - SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
167   - SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
168   - SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
169   - SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
170   - SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
171   - SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
172   - SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
173   - SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
174   - SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
175   - SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
  167 + [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
  168 + [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
  169 + [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
  170 + [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
  171 + [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
  172 + [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
  173 + [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
  174 + [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
  175 + [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
  176 + [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
  177 + [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
  178 + [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
176 179 };
177 180  
178 181 static struct clk_lookup lookups[] = {
179 182  
180 183  
181 184  
182 185  
183 186  
... ... @@ -205,27 +208,27 @@
205 208 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),
206 209  
207 210 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
208   - CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
  211 + CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
209 212 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
210 213  
211   - CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
212   - CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
213   - CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
  214 + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
  215 + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
  216 + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
214 217  
215 218 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
216 219 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
217   - CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
218   - CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
  220 + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]),
  221 + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
219 222 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
220 223 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
221   - CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
222   - CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
  224 + CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
  225 + CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
223 226 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
224 227 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
225   - CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
  228 + CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
226 229 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
227 230 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
228   - CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
  231 + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
229 232 };
230 233  
231 234 int __init arch_clk_init(void)
... ... @@ -258,7 +261,7 @@
258 261 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
259 262  
260 263 if (!ret)
261   - ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
  264 + ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
262 265  
263 266 return ret;
264 267 }
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
... ... @@ -23,8 +23,8 @@
23 23 #include <linux/io.h>
24 24 #include <linux/clk.h>
25 25 #include <linux/clkdev.h>
  26 +#include <linux/sh_clk.h>
26 27 #include <asm/clock.h>
27   -#include <asm/hwblk.h>
28 28 #include <cpu/sh7723.h>
29 29  
30 30 /* SH7723 registers */
... ... @@ -34,6 +34,9 @@
34 34 #define SCLKBCR 0xa415000c
35 35 #define IRDACLKCR 0xa4150018
36 36 #define PLLCR 0xa4150024
  37 +#define MSTPCR0 0xa4150030
  38 +#define MSTPCR1 0xa4150034
  39 +#define MSTPCR2 0xa4150038
37 40 #define DLLFRQ 0xa4150050
38 41  
39 42 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
40 43  
41 44  
... ... @@ -149,55 +152,55 @@
149 152  
150 153 static struct clk mstp_clks[] = {
151 154 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
152   - SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
153   - SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
154   - SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
155   - SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
156   - SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
157   - SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
158   - SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
159   - SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
160   - SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
161   - SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
162   - SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
163   - SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
164   - SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
165   - SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
166   - SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
167   - SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
168   - SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
169   - SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
170   - SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
171   - SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
172   - SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
173   - SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
174   - SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
175   - SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
176   - SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
177   - SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
  155 + [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
  156 + [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
  157 + [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
  158 + [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
  159 + [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
  160 + [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
  161 + [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
  162 + [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
  163 + [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
  164 + [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
  165 + [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
  166 + [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
  167 + [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
  168 + [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
  169 + [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
  170 + [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
  171 + [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
  172 + [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
  173 + [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
  174 + [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
  175 + [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
  176 + [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
  177 + [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
  178 + [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
  179 + [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
  180 + [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
178 181  
179   - SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
180   - SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
  182 + [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
  183 + [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
181 184  
182   - SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
183   - SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
184   - SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
185   - SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
186   - SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
187   - SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
188   - SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
189   - SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
190   - SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
191   - SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
192   - SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
193   - SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
194   - SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
195   - SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
196   - SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
197   - SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
198   - SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
199   - SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
200   - SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
  185 + [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
  186 + [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
  187 + [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
  188 + [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
  189 + [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
  190 + [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
  191 + [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
  192 + [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
  193 + [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
  194 + [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0),
  195 + [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0),
  196 + [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
  197 + [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
  198 + [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
  199 + [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
  200 + [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
  201 + [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
  202 + [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
  203 + [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
201 204 };
202 205  
203 206 static struct clk_lookup lookups[] = {
204 207  
205 208  
... ... @@ -229,17 +232,17 @@
229 232 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
230 233 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
231 234 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
232   - CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
  235 + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
233 236 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
234 237 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
235 238 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
236 239 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
237   - CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
238   - CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
  240 + CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
  241 + CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
239 242 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
240   - CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
241   - CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
242   - CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
  243 + CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
  244 + CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
  245 + CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[HWBLK_MERAM]),
243 246 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
244 247 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
245 248 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
246 249  
247 250  
248 251  
249 252  
... ... @@ -248,19 +251,18 @@
248 251 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
249 252 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
250 253 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
251   - CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
252   - CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
253   - CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
  254 + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
  255 + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
  256 + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
254 257 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
255 258 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
256   - CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
  259 + CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
257 260 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
258   - CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
  261 + CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
259 262 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
260   - CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
  263 + CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
261 264 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
262 265 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
263   - CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
264 266  
265 267 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
266 268 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
267 269  
... ... @@ -268,12 +270,15 @@
268 270 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
269 271 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
270 272 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
  273 +
271 274 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
272 275 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
273 276 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
274 277 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
275 278 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
276 279 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
  280 +
  281 + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
277 282 };
278 283  
279 284 int __init arch_clk_init(void)
... ... @@ -306,7 +311,7 @@
306 311 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
307 312  
308 313 if (!ret)
309   - ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
  314 + ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
310 315  
311 316 return ret;
312 317 }
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
... ... @@ -23,8 +23,8 @@
23 23 #include <linux/io.h>
24 24 #include <linux/clk.h>
25 25 #include <linux/clkdev.h>
  26 +#include <linux/sh_clk.h>
26 27 #include <asm/clock.h>
27   -#include <asm/hwblk.h>
28 28 #include <cpu/sh7724.h>
29 29  
30 30 /* SH7724 registers */
... ... @@ -35,6 +35,9 @@
35 35 #define FCLKBCR 0xa415000c
36 36 #define IRDACLKCR 0xa4150018
37 37 #define PLLCR 0xa4150024
  38 +#define MSTPCR0 0xa4150030
  39 +#define MSTPCR1 0xa4150034
  40 +#define MSTPCR2 0xa4150038
38 41 #define SPUCLKCR 0xa415003c
39 42 #define FLLFRQ 0xa4150050
40 43 #define LSTATS 0xa4150060
41 44  
42 45  
... ... @@ -209,60 +212,60 @@
209 212 };
210 213  
211 214 static struct clk mstp_clks[HWBLK_NR] = {
212   - SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
213   - SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
214   - SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
215   - SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
216   - SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
217   - SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
218   - SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
219   - SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
220   - SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
221   - SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
222   - SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
223   - SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
224   - SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
225   - SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
226   - SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
227   - SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
228   - SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
229   - SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
230   - SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
231   - SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
232   - SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
233   - SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
234   - SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
235   - SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
236   - SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
  215 + [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
  216 + [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
  217 + [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
  218 + [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
  219 + [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
  220 + [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
  221 + [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
  222 + [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
  223 + [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
  224 + [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
  225 + [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
  226 + [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
  227 + [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
  228 + [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
  229 + [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
  230 + [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
  231 + [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
  232 + [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
  233 + [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
  234 + [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
  235 + [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
  236 + [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
  237 + [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
  238 + [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
  239 + [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
237 240  
238   - SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
239   - SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
240   - SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
241   - SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
  241 + [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
  242 + [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
  243 + [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
  244 + [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
242 245  
243   - SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
244   - SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
245   - SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
246   - SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
247   - SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
248   - SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
249   - SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
250   - SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
251   - SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
252   - SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
253   - SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
254   - SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
255   - SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
256   - SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
257   - SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
258   - SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
259   - SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
260   - SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
261   - SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
262   - SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
263   - SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
264   - SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
265   - SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
  246 + [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),
  247 + [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),
  248 + [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0),
  249 + [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
  250 + [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
  251 + [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
  252 + [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0),
  253 + [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0),
  254 + [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0),
  255 + [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
  256 + [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
  257 + [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0),
  258 + [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0),
  259 + [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0),
  260 + [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
  261 + [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
  262 + [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
  263 + [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
  264 + [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
  265 + [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
  266 + [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
  267 + [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
  268 + [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
266 269 };
267 270  
268 271 static struct clk_lookup lookups[] = {
... ... @@ -296,7 +299,7 @@
296 299 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
297 300 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
298 301 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
299   - CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
  302 + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
300 303 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
301 304 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
302 305 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
303 306  
304 307  
305 308  
... ... @@ -307,26 +310,26 @@
307 310 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
308 311  
309 312 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
310   - CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
311   - CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
  313 + CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
  314 + CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
312 315  
313 316 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
314 317 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
315   - CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
316   - CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
317   - CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
318   - CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
319   - CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
320   - CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
  318 + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
  319 + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
  320 + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
  321 + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
  322 + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
  323 + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
321 324  
322   - CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
323   - CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
324   - CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
  325 + CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
  326 + CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
  327 + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
325 328 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
326 329 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
327 330 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
328   - CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
329   - CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
  331 + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]),
  332 + CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[HWBLK_ETHER]),
330 333 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
331 334 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
332 335 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
333 336  
334 337  
335 338  
336 339  
... ... @@ -334,20 +337,20 @@
334 337 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
335 338 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
336 339 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
337   - CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
338   - CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
  340 + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
  341 + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
339 342 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
340   - CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
  343 + CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]),
341 344 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
342 345 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
343 346 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
344 347 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
345   - CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
  348 + CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
346 349 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
347   - CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
  350 + CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU0]),
348 351 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
349 352 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
350   - CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
  353 + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
351 354 };
352 355  
353 356 int __init arch_clk_init(void)
... ... @@ -372,7 +375,7 @@
372 375 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
373 376  
374 377 if (!ret)
375   - ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
  378 + ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
376 379  
377 380 return ret;
378 381 }
arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
1   -/*
2   - * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
3   - *
4   - * SH7722 hardware block support
5   - *
6   - * Copyright (C) 2009 Magnus Damm
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License as published by
10   - * the Free Software Foundation; either version 2 of the License
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU General Public License
18   - * along with this program; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20   - */
21   -#include <linux/init.h>
22   -#include <linux/kernel.h>
23   -#include <linux/io.h>
24   -#include <asm/suspend.h>
25   -#include <asm/hwblk.h>
26   -#include <cpu/sh7722.h>
27   -
28   -/* SH7722 registers */
29   -#define MSTPCR0 0xa4150030
30   -#define MSTPCR1 0xa4150034
31   -#define MSTPCR2 0xa4150038
32   -
33   -/* SH7722 Power Domains */
34   -enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35   -static struct hwblk_area sh7722_hwblk_area[] = {
36   - [CORE_AREA] = HWBLK_AREA(0, 0),
37   - [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38   - [SUB_AREA] = HWBLK_AREA(0, 0),
39   -};
40   -
41   -/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42   -static struct hwblk sh7722_hwblk[HWBLK_NR] = {
43   - [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44   - [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45   - [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46   - [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47   - [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA),
48   - [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
49   - [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
50   - [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
51   - [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
52   - [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
53   - [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA),
54   - [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
55   - [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
56   - [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
57   - [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA),
58   - [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA),
59   - [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA),
60   - [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA),
61   - [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
62   - [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
63   -
64   - [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
65   - [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
66   -
67   - [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
68   - [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
69   - [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
70   - [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
71   - [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
72   - [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
73   - [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
74   - [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
75   - [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
76   - [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
77   - [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
78   - [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
79   - [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
80   - [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
81   - [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
82   - [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
83   -};
84   -
85   -static struct hwblk_info sh7722_hwblk_info = {
86   - .areas = sh7722_hwblk_area,
87   - .nr_areas = ARRAY_SIZE(sh7722_hwblk_area),
88   - .hwblks = sh7722_hwblk,
89   - .nr_hwblks = ARRAY_SIZE(sh7722_hwblk),
90   -};
91   -
92   -int arch_hwblk_sleep_mode(void)
93   -{
94   - if (!sh7722_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
95   - return SUSP_SH_STANDBY | SUSP_SH_SF;
96   -
97   - if (!sh7722_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
98   - return SUSP_SH_SLEEP | SUSP_SH_SF;
99   -
100   - return SUSP_SH_SLEEP;
101   -}
102   -
103   -int __init arch_hwblk_init(void)
104   -{
105   - return hwblk_register(&sh7722_hwblk_info);
106   -}
arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
1   -/*
2   - * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
3   - *
4   - * SH7723 hardware block support
5   - *
6   - * Copyright (C) 2009 Magnus Damm
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License as published by
10   - * the Free Software Foundation; either version 2 of the License
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU General Public License
18   - * along with this program; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20   - */
21   -#include <linux/init.h>
22   -#include <linux/kernel.h>
23   -#include <linux/io.h>
24   -#include <asm/suspend.h>
25   -#include <asm/hwblk.h>
26   -#include <cpu/sh7723.h>
27   -
28   -/* SH7723 registers */
29   -#define MSTPCR0 0xa4150030
30   -#define MSTPCR1 0xa4150034
31   -#define MSTPCR2 0xa4150038
32   -
33   -/* SH7723 Power Domains */
34   -enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35   -static struct hwblk_area sh7723_hwblk_area[] = {
36   - [CORE_AREA] = HWBLK_AREA(0, 0),
37   - [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38   - [SUB_AREA] = HWBLK_AREA(0, 0),
39   -};
40   -
41   -/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42   -static struct hwblk sh7723_hwblk[HWBLK_NR] = {
43   - [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44   - [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45   - [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46   - [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA),
47   - [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48   - [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
49   - [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
50   - [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
51   - [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
52   - [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
53   - [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
54   - [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
55   - [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA),
56   - [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57   - [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58   - [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59   - [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60   - [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA),
61   - [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
62   - [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
63   - [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
64   - [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
65   - [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
66   - [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
67   - [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
68   - [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
69   - [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
70   - [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA),
71   -
72   - [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
73   - [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
74   -
75   - [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
76   - [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
77   - [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
78   - [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
79   - [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
80   - [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
81   - [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
82   - [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
83   - [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
84   - [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA),
85   - [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
86   - [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
87   - [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
88   - [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
89   - [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
90   - [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
91   - [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
92   - [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
93   - [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
94   -};
95   -
96   -static struct hwblk_info sh7723_hwblk_info = {
97   - .areas = sh7723_hwblk_area,
98   - .nr_areas = ARRAY_SIZE(sh7723_hwblk_area),
99   - .hwblks = sh7723_hwblk,
100   - .nr_hwblks = ARRAY_SIZE(sh7723_hwblk),
101   -};
102   -
103   -int arch_hwblk_sleep_mode(void)
104   -{
105   - if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
106   - return SUSP_SH_STANDBY | SUSP_SH_SF;
107   -
108   - if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
109   - return SUSP_SH_SLEEP | SUSP_SH_SF;
110   -
111   - return SUSP_SH_SLEEP;
112   -}
113   -
114   -int __init arch_hwblk_init(void)
115   -{
116   - return hwblk_register(&sh7723_hwblk_info);
117   -}
arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
1   -/*
2   - * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
3   - *
4   - * SH7724 hardware block support
5   - *
6   - * Copyright (C) 2009 Magnus Damm
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License as published by
10   - * the Free Software Foundation; either version 2 of the License
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU General Public License
18   - * along with this program; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20   - */
21   -#include <linux/init.h>
22   -#include <linux/kernel.h>
23   -#include <linux/io.h>
24   -#include <asm/suspend.h>
25   -#include <asm/hwblk.h>
26   -#include <cpu/sh7724.h>
27   -
28   -/* SH7724 registers */
29   -#define MSTPCR0 0xa4150030
30   -#define MSTPCR1 0xa4150034
31   -#define MSTPCR2 0xa4150038
32   -
33   -/* SH7724 Power Domains */
34   -enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35   -static struct hwblk_area sh7724_hwblk_area[] = {
36   - [CORE_AREA] = HWBLK_AREA(0, 0),
37   - [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38   - [SUB_AREA] = HWBLK_AREA(0, 0),
39   -};
40   -
41   -/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42   -static struct hwblk sh7724_hwblk[HWBLK_NR] = {
43   - [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44   - [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45   - [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46   - [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47   - [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48   - [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
49   - [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
50   - [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
51   - [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
52   - [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
53   - [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
54   - [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
55   - [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
56   - [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57   - [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58   - [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59   - [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60   - [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
61   - [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
62   - [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
63   - [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
64   - [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
65   - [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
66   - [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
67   - [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
68   - [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
69   -
70   - [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
71   - [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
72   - [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
73   - [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
74   -
75   - [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
76   - [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
77   - [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
78   - [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
79   - [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
80   - [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
81   - [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
82   - [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
83   - [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
84   - [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
85   - [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
86   - [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
87   - [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
88   - [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
89   - [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
90   - [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
91   - [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
92   - [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
93   - [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
94   - [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
95   - [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
96   - [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
97   - [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
98   -};
99   -
100   -static struct hwblk_info sh7724_hwblk_info = {
101   - .areas = sh7724_hwblk_area,
102   - .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
103   - .hwblks = sh7724_hwblk,
104   - .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
105   -};
106   -
107   -int arch_hwblk_sleep_mode(void)
108   -{
109   - if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
110   - return SUSP_SH_STANDBY | SUSP_SH_SF;
111   -
112   - if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
113   - return SUSP_SH_SLEEP | SUSP_SH_SF;
114   -
115   - return SUSP_SH_SLEEP;
116   -}
117   -
118   -int __init arch_hwblk_init(void)
119   -{
120   - return hwblk_register(&sh7724_hwblk_info);
121   -}
arch/sh/kernel/cpu/shmobile/Makefile
... ... @@ -5,5 +5,4 @@
5 5 # Power Management & Sleep mode
6 6 obj-$(CONFIG_PM) += pm.o sleep.o
7 7 obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8   -obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o
arch/sh/kernel/cpu/shmobile/pm_runtime.c
1   -/*
2   - * arch/sh/kernel/cpu/shmobile/pm_runtime.c
3   - *
4   - * Runtime PM support code for SuperH Mobile
5   - *
6   - * Copyright (C) 2009 Magnus Damm
7   - *
8   - * This file is subject to the terms and conditions of the GNU General Public
9   - * License. See the file "COPYING" in the main directory of this archive
10   - * for more details.
11   - */
12   -#include <linux/init.h>
13   -#include <linux/kernel.h>
14   -#include <linux/io.h>
15   -#include <linux/pm_runtime.h>
16   -#include <linux/platform_device.h>
17   -#include <linux/mutex.h>
18   -#include <asm/hwblk.h>
19   -
20   -static DEFINE_SPINLOCK(hwblk_lock);
21   -static LIST_HEAD(hwblk_idle_list);
22   -static struct work_struct hwblk_work;
23   -
24   -extern struct hwblk_info *hwblk_info;
25   -
26   -static void platform_pm_runtime_not_idle(struct platform_device *pdev)
27   -{
28   - unsigned long flags;
29   -
30   - /* remove device from idle list */
31   - spin_lock_irqsave(&hwblk_lock, flags);
32   - if (test_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags)) {
33   - list_del(&pdev->archdata.entry);
34   - __clear_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
35   - }
36   - spin_unlock_irqrestore(&hwblk_lock, flags);
37   -}
38   -
39   -static int __platform_pm_runtime_resume(struct platform_device *pdev)
40   -{
41   - struct device *d = &pdev->dev;
42   - struct pdev_archdata *ad = &pdev->archdata;
43   - int hwblk = ad->hwblk_id;
44   - int ret = -ENOSYS;
45   -
46   - dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk);
47   -
48   - if (d->driver) {
49   - hwblk_enable(hwblk_info, hwblk);
50   - ret = 0;
51   -
52   - if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) {
53   - if (d->driver->pm && d->driver->pm->runtime_resume)
54   - ret = d->driver->pm->runtime_resume(d);
55   -
56   - if (!ret)
57   - clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
58   - else
59   - hwblk_disable(hwblk_info, hwblk);
60   - }
61   - }
62   -
63   - dev_dbg(d, "__platform_pm_runtime_resume() [%d] - returns %d\n",
64   - hwblk, ret);
65   -
66   - return ret;
67   -}
68   -
69   -static int __platform_pm_runtime_suspend(struct platform_device *pdev)
70   -{
71   - struct device *d = &pdev->dev;
72   - struct pdev_archdata *ad = &pdev->archdata;
73   - int hwblk = ad->hwblk_id;
74   - int ret = -ENOSYS;
75   -
76   - dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk);
77   -
78   - if (d->driver) {
79   - BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags));
80   - ret = 0;
81   -
82   - if (d->driver->pm && d->driver->pm->runtime_suspend) {
83   - hwblk_enable(hwblk_info, hwblk);
84   - ret = d->driver->pm->runtime_suspend(d);
85   - hwblk_disable(hwblk_info, hwblk);
86   - }
87   -
88   - if (!ret) {
89   - set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
90