diff --git a/arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-common.dtsi b/arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-common.dtsi
index ddca6fc..cfe2e83 100644
--- a/arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-common.dtsi
+++ b/arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-common.dtsi
@@ -162,7 +162,7 @@
                                 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5                 0x41    /*PCIE_WAKE#*/
                                	MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x41    /*LID#*/
                                	MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x41    /*SLEEP#*/
-                               	MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1               0x41    /*CHARGING#*/
+                               	MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x41	/*CHARGING#*/
                                	MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22               0x41    /*CHARGER_PRSNT#*/
                                 MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2                0x19    /*CARRIER_STBY#*/
                                	MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21              	0x41    /*BATLOW#*/
@@ -283,8 +283,8 @@
                         fsl,pins = <
                                 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x49
                                 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x49
-                                MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11             0x19
-                                MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10             0x19
+				MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
+				MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
                         >;
                 };
 
@@ -297,8 +297,8 @@
 
                 pinctrl_uart4: uart4grp {
                         fsl,pins = <
-                                MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX             0x49
-                                MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX             0x49
+				MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
+				MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
                                 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B        0x49
                                 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B         0x49
                         >;
@@ -516,6 +516,12 @@
                                 MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2          	0x16
                         >;
                 };
+
+		pinctrl_hdmi: hdmigrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1		0xc1
+			>;
+		};
         };
 };
 
@@ -626,7 +632,6 @@
                         vgen6_reg: vgen6 {
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <3300000>;
-				regulator-always-on;
                         };
                 };
         };
@@ -808,9 +813,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
         assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
-        assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
-        cts-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
-        rts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
         fsl,uart-has-rtscts;
         status = "okay";
 };
diff --git a/arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-hdmi.dtsi b/arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-hdmi.dtsi
index 98be87d..dfc0a3d 100644
--- a/arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-hdmi.dtsi
+++ b/arch/arm64/boot/dts/embedian/fsl-smarcimx8mq-hdmi.dtsi
@@ -1,6 +1,6 @@
 /*
  * Copyright 2017 NXP
- * Copyright 2018-2019 Variscite Ltd.
+ * Copyright 2018-2019 Embedian, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -31,3 +31,15 @@
 &hdmi {
 	status = "okay";
 };
+
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hdmi>;
+
+        hdmi_on_hog {
+                gpio-hog;
+                gpios = <1 0>;
+                output-high;
+                line-name = "hdmi_on";
+        };
+};