Eric Lee / smarc-fsl-linux-kernel

Commit bbb0aef5cfe95fe9b51a7eeba4a440b69037b01f

Authored by Joe Perches 14 years ago

Committed by Dave Airlie 14 years ago

Exists in master and in 39 other branches

drm: Verify debug message arguments

Add __attribute__((format (printf, 4, 5))) to drm_ut_debug_printk
and fix fallout.

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

Showing 5 changed files with 17 additions and 14 deletions Inline Diff

drivers/gpu/drm/drm_irq.c
drivers/gpu/drm/i915/intel_bios.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/radeon/radeon_display.c
include/drm/drmP.h

drivers/gpu/drm/drm_irq.c

Diff comments View file @ bbb0aef

 /**
  * \file drm_irq.c
  * IRQ support
  *
  * \author Rickard E. (Rik) Faith <faith@valinux.com>
  * \author Gareth Hughes <gareth@valinux.com>
  */
 /*
  * Created: Fri Mar 19 14:30:16 1999 by faith@valinux.com
  *
  * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 #include "drmP.h"
 #include "drm_trace.h"
 #include <linux/interrupt.h>	/* For task queue support */
 #include <linux/slab.h>
 #include <linux/vgaarb.h>
 /* Access macro for slots in vblank timestamp ringbuffer. */
 #define vblanktimestamp(dev, crtc, count) ( \
 	(dev)->_vblank_time[(crtc) * DRM_VBLANKTIME_RBSIZE + \
 	((count) % DRM_VBLANKTIME_RBSIZE)])
 /* Retry timestamp calculation up to 3 times to satisfy
  * drm_timestamp_precision before giving up.
  */
 #define DRM_TIMESTAMP_MAXRETRIES 3
 /* Threshold in nanoseconds for detection of redundant
  * vblank irq in drm_handle_vblank(). 1 msec should be ok.
  */
 #define DRM_REDUNDANT_VBLIRQ_THRESH_NS 1000000
 /**
  * Get interrupt from bus id.
  *
  * \param inode device inode.
  * \param file_priv DRM file private.
  * \param cmd command.
  * \param arg user argument, pointing to a drm_irq_busid structure.
  * \return zero on success or a negative number on failure.
  *
  * Finds the PCI device with the specified bus id and gets its IRQ number.
  * This IOCTL is deprecated, and will now return EINVAL for any busid not equal
  * to that of the device that this DRM instance attached to.
  */
 int drm_irq_by_busid(struct drm_device *dev, void *data,
 		     struct drm_file *file_priv)
 {
 	struct drm_irq_busid *p = data;
 	if (!dev->driver->bus->irq_by_busid)
 		return -EINVAL;
 	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
 		return -EINVAL;
 	return dev->driver->bus->irq_by_busid(dev, p);
 }
 /*
  * Clear vblank timestamp buffer for a crtc.
  */
 static void clear_vblank_timestamps(struct drm_device *dev, int crtc)
 {
 	memset(&dev->_vblank_time[crtc * DRM_VBLANKTIME_RBSIZE], 0,
 		DRM_VBLANKTIME_RBSIZE * sizeof(struct timeval));
 }
 /*
  * Disable vblank irq's on crtc, make sure that last vblank count
  * of hardware and corresponding consistent software vblank counter
  * are preserved, even if there are any spurious vblank irq's after
  * disable.
  */
 static void vblank_disable_and_save(struct drm_device *dev, int crtc)
 {
 	unsigned long irqflags;
 	u32 vblcount;
 	s64 diff_ns;
 	int vblrc;
 	struct timeval tvblank;
 	/* Prevent vblank irq processing while disabling vblank irqs,
 	 * so no updates of timestamps or count can happen after we've
 	 * disabled. Needed to prevent races in case of delayed irq's.
 	 * Disable preemption, so vblank_time_lock is held as short as
 	 * possible, even under a kernel with PREEMPT_RT patches.
 	 */
 	preempt_disable();
 	spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
 	dev->driver->disable_vblank(dev, crtc);
 	dev->vblank_enabled[crtc] = 0;
 	/* No further vblank irq's will be processed after
 	 * this point. Get current hardware vblank count and
 	 * vblank timestamp, repeat until they are consistent.
 	 *
 	 * FIXME: There is still a race condition here and in
 	 * drm_update_vblank_count() which can cause off-by-one
 	 * reinitialization of software vblank counter. If gpu
 	 * vblank counter doesn't increment exactly at the leading
 	 * edge of a vblank interval, then we can lose 1 count if
 	 * we happen to execute between start of vblank and the
 	 * delayed gpu counter increment.
 	 */
 	do {
 		dev->last_vblank[crtc] = dev->driver->get_vblank_counter(dev, crtc);
 		vblrc = drm_get_last_vbltimestamp(dev, crtc, &tvblank, 0);
 	} while (dev->last_vblank[crtc] != dev->driver->get_vblank_counter(dev, crtc));
 	/* Compute time difference to stored timestamp of last vblank
 	 * as updated by last invocation of drm_handle_vblank() in vblank irq.
 	 */
 	vblcount = atomic_read(&dev->_vblank_count[crtc]);
 	diff_ns = timeval_to_ns(&tvblank) -
 		  timeval_to_ns(&vblanktimestamp(dev, crtc, vblcount));
 	/* If there is at least 1 msec difference between the last stored
 	 * timestamp and tvblank, then we are currently executing our
 	 * disable inside a new vblank interval, the tvblank timestamp
 	 * corresponds to this new vblank interval and the irq handler
 	 * for this vblank didn't run yet and won't run due to our disable.
 	 * Therefore we need to do the job of drm_handle_vblank() and
 	 * increment the vblank counter by one to account for this vblank.
 	 *
 	 * Skip this step if there isn't any high precision timestamp
 	 * available. In that case we can't account for this and just
 	 * hope for the best.
 	 */
 	if ((vblrc > 0) && (abs64(diff_ns) > 1000000)) {
 		atomic_inc(&dev->_vblank_count[crtc]);
 		smp_mb__after_atomic_inc();
 	}
 	/* Invalidate all timestamps while vblank irq's are off. */
 	clear_vblank_timestamps(dev, crtc);
 	spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
 	preempt_enable();
 }
 static void vblank_disable_fn(unsigned long arg)
 {
 	struct drm_device *dev = (struct drm_device *)arg;
 	unsigned long irqflags;
 	int i;
 	if (!dev->vblank_disable_allowed)
 		return;
 	for (i = 0; i < dev->num_crtcs; i++) {
 		spin_lock_irqsave(&dev->vbl_lock, irqflags);
 		if (atomic_read(&dev->vblank_refcount[i]) == 0 &&
 		    dev->vblank_enabled[i]) {
 			DRM_DEBUG("disabling vblank on crtc %d\n", i);
 			vblank_disable_and_save(dev, i);
 		}
 		spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
 	}
 }
 void drm_vblank_cleanup(struct drm_device *dev)
 {
 	/* Bail if the driver didn't call drm_vblank_init() */
 	if (dev->num_crtcs == 0)
 		return;
 	del_timer(&dev->vblank_disable_timer);
 	vblank_disable_fn((unsigned long)dev);
 	kfree(dev->vbl_queue);
 	kfree(dev->_vblank_count);
 	kfree(dev->vblank_refcount);
 	kfree(dev->vblank_enabled);
 	kfree(dev->last_vblank);
 	kfree(dev->last_vblank_wait);
 	kfree(dev->vblank_inmodeset);
 	kfree(dev->_vblank_time);
 	dev->num_crtcs = 0;
 }
 EXPORT_SYMBOL(drm_vblank_cleanup);
 int drm_vblank_init(struct drm_device *dev, int num_crtcs)
 {
 	int i, ret = -ENOMEM;
 	setup_timer(&dev->vblank_disable_timer, vblank_disable_fn,
 		    (unsigned long)dev);
 	spin_lock_init(&dev->vbl_lock);
 	spin_lock_init(&dev->vblank_time_lock);
 	dev->num_crtcs = num_crtcs;
 	dev->vbl_queue = kmalloc(sizeof(wait_queue_head_t) * num_crtcs,
 				 GFP_KERNEL);
 	if (!dev->vbl_queue)
 		goto err;
 	dev->_vblank_count = kmalloc(sizeof(atomic_t) * num_crtcs, GFP_KERNEL);
 	if (!dev->_vblank_count)
 		goto err;
 	dev->vblank_refcount = kmalloc(sizeof(atomic_t) * num_crtcs,
 				       GFP_KERNEL);
 	if (!dev->vblank_refcount)
 		goto err;
 	dev->vblank_enabled = kcalloc(num_crtcs, sizeof(int), GFP_KERNEL);
 	if (!dev->vblank_enabled)
 		goto err;
 	dev->last_vblank = kcalloc(num_crtcs, sizeof(u32), GFP_KERNEL);
 	if (!dev->last_vblank)
 		goto err;
 	dev->last_vblank_wait = kcalloc(num_crtcs, sizeof(u32), GFP_KERNEL);
 	if (!dev->last_vblank_wait)
 		goto err;
 	dev->vblank_inmodeset = kcalloc(num_crtcs, sizeof(int), GFP_KERNEL);
 	if (!dev->vblank_inmodeset)
 		goto err;
 	dev->_vblank_time = kcalloc(num_crtcs * DRM_VBLANKTIME_RBSIZE,
 				    sizeof(struct timeval), GFP_KERNEL);
 	if (!dev->_vblank_time)
 		goto err;
 	DRM_INFO("Supports vblank timestamp caching Rev 1 (10.10.2010).\n");
 	/* Driver specific high-precision vblank timestamping supported? */
 	if (dev->driver->get_vblank_timestamp)
 		DRM_INFO("Driver supports precise vblank timestamp query.\n");
 	else
 		DRM_INFO("No driver support for vblank timestamp query.\n");
 	/* Zero per-crtc vblank stuff */
 	for (i = 0; i < num_crtcs; i++) {
 		init_waitqueue_head(&dev->vbl_queue[i]);
 		atomic_set(&dev->_vblank_count[i], 0);
 		atomic_set(&dev->vblank_refcount[i], 0);
 	}
 	dev->vblank_disable_allowed = 0;
 	return 0;
 err:
 	drm_vblank_cleanup(dev);
 	return ret;
 }
 EXPORT_SYMBOL(drm_vblank_init);
 static void drm_irq_vgaarb_nokms(void *cookie, bool state)
 {
 	struct drm_device *dev = cookie;
 	if (dev->driver->vgaarb_irq) {
 		dev->driver->vgaarb_irq(dev, state);
 		return;
 	}
 	if (!dev->irq_enabled)
 		return;
 	if (state)
 		dev->driver->irq_uninstall(dev);
 	else {
 		dev->driver->irq_preinstall(dev);
 		dev->driver->irq_postinstall(dev);
 	}
 }
 /**
  * Install IRQ handler.
  *
  * \param dev DRM device.
  *
  * Initializes the IRQ related data. Installs the handler, calling the driver
  * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions
  * before and after the installation.
  */
 int drm_irq_install(struct drm_device *dev)
 {
 	int ret = 0;
 	unsigned long sh_flags = 0;
 	char *irqname;
 	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
 		return -EINVAL;
 	if (drm_dev_to_irq(dev) == 0)
 		return -EINVAL;
 	mutex_lock(&dev->struct_mutex);
 	/* Driver must have been initialized */
 	if (!dev->dev_private) {
 		mutex_unlock(&dev->struct_mutex);
 		return -EINVAL;
 	}
 	if (dev->irq_enabled) {
 		mutex_unlock(&dev->struct_mutex);
 		return -EBUSY;
 	}
 	dev->irq_enabled = 1;
 	mutex_unlock(&dev->struct_mutex);
 	DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
 	/* Before installing handler */
 	dev->driver->irq_preinstall(dev);
 	/* Install handler */
 	if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED))
 		sh_flags = IRQF_SHARED;
 	if (dev->devname)
 		irqname = dev->devname;
 	else
 		irqname = dev->driver->name;
 	ret = request_irq(drm_dev_to_irq(dev), dev->driver->irq_handler,
 			  sh_flags, irqname, dev);
 	if (ret < 0) {
 		mutex_lock(&dev->struct_mutex);
 		dev->irq_enabled = 0;
 		mutex_unlock(&dev->struct_mutex);
 		return ret;
 	}
 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
 		vga_client_register(dev->pdev, (void *)dev, drm_irq_vgaarb_nokms, NULL);
 	/* After installing handler */
 	ret = dev->driver->irq_postinstall(dev);
 	if (ret < 0) {
 		mutex_lock(&dev->struct_mutex);
 		dev->irq_enabled = 0;
 		mutex_unlock(&dev->struct_mutex);
 	}
 	return ret;
 }
 EXPORT_SYMBOL(drm_irq_install);
 /**
  * Uninstall the IRQ handler.
  *
  * \param dev DRM device.
  *
  * Calls the driver's \c drm_driver_irq_uninstall() function, and stops the irq.
  */
 int drm_irq_uninstall(struct drm_device *dev)
 {
 	unsigned long irqflags;
 	int irq_enabled, i;
 	if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
 		return -EINVAL;
 	mutex_lock(&dev->struct_mutex);
 	irq_enabled = dev->irq_enabled;
 	dev->irq_enabled = 0;
 	mutex_unlock(&dev->struct_mutex);
 	/*
 	 * Wake up any waiters so they don't hang.
 	 */
 	spin_lock_irqsave(&dev->vbl_lock, irqflags);
 	for (i = 0; i < dev->num_crtcs; i++) {
 		DRM_WAKEUP(&dev->vbl_queue[i]);
 		dev->vblank_enabled[i] = 0;
 		dev->last_vblank[i] = dev->driver->get_vblank_counter(dev, i);
 	}
 	spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
 	if (!irq_enabled)
 		return -EINVAL;
 	DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
 		vga_client_register(dev->pdev, NULL, NULL, NULL);
 	dev->driver->irq_uninstall(dev);
 	free_irq(drm_dev_to_irq(dev), dev);
 	return 0;
 }
 EXPORT_SYMBOL(drm_irq_uninstall);
 /**
  * IRQ control ioctl.
  *
  * \param inode device inode.
  * \param file_priv DRM file private.
  * \param cmd command.
  * \param arg user argument, pointing to a drm_control structure.
  * \return zero on success or a negative number on failure.
  *
  * Calls irq_install() or irq_uninstall() according to \p arg.
  */
 int drm_control(struct drm_device *dev, void *data,
 		struct drm_file *file_priv)
 {
 	struct drm_control *ctl = data;
 	/* if we haven't irq we fallback for compatibility reasons -
 	 * this used to be a separate function in drm_dma.h
 	 */
 	switch (ctl->func) {
 	case DRM_INST_HANDLER:
 		if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
 			return 0;
 		if (drm_core_check_feature(dev, DRIVER_MODESET))
 			return 0;
 		if (dev->if_version < DRM_IF_VERSION(1, 2) &&
 		    ctl->irq != drm_dev_to_irq(dev))
 			return -EINVAL;
 		return drm_irq_install(dev);
 	case DRM_UNINST_HANDLER:
 		if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
 			return 0;
 		if (drm_core_check_feature(dev, DRIVER_MODESET))
 			return 0;
 		return drm_irq_uninstall(dev);
 	default:
 		return -EINVAL;
 	}
 }
 /**
  * drm_calc_timestamping_constants - Calculate and
  * store various constants which are later needed by
  * vblank and swap-completion timestamping, e.g, by
  * drm_calc_vbltimestamp_from_scanoutpos().
  * They are derived from crtc's true scanout timing,
  * so they take things like panel scaling or other
  * adjustments into account.
  *
  * @crtc drm_crtc whose timestamp constants should be updated.
  *
  */
 void drm_calc_timestamping_constants(struct drm_crtc *crtc)
 {
 	s64 linedur_ns = 0, pixeldur_ns = 0, framedur_ns = 0;
 	u64 dotclock;
 	/* Dot clock in Hz: */
 	dotclock = (u64) crtc->hwmode.clock * 1000;
 	/* Fields of interlaced scanout modes are only halve a frame duration.
 	 * Double the dotclock to get halve the frame-/line-/pixelduration.
 	 */
 	if (crtc->hwmode.flags & DRM_MODE_FLAG_INTERLACE)
 		dotclock *= 2;
 	/* Valid dotclock? */
 	if (dotclock > 0) {
 		/* Convert scanline length in pixels and video dot clock to
 		 * line duration, frame duration and pixel duration in
 		 * nanoseconds:
 		 */
 		pixeldur_ns = (s64) div64_u64(1000000000, dotclock);
 		linedur_ns  = (s64) div64_u64(((u64) crtc->hwmode.crtc_htotal *
 					      1000000000), dotclock);
 		framedur_ns = (s64) crtc->hwmode.crtc_vtotal * linedur_ns;
 	} else
 		DRM_ERROR("crtc %d: Can't calculate constants, dotclock = 0!\n",
 			  crtc->base.id);
 	crtc->pixeldur_ns = pixeldur_ns;
 	crtc->linedur_ns  = linedur_ns;
 	crtc->framedur_ns = framedur_ns;
 	DRM_DEBUG("crtc %d: hwmode: htotal %d, vtotal %d, vdisplay %d\n",
 		  crtc->base.id, crtc->hwmode.crtc_htotal,
 		  crtc->hwmode.crtc_vtotal, crtc->hwmode.crtc_vdisplay);
 	DRM_DEBUG("crtc %d: clock %d kHz framedur %d linedur %d, pixeldur %d\n",
 		  crtc->base.id, (int) dotclock/1000, (int) framedur_ns,
 		  (int) linedur_ns, (int) pixeldur_ns);
 }
 EXPORT_SYMBOL(drm_calc_timestamping_constants);
 /**
  * drm_calc_vbltimestamp_from_scanoutpos - helper routine for kms
  * drivers. Implements calculation of exact vblank timestamps from
  * given drm_display_mode timings and current video scanout position
  * of a crtc. This can be called from within get_vblank_timestamp()
  * implementation of a kms driver to implement the actual timestamping.
  *
  * Should return timestamps conforming to the OML_sync_control OpenML
  * extension specification. The timestamp corresponds to the end of
  * the vblank interval, aka start of scanout of topmost-leftmost display
  * pixel in the following video frame.
  *
  * Requires support for optional dev->driver->get_scanout_position()
  * in kms driver, plus a bit of setup code to provide a drm_display_mode
  * that corresponds to the true scanout timing.
  *
  * The current implementation only handles standard video modes. It
  * returns as no operation if a doublescan or interlaced video mode is
  * active. Higher level code is expected to handle this.
  *
  * @dev: DRM device.
  * @crtc: Which crtc's vblank timestamp to retrieve.
  * @max_error: Desired maximum allowable error in timestamps (nanosecs).
  *             On return contains true maximum error of timestamp.
  * @vblank_time: Pointer to struct timeval which should receive the timestamp.
  * @flags: Flags to pass to driver:
  *         0 = Default.
  *         DRM_CALLED_FROM_VBLIRQ = If function is called from vbl irq handler.
  * @refcrtc: drm_crtc* of crtc which defines scanout timing.
  *
  * Returns negative value on error, failure or if not supported in current
  * video mode:
  *
  * -EINVAL   - Invalid crtc.
  * -EAGAIN   - Temporary unavailable, e.g., called before initial modeset.
  * -ENOTSUPP - Function not supported in current display mode.
  * -EIO      - Failed, e.g., due to failed scanout position query.
  *
  * Returns or'ed positive status flags on success:
  *
  * DRM_VBLANKTIME_SCANOUTPOS_METHOD - Signal this method used for timestamping.
  * DRM_VBLANKTIME_INVBL - Timestamp taken while scanout was in vblank interval.
  *
  */
 int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, int crtc,
 					  int *max_error,
 					  struct timeval *vblank_time,
 					  unsigned flags,
 					  struct drm_crtc *refcrtc)
 {
 	struct timeval stime, raw_time;
 	struct drm_display_mode *mode;
 	int vbl_status, vtotal, vdisplay;
 	int vpos, hpos, i;
 	s64 framedur_ns, linedur_ns, pixeldur_ns, delta_ns, duration_ns;
 	bool invbl;
 	if (crtc < 0 || crtc >= dev->num_crtcs) {
 		DRM_ERROR("Invalid crtc %d\n", crtc);
 		return -EINVAL;
 	}
 	/* Scanout position query not supported? Should not happen. */
 	if (!dev->driver->get_scanout_position) {
 		DRM_ERROR("Called from driver w/o get_scanout_position()!?\n");
 		return -EIO;
 	}
 	mode = &refcrtc->hwmode;
 	vtotal = mode->crtc_vtotal;
 	vdisplay = mode->crtc_vdisplay;
 	/* Durations of frames, lines, pixels in nanoseconds. */
 	framedur_ns = refcrtc->framedur_ns;
 	linedur_ns  = refcrtc->linedur_ns;
 	pixeldur_ns = refcrtc->pixeldur_ns;
 	/* If mode timing undefined, just return as no-op:
 	 * Happens during initial modesetting of a crtc.
 	 */
 	if (vtotal <= 0 || vdisplay <= 0 || framedur_ns == 0) {
 		DRM_DEBUG("crtc %d: Noop due to uninitialized mode.\n", crtc);
 		return -EAGAIN;
 	}
 	/* Get current scanout position with system timestamp.
 	 * Repeat query up to DRM_TIMESTAMP_MAXRETRIES times
 	 * if single query takes longer than max_error nanoseconds.
 	 *
 	 * This guarantees a tight bound on maximum error if
 	 * code gets preempted or delayed for some reason.
 	 */
 	for (i = 0; i < DRM_TIMESTAMP_MAXRETRIES; i++) {
 		/* Disable preemption to make it very likely to
 		 * succeed in the first iteration even on PREEMPT_RT kernel.
 		 */
 		preempt_disable();
 		/* Get system timestamp before query. */
 		do_gettimeofday(&stime);
 		/* Get vertical and horizontal scanout pos. vpos, hpos. */
 		vbl_status = dev->driver->get_scanout_position(dev, crtc, &vpos, &hpos);
 		/* Get system timestamp after query. */
 		do_gettimeofday(&raw_time);
 		preempt_enable();
 		/* Return as no-op if scanout query unsupported or failed. */
 		if (!(vbl_status & DRM_SCANOUTPOS_VALID)) {
 			DRM_DEBUG("crtc %d : scanoutpos query failed [%d].\n",
 				  crtc, vbl_status);
 			return -EIO;
 		}
 		duration_ns = timeval_to_ns(&raw_time) - timeval_to_ns(&stime);
 		/* Accept result with <  max_error nsecs timing uncertainty. */
 		if (duration_ns <= (s64) *max_error)
 			break;
 	}
 	/* Noisy system timing? */
 	if (i == DRM_TIMESTAMP_MAXRETRIES) {
 		DRM_DEBUG("crtc %d: Noisy timestamp %d us > %d us [%d reps].\n",
 			  crtc, (int) duration_ns/1000, *max_error/1000, i);
 	}
 	/* Return upper bound of timestamp precision error. */
 	*max_error = (int) duration_ns;
 	/* Check if in vblank area:
 	 * vpos is >=0 in video scanout area, but negative
 	 * within vblank area, counting down the number of lines until
 	 * start of scanout.
 	 */
 	invbl = vbl_status & DRM_SCANOUTPOS_INVBL;
 	/* Convert scanout position into elapsed time at raw_time query
 	 * since start of scanout at first display scanline. delta_ns
 	 * can be negative if start of scanout hasn't happened yet.
 	 */
 	delta_ns = (s64) vpos * linedur_ns + (s64) hpos * pixeldur_ns;
 	/* Is vpos outside nominal vblank area, but less than
 	 * 1/100 of a frame height away from start of vblank?
 	 * If so, assume this isn't a massively delayed vblank
 	 * interrupt, but a vblank interrupt that fired a few
 	 * microseconds before true start of vblank. Compensate
 	 * by adding a full frame duration to the final timestamp.
 	 * Happens, e.g., on ATI R500, R600.
 	 *
 	 * We only do this if DRM_CALLED_FROM_VBLIRQ.
 	 */
 	if ((flags & DRM_CALLED_FROM_VBLIRQ) && !invbl &&
 	    ((vdisplay - vpos) < vtotal / 100)) {
 		delta_ns = delta_ns - framedur_ns;
 		/* Signal this correction as "applied". */
 		vbl_status |= 0x8;
 	}
 	/* Subtract time delta from raw timestamp to get final
 	 * vblank_time timestamp for end of vblank.
 	 */
 	*vblank_time = ns_to_timeval(timeval_to_ns(&raw_time) - delta_ns);
-	DRM_DEBUG("crtc %d : v %d p(%d,%d)@ %d.%d -> %d.%d [e %d us, %d rep]\n",
+	DRM_DEBUG("crtc %d : v %d p(%d,%d)@ %ld.%ld -> %ld.%ld [e %d us, %d rep]\n",
-		  crtc, (int) vbl_status, hpos, vpos, raw_time.tv_sec,
+		  crtc, (int)vbl_status, hpos, vpos,
-		  raw_time.tv_usec, vblank_time->tv_sec, vblank_time->tv_usec,
+		  (long)raw_time.tv_sec, (long)raw_time.tv_usec,
-		  (int) duration_ns/1000, i);
+		  (long)vblank_time->tv_sec, (long)vblank_time->tv_usec,
+		  (int)duration_ns/1000, i);
 	vbl_status = DRM_VBLANKTIME_SCANOUTPOS_METHOD;
 	if (invbl)
 		vbl_status |= DRM_VBLANKTIME_INVBL;
 	return vbl_status;
 }
 EXPORT_SYMBOL(drm_calc_vbltimestamp_from_scanoutpos);
 /**
  * drm_get_last_vbltimestamp - retrieve raw timestamp for the most recent
  * vblank interval.
  *
  * @dev: DRM device
  * @crtc: which crtc's vblank timestamp to retrieve
  * @tvblank: Pointer to target struct timeval which should receive the timestamp
  * @flags: Flags to pass to driver:
  *         0 = Default.
  *         DRM_CALLED_FROM_VBLIRQ = If function is called from vbl irq handler.
  *
  * Fetches the system timestamp corresponding to the time of the most recent
  * vblank interval on specified crtc. May call into kms-driver to
  * compute the timestamp with a high-precision GPU specific method.
  *
  * Returns zero if timestamp originates from uncorrected do_gettimeofday()
  * call, i.e., it isn't very precisely locked to the true vblank.
  *
  * Returns non-zero if timestamp is considered to be very precise.
  */
 u32 drm_get_last_vbltimestamp(struct drm_device *dev, int crtc,
 			      struct timeval *tvblank, unsigned flags)
 {
 	int ret = 0;
 	/* Define requested maximum error on timestamps (nanoseconds). */
 	int max_error = (int) drm_timestamp_precision * 1000;
 	/* Query driver if possible and precision timestamping enabled. */
 	if (dev->driver->get_vblank_timestamp && (max_error > 0)) {
 		ret = dev->driver->get_vblank_timestamp(dev, crtc, &max_error,
 							tvblank, flags);
 		if (ret > 0)
 			return (u32) ret;
 	}
 	/* GPU high precision timestamp query unsupported or failed.
 	 * Return gettimeofday timestamp as best estimate.
 	 */
 	do_gettimeofday(tvblank);
 	return 0;
 }
 EXPORT_SYMBOL(drm_get_last_vbltimestamp);
 /**
  * drm_vblank_count - retrieve "cooked" vblank counter value
  * @dev: DRM device
  * @crtc: which counter to retrieve
  *
  * Fetches the "cooked" vblank count value that represents the number of
  * vblank events since the system was booted, including lost events due to
  * modesetting activity.
  */
 u32 drm_vblank_count(struct drm_device *dev, int crtc)
 {
 	return atomic_read(&dev->_vblank_count[crtc]);
 }
 EXPORT_SYMBOL(drm_vblank_count);
 /**
  * drm_vblank_count_and_time - retrieve "cooked" vblank counter value
  * and the system timestamp corresponding to that vblank counter value.
  *
  * @dev: DRM device
  * @crtc: which counter to retrieve
  * @vblanktime: Pointer to struct timeval to receive the vblank timestamp.
  *
  * Fetches the "cooked" vblank count value that represents the number of
  * vblank events since the system was booted, including lost events due to
  * modesetting activity. Returns corresponding system timestamp of the time
  * of the vblank interval that corresponds to the current value vblank counter
  * value.
  */
 u32 drm_vblank_count_and_time(struct drm_device *dev, int crtc,
 			      struct timeval *vblanktime)
 {
 	u32 cur_vblank;
 	/* Read timestamp from slot of _vblank_time ringbuffer
 	 * that corresponds to current vblank count. Retry if
 	 * count has incremented during readout. This works like
 	 * a seqlock.
 	 */
 	do {
 		cur_vblank = atomic_read(&dev->_vblank_count[crtc]);
 		*vblanktime = vblanktimestamp(dev, crtc, cur_vblank);
 		smp_rmb();
 	} while (cur_vblank != atomic_read(&dev->_vblank_count[crtc]));
 	return cur_vblank;
 }
 EXPORT_SYMBOL(drm_vblank_count_and_time);
 /**
  * drm_update_vblank_count - update the master vblank counter
  * @dev: DRM device
  * @crtc: counter to update
  *
  * Call back into the driver to update the appropriate vblank counter
  * (specified by @crtc).  Deal with wraparound, if it occurred, and
  * update the last read value so we can deal with wraparound on the next
  * call if necessary.
  *
  * Only necessary when going from off->on, to account for frames we
  * didn't get an interrupt for.
  *
  * Note: caller must hold dev->vbl_lock since this reads & writes
  * device vblank fields.
  */
 static void drm_update_vblank_count(struct drm_device *dev, int crtc)
 {
 	u32 cur_vblank, diff, tslot, rc;
 	struct timeval t_vblank;
 	/*
 	 * Interrupts were disabled prior to this call, so deal with counter
 	 * wrap if needed.
 	 * NOTE!  It's possible we lost a full dev->max_vblank_count events
 	 * here if the register is small or we had vblank interrupts off for
 	 * a long time.
 	 *
 	 * We repeat the hardware vblank counter & timestamp query until
 	 * we get consistent results. This to prevent races between gpu
 	 * updating its hardware counter while we are retrieving the
 	 * corresponding vblank timestamp.
 	 */
 	do {
 		cur_vblank = dev->driver->get_vblank_counter(dev, crtc);
 		rc = drm_get_last_vbltimestamp(dev, crtc, &t_vblank, 0);
 	} while (cur_vblank != dev->driver->get_vblank_counter(dev, crtc));
 	/* Deal with counter wrap */
 	diff = cur_vblank - dev->last_vblank[crtc];
 	if (cur_vblank < dev->last_vblank[crtc]) {
 		diff += dev->max_vblank_count;
 		DRM_DEBUG("last_vblank[%d]=0x%x, cur_vblank=0x%x => diff=0x%x\n",
 			  crtc, dev->last_vblank[crtc], cur_vblank, diff);
 	}
 	DRM_DEBUG("enabling vblank interrupts on crtc %d, missed %d\n",
 		  crtc, diff);
 	/* Reinitialize corresponding vblank timestamp if high-precision query
 	 * available. Skip this step if query unsupported or failed. Will
 	 * reinitialize delayed at next vblank interrupt in that case.
 	 */
 	if (rc) {
 		tslot = atomic_read(&dev->_vblank_count[crtc]) + diff;
 		vblanktimestamp(dev, crtc, tslot) = t_vblank;
 	}
 	smp_mb__before_atomic_inc();
 	atomic_add(diff, &dev->_vblank_count[crtc]);
 	smp_mb__after_atomic_inc();
 }
 /**
  * drm_vblank_get - get a reference count on vblank events
  * @dev: DRM device
  * @crtc: which CRTC to own
  *
  * Acquire a reference count on vblank events to avoid having them disabled
  * while in use.
  *
  * RETURNS
  * Zero on success, nonzero on failure.
  */
 int drm_vblank_get(struct drm_device *dev, int crtc)
 {
 	unsigned long irqflags, irqflags2;
 	int ret = 0;
 	spin_lock_irqsave(&dev->vbl_lock, irqflags);
 	/* Going from 0->1 means we have to enable interrupts again */
 	if (atomic_add_return(1, &dev->vblank_refcount[crtc]) == 1) {
 		/* Disable preemption while holding vblank_time_lock. Do
 		 * it explicitely to guard against PREEMPT_RT kernel.
 		 */
 		preempt_disable();
 		spin_lock_irqsave(&dev->vblank_time_lock, irqflags2);
 		if (!dev->vblank_enabled[crtc]) {
 			/* Enable vblank irqs under vblank_time_lock protection.
 			 * All vblank count & timestamp updates are held off
 			 * until we are done reinitializing master counter and
 			 * timestamps. Filtercode in drm_handle_vblank() will
 			 * prevent double-accounting of same vblank interval.
 			 */
 			ret = dev->driver->enable_vblank(dev, crtc);
 			DRM_DEBUG("enabling vblank on crtc %d, ret: %d\n",
 				  crtc, ret);
 			if (ret)
 				atomic_dec(&dev->vblank_refcount[crtc]);
 			else {
 				dev->vblank_enabled[crtc] = 1;
 				drm_update_vblank_count(dev, crtc);
 			}
 		}
 		spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags2);
 		preempt_enable();
 	} else {
 		if (!dev->vblank_enabled[crtc]) {
 			atomic_dec(&dev->vblank_refcount[crtc]);
 			ret = -EINVAL;
 		}
 	}
 	spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
 	return ret;
 }
 EXPORT_SYMBOL(drm_vblank_get);
 /**
  * drm_vblank_put - give up ownership of vblank events
  * @dev: DRM device
  * @crtc: which counter to give up
  *
  * Release ownership of a given vblank counter, turning off interrupts
  * if possible. Disable interrupts after drm_vblank_offdelay milliseconds.
  */
 void drm_vblank_put(struct drm_device *dev, int crtc)
 {
 	BUG_ON(atomic_read(&dev->vblank_refcount[crtc]) == 0);
 	/* Last user schedules interrupt disable */
 	if (atomic_dec_and_test(&dev->vblank_refcount[crtc]) &&
 	    (drm_vblank_offdelay > 0))
 		mod_timer(&dev->vblank_disable_timer,
 			  jiffies + ((drm_vblank_offdelay * DRM_HZ)/1000));
 }
 EXPORT_SYMBOL(drm_vblank_put);
 void drm_vblank_off(struct drm_device *dev, int crtc)
 {
 	unsigned long irqflags;
 	spin_lock_irqsave(&dev->vbl_lock, irqflags);
 	vblank_disable_and_save(dev, crtc);
 	DRM_WAKEUP(&dev->vbl_queue[crtc]);
 	spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
 }
 EXPORT_SYMBOL(drm_vblank_off);
 /**
  * drm_vblank_pre_modeset - account for vblanks across mode sets
  * @dev: DRM device
  * @crtc: CRTC in question
  * @post: post or pre mode set?
  *
  * Account for vblank events across mode setting events, which will likely
  * reset the hardware frame counter.
  */
 void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
 {
 	/* vblank is not initialized (IRQ not installed ?) */
 	if (!dev->num_crtcs)
 		return;
 	/*
 	 * To avoid all the problems that might happen if interrupts
 	 * were enabled/disabled around or between these calls, we just
 	 * have the kernel take a reference on the CRTC (just once though
 	 * to avoid corrupting the count if multiple, mismatch calls occur),
 	 * so that interrupts remain enabled in the interim.
 	 */
 	if (!dev->vblank_inmodeset[crtc]) {
 		dev->vblank_inmodeset[crtc] = 0x1;
 		if (drm_vblank_get(dev, crtc) == 0)
 			dev->vblank_inmodeset[crtc] |= 0x2;
 	}
 }
 EXPORT_SYMBOL(drm_vblank_pre_modeset);
 void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
 {
 	unsigned long irqflags;
 	if (dev->vblank_inmodeset[crtc]) {
 		spin_lock_irqsave(&dev->vbl_lock, irqflags);
 		dev->vblank_disable_allowed = 1;
 		spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
 		if (dev->vblank_inmodeset[crtc] & 0x2)
 			drm_vblank_put(dev, crtc);
 		dev->vblank_inmodeset[crtc] = 0;
 	}
 }
 EXPORT_SYMBOL(drm_vblank_post_modeset);
 /**
  * drm_modeset_ctl - handle vblank event counter changes across mode switch
  * @DRM_IOCTL_ARGS: standard ioctl arguments
  *
  * Applications should call the %_DRM_PRE_MODESET and %_DRM_POST_MODESET
  * ioctls around modesetting so that any lost vblank events are accounted for.
  *
  * Generally the counter will reset across mode sets.  If interrupts are
  * enabled around this call, we don't have to do anything since the counter
  * will have already been incremented.
  */
 int drm_modeset_ctl(struct drm_device *dev, void *data,
 		    struct drm_file *file_priv)
 {
 	struct drm_modeset_ctl *modeset = data;
 	int ret = 0;
 	unsigned int crtc;
 	/* If drm_vblank_init() hasn't been called yet, just no-op */
 	if (!dev->num_crtcs)
 		goto out;
 	crtc = modeset->crtc;
 	if (crtc >= dev->num_crtcs) {
 		ret = -EINVAL;
 		goto out;
 	}
 	switch (modeset->cmd) {
 	case _DRM_PRE_MODESET:
 		drm_vblank_pre_modeset(dev, crtc);
 		break;
 	case _DRM_POST_MODESET:
 		drm_vblank_post_modeset(dev, crtc);
 		break;
 	default:
 		ret = -EINVAL;
 		break;
 	}
 out:
 	return ret;
 }
 static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
 				  union drm_wait_vblank *vblwait,
 				  struct drm_file *file_priv)
 {
 	struct drm_pending_vblank_event *e;
 	struct timeval now;
 	unsigned long flags;
 	unsigned int seq;
 	int ret;
 	e = kzalloc(sizeof *e, GFP_KERNEL);
 	if (e == NULL) {
 		ret = -ENOMEM;
 		goto err_put;
 	}
 	e->pipe = pipe;
 	e->base.pid = current->pid;
 	e->event.base.type = DRM_EVENT_VBLANK;
 	e->event.base.length = sizeof e->event;
 	e->event.user_data = vblwait->request.signal;
 	e->base.event = &e->event.base;
 	e->base.file_priv = file_priv;
 	e->base.destroy = (void (*) (struct drm_pending_event *)) kfree;
 	spin_lock_irqsave(&dev->event_lock, flags);
 	if (file_priv->event_space < sizeof e->event) {
 		ret = -EBUSY;
 		goto err_unlock;
 	}
 	file_priv->event_space -= sizeof e->event;
 	seq = drm_vblank_count_and_time(dev, pipe, &now);
 	if ((vblwait->request.type & _DRM_VBLANK_NEXTONMISS) &&
 	    (seq - vblwait->request.sequence) <= (1 << 23)) {
 		vblwait->request.sequence = seq + 1;
 		vblwait->reply.sequence = vblwait->request.sequence;
 	}
 	DRM_DEBUG("event on vblank count %d, current %d, crtc %d\n",
 		  vblwait->request.sequence, seq, pipe);
 	trace_drm_vblank_event_queued(current->pid, pipe,
 				      vblwait->request.sequence);
 	e->event.sequence = vblwait->request.sequence;
 	if ((seq - vblwait->request.sequence) <= (1 << 23)) {
 		e->event.sequence = seq;
 		e->event.tv_sec = now.tv_sec;
 		e->event.tv_usec = now.tv_usec;
 		drm_vblank_put(dev, pipe);
 		list_add_tail(&e->base.link, &e->base.file_priv->event_list);
 		wake_up_interruptible(&e->base.file_priv->event_wait);
 		vblwait->reply.sequence = seq;
 		trace_drm_vblank_event_delivered(current->pid, pipe,
 						 vblwait->request.sequence);
 	} else {
 		list_add_tail(&e->base.link, &dev->vblank_event_list);
 		vblwait->reply.sequence = vblwait->request.sequence;
 	}
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	return 0;
 err_unlock:
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	kfree(e);
 err_put:
 	drm_vblank_put(dev, pipe);
 	return ret;
 }
 /**
  * Wait for VBLANK.
  *
  * \param inode device inode.
  * \param file_priv DRM file private.
  * \param cmd command.
  * \param data user argument, pointing to a drm_wait_vblank structure.
  * \return zero on success or a negative number on failure.
  *
  * This function enables the vblank interrupt on the pipe requested, then
  * sleeps waiting for the requested sequence number to occur, and drops
  * the vblank interrupt refcount afterwards. (vblank irq disable follows that
  * after a timeout with no further vblank waits scheduled).
  */
 int drm_wait_vblank(struct drm_device *dev, void *data,
 		    struct drm_file *file_priv)
 {
 	union drm_wait_vblank *vblwait = data;
 	int ret = 0;
 	unsigned int flags, seq, crtc, high_crtc;
 	if ((!drm_dev_to_irq(dev)) || (!dev->irq_enabled))
 		return -EINVAL;
 	if (vblwait->request.type & _DRM_VBLANK_SIGNAL)
 		return -EINVAL;
 	if (vblwait->request.type &
 	    ~(_DRM_VBLANK_TYPES_MASK | _DRM_VBLANK_FLAGS_MASK |
 	      _DRM_VBLANK_HIGH_CRTC_MASK)) {
 		DRM_ERROR("Unsupported type value 0x%x, supported mask 0x%x\n",
 			  vblwait->request.type,
 			  (_DRM_VBLANK_TYPES_MASK | _DRM_VBLANK_FLAGS_MASK |
 			   _DRM_VBLANK_HIGH_CRTC_MASK));
 		return -EINVAL;
 	}
 	flags = vblwait->request.type & _DRM_VBLANK_FLAGS_MASK;
 	high_crtc = (vblwait->request.type & _DRM_VBLANK_HIGH_CRTC_MASK);
 	if (high_crtc)
 		crtc = high_crtc >> _DRM_VBLANK_HIGH_CRTC_SHIFT;
 	else
 		crtc = flags & _DRM_VBLANK_SECONDARY ? 1 : 0;
 	if (crtc >= dev->num_crtcs)
 		return -EINVAL;
 	ret = drm_vblank_get(dev, crtc);
 	if (ret) {
 		DRM_DEBUG("failed to acquire vblank counter, %d\n", ret);
 		return ret;
 	}
 	seq = drm_vblank_count(dev, crtc);
 	switch (vblwait->request.type & _DRM_VBLANK_TYPES_MASK) {
 	case _DRM_VBLANK_RELATIVE:
 		vblwait->request.sequence += seq;
 		vblwait->request.type &= ~_DRM_VBLANK_RELATIVE;
 	case _DRM_VBLANK_ABSOLUTE:
 		break;
 	default:
 		ret = -EINVAL;
 		goto done;
 	}
 	if (flags & _DRM_VBLANK_EVENT)
 		return drm_queue_vblank_event(dev, crtc, vblwait, file_priv);
 	if ((flags & _DRM_VBLANK_NEXTONMISS) &&
 	    (seq - vblwait->request.sequence) <= (1<<23)) {
 		vblwait->request.sequence = seq + 1;
 	}
 	DRM_DEBUG("waiting on vblank count %d, crtc %d\n",
 		  vblwait->request.sequence, crtc);
 	dev->last_vblank_wait[crtc] = vblwait->request.sequence;
 	DRM_WAIT_ON(ret, dev->vbl_queue[crtc], 3 * DRM_HZ,
 		    (((drm_vblank_count(dev, crtc) -
 		       vblwait->request.sequence) <= (1 << 23)) ||
 		     !dev->irq_enabled));
 	if (ret != -EINTR) {
 		struct timeval now;
 		vblwait->reply.sequence = drm_vblank_count_and_time(dev, crtc, &now);
 		vblwait->reply.tval_sec = now.tv_sec;
 		vblwait->reply.tval_usec = now.tv_usec;
 		DRM_DEBUG("returning %d to client\n",
 			  vblwait->reply.sequence);
 	} else {
 		DRM_DEBUG("vblank wait interrupted by signal\n");
 	}
 done:
 	drm_vblank_put(dev, crtc);
 	return ret;
 }
 void drm_handle_vblank_events(struct drm_device *dev, int crtc)
 {
 	struct drm_pending_vblank_event *e, *t;
 	struct timeval now;
 	unsigned long flags;
 	unsigned int seq;
 	seq = drm_vblank_count_and_time(dev, crtc, &now);
 	spin_lock_irqsave(&dev->event_lock, flags);
 	list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) {
 		if (e->pipe != crtc)
 			continue;
 		if ((seq - e->event.sequence) > (1<<23))
 			continue;
 		DRM_DEBUG("vblank event on %d, current %d\n",
 			  e->event.sequence, seq);
 		e->event.sequence = seq;
 		e->event.tv_sec = now.tv_sec;
 		e->event.tv_usec = now.tv_usec;
 		drm_vblank_put(dev, e->pipe);
 		list_move_tail(&e->base.link, &e->base.file_priv->event_list);
 		wake_up_interruptible(&e->base.file_priv->event_wait);
 		trace_drm_vblank_event_delivered(e->base.pid, e->pipe,
 						 e->event.sequence);
 	}
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	trace_drm_vblank_event(crtc, seq);
 }
 /**
  * drm_handle_vblank - handle a vblank event
  * @dev: DRM device
  * @crtc: where this event occurred
  *
  * Drivers should call this routine in their vblank interrupt handlers to
  * update the vblank counter and send any signals that may be pending.
  */
 bool drm_handle_vblank(struct drm_device *dev, int crtc)
 {
 	u32 vblcount;
 	s64 diff_ns;
 	struct timeval tvblank;
 	unsigned long irqflags;
 	if (!dev->num_crtcs)
 		return false;
 	/* Need timestamp lock to prevent concurrent execution with
 	 * vblank enable/disable, as this would cause inconsistent
 	 * or corrupted timestamps and vblank counts.
 	 */
 	spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
 	/* Vblank irq handling disabled. Nothing to do. */
 	if (!dev->vblank_enabled[crtc]) {
 		spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
 		return false;
 	}
 	/* Fetch corresponding timestamp for this vblank interval from
 	 * driver and store it in proper slot of timestamp ringbuffer.
 	 */
 	/* Get current timestamp and count. */
 	vblcount = atomic_read(&dev->_vblank_count[crtc]);
 	drm_get_last_vbltimestamp(dev, crtc, &tvblank, DRM_CALLED_FROM_VBLIRQ);
 	/* Compute time difference to timestamp of last vblank */
 	diff_ns = timeval_to_ns(&tvblank) -
 		  timeval_to_ns(&vblanktimestamp(dev, crtc, vblcount));
 	/* Update vblank timestamp and count if at least
 	 * DRM_REDUNDANT_VBLIRQ_THRESH_NS nanoseconds
 	 * difference between last stored timestamp and current
 	 * timestamp. A smaller difference means basically
 	 * identical timestamps. Happens if this vblank has
 	 * been already processed and this is a redundant call,
 	 * e.g., due to spurious vblank interrupts. We need to
 	 * ignore those for accounting.
 	 */
 	if (abs64(diff_ns) > DRM_REDUNDANT_VBLIRQ_THRESH_NS) {
 		/* Store new timestamp in ringbuffer. */
 		vblanktimestamp(dev, crtc, vblcount + 1) = tvblank;
 		/* Increment cooked vblank count. This also atomically commits
 		 * the timestamp computed above.
 		 */
 		smp_mb__before_atomic_inc();
 		atomic_inc(&dev->_vblank_count[crtc]);
 		smp_mb__after_atomic_inc();
 	} else {
 		DRM_DEBUG("crtc %d: Redundant vblirq ignored. diff_ns = %d\n",
 			  crtc, (int) diff_ns);
 	}
 	DRM_WAKEUP(&dev->vbl_queue[crtc]);
 	drm_handle_vblank_events(dev, crtc);
 	spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
 	return true;
 }
 EXPORT_SYMBOL(drm_handle_vblank);

drivers/gpu/drm/i915/intel_bios.c

Diff comments View file @ bbb0aef

1	/*	1	/*
2	* Copyright © 2006 Intel Corporation	2	* Copyright © 2006 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21	* SOFTWARE.	21	* SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt <eric@anholt.net>	24	* Eric Anholt <eric@anholt.net>
25	*	25	*
26	*/	26	*/
27	#include <drm/drm_dp_helper.h>	27	#include <drm/drm_dp_helper.h>
28	#include "drmP.h"	28	#include "drmP.h"
29	#include "drm.h"	29	#include "drm.h"
30	#include "i915_drm.h"	30	#include "i915_drm.h"
31	#include "i915_drv.h"	31	#include "i915_drv.h"
32	#include "intel_bios.h"	32	#include "intel_bios.h"
33		33
34	#define SLAVE_ADDR1 0x70	34	#define SLAVE_ADDR1 0x70
35	#define SLAVE_ADDR2 0x72	35	#define SLAVE_ADDR2 0x72
36		36
37	static int panel_type;	37	static int panel_type;
38		38
39	static void *	39	static void *
40	find_section(struct bdb_header *bdb, int section_id)	40	find_section(struct bdb_header *bdb, int section_id)
41	{	41	{
42	u8 base = (u8 )bdb;	42	u8 base = (u8 )bdb;
43	int index = 0;	43	int index = 0;
44	u16 total, current_size;	44	u16 total, current_size;
45	u8 current_id;	45	u8 current_id;
46		46
47	/* skip to first section */	47	/* skip to first section */
48	index += bdb->header_size;	48	index += bdb->header_size;
49	total = bdb->bdb_size;	49	total = bdb->bdb_size;
50		50
51	/* walk the sections looking for section_id */	51	/* walk the sections looking for section_id */
52	while (index < total) {	52	while (index < total) {
53	current_id = *(base + index);	53	current_id = *(base + index);
54	index++;	54	index++;
55	current_size = ((u16 )(base + index));	55	current_size = ((u16 )(base + index));
56	index += 2;	56	index += 2;
57	if (current_id == section_id)	57	if (current_id == section_id)
58	return base + index;	58	return base + index;
59	index += current_size;	59	index += current_size;
60	}	60	}
61		61
62	return NULL;	62	return NULL;
63	}	63	}
64		64
65	static u16	65	static u16
66	get_blocksize(void *p)	66	get_blocksize(void *p)
67	{	67	{
68	u16 *block_ptr, block_size;	68	u16 *block_ptr, block_size;
69		69
70	block_ptr = (u16 )((char )p - 2);	70	block_ptr = (u16 )((char )p - 2);
71	block_size = *block_ptr;	71	block_size = *block_ptr;
72	return block_size;	72	return block_size;
73	}	73	}
74		74
75	static void	75	static void
76	fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,	76	fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
77	struct lvds_dvo_timing *dvo_timing)	77	struct lvds_dvo_timing *dvo_timing)
78	{	78	{
79	panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) \|	79	panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) \|
80	dvo_timing->hactive_lo;	80	dvo_timing->hactive_lo;
81	panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +	81	panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
82	((dvo_timing->hsync_off_hi << 8) \| dvo_timing->hsync_off_lo);	82	((dvo_timing->hsync_off_hi << 8) \| dvo_timing->hsync_off_lo);
83	panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +	83	panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
84	dvo_timing->hsync_pulse_width;	84	dvo_timing->hsync_pulse_width;
85	panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +	85	panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
86	((dvo_timing->hblank_hi << 8) \| dvo_timing->hblank_lo);	86	((dvo_timing->hblank_hi << 8) \| dvo_timing->hblank_lo);
87		87
88	panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) \|	88	panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) \|
89	dvo_timing->vactive_lo;	89	dvo_timing->vactive_lo;
90	panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +	90	panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
91	dvo_timing->vsync_off;	91	dvo_timing->vsync_off;
92	panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +	92	panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
93	dvo_timing->vsync_pulse_width;	93	dvo_timing->vsync_pulse_width;
94	panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +	94	panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
95	((dvo_timing->vblank_hi << 8) \| dvo_timing->vblank_lo);	95	((dvo_timing->vblank_hi << 8) \| dvo_timing->vblank_lo);
96	panel_fixed_mode->clock = dvo_timing->clock * 10;	96	panel_fixed_mode->clock = dvo_timing->clock * 10;
97	panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;	97	panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
98		98
99	if (dvo_timing->hsync_positive)	99	if (dvo_timing->hsync_positive)
100	panel_fixed_mode->flags \|= DRM_MODE_FLAG_PHSYNC;	100	panel_fixed_mode->flags \|= DRM_MODE_FLAG_PHSYNC;
101	else	101	else
102	panel_fixed_mode->flags \|= DRM_MODE_FLAG_NHSYNC;	102	panel_fixed_mode->flags \|= DRM_MODE_FLAG_NHSYNC;
103		103
104	if (dvo_timing->vsync_positive)	104	if (dvo_timing->vsync_positive)
105	panel_fixed_mode->flags \|= DRM_MODE_FLAG_PVSYNC;	105	panel_fixed_mode->flags \|= DRM_MODE_FLAG_PVSYNC;
106	else	106	else
107	panel_fixed_mode->flags \|= DRM_MODE_FLAG_NVSYNC;	107	panel_fixed_mode->flags \|= DRM_MODE_FLAG_NVSYNC;
108		108
109	/* Some VBTs have bogus h/vtotal values */	109	/* Some VBTs have bogus h/vtotal values */
110	if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)	110	if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
111	panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;	111	panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
112	if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)	112	if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
113	panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;	113	panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
114		114
115	drm_mode_set_name(panel_fixed_mode);	115	drm_mode_set_name(panel_fixed_mode);
116	}	116	}
117		117
118	/* Try to find integrated panel data */	118	/* Try to find integrated panel data */
119	static void	119	static void
120	parse_lfp_panel_data(struct drm_i915_private *dev_priv,	120	parse_lfp_panel_data(struct drm_i915_private *dev_priv,
121	struct bdb_header *bdb)	121	struct bdb_header *bdb)
122	{	122	{
123	struct bdb_lvds_options *lvds_options;	123	struct bdb_lvds_options *lvds_options;
124	struct bdb_lvds_lfp_data *lvds_lfp_data;	124	struct bdb_lvds_lfp_data *lvds_lfp_data;
125	struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;	125	struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
126	struct bdb_lvds_lfp_data_entry *entry;	126	struct bdb_lvds_lfp_data_entry *entry;
127	struct lvds_dvo_timing *dvo_timing;	127	struct lvds_dvo_timing *dvo_timing;
128	struct drm_display_mode *panel_fixed_mode;	128	struct drm_display_mode *panel_fixed_mode;
129	int lfp_data_size, dvo_timing_offset;	129	int lfp_data_size, dvo_timing_offset;
130	int i, temp_downclock;	130	int i, temp_downclock;
131	struct drm_display_mode *temp_mode;	131	struct drm_display_mode *temp_mode;
132		132
133	lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);	133	lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
134	if (!lvds_options)	134	if (!lvds_options)
135	return;	135	return;
136		136
137	dev_priv->lvds_dither = lvds_options->pixel_dither;	137	dev_priv->lvds_dither = lvds_options->pixel_dither;
138	if (lvds_options->panel_type == 0xff)	138	if (lvds_options->panel_type == 0xff)
139	return;	139	return;
140		140
141	panel_type = lvds_options->panel_type;	141	panel_type = lvds_options->panel_type;
142		142
143	lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);	143	lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
144	if (!lvds_lfp_data)	144	if (!lvds_lfp_data)
145	return;	145	return;
146		146
147	lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);	147	lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
148	if (!lvds_lfp_data_ptrs)	148	if (!lvds_lfp_data_ptrs)
149	return;	149	return;
150		150
151	dev_priv->lvds_vbt = 1;	151	dev_priv->lvds_vbt = 1;
152		152
153	lfp_data_size = lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -	153	lfp_data_size = lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
154	lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;	154	lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
155	entry = (struct bdb_lvds_lfp_data_entry *)	155	entry = (struct bdb_lvds_lfp_data_entry *)
156	((uint8_t )lvds_lfp_data->data + (lfp_data_size	156	((uint8_t )lvds_lfp_data->data + (lfp_data_size
157	lvds_options->panel_type));	157	lvds_options->panel_type));
158	dvo_timing_offset = lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -	158	dvo_timing_offset = lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
159	lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;	159	lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
160		160
161	/*	161	/*
162	* the size of fp_timing varies on the different platform.	162	* the size of fp_timing varies on the different platform.
163	* So calculate the DVO timing relative offset in LVDS data	163	* So calculate the DVO timing relative offset in LVDS data
164	* entry to get the DVO timing entry	164	* entry to get the DVO timing entry
165	*/	165	*/
166	dvo_timing = (struct lvds_dvo_timing *)	166	dvo_timing = (struct lvds_dvo_timing *)
167	((unsigned char *)entry + dvo_timing_offset);	167	((unsigned char *)entry + dvo_timing_offset);
168		168
169	panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);	169	panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
170	if (!panel_fixed_mode)	170	if (!panel_fixed_mode)
171	return;	171	return;
172		172
173	fill_detail_timing_data(panel_fixed_mode, dvo_timing);	173	fill_detail_timing_data(panel_fixed_mode, dvo_timing);
174		174
175	dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;	175	dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;
176		176
177	DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");	177	DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
178	drm_mode_debug_printmodeline(panel_fixed_mode);	178	drm_mode_debug_printmodeline(panel_fixed_mode);
179		179
180	temp_mode = kzalloc(sizeof(*temp_mode), GFP_KERNEL);	180	temp_mode = kzalloc(sizeof(*temp_mode), GFP_KERNEL);
181	temp_downclock = panel_fixed_mode->clock;	181	temp_downclock = panel_fixed_mode->clock;
182	/*	182	/*
183	* enumerate the LVDS panel timing info entry in VBT to check whether	183	* enumerate the LVDS panel timing info entry in VBT to check whether
184	* the LVDS downclock is found.	184	* the LVDS downclock is found.
185	*/	185	*/
186	for (i = 0; i < 16; i++) {	186	for (i = 0; i < 16; i++) {
187	entry = (struct bdb_lvds_lfp_data_entry *)	187	entry = (struct bdb_lvds_lfp_data_entry *)
188	((uint8_t )lvds_lfp_data->data + (lfp_data_size i));	188	((uint8_t )lvds_lfp_data->data + (lfp_data_size i));
189	dvo_timing = (struct lvds_dvo_timing *)	189	dvo_timing = (struct lvds_dvo_timing *)
190	((unsigned char *)entry + dvo_timing_offset);	190	((unsigned char *)entry + dvo_timing_offset);
191		191
192	fill_detail_timing_data(temp_mode, dvo_timing);	192	fill_detail_timing_data(temp_mode, dvo_timing);
193		193
194	if (temp_mode->hdisplay == panel_fixed_mode->hdisplay &&	194	if (temp_mode->hdisplay == panel_fixed_mode->hdisplay &&
195	temp_mode->hsync_start == panel_fixed_mode->hsync_start &&	195	temp_mode->hsync_start == panel_fixed_mode->hsync_start &&
196	temp_mode->hsync_end == panel_fixed_mode->hsync_end &&	196	temp_mode->hsync_end == panel_fixed_mode->hsync_end &&
197	temp_mode->htotal == panel_fixed_mode->htotal &&	197	temp_mode->htotal == panel_fixed_mode->htotal &&
198	temp_mode->vdisplay == panel_fixed_mode->vdisplay &&	198	temp_mode->vdisplay == panel_fixed_mode->vdisplay &&
199	temp_mode->vsync_start == panel_fixed_mode->vsync_start &&	199	temp_mode->vsync_start == panel_fixed_mode->vsync_start &&
200	temp_mode->vsync_end == panel_fixed_mode->vsync_end &&	200	temp_mode->vsync_end == panel_fixed_mode->vsync_end &&
201	temp_mode->vtotal == panel_fixed_mode->vtotal &&	201	temp_mode->vtotal == panel_fixed_mode->vtotal &&
202	temp_mode->clock < temp_downclock) {	202	temp_mode->clock < temp_downclock) {
203	/*	203	/*
204	* downclock is already found. But we expect	204	* downclock is already found. But we expect
205	* to find the lower downclock.	205	* to find the lower downclock.
206	*/	206	*/
207	temp_downclock = temp_mode->clock;	207	temp_downclock = temp_mode->clock;
208	}	208	}
209	/* clear it to zero */	209	/* clear it to zero */
210	memset(temp_mode, 0, sizeof(*temp_mode));	210	memset(temp_mode, 0, sizeof(*temp_mode));
211	}	211	}
212	kfree(temp_mode);	212	kfree(temp_mode);
213	if (temp_downclock < panel_fixed_mode->clock &&	213	if (temp_downclock < panel_fixed_mode->clock &&
214	i915_lvds_downclock) {	214	i915_lvds_downclock) {
215	dev_priv->lvds_downclock_avail = 1;	215	dev_priv->lvds_downclock_avail = 1;
216	dev_priv->lvds_downclock = temp_downclock;	216	dev_priv->lvds_downclock = temp_downclock;
217	DRM_DEBUG_KMS("LVDS downclock is found in VBT. ",	217	DRM_DEBUG_KMS("LVDS downclock is found in VBT. "
218	"Normal Clock %dKHz, downclock %dKHz\n",	218	"Normal Clock %dKHz, downclock %dKHz\n",
219	temp_downclock, panel_fixed_mode->clock);	219	temp_downclock, panel_fixed_mode->clock);
220	}	220	}
221	return;	221	return;
222	}	222	}
223		223
224	/* Try to find sdvo panel data */	224	/* Try to find sdvo panel data */
225	static void	225	static void
226	parse_sdvo_panel_data(struct drm_i915_private *dev_priv,	226	parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
227	struct bdb_header *bdb)	227	struct bdb_header *bdb)
228	{	228	{
229	struct lvds_dvo_timing *dvo_timing;	229	struct lvds_dvo_timing *dvo_timing;
230	struct drm_display_mode *panel_fixed_mode;	230	struct drm_display_mode *panel_fixed_mode;
231	int index;	231	int index;
232		232
233	index = i915_vbt_sdvo_panel_type;	233	index = i915_vbt_sdvo_panel_type;
234	if (index == -1) {	234	if (index == -1) {
235	struct bdb_sdvo_lvds_options *sdvo_lvds_options;	235	struct bdb_sdvo_lvds_options *sdvo_lvds_options;
236		236
237	sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);	237	sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
238	if (!sdvo_lvds_options)	238	if (!sdvo_lvds_options)
239	return;	239	return;
240		240
241	index = sdvo_lvds_options->panel_type;	241	index = sdvo_lvds_options->panel_type;
242	}	242	}
243		243
244	dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);	244	dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
245	if (!dvo_timing)	245	if (!dvo_timing)
246	return;	246	return;
247		247
248	panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);	248	panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
249	if (!panel_fixed_mode)	249	if (!panel_fixed_mode)
250	return;	250	return;
251		251
252	fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);	252	fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);
253		253
254	dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode;	254	dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode;
255		255
256	DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");	256	DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
257	drm_mode_debug_printmodeline(panel_fixed_mode);	257	drm_mode_debug_printmodeline(panel_fixed_mode);
258	}	258	}
259		259
260	static int intel_bios_ssc_frequency(struct drm_device *dev,	260	static int intel_bios_ssc_frequency(struct drm_device *dev,
261	bool alternate)	261	bool alternate)
262	{	262	{
263	switch (INTEL_INFO(dev)->gen) {	263	switch (INTEL_INFO(dev)->gen) {
264	case 2:	264	case 2:
265	return alternate ? 66 : 48;	265	return alternate ? 66 : 48;
266	case 3:	266	case 3:
267	case 4:	267	case 4:
268	return alternate ? 100 : 96;	268	return alternate ? 100 : 96;
269	default:	269	default:
270	return alternate ? 100 : 120;	270	return alternate ? 100 : 120;
271	}	271	}
272	}	272	}
273		273
274	static void	274	static void
275	parse_general_features(struct drm_i915_private *dev_priv,	275	parse_general_features(struct drm_i915_private *dev_priv,
276	struct bdb_header *bdb)	276	struct bdb_header *bdb)
277	{	277	{
278	struct drm_device *dev = dev_priv->dev;	278	struct drm_device *dev = dev_priv->dev;
279	struct bdb_general_features *general;	279	struct bdb_general_features *general;
280		280
281	general = find_section(bdb, BDB_GENERAL_FEATURES);	281	general = find_section(bdb, BDB_GENERAL_FEATURES);
282	if (general) {	282	if (general) {
283	dev_priv->int_tv_support = general->int_tv_support;	283	dev_priv->int_tv_support = general->int_tv_support;
284	dev_priv->int_crt_support = general->int_crt_support;	284	dev_priv->int_crt_support = general->int_crt_support;
285	dev_priv->lvds_use_ssc = general->enable_ssc;	285	dev_priv->lvds_use_ssc = general->enable_ssc;
286	dev_priv->lvds_ssc_freq =	286	dev_priv->lvds_ssc_freq =
287	intel_bios_ssc_frequency(dev, general->ssc_freq);	287	intel_bios_ssc_frequency(dev, general->ssc_freq);
288	}	288	}
289	}	289	}
290		290
291	static void	291	static void
292	parse_general_definitions(struct drm_i915_private *dev_priv,	292	parse_general_definitions(struct drm_i915_private *dev_priv,
293	struct bdb_header *bdb)	293	struct bdb_header *bdb)
294	{	294	{
295	struct bdb_general_definitions *general;	295	struct bdb_general_definitions *general;
296		296
297	general = find_section(bdb, BDB_GENERAL_DEFINITIONS);	297	general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
298	if (general) {	298	if (general) {
299	u16 block_size = get_blocksize(general);	299	u16 block_size = get_blocksize(general);
300	if (block_size >= sizeof(*general)) {	300	if (block_size >= sizeof(*general)) {
301	int bus_pin = general->crt_ddc_gmbus_pin;	301	int bus_pin = general->crt_ddc_gmbus_pin;
302	DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);	302	DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
303	if (bus_pin >= 1 && bus_pin <= 6)	303	if (bus_pin >= 1 && bus_pin <= 6)
304	dev_priv->crt_ddc_pin = bus_pin;	304	dev_priv->crt_ddc_pin = bus_pin;
305	} else {	305	} else {
306	DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",	306	DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
307	block_size);	307	block_size);
308	}	308	}
309	}	309	}
310	}	310	}
311		311
312	static void	312	static void
313	parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,	313	parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
314	struct bdb_header *bdb)	314	struct bdb_header *bdb)
315	{	315	{
316	struct sdvo_device_mapping *p_mapping;	316	struct sdvo_device_mapping *p_mapping;
317	struct bdb_general_definitions *p_defs;	317	struct bdb_general_definitions *p_defs;
318	struct child_device_config *p_child;	318	struct child_device_config *p_child;
319	int i, child_device_num, count;	319	int i, child_device_num, count;
320	u16 block_size;	320	u16 block_size;
321		321
322	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);	322	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
323	if (!p_defs) {	323	if (!p_defs) {
324	DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");	324	DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
325	return;	325	return;
326	}	326	}
327	/* judge whether the size of child device meets the requirements.	327	/* judge whether the size of child device meets the requirements.
328	* If the child device size obtained from general definition block	328	* If the child device size obtained from general definition block
329	* is different with sizeof(struct child_device_config), skip the	329	* is different with sizeof(struct child_device_config), skip the
330	* parsing of sdvo device info	330	* parsing of sdvo device info
331	*/	331	*/
332	if (p_defs->child_dev_size != sizeof(*p_child)) {	332	if (p_defs->child_dev_size != sizeof(*p_child)) {
333	/* different child dev size . Ignore it */	333	/* different child dev size . Ignore it */
334	DRM_DEBUG_KMS("different child size is found. Invalid.\n");	334	DRM_DEBUG_KMS("different child size is found. Invalid.\n");
335	return;	335	return;
336	}	336	}
337	/* get the block size of general definitions */	337	/* get the block size of general definitions */
338	block_size = get_blocksize(p_defs);	338	block_size = get_blocksize(p_defs);
339	/* get the number of child device */	339	/* get the number of child device */
340	child_device_num = (block_size - sizeof(*p_defs)) /	340	child_device_num = (block_size - sizeof(*p_defs)) /
341	sizeof(*p_child);	341	sizeof(*p_child);
342	count = 0;	342	count = 0;
343	for (i = 0; i < child_device_num; i++) {	343	for (i = 0; i < child_device_num; i++) {
344	p_child = &(p_defs->devices[i]);	344	p_child = &(p_defs->devices[i]);
345	if (!p_child->device_type) {	345	if (!p_child->device_type) {
346	/* skip the device block if device type is invalid */	346	/* skip the device block if device type is invalid */
347	continue;	347	continue;
348	}	348	}
349	if (p_child->slave_addr != SLAVE_ADDR1 &&	349	if (p_child->slave_addr != SLAVE_ADDR1 &&
350	p_child->slave_addr != SLAVE_ADDR2) {	350	p_child->slave_addr != SLAVE_ADDR2) {
351	/*	351	/*
352	* If the slave address is neither 0x70 nor 0x72,	352	* If the slave address is neither 0x70 nor 0x72,
353	* it is not a SDVO device. Skip it.	353	* it is not a SDVO device. Skip it.
354	*/	354	*/
355	continue;	355	continue;
356	}	356	}
357	if (p_child->dvo_port != DEVICE_PORT_DVOB &&	357	if (p_child->dvo_port != DEVICE_PORT_DVOB &&
358	p_child->dvo_port != DEVICE_PORT_DVOC) {	358	p_child->dvo_port != DEVICE_PORT_DVOC) {
359	/* skip the incorrect SDVO port */	359	/* skip the incorrect SDVO port */
360	DRM_DEBUG_KMS("Incorrect SDVO port. Skip it \n");	360	DRM_DEBUG_KMS("Incorrect SDVO port. Skip it \n");
361	continue;	361	continue;
362	}	362	}
363	DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"	363	DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
364	" %s port\n",	364	" %s port\n",
365	p_child->slave_addr,	365	p_child->slave_addr,
366	(p_child->dvo_port == DEVICE_PORT_DVOB) ?	366	(p_child->dvo_port == DEVICE_PORT_DVOB) ?
367	"SDVOB" : "SDVOC");	367	"SDVOB" : "SDVOC");
368	p_mapping = &(dev_priv->sdvo_mappings[p_child->dvo_port - 1]);	368	p_mapping = &(dev_priv->sdvo_mappings[p_child->dvo_port - 1]);
369	if (!p_mapping->initialized) {	369	if (!p_mapping->initialized) {
370	p_mapping->dvo_port = p_child->dvo_port;	370	p_mapping->dvo_port = p_child->dvo_port;
371	p_mapping->slave_addr = p_child->slave_addr;	371	p_mapping->slave_addr = p_child->slave_addr;
372	p_mapping->dvo_wiring = p_child->dvo_wiring;	372	p_mapping->dvo_wiring = p_child->dvo_wiring;
373	p_mapping->ddc_pin = p_child->ddc_pin;	373	p_mapping->ddc_pin = p_child->ddc_pin;
374	p_mapping->i2c_pin = p_child->i2c_pin;	374	p_mapping->i2c_pin = p_child->i2c_pin;
375	p_mapping->i2c_speed = p_child->i2c_speed;	375	p_mapping->i2c_speed = p_child->i2c_speed;
376	p_mapping->initialized = 1;	376	p_mapping->initialized = 1;
377	DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d, i2c_speed=%d\n",	377	DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d, i2c_speed=%d\n",
378	p_mapping->dvo_port,	378	p_mapping->dvo_port,
379	p_mapping->slave_addr,	379	p_mapping->slave_addr,
380	p_mapping->dvo_wiring,	380	p_mapping->dvo_wiring,
381	p_mapping->ddc_pin,	381	p_mapping->ddc_pin,
382	p_mapping->i2c_pin,	382	p_mapping->i2c_pin,
383	p_mapping->i2c_speed);	383	p_mapping->i2c_speed);
384	} else {	384	} else {
385	DRM_DEBUG_KMS("Maybe one SDVO port is shared by "	385	DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
386	"two SDVO device.\n");	386	"two SDVO device.\n");
387	}	387	}
388	if (p_child->slave2_addr) {	388	if (p_child->slave2_addr) {
389	/* Maybe this is a SDVO device with multiple inputs */	389	/* Maybe this is a SDVO device with multiple inputs */
390	/* And the mapping info is not added */	390	/* And the mapping info is not added */
391	DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"	391	DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
392	" is a SDVO device with multiple inputs.\n");	392	" is a SDVO device with multiple inputs.\n");
393	}	393	}
394	count++;	394	count++;
395	}	395	}
396		396
397	if (!count) {	397	if (!count) {
398	/* No SDVO device info is found */	398	/* No SDVO device info is found */
399	DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");	399	DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
400	}	400	}
401	return;	401	return;
402	}	402	}
403		403
404	static void	404	static void
405	parse_driver_features(struct drm_i915_private *dev_priv,	405	parse_driver_features(struct drm_i915_private *dev_priv,
406	struct bdb_header *bdb)	406	struct bdb_header *bdb)
407	{	407	{
408	struct drm_device *dev = dev_priv->dev;	408	struct drm_device *dev = dev_priv->dev;
409	struct bdb_driver_features *driver;	409	struct bdb_driver_features *driver;
410		410
411	driver = find_section(bdb, BDB_DRIVER_FEATURES);	411	driver = find_section(bdb, BDB_DRIVER_FEATURES);
412	if (!driver)	412	if (!driver)
413	return;	413	return;
414		414
415	if (SUPPORTS_EDP(dev) &&	415	if (SUPPORTS_EDP(dev) &&
416	driver->lvds_config == BDB_DRIVER_FEATURE_EDP)	416	driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
417	dev_priv->edp.support = 1;	417	dev_priv->edp.support = 1;
418		418
419	if (driver->dual_frequency)	419	if (driver->dual_frequency)
420	dev_priv->render_reclock_avail = true;	420	dev_priv->render_reclock_avail = true;
421	}	421	}
422		422
423	static void	423	static void
424	parse_edp(struct drm_i915_private dev_priv, struct bdb_header bdb)	424	parse_edp(struct drm_i915_private dev_priv, struct bdb_header bdb)
425	{	425	{
426	struct bdb_edp *edp;	426	struct bdb_edp *edp;
427	struct edp_power_seq *edp_pps;	427	struct edp_power_seq *edp_pps;
428	struct edp_link_params *edp_link_params;	428	struct edp_link_params *edp_link_params;
429		429
430	edp = find_section(bdb, BDB_EDP);	430	edp = find_section(bdb, BDB_EDP);
431	if (!edp) {	431	if (!edp) {
432	if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support) {	432	if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support) {
433	DRM_DEBUG_KMS("No eDP BDB found but eDP panel "	433	DRM_DEBUG_KMS("No eDP BDB found but eDP panel "
434	"supported, assume %dbpp panel color "	434	"supported, assume %dbpp panel color "
435	"depth.\n",	435	"depth.\n",
436	dev_priv->edp.bpp);	436	dev_priv->edp.bpp);
437	}	437	}
438	return;	438	return;
439	}	439	}
440		440
441	switch ((edp->color_depth >> (panel_type * 2)) & 3) {	441	switch ((edp->color_depth >> (panel_type * 2)) & 3) {
442	case EDP_18BPP:	442	case EDP_18BPP:
443	dev_priv->edp.bpp = 18;	443	dev_priv->edp.bpp = 18;
444	break;	444	break;
445	case EDP_24BPP:	445	case EDP_24BPP:
446	dev_priv->edp.bpp = 24;	446	dev_priv->edp.bpp = 24;
447	break;	447	break;
448	case EDP_30BPP:	448	case EDP_30BPP:
449	dev_priv->edp.bpp = 30;	449	dev_priv->edp.bpp = 30;
450	break;	450	break;
451	}	451	}
452		452
453	/* Get the eDP sequencing and link info */	453	/* Get the eDP sequencing and link info */
454	edp_pps = &edp->power_seqs[panel_type];	454	edp_pps = &edp->power_seqs[panel_type];
455	edp_link_params = &edp->link_params[panel_type];	455	edp_link_params = &edp->link_params[panel_type];
456		456
457	dev_priv->edp.pps = *edp_pps;	457	dev_priv->edp.pps = *edp_pps;
458		458
459	dev_priv->edp.rate = edp_link_params->rate ? DP_LINK_BW_2_7 :	459	dev_priv->edp.rate = edp_link_params->rate ? DP_LINK_BW_2_7 :
460	DP_LINK_BW_1_62;	460	DP_LINK_BW_1_62;
461	switch (edp_link_params->lanes) {	461	switch (edp_link_params->lanes) {
462	case 0:	462	case 0:
463	dev_priv->edp.lanes = 1;	463	dev_priv->edp.lanes = 1;
464	break;	464	break;
465	case 1:	465	case 1:
466	dev_priv->edp.lanes = 2;	466	dev_priv->edp.lanes = 2;
467	break;	467	break;
468	case 3:	468	case 3:
469	default:	469	default:
470	dev_priv->edp.lanes = 4;	470	dev_priv->edp.lanes = 4;
471	break;	471	break;
472	}	472	}
473	switch (edp_link_params->preemphasis) {	473	switch (edp_link_params->preemphasis) {
474	case 0:	474	case 0:
475	dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_0;	475	dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
476	break;	476	break;
477	case 1:	477	case 1:
478	dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;	478	dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
479	break;	479	break;
480	case 2:	480	case 2:
481	dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_6;	481	dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
482	break;	482	break;
483	case 3:	483	case 3:
484	dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;	484	dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
485	break;	485	break;
486	}	486	}
487	switch (edp_link_params->vswing) {	487	switch (edp_link_params->vswing) {
488	case 0:	488	case 0:
489	dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_400;	489	dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_400;
490	break;	490	break;
491	case 1:	491	case 1:
492	dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_600;	492	dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_600;
493	break;	493	break;
494	case 2:	494	case 2:
495	dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_800;	495	dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_800;
496	break;	496	break;
497	case 3:	497	case 3:
498	dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_1200;	498	dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_1200;
499	break;	499	break;
500	}	500	}
501	}	501	}
502		502
503	static void	503	static void
504	parse_device_mapping(struct drm_i915_private *dev_priv,	504	parse_device_mapping(struct drm_i915_private *dev_priv,
505	struct bdb_header *bdb)	505	struct bdb_header *bdb)
506	{	506	{
507	struct bdb_general_definitions *p_defs;	507	struct bdb_general_definitions *p_defs;
508	struct child_device_config p_child, child_dev_ptr;	508	struct child_device_config p_child, child_dev_ptr;
509	int i, child_device_num, count;	509	int i, child_device_num, count;
510	u16 block_size;	510	u16 block_size;
511		511
512	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);	512	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
513	if (!p_defs) {	513	if (!p_defs) {
514	DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");	514	DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
515	return;	515	return;
516	}	516	}
517	/* judge whether the size of child device meets the requirements.	517	/* judge whether the size of child device meets the requirements.
518	* If the child device size obtained from general definition block	518	* If the child device size obtained from general definition block
519	* is different with sizeof(struct child_device_config), skip the	519	* is different with sizeof(struct child_device_config), skip the
520	* parsing of sdvo device info	520	* parsing of sdvo device info
521	*/	521	*/
522	if (p_defs->child_dev_size != sizeof(*p_child)) {	522	if (p_defs->child_dev_size != sizeof(*p_child)) {
523	/* different child dev size . Ignore it */	523	/* different child dev size . Ignore it */
524	DRM_DEBUG_KMS("different child size is found. Invalid.\n");	524	DRM_DEBUG_KMS("different child size is found. Invalid.\n");
525	return;	525	return;
526	}	526	}
527	/* get the block size of general definitions */	527	/* get the block size of general definitions */
528	block_size = get_blocksize(p_defs);	528	block_size = get_blocksize(p_defs);
529	/* get the number of child device */	529	/* get the number of child device */
530	child_device_num = (block_size - sizeof(*p_defs)) /	530	child_device_num = (block_size - sizeof(*p_defs)) /
531	sizeof(*p_child);	531	sizeof(*p_child);
532	count = 0;	532	count = 0;
533	/* get the number of child device that is present */	533	/* get the number of child device that is present */
534	for (i = 0; i < child_device_num; i++) {	534	for (i = 0; i < child_device_num; i++) {
535	p_child = &(p_defs->devices[i]);	535	p_child = &(p_defs->devices[i]);
536	if (!p_child->device_type) {	536	if (!p_child->device_type) {
537	/* skip the device block if device type is invalid */	537	/* skip the device block if device type is invalid */
538	continue;	538	continue;
539	}	539	}
540	count++;	540	count++;
541	}	541	}
542	if (!count) {	542	if (!count) {
543	DRM_DEBUG_KMS("no child dev is parsed from VBT \n");	543	DRM_DEBUG_KMS("no child dev is parsed from VBT \n");
544	return;	544	return;
545	}	545	}
546	dev_priv->child_dev = kzalloc(sizeof(p_child) count, GFP_KERNEL);	546	dev_priv->child_dev = kzalloc(sizeof(p_child) count, GFP_KERNEL);
547	if (!dev_priv->child_dev) {	547	if (!dev_priv->child_dev) {
548	DRM_DEBUG_KMS("No memory space for child device\n");	548	DRM_DEBUG_KMS("No memory space for child device\n");
549	return;	549	return;
550	}	550	}
551		551
552	dev_priv->child_dev_num = count;	552	dev_priv->child_dev_num = count;
553	count = 0;	553	count = 0;
554	for (i = 0; i < child_device_num; i++) {	554	for (i = 0; i < child_device_num; i++) {
555	p_child = &(p_defs->devices[i]);	555	p_child = &(p_defs->devices[i]);
556	if (!p_child->device_type) {	556	if (!p_child->device_type) {
557	/* skip the device block if device type is invalid */	557	/* skip the device block if device type is invalid */
558	continue;	558	continue;
559	}	559	}
560	child_dev_ptr = dev_priv->child_dev + count;	560	child_dev_ptr = dev_priv->child_dev + count;
561	count++;	561	count++;
562	memcpy((void )child_dev_ptr, (void )p_child,	562	memcpy((void )child_dev_ptr, (void )p_child,
563	sizeof(*p_child));	563	sizeof(*p_child));
564	}	564	}
565	return;	565	return;
566	}	566	}
567		567
568	static void	568	static void
569	init_vbt_defaults(struct drm_i915_private *dev_priv)	569	init_vbt_defaults(struct drm_i915_private *dev_priv)
570	{	570	{
571	struct drm_device *dev = dev_priv->dev;	571	struct drm_device *dev = dev_priv->dev;
572		572
573	dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC;	573	dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC;
574		574
575	/* LFP panel data */	575	/* LFP panel data */
576	dev_priv->lvds_dither = 1;	576	dev_priv->lvds_dither = 1;
577	dev_priv->lvds_vbt = 0;	577	dev_priv->lvds_vbt = 0;
578		578
579	/* SDVO panel data */	579	/* SDVO panel data */
580	dev_priv->sdvo_lvds_vbt_mode = NULL;	580	dev_priv->sdvo_lvds_vbt_mode = NULL;
581		581
582	/* general features */	582	/* general features */
583	dev_priv->int_tv_support = 1;	583	dev_priv->int_tv_support = 1;
584	dev_priv->int_crt_support = 1;	584	dev_priv->int_crt_support = 1;
585		585
586	/* Default to using SSC */	586	/* Default to using SSC */
587	dev_priv->lvds_use_ssc = 1;	587	dev_priv->lvds_use_ssc = 1;
588	dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);	588	dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
589	DRM_DEBUG("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);	589	DRM_DEBUG("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
590		590
591	/* eDP data */	591	/* eDP data */
592	dev_priv->edp.bpp = 18;	592	dev_priv->edp.bpp = 18;
593	}	593	}
594		594
595	/**	595	/**
596	* intel_parse_bios - find VBT and initialize settings from the BIOS	596	* intel_parse_bios - find VBT and initialize settings from the BIOS
597	* @dev: DRM device	597	* @dev: DRM device
598	*	598	*
599	* Loads the Video BIOS and checks that the VBT exists. Sets scratch registers	599	* Loads the Video BIOS and checks that the VBT exists. Sets scratch registers
600	* to appropriate values.	600	* to appropriate values.
601	*	601	*
602	* Returns 0 on success, nonzero on failure.	602	* Returns 0 on success, nonzero on failure.
603	*/	603	*/
604	bool	604	bool
605	intel_parse_bios(struct drm_device *dev)	605	intel_parse_bios(struct drm_device *dev)
606	{	606	{
607	struct drm_i915_private *dev_priv = dev->dev_private;	607	struct drm_i915_private *dev_priv = dev->dev_private;
608	struct pci_dev *pdev = dev->pdev;	608	struct pci_dev *pdev = dev->pdev;
609	struct bdb_header *bdb = NULL;	609	struct bdb_header *bdb = NULL;
610	u8 __iomem *bios = NULL;	610	u8 __iomem *bios = NULL;
611		611
612	init_vbt_defaults(dev_priv);	612	init_vbt_defaults(dev_priv);
613		613
614	/* XXX Should this validation be moved to intel_opregion.c? */	614	/* XXX Should this validation be moved to intel_opregion.c? */
615	if (dev_priv->opregion.vbt) {	615	if (dev_priv->opregion.vbt) {
616	struct vbt_header *vbt = dev_priv->opregion.vbt;	616	struct vbt_header *vbt = dev_priv->opregion.vbt;
617	if (memcmp(vbt->signature, "$VBT", 4) == 0) {	617	if (memcmp(vbt->signature, "$VBT", 4) == 0) {
618	DRM_DEBUG_DRIVER("Using VBT from OpRegion: %20s\n",	618	DRM_DEBUG_DRIVER("Using VBT from OpRegion: %20s\n",
619	vbt->signature);	619	vbt->signature);
620	bdb = (struct bdb_header )((char )vbt + vbt->bdb_offset);	620	bdb = (struct bdb_header )((char )vbt + vbt->bdb_offset);
621	} else	621	} else
622	dev_priv->opregion.vbt = NULL;	622	dev_priv->opregion.vbt = NULL;
623	}	623	}
624		624
625	if (bdb == NULL) {	625	if (bdb == NULL) {
626	struct vbt_header *vbt = NULL;	626	struct vbt_header *vbt = NULL;
627	size_t size;	627	size_t size;
628	int i;	628	int i;
629		629
630	bios = pci_map_rom(pdev, &size);	630	bios = pci_map_rom(pdev, &size);
631	if (!bios)	631	if (!bios)
632	return -1;	632	return -1;
633		633
634	/* Scour memory looking for the VBT signature */	634	/* Scour memory looking for the VBT signature */
635	for (i = 0; i + 4 < size; i++) {	635	for (i = 0; i + 4 < size; i++) {
636	if (!memcmp(bios + i, "$VBT", 4)) {	636	if (!memcmp(bios + i, "$VBT", 4)) {
637	vbt = (struct vbt_header *)(bios + i);	637	vbt = (struct vbt_header *)(bios + i);
638	break;	638	break;
639	}	639	}
640	}	640	}
641		641
642	if (!vbt) {	642	if (!vbt) {
643	DRM_ERROR("VBT signature missing\n");	643	DRM_ERROR("VBT signature missing\n");
644	pci_unmap_rom(pdev, bios);	644	pci_unmap_rom(pdev, bios);
645	return -1;	645	return -1;
646	}	646	}
647		647
648	bdb = (struct bdb_header *)(bios + i + vbt->bdb_offset);	648	bdb = (struct bdb_header *)(bios + i + vbt->bdb_offset);
649	}	649	}
650		650
651	/* Grab useful general definitions */	651	/* Grab useful general definitions */
652	parse_general_features(dev_priv, bdb);	652	parse_general_features(dev_priv, bdb);
653	parse_general_definitions(dev_priv, bdb);	653	parse_general_definitions(dev_priv, bdb);
654	parse_lfp_panel_data(dev_priv, bdb);	654	parse_lfp_panel_data(dev_priv, bdb);
655	parse_sdvo_panel_data(dev_priv, bdb);	655	parse_sdvo_panel_data(dev_priv, bdb);
656	parse_sdvo_device_mapping(dev_priv, bdb);	656	parse_sdvo_device_mapping(dev_priv, bdb);
657	parse_device_mapping(dev_priv, bdb);	657	parse_device_mapping(dev_priv, bdb);
658	parse_driver_features(dev_priv, bdb);	658	parse_driver_features(dev_priv, bdb);
659	parse_edp(dev_priv, bdb);	659	parse_edp(dev_priv, bdb);
660		660
661	if (bios)	661	if (bios)
662	pci_unmap_rom(pdev, bios);	662	pci_unmap_rom(pdev, bios);
663		663
664	return 0;	664	return 0;
665	}	665	}
666		666
667	/* Ensure that vital registers have been initialised, even if the BIOS	667	/* Ensure that vital registers have been initialised, even if the BIOS
668	* is absent or just failing to do its job.	668	* is absent or just failing to do its job.
669	*/	669	*/
670	void intel_setup_bios(struct drm_device *dev)	670	void intel_setup_bios(struct drm_device *dev)
671	{	671	{
672	struct drm_i915_private *dev_priv = dev->dev_private;	672	struct drm_i915_private *dev_priv = dev->dev_private;
673		673
674	/* Set the Panel Power On/Off timings if uninitialized. */	674	/* Set the Panel Power On/Off timings if uninitialized. */
675	if ((I915_READ(PP_ON_DELAYS) == 0) && (I915_READ(PP_OFF_DELAYS) == 0)) {	675	if ((I915_READ(PP_ON_DELAYS) == 0) && (I915_READ(PP_OFF_DELAYS) == 0)) {
676	/* Set T2 to 40ms and T5 to 200ms */	676	/* Set T2 to 40ms and T5 to 200ms */
677	I915_WRITE(PP_ON_DELAYS, 0x019007d0);	677	I915_WRITE(PP_ON_DELAYS, 0x019007d0);
678		678
679	/* Set T3 to 35ms and Tx to 200ms */	679	/* Set T3 to 35ms and Tx to 200ms */
680	I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);	680	I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);
681	}	681	}
682	}	682	}
683		683

drivers/gpu/drm/i915/intel_display.c

Diff comments View file @ bbb0aef

1	/*	1	/*
2	* Copyright © 2006-2007 Intel Corporation	2	* Copyright © 2006-2007 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.	21	* DEALINGS IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt <eric@anholt.net>	24	* Eric Anholt <eric@anholt.net>
25	*/	25	*/
26		26
27	#include <linux/module.h>	27	#include <linux/module.h>
28	#include <linux/input.h>	28	#include <linux/input.h>
29	#include <linux/i2c.h>	29	#include <linux/i2c.h>
30	#include <linux/kernel.h>	30	#include <linux/kernel.h>
31	#include <linux/slab.h>	31	#include <linux/slab.h>
32	#include <linux/vgaarb.h>	32	#include <linux/vgaarb.h>
33	#include "drmP.h"	33	#include "drmP.h"
34	#include "intel_drv.h"	34	#include "intel_drv.h"
35	#include "i915_drm.h"	35	#include "i915_drm.h"
36	#include "i915_drv.h"	36	#include "i915_drv.h"
37	#include "i915_trace.h"	37	#include "i915_trace.h"
38	#include "drm_dp_helper.h"	38	#include "drm_dp_helper.h"
39		39
40	#include "drm_crtc_helper.h"	40	#include "drm_crtc_helper.h"
41		41
42	#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))	42	#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43		43
44	bool intel_pipe_has_type (struct drm_crtc *crtc, int type);	44	bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45	static void intel_update_watermarks(struct drm_device *dev);	45	static void intel_update_watermarks(struct drm_device *dev);
46	static void intel_increase_pllclock(struct drm_crtc *crtc);	46	static void intel_increase_pllclock(struct drm_crtc *crtc);
47	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);	47	static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48		48
49	typedef struct {	49	typedef struct {
50	/* given values */	50	/* given values */
51	int n;	51	int n;
52	int m1, m2;	52	int m1, m2;
53	int p1, p2;	53	int p1, p2;
54	/* derived values */	54	/* derived values */
55	int dot;	55	int dot;
56	int vco;	56	int vco;
57	int m;	57	int m;
58	int p;	58	int p;
59	} intel_clock_t;	59	} intel_clock_t;
60		60
61	typedef struct {	61	typedef struct {
62	int min, max;	62	int min, max;
63	} intel_range_t;	63	} intel_range_t;
64		64
65	typedef struct {	65	typedef struct {
66	int dot_limit;	66	int dot_limit;
67	int p2_slow, p2_fast;	67	int p2_slow, p2_fast;
68	} intel_p2_t;	68	} intel_p2_t;
69		69
70	#define INTEL_P2_NUM 2	70	#define INTEL_P2_NUM 2
71	typedef struct intel_limit intel_limit_t;	71	typedef struct intel_limit intel_limit_t;
72	struct intel_limit {	72	struct intel_limit {
73	intel_range_t dot, vco, n, m, m1, m2, p, p1;	73	intel_range_t dot, vco, n, m, m1, m2, p, p1;
74	intel_p2_t p2;	74	intel_p2_t p2;
75	bool (* find_pll)(const intel_limit_t , struct drm_crtc ,	75	bool (* find_pll)(const intel_limit_t , struct drm_crtc ,
76	int, int, intel_clock_t *);	76	int, int, intel_clock_t *);
77	};	77	};
78		78
79	#define I8XX_DOT_MIN 25000	79	#define I8XX_DOT_MIN 25000
80	#define I8XX_DOT_MAX 350000	80	#define I8XX_DOT_MAX 350000
81	#define I8XX_VCO_MIN 930000	81	#define I8XX_VCO_MIN 930000
82	#define I8XX_VCO_MAX 1400000	82	#define I8XX_VCO_MAX 1400000
83	#define I8XX_N_MIN 3	83	#define I8XX_N_MIN 3
84	#define I8XX_N_MAX 16	84	#define I8XX_N_MAX 16
85	#define I8XX_M_MIN 96	85	#define I8XX_M_MIN 96
86	#define I8XX_M_MAX 140	86	#define I8XX_M_MAX 140
87	#define I8XX_M1_MIN 18	87	#define I8XX_M1_MIN 18
88	#define I8XX_M1_MAX 26	88	#define I8XX_M1_MAX 26
89	#define I8XX_M2_MIN 6	89	#define I8XX_M2_MIN 6
90	#define I8XX_M2_MAX 16	90	#define I8XX_M2_MAX 16
91	#define I8XX_P_MIN 4	91	#define I8XX_P_MIN 4
92	#define I8XX_P_MAX 128	92	#define I8XX_P_MAX 128
93	#define I8XX_P1_MIN 2	93	#define I8XX_P1_MIN 2
94	#define I8XX_P1_MAX 33	94	#define I8XX_P1_MAX 33
95	#define I8XX_P1_LVDS_MIN 1	95	#define I8XX_P1_LVDS_MIN 1
96	#define I8XX_P1_LVDS_MAX 6	96	#define I8XX_P1_LVDS_MAX 6
97	#define I8XX_P2_SLOW 4	97	#define I8XX_P2_SLOW 4
98	#define I8XX_P2_FAST 2	98	#define I8XX_P2_FAST 2
99	#define I8XX_P2_LVDS_SLOW 14	99	#define I8XX_P2_LVDS_SLOW 14
100	#define I8XX_P2_LVDS_FAST 7	100	#define I8XX_P2_LVDS_FAST 7
101	#define I8XX_P2_SLOW_LIMIT 165000	101	#define I8XX_P2_SLOW_LIMIT 165000
102		102
103	#define I9XX_DOT_MIN 20000	103	#define I9XX_DOT_MIN 20000
104	#define I9XX_DOT_MAX 400000	104	#define I9XX_DOT_MAX 400000
105	#define I9XX_VCO_MIN 1400000	105	#define I9XX_VCO_MIN 1400000
106	#define I9XX_VCO_MAX 2800000	106	#define I9XX_VCO_MAX 2800000
107	#define PINEVIEW_VCO_MIN 1700000	107	#define PINEVIEW_VCO_MIN 1700000
108	#define PINEVIEW_VCO_MAX 3500000	108	#define PINEVIEW_VCO_MAX 3500000
109	#define I9XX_N_MIN 1	109	#define I9XX_N_MIN 1
110	#define I9XX_N_MAX 6	110	#define I9XX_N_MAX 6
111	/* Pineview's Ncounter is a ring counter */	111	/* Pineview's Ncounter is a ring counter */
112	#define PINEVIEW_N_MIN 3	112	#define PINEVIEW_N_MIN 3
113	#define PINEVIEW_N_MAX 6	113	#define PINEVIEW_N_MAX 6
114	#define I9XX_M_MIN 70	114	#define I9XX_M_MIN 70
115	#define I9XX_M_MAX 120	115	#define I9XX_M_MAX 120
116	#define PINEVIEW_M_MIN 2	116	#define PINEVIEW_M_MIN 2
117	#define PINEVIEW_M_MAX 256	117	#define PINEVIEW_M_MAX 256
118	#define I9XX_M1_MIN 10	118	#define I9XX_M1_MIN 10
119	#define I9XX_M1_MAX 22	119	#define I9XX_M1_MAX 22
120	#define I9XX_M2_MIN 5	120	#define I9XX_M2_MIN 5
121	#define I9XX_M2_MAX 9	121	#define I9XX_M2_MAX 9
122	/* Pineview M1 is reserved, and must be 0 */	122	/* Pineview M1 is reserved, and must be 0 */
123	#define PINEVIEW_M1_MIN 0	123	#define PINEVIEW_M1_MIN 0
124	#define PINEVIEW_M1_MAX 0	124	#define PINEVIEW_M1_MAX 0
125	#define PINEVIEW_M2_MIN 0	125	#define PINEVIEW_M2_MIN 0
126	#define PINEVIEW_M2_MAX 254	126	#define PINEVIEW_M2_MAX 254
127	#define I9XX_P_SDVO_DAC_MIN 5	127	#define I9XX_P_SDVO_DAC_MIN 5
128	#define I9XX_P_SDVO_DAC_MAX 80	128	#define I9XX_P_SDVO_DAC_MAX 80
129	#define I9XX_P_LVDS_MIN 7	129	#define I9XX_P_LVDS_MIN 7
130	#define I9XX_P_LVDS_MAX 98	130	#define I9XX_P_LVDS_MAX 98
131	#define PINEVIEW_P_LVDS_MIN 7	131	#define PINEVIEW_P_LVDS_MIN 7
132	#define PINEVIEW_P_LVDS_MAX 112	132	#define PINEVIEW_P_LVDS_MAX 112
133	#define I9XX_P1_MIN 1	133	#define I9XX_P1_MIN 1
134	#define I9XX_P1_MAX 8	134	#define I9XX_P1_MAX 8
135	#define I9XX_P2_SDVO_DAC_SLOW 10	135	#define I9XX_P2_SDVO_DAC_SLOW 10
136	#define I9XX_P2_SDVO_DAC_FAST 5	136	#define I9XX_P2_SDVO_DAC_FAST 5
137	#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000	137	#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138	#define I9XX_P2_LVDS_SLOW 14	138	#define I9XX_P2_LVDS_SLOW 14
139	#define I9XX_P2_LVDS_FAST 7	139	#define I9XX_P2_LVDS_FAST 7
140	#define I9XX_P2_LVDS_SLOW_LIMIT 112000	140	#define I9XX_P2_LVDS_SLOW_LIMIT 112000
141		141
142	/The parameter is for SDVO on G4x platform/	142	/The parameter is for SDVO on G4x platform/
143	#define G4X_DOT_SDVO_MIN 25000	143	#define G4X_DOT_SDVO_MIN 25000
144	#define G4X_DOT_SDVO_MAX 270000	144	#define G4X_DOT_SDVO_MAX 270000
145	#define G4X_VCO_MIN 1750000	145	#define G4X_VCO_MIN 1750000
146	#define G4X_VCO_MAX 3500000	146	#define G4X_VCO_MAX 3500000
147	#define G4X_N_SDVO_MIN 1	147	#define G4X_N_SDVO_MIN 1
148	#define G4X_N_SDVO_MAX 4	148	#define G4X_N_SDVO_MAX 4
149	#define G4X_M_SDVO_MIN 104	149	#define G4X_M_SDVO_MIN 104
150	#define G4X_M_SDVO_MAX 138	150	#define G4X_M_SDVO_MAX 138
151	#define G4X_M1_SDVO_MIN 17	151	#define G4X_M1_SDVO_MIN 17
152	#define G4X_M1_SDVO_MAX 23	152	#define G4X_M1_SDVO_MAX 23
153	#define G4X_M2_SDVO_MIN 5	153	#define G4X_M2_SDVO_MIN 5
154	#define G4X_M2_SDVO_MAX 11	154	#define G4X_M2_SDVO_MAX 11
155	#define G4X_P_SDVO_MIN 10	155	#define G4X_P_SDVO_MIN 10
156	#define G4X_P_SDVO_MAX 30	156	#define G4X_P_SDVO_MAX 30
157	#define G4X_P1_SDVO_MIN 1	157	#define G4X_P1_SDVO_MIN 1
158	#define G4X_P1_SDVO_MAX 3	158	#define G4X_P1_SDVO_MAX 3
159	#define G4X_P2_SDVO_SLOW 10	159	#define G4X_P2_SDVO_SLOW 10
160	#define G4X_P2_SDVO_FAST 10	160	#define G4X_P2_SDVO_FAST 10
161	#define G4X_P2_SDVO_LIMIT 270000	161	#define G4X_P2_SDVO_LIMIT 270000
162		162
163	/The parameter is for HDMI_DAC on G4x platform/	163	/The parameter is for HDMI_DAC on G4x platform/
164	#define G4X_DOT_HDMI_DAC_MIN 22000	164	#define G4X_DOT_HDMI_DAC_MIN 22000
165	#define G4X_DOT_HDMI_DAC_MAX 400000	165	#define G4X_DOT_HDMI_DAC_MAX 400000
166	#define G4X_N_HDMI_DAC_MIN 1	166	#define G4X_N_HDMI_DAC_MIN 1
167	#define G4X_N_HDMI_DAC_MAX 4	167	#define G4X_N_HDMI_DAC_MAX 4
168	#define G4X_M_HDMI_DAC_MIN 104	168	#define G4X_M_HDMI_DAC_MIN 104
169	#define G4X_M_HDMI_DAC_MAX 138	169	#define G4X_M_HDMI_DAC_MAX 138
170	#define G4X_M1_HDMI_DAC_MIN 16	170	#define G4X_M1_HDMI_DAC_MIN 16
171	#define G4X_M1_HDMI_DAC_MAX 23	171	#define G4X_M1_HDMI_DAC_MAX 23
172	#define G4X_M2_HDMI_DAC_MIN 5	172	#define G4X_M2_HDMI_DAC_MIN 5
173	#define G4X_M2_HDMI_DAC_MAX 11	173	#define G4X_M2_HDMI_DAC_MAX 11
174	#define G4X_P_HDMI_DAC_MIN 5	174	#define G4X_P_HDMI_DAC_MIN 5
175	#define G4X_P_HDMI_DAC_MAX 80	175	#define G4X_P_HDMI_DAC_MAX 80
176	#define G4X_P1_HDMI_DAC_MIN 1	176	#define G4X_P1_HDMI_DAC_MIN 1
177	#define G4X_P1_HDMI_DAC_MAX 8	177	#define G4X_P1_HDMI_DAC_MAX 8
178	#define G4X_P2_HDMI_DAC_SLOW 10	178	#define G4X_P2_HDMI_DAC_SLOW 10
179	#define G4X_P2_HDMI_DAC_FAST 5	179	#define G4X_P2_HDMI_DAC_FAST 5
180	#define G4X_P2_HDMI_DAC_LIMIT 165000	180	#define G4X_P2_HDMI_DAC_LIMIT 165000
181		181
182	/The parameter is for SINGLE_CHANNEL_LVDS on G4x platform/	182	/The parameter is for SINGLE_CHANNEL_LVDS on G4x platform/
183	#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000	183	#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184	#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000	184	#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185	#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1	185	#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186	#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3	186	#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187	#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104	187	#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188	#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138	188	#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189	#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17	189	#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190	#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23	190	#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191	#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5	191	#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192	#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11	192	#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193	#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28	193	#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194	#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112	194	#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195	#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2	195	#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196	#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8	196	#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197	#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14	197	#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198	#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14	198	#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199	#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0	199	#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200		200
201	/The parameter is for DUAL_CHANNEL_LVDS on G4x platform/	201	/The parameter is for DUAL_CHANNEL_LVDS on G4x platform/
202	#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000	202	#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203	#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000	203	#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204	#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1	204	#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205	#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3	205	#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206	#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104	206	#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207	#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138	207	#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208	#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17	208	#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209	#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23	209	#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210	#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5	210	#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211	#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11	211	#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212	#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14	212	#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213	#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42	213	#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214	#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2	214	#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215	#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6	215	#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216	#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7	216	#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217	#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7	217	#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218	#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0	218	#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219		219
220	/The parameter is for DISPLAY PORT on G4x platform/	220	/The parameter is for DISPLAY PORT on G4x platform/
221	#define G4X_DOT_DISPLAY_PORT_MIN 161670	221	#define G4X_DOT_DISPLAY_PORT_MIN 161670
222	#define G4X_DOT_DISPLAY_PORT_MAX 227000	222	#define G4X_DOT_DISPLAY_PORT_MAX 227000
223	#define G4X_N_DISPLAY_PORT_MIN 1	223	#define G4X_N_DISPLAY_PORT_MIN 1
224	#define G4X_N_DISPLAY_PORT_MAX 2	224	#define G4X_N_DISPLAY_PORT_MAX 2
225	#define G4X_M_DISPLAY_PORT_MIN 97	225	#define G4X_M_DISPLAY_PORT_MIN 97
226	#define G4X_M_DISPLAY_PORT_MAX 108	226	#define G4X_M_DISPLAY_PORT_MAX 108
227	#define G4X_M1_DISPLAY_PORT_MIN 0x10	227	#define G4X_M1_DISPLAY_PORT_MIN 0x10
228	#define G4X_M1_DISPLAY_PORT_MAX 0x12	228	#define G4X_M1_DISPLAY_PORT_MAX 0x12
229	#define G4X_M2_DISPLAY_PORT_MIN 0x05	229	#define G4X_M2_DISPLAY_PORT_MIN 0x05
230	#define G4X_M2_DISPLAY_PORT_MAX 0x06	230	#define G4X_M2_DISPLAY_PORT_MAX 0x06
231	#define G4X_P_DISPLAY_PORT_MIN 10	231	#define G4X_P_DISPLAY_PORT_MIN 10
232	#define G4X_P_DISPLAY_PORT_MAX 20	232	#define G4X_P_DISPLAY_PORT_MAX 20
233	#define G4X_P1_DISPLAY_PORT_MIN 1	233	#define G4X_P1_DISPLAY_PORT_MIN 1
234	#define G4X_P1_DISPLAY_PORT_MAX 2	234	#define G4X_P1_DISPLAY_PORT_MAX 2
235	#define G4X_P2_DISPLAY_PORT_SLOW 10	235	#define G4X_P2_DISPLAY_PORT_SLOW 10
236	#define G4X_P2_DISPLAY_PORT_FAST 10	236	#define G4X_P2_DISPLAY_PORT_FAST 10
237	#define G4X_P2_DISPLAY_PORT_LIMIT 0	237	#define G4X_P2_DISPLAY_PORT_LIMIT 0
238		238
239	/* Ironlake / Sandybridge */	239	/* Ironlake / Sandybridge */
240	/* as we calculate clock using (register_value + 2) for	240	/* as we calculate clock using (register_value + 2) for
241	N/M1/M2, so here the range value for them is (actual_value-2).	241	N/M1/M2, so here the range value for them is (actual_value-2).
242	*/	242	*/
243	#define IRONLAKE_DOT_MIN 25000	243	#define IRONLAKE_DOT_MIN 25000
244	#define IRONLAKE_DOT_MAX 350000	244	#define IRONLAKE_DOT_MAX 350000
245	#define IRONLAKE_VCO_MIN 1760000	245	#define IRONLAKE_VCO_MIN 1760000
246	#define IRONLAKE_VCO_MAX 3510000	246	#define IRONLAKE_VCO_MAX 3510000
247	#define IRONLAKE_M1_MIN 12	247	#define IRONLAKE_M1_MIN 12
248	#define IRONLAKE_M1_MAX 22	248	#define IRONLAKE_M1_MAX 22
249	#define IRONLAKE_M2_MIN 5	249	#define IRONLAKE_M2_MIN 5
250	#define IRONLAKE_M2_MAX 9	250	#define IRONLAKE_M2_MAX 9
251	#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */	251	#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252		252
253	/* We have parameter ranges for different type of outputs. */	253	/* We have parameter ranges for different type of outputs. */
254		254
255	/* DAC & HDMI Refclk 120Mhz */	255	/* DAC & HDMI Refclk 120Mhz */
256	#define IRONLAKE_DAC_N_MIN 1	256	#define IRONLAKE_DAC_N_MIN 1
257	#define IRONLAKE_DAC_N_MAX 5	257	#define IRONLAKE_DAC_N_MAX 5
258	#define IRONLAKE_DAC_M_MIN 79	258	#define IRONLAKE_DAC_M_MIN 79
259	#define IRONLAKE_DAC_M_MAX 127	259	#define IRONLAKE_DAC_M_MAX 127
260	#define IRONLAKE_DAC_P_MIN 5	260	#define IRONLAKE_DAC_P_MIN 5
261	#define IRONLAKE_DAC_P_MAX 80	261	#define IRONLAKE_DAC_P_MAX 80
262	#define IRONLAKE_DAC_P1_MIN 1	262	#define IRONLAKE_DAC_P1_MIN 1
263	#define IRONLAKE_DAC_P1_MAX 8	263	#define IRONLAKE_DAC_P1_MAX 8
264	#define IRONLAKE_DAC_P2_SLOW 10	264	#define IRONLAKE_DAC_P2_SLOW 10
265	#define IRONLAKE_DAC_P2_FAST 5	265	#define IRONLAKE_DAC_P2_FAST 5
266		266
267	/* LVDS single-channel 120Mhz refclk */	267	/* LVDS single-channel 120Mhz refclk */
268	#define IRONLAKE_LVDS_S_N_MIN 1	268	#define IRONLAKE_LVDS_S_N_MIN 1
269	#define IRONLAKE_LVDS_S_N_MAX 3	269	#define IRONLAKE_LVDS_S_N_MAX 3
270	#define IRONLAKE_LVDS_S_M_MIN 79	270	#define IRONLAKE_LVDS_S_M_MIN 79
271	#define IRONLAKE_LVDS_S_M_MAX 118	271	#define IRONLAKE_LVDS_S_M_MAX 118
272	#define IRONLAKE_LVDS_S_P_MIN 28	272	#define IRONLAKE_LVDS_S_P_MIN 28
273	#define IRONLAKE_LVDS_S_P_MAX 112	273	#define IRONLAKE_LVDS_S_P_MAX 112
274	#define IRONLAKE_LVDS_S_P1_MIN 2	274	#define IRONLAKE_LVDS_S_P1_MIN 2
275	#define IRONLAKE_LVDS_S_P1_MAX 8	275	#define IRONLAKE_LVDS_S_P1_MAX 8
276	#define IRONLAKE_LVDS_S_P2_SLOW 14	276	#define IRONLAKE_LVDS_S_P2_SLOW 14
277	#define IRONLAKE_LVDS_S_P2_FAST 14	277	#define IRONLAKE_LVDS_S_P2_FAST 14
278		278
279	/* LVDS dual-channel 120Mhz refclk */	279	/* LVDS dual-channel 120Mhz refclk */
280	#define IRONLAKE_LVDS_D_N_MIN 1	280	#define IRONLAKE_LVDS_D_N_MIN 1
281	#define IRONLAKE_LVDS_D_N_MAX 3	281	#define IRONLAKE_LVDS_D_N_MAX 3
282	#define IRONLAKE_LVDS_D_M_MIN 79	282	#define IRONLAKE_LVDS_D_M_MIN 79
283	#define IRONLAKE_LVDS_D_M_MAX 127	283	#define IRONLAKE_LVDS_D_M_MAX 127
284	#define IRONLAKE_LVDS_D_P_MIN 14	284	#define IRONLAKE_LVDS_D_P_MIN 14
285	#define IRONLAKE_LVDS_D_P_MAX 56	285	#define IRONLAKE_LVDS_D_P_MAX 56
286	#define IRONLAKE_LVDS_D_P1_MIN 2	286	#define IRONLAKE_LVDS_D_P1_MIN 2
287	#define IRONLAKE_LVDS_D_P1_MAX 8	287	#define IRONLAKE_LVDS_D_P1_MAX 8
288	#define IRONLAKE_LVDS_D_P2_SLOW 7	288	#define IRONLAKE_LVDS_D_P2_SLOW 7
289	#define IRONLAKE_LVDS_D_P2_FAST 7	289	#define IRONLAKE_LVDS_D_P2_FAST 7
290		290
291	/* LVDS single-channel 100Mhz refclk */	291	/* LVDS single-channel 100Mhz refclk */
292	#define IRONLAKE_LVDS_S_SSC_N_MIN 1	292	#define IRONLAKE_LVDS_S_SSC_N_MIN 1
293	#define IRONLAKE_LVDS_S_SSC_N_MAX 2	293	#define IRONLAKE_LVDS_S_SSC_N_MAX 2
294	#define IRONLAKE_LVDS_S_SSC_M_MIN 79	294	#define IRONLAKE_LVDS_S_SSC_M_MIN 79
295	#define IRONLAKE_LVDS_S_SSC_M_MAX 126	295	#define IRONLAKE_LVDS_S_SSC_M_MAX 126
296	#define IRONLAKE_LVDS_S_SSC_P_MIN 28	296	#define IRONLAKE_LVDS_S_SSC_P_MIN 28
297	#define IRONLAKE_LVDS_S_SSC_P_MAX 112	297	#define IRONLAKE_LVDS_S_SSC_P_MAX 112
298	#define IRONLAKE_LVDS_S_SSC_P1_MIN 2	298	#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299	#define IRONLAKE_LVDS_S_SSC_P1_MAX 8	299	#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300	#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14	300	#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301	#define IRONLAKE_LVDS_S_SSC_P2_FAST 14	301	#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302		302
303	/* LVDS dual-channel 100Mhz refclk */	303	/* LVDS dual-channel 100Mhz refclk */
304	#define IRONLAKE_LVDS_D_SSC_N_MIN 1	304	#define IRONLAKE_LVDS_D_SSC_N_MIN 1
305	#define IRONLAKE_LVDS_D_SSC_N_MAX 3	305	#define IRONLAKE_LVDS_D_SSC_N_MAX 3
306	#define IRONLAKE_LVDS_D_SSC_M_MIN 79	306	#define IRONLAKE_LVDS_D_SSC_M_MIN 79
307	#define IRONLAKE_LVDS_D_SSC_M_MAX 126	307	#define IRONLAKE_LVDS_D_SSC_M_MAX 126
308	#define IRONLAKE_LVDS_D_SSC_P_MIN 14	308	#define IRONLAKE_LVDS_D_SSC_P_MIN 14
309	#define IRONLAKE_LVDS_D_SSC_P_MAX 42	309	#define IRONLAKE_LVDS_D_SSC_P_MAX 42
310	#define IRONLAKE_LVDS_D_SSC_P1_MIN 2	310	#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311	#define IRONLAKE_LVDS_D_SSC_P1_MAX 6	311	#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312	#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7	312	#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313	#define IRONLAKE_LVDS_D_SSC_P2_FAST 7	313	#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314		314
315	/* DisplayPort */	315	/* DisplayPort */
316	#define IRONLAKE_DP_N_MIN 1	316	#define IRONLAKE_DP_N_MIN 1
317	#define IRONLAKE_DP_N_MAX 2	317	#define IRONLAKE_DP_N_MAX 2
318	#define IRONLAKE_DP_M_MIN 81	318	#define IRONLAKE_DP_M_MIN 81
319	#define IRONLAKE_DP_M_MAX 90	319	#define IRONLAKE_DP_M_MAX 90
320	#define IRONLAKE_DP_P_MIN 10	320	#define IRONLAKE_DP_P_MIN 10
321	#define IRONLAKE_DP_P_MAX 20	321	#define IRONLAKE_DP_P_MAX 20
322	#define IRONLAKE_DP_P2_FAST 10	322	#define IRONLAKE_DP_P2_FAST 10
323	#define IRONLAKE_DP_P2_SLOW 10	323	#define IRONLAKE_DP_P2_SLOW 10
324	#define IRONLAKE_DP_P2_LIMIT 0	324	#define IRONLAKE_DP_P2_LIMIT 0
325	#define IRONLAKE_DP_P1_MIN 1	325	#define IRONLAKE_DP_P1_MIN 1
326	#define IRONLAKE_DP_P1_MAX 2	326	#define IRONLAKE_DP_P1_MAX 2
327		327
328	/* FDI */	328	/* FDI */
329	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */	329	#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330		330
331	static bool	331	static bool
332	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,	332	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
333	int target, int refclk, intel_clock_t *best_clock);	333	int target, int refclk, intel_clock_t *best_clock);
334	static bool	334	static bool
335	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,	335	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
336	int target, int refclk, intel_clock_t *best_clock);	336	int target, int refclk, intel_clock_t *best_clock);
337		337
338	static bool	338	static bool
339	intel_find_pll_g4x_dp(const intel_limit_t , struct drm_crtc crtc,	339	intel_find_pll_g4x_dp(const intel_limit_t , struct drm_crtc crtc,
340	int target, int refclk, intel_clock_t *best_clock);	340	int target, int refclk, intel_clock_t *best_clock);
341	static bool	341	static bool
342	intel_find_pll_ironlake_dp(const intel_limit_t , struct drm_crtc crtc,	342	intel_find_pll_ironlake_dp(const intel_limit_t , struct drm_crtc crtc,
343	int target, int refclk, intel_clock_t *best_clock);	343	int target, int refclk, intel_clock_t *best_clock);
344		344
345	static inline u32 /* units of 100MHz */	345	static inline u32 /* units of 100MHz */
346	intel_fdi_link_freq(struct drm_device *dev)	346	intel_fdi_link_freq(struct drm_device *dev)
347	{	347	{
348	if (IS_GEN5(dev)) {	348	if (IS_GEN5(dev)) {
349	struct drm_i915_private *dev_priv = dev->dev_private;	349	struct drm_i915_private *dev_priv = dev->dev_private;
350	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;	350	return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351	} else	351	} else
352	return 27;	352	return 27;
353	}	353	}
354		354
355	static const intel_limit_t intel_limits_i8xx_dvo = {	355	static const intel_limit_t intel_limits_i8xx_dvo = {
356	.dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },	356	.dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357	.vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },	357	.vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358	.n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },	358	.n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359	.m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },	359	.m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360	.m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },	360	.m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361	.m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },	361	.m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362	.p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },	362	.p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363	.p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },	363	.p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364	.p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,	364	.p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365	.p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },	365	.p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366	.find_pll = intel_find_best_PLL,	366	.find_pll = intel_find_best_PLL,
367	};	367	};
368		368
369	static const intel_limit_t intel_limits_i8xx_lvds = {	369	static const intel_limit_t intel_limits_i8xx_lvds = {
370	.dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },	370	.dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371	.vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },	371	.vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372	.n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },	372	.n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373	.m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },	373	.m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374	.m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },	374	.m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375	.m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },	375	.m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376	.p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },	376	.p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377	.p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },	377	.p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378	.p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,	378	.p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379	.p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },	379	.p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380	.find_pll = intel_find_best_PLL,	380	.find_pll = intel_find_best_PLL,
381	};	381	};
382		382
383	static const intel_limit_t intel_limits_i9xx_sdvo = {	383	static const intel_limit_t intel_limits_i9xx_sdvo = {
384	.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },	384	.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385	.vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },	385	.vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386	.n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },	386	.n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387	.m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },	387	.m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388	.m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },	388	.m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389	.m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },	389	.m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390	.p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },	390	.p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391	.p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },	391	.p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392	.p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,	392	.p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393	.p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },	393	.p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394	.find_pll = intel_find_best_PLL,	394	.find_pll = intel_find_best_PLL,
395	};	395	};
396		396
397	static const intel_limit_t intel_limits_i9xx_lvds = {	397	static const intel_limit_t intel_limits_i9xx_lvds = {
398	.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },	398	.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399	.vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },	399	.vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400	.n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },	400	.n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401	.m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },	401	.m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402	.m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },	402	.m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403	.m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },	403	.m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404	.p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },	404	.p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405	.p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },	405	.p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406	/* The single-channel range is 25-112Mhz, and dual-channel	406	/* The single-channel range is 25-112Mhz, and dual-channel
407	* is 80-224Mhz. Prefer single channel as much as possible.	407	* is 80-224Mhz. Prefer single channel as much as possible.
408	*/	408	*/
409	.p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,	409	.p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410	.p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },	410	.p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411	.find_pll = intel_find_best_PLL,	411	.find_pll = intel_find_best_PLL,
412	};	412	};
413		413
414	/* below parameter and function is for G4X Chipset Family*/	414	/* below parameter and function is for G4X Chipset Family*/
415	static const intel_limit_t intel_limits_g4x_sdvo = {	415	static const intel_limit_t intel_limits_g4x_sdvo = {
416	.dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },	416	.dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417	.vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},	417	.vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418	.n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },	418	.n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419	.m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },	419	.m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420	.m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },	420	.m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421	.m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },	421	.m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422	.p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },	422	.p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423	.p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},	423	.p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424	.p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,	424	.p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425	.p2_slow = G4X_P2_SDVO_SLOW,	425	.p2_slow = G4X_P2_SDVO_SLOW,
426	.p2_fast = G4X_P2_SDVO_FAST	426	.p2_fast = G4X_P2_SDVO_FAST
427	},	427	},
428	.find_pll = intel_g4x_find_best_PLL,	428	.find_pll = intel_g4x_find_best_PLL,
429	};	429	};
430		430
431	static const intel_limit_t intel_limits_g4x_hdmi = {	431	static const intel_limit_t intel_limits_g4x_hdmi = {
432	.dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },	432	.dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433	.vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},	433	.vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434	.n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },	434	.n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435	.m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },	435	.m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436	.m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },	436	.m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437	.m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },	437	.m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438	.p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },	438	.p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439	.p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},	439	.p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440	.p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,	440	.p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441	.p2_slow = G4X_P2_HDMI_DAC_SLOW,	441	.p2_slow = G4X_P2_HDMI_DAC_SLOW,
442	.p2_fast = G4X_P2_HDMI_DAC_FAST	442	.p2_fast = G4X_P2_HDMI_DAC_FAST
443	},	443	},
444	.find_pll = intel_g4x_find_best_PLL,	444	.find_pll = intel_g4x_find_best_PLL,
445	};	445	};
446		446
447	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {	447	static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448	.dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,	448	.dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449	.max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },	449	.max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450	.vco = { .min = G4X_VCO_MIN,	450	.vco = { .min = G4X_VCO_MIN,
451	.max = G4X_VCO_MAX },	451	.max = G4X_VCO_MAX },
452	.n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,	452	.n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453	.max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },	453	.max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454	.m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,	454	.m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455	.max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },	455	.max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456	.m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,	456	.m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457	.max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },	457	.max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458	.m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,	458	.m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459	.max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },	459	.max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460	.p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,	460	.p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461	.max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },	461	.max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462	.p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,	462	.p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463	.max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },	463	.max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464	.p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,	464	.p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465	.p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,	465	.p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466	.p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST	466	.p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467	},	467	},
468	.find_pll = intel_g4x_find_best_PLL,	468	.find_pll = intel_g4x_find_best_PLL,
469	};	469	};
470		470
471	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {	471	static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472	.dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,	472	.dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473	.max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },	473	.max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474	.vco = { .min = G4X_VCO_MIN,	474	.vco = { .min = G4X_VCO_MIN,
475	.max = G4X_VCO_MAX },	475	.max = G4X_VCO_MAX },
476	.n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,	476	.n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477	.max = G4X_N_DUAL_CHANNEL_LVDS_MAX },	477	.max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478	.m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,	478	.m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479	.max = G4X_M_DUAL_CHANNEL_LVDS_MAX },	479	.max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480	.m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,	480	.m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481	.max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },	481	.max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482	.m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,	482	.m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483	.max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },	483	.max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484	.p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,	484	.p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485	.max = G4X_P_DUAL_CHANNEL_LVDS_MAX },	485	.max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486	.p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,	486	.p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487	.max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },	487	.max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488	.p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,	488	.p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489	.p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,	489	.p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490	.p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST	490	.p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491	},	491	},
492	.find_pll = intel_g4x_find_best_PLL,	492	.find_pll = intel_g4x_find_best_PLL,
493	};	493	};
494		494
495	static const intel_limit_t intel_limits_g4x_display_port = {	495	static const intel_limit_t intel_limits_g4x_display_port = {
496	.dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,	496	.dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497	.max = G4X_DOT_DISPLAY_PORT_MAX },	497	.max = G4X_DOT_DISPLAY_PORT_MAX },
498	.vco = { .min = G4X_VCO_MIN,	498	.vco = { .min = G4X_VCO_MIN,
499	.max = G4X_VCO_MAX},	499	.max = G4X_VCO_MAX},
500	.n = { .min = G4X_N_DISPLAY_PORT_MIN,	500	.n = { .min = G4X_N_DISPLAY_PORT_MIN,
501	.max = G4X_N_DISPLAY_PORT_MAX },	501	.max = G4X_N_DISPLAY_PORT_MAX },
502	.m = { .min = G4X_M_DISPLAY_PORT_MIN,	502	.m = { .min = G4X_M_DISPLAY_PORT_MIN,
503	.max = G4X_M_DISPLAY_PORT_MAX },	503	.max = G4X_M_DISPLAY_PORT_MAX },
504	.m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,	504	.m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505	.max = G4X_M1_DISPLAY_PORT_MAX },	505	.max = G4X_M1_DISPLAY_PORT_MAX },
506	.m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,	506	.m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507	.max = G4X_M2_DISPLAY_PORT_MAX },	507	.max = G4X_M2_DISPLAY_PORT_MAX },
508	.p = { .min = G4X_P_DISPLAY_PORT_MIN,	508	.p = { .min = G4X_P_DISPLAY_PORT_MIN,
509	.max = G4X_P_DISPLAY_PORT_MAX },	509	.max = G4X_P_DISPLAY_PORT_MAX },
510	.p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,	510	.p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511	.max = G4X_P1_DISPLAY_PORT_MAX},	511	.max = G4X_P1_DISPLAY_PORT_MAX},
512	.p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,	512	.p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513	.p2_slow = G4X_P2_DISPLAY_PORT_SLOW,	513	.p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514	.p2_fast = G4X_P2_DISPLAY_PORT_FAST },	514	.p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515	.find_pll = intel_find_pll_g4x_dp,	515	.find_pll = intel_find_pll_g4x_dp,
516	};	516	};
517		517
518	static const intel_limit_t intel_limits_pineview_sdvo = {	518	static const intel_limit_t intel_limits_pineview_sdvo = {
519	.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},	519	.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520	.vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },	520	.vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521	.n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },	521	.n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522	.m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },	522	.m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523	.m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },	523	.m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524	.m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },	524	.m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525	.p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },	525	.p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526	.p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },	526	.p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527	.p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,	527	.p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528	.p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },	528	.p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529	.find_pll = intel_find_best_PLL,	529	.find_pll = intel_find_best_PLL,
530	};	530	};
531		531
532	static const intel_limit_t intel_limits_pineview_lvds = {	532	static const intel_limit_t intel_limits_pineview_lvds = {
533	.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },	533	.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534	.vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },	534	.vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535	.n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },	535	.n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536	.m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },	536	.m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537	.m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },	537	.m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538	.m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },	538	.m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539	.p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },	539	.p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540	.p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },	540	.p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541	/* Pineview only supports single-channel mode. */	541	/* Pineview only supports single-channel mode. */
542	.p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,	542	.p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543	.p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },	543	.p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544	.find_pll = intel_find_best_PLL,	544	.find_pll = intel_find_best_PLL,
545	};	545	};
546		546
547	static const intel_limit_t intel_limits_ironlake_dac = {	547	static const intel_limit_t intel_limits_ironlake_dac = {
548	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },	548	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },	549	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550	.n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },	550	.n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551	.m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },	551	.m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },	552	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },	553	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554	.p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },	554	.p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555	.p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },	555	.p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,	556	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557	.p2_slow = IRONLAKE_DAC_P2_SLOW,	557	.p2_slow = IRONLAKE_DAC_P2_SLOW,
558	.p2_fast = IRONLAKE_DAC_P2_FAST },	558	.p2_fast = IRONLAKE_DAC_P2_FAST },
559	.find_pll = intel_g4x_find_best_PLL,	559	.find_pll = intel_g4x_find_best_PLL,
560	};	560	};
561		561
562	static const intel_limit_t intel_limits_ironlake_single_lvds = {	562	static const intel_limit_t intel_limits_ironlake_single_lvds = {
563	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },	563	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },	564	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565	.n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },	565	.n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566	.m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },	566	.m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },	567	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },	568	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569	.p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },	569	.p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570	.p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },	570	.p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,	571	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572	.p2_slow = IRONLAKE_LVDS_S_P2_SLOW,	572	.p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573	.p2_fast = IRONLAKE_LVDS_S_P2_FAST },	573	.p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574	.find_pll = intel_g4x_find_best_PLL,	574	.find_pll = intel_g4x_find_best_PLL,
575	};	575	};
576		576
577	static const intel_limit_t intel_limits_ironlake_dual_lvds = {	577	static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },	578	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },	579	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580	.n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },	580	.n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581	.m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },	581	.m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },	582	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },	583	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584	.p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },	584	.p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585	.p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },	585	.p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,	586	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587	.p2_slow = IRONLAKE_LVDS_D_P2_SLOW,	587	.p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588	.p2_fast = IRONLAKE_LVDS_D_P2_FAST },	588	.p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589	.find_pll = intel_g4x_find_best_PLL,	589	.find_pll = intel_g4x_find_best_PLL,
590	};	590	};
591		591
592	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {	592	static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },	593	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },	594	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595	.n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },	595	.n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596	.m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },	596	.m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },	597	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },	598	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599	.p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },	599	.p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600	.p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },	600	.p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,	601	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602	.p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,	602	.p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603	.p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },	603	.p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604	.find_pll = intel_g4x_find_best_PLL,	604	.find_pll = intel_g4x_find_best_PLL,
605	};	605	};
606		606
607	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {	607	static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },	608	.dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },	609	.vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610	.n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },	610	.n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611	.m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },	611	.m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },	612	.m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },	613	.m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614	.p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },	614	.p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615	.p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },	615	.p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,	616	.p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617	.p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,	617	.p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618	.p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },	618	.p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619	.find_pll = intel_g4x_find_best_PLL,	619	.find_pll = intel_g4x_find_best_PLL,
620	};	620	};
621		621
622	static const intel_limit_t intel_limits_ironlake_display_port = {	622	static const intel_limit_t intel_limits_ironlake_display_port = {
623	.dot = { .min = IRONLAKE_DOT_MIN,	623	.dot = { .min = IRONLAKE_DOT_MIN,
624	.max = IRONLAKE_DOT_MAX },	624	.max = IRONLAKE_DOT_MAX },
625	.vco = { .min = IRONLAKE_VCO_MIN,	625	.vco = { .min = IRONLAKE_VCO_MIN,
626	.max = IRONLAKE_VCO_MAX},	626	.max = IRONLAKE_VCO_MAX},
627	.n = { .min = IRONLAKE_DP_N_MIN,	627	.n = { .min = IRONLAKE_DP_N_MIN,
628	.max = IRONLAKE_DP_N_MAX },	628	.max = IRONLAKE_DP_N_MAX },
629	.m = { .min = IRONLAKE_DP_M_MIN,	629	.m = { .min = IRONLAKE_DP_M_MIN,
630	.max = IRONLAKE_DP_M_MAX },	630	.max = IRONLAKE_DP_M_MAX },
631	.m1 = { .min = IRONLAKE_M1_MIN,	631	.m1 = { .min = IRONLAKE_M1_MIN,
632	.max = IRONLAKE_M1_MAX },	632	.max = IRONLAKE_M1_MAX },
633	.m2 = { .min = IRONLAKE_M2_MIN,	633	.m2 = { .min = IRONLAKE_M2_MIN,
634	.max = IRONLAKE_M2_MAX },	634	.max = IRONLAKE_M2_MAX },
635	.p = { .min = IRONLAKE_DP_P_MIN,	635	.p = { .min = IRONLAKE_DP_P_MIN,
636	.max = IRONLAKE_DP_P_MAX },	636	.max = IRONLAKE_DP_P_MAX },
637	.p1 = { .min = IRONLAKE_DP_P1_MIN,	637	.p1 = { .min = IRONLAKE_DP_P1_MIN,
638	.max = IRONLAKE_DP_P1_MAX},	638	.max = IRONLAKE_DP_P1_MAX},
639	.p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,	639	.p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640	.p2_slow = IRONLAKE_DP_P2_SLOW,	640	.p2_slow = IRONLAKE_DP_P2_SLOW,
641	.p2_fast = IRONLAKE_DP_P2_FAST },	641	.p2_fast = IRONLAKE_DP_P2_FAST },
642	.find_pll = intel_find_pll_ironlake_dp,	642	.find_pll = intel_find_pll_ironlake_dp,
643	};	643	};
644		644
645	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,	645	static const intel_limit_t intel_ironlake_limit(struct drm_crtc crtc,
646	int refclk)	646	int refclk)
647	{	647	{
648	struct drm_device *dev = crtc->dev;	648	struct drm_device *dev = crtc->dev;
649	struct drm_i915_private *dev_priv = dev->dev_private;	649	struct drm_i915_private *dev_priv = dev->dev_private;
650	const intel_limit_t *limit;	650	const intel_limit_t *limit;
651		651
652	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {	652	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653	if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==	653	if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654	LVDS_CLKB_POWER_UP) {	654	LVDS_CLKB_POWER_UP) {
655	/* LVDS dual channel */	655	/* LVDS dual channel */
656	if (refclk == 100000)	656	if (refclk == 100000)
657	limit = &intel_limits_ironlake_dual_lvds_100m;	657	limit = &intel_limits_ironlake_dual_lvds_100m;
658	else	658	else
659	limit = &intel_limits_ironlake_dual_lvds;	659	limit = &intel_limits_ironlake_dual_lvds;
660	} else {	660	} else {
661	if (refclk == 100000)	661	if (refclk == 100000)
662	limit = &intel_limits_ironlake_single_lvds_100m;	662	limit = &intel_limits_ironlake_single_lvds_100m;
663	else	663	else
664	limit = &intel_limits_ironlake_single_lvds;	664	limit = &intel_limits_ironlake_single_lvds;
665	}	665	}
666	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|	666	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) \|\|
667	HAS_eDP)	667	HAS_eDP)
668	limit = &intel_limits_ironlake_display_port;	668	limit = &intel_limits_ironlake_display_port;
669	else	669	else
670	limit = &intel_limits_ironlake_dac;	670	limit = &intel_limits_ironlake_dac;
671		671
672	return limit;	672	return limit;
673	}	673	}
674		674
675	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)	675	static const intel_limit_t intel_g4x_limit(struct drm_crtc crtc)
676	{	676	{
677	struct drm_device *dev = crtc->dev;	677	struct drm_device *dev = crtc->dev;
678	struct drm_i915_private *dev_priv = dev->dev_private;	678	struct drm_i915_private *dev_priv = dev->dev_private;
679	const intel_limit_t *limit;	679	const intel_limit_t *limit;
680		680
681	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {	681	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682	if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==	682	if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683	LVDS_CLKB_POWER_UP)	683	LVDS_CLKB_POWER_UP)
684	/* LVDS with dual channel */	684	/* LVDS with dual channel */
685	limit = &intel_limits_g4x_dual_channel_lvds;	685	limit = &intel_limits_g4x_dual_channel_lvds;
686	else	686	else
687	/* LVDS with dual channel */	687	/* LVDS with dual channel */
688	limit = &intel_limits_g4x_single_channel_lvds;	688	limit = &intel_limits_g4x_single_channel_lvds;
689	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|	689	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) \|\|
690	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {	690	intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691	limit = &intel_limits_g4x_hdmi;	691	limit = &intel_limits_g4x_hdmi;
692	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {	692	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693	limit = &intel_limits_g4x_sdvo;	693	limit = &intel_limits_g4x_sdvo;
694	} else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {	694	} else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695	limit = &intel_limits_g4x_display_port;	695	limit = &intel_limits_g4x_display_port;
696	} else /* The option is for other outputs */	696	} else /* The option is for other outputs */
697	limit = &intel_limits_i9xx_sdvo;	697	limit = &intel_limits_i9xx_sdvo;
698		698
699	return limit;	699	return limit;
700	}	700	}
701		701
702	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)	702	static const intel_limit_t intel_limit(struct drm_crtc crtc, int refclk)
703	{	703	{
704	struct drm_device *dev = crtc->dev;	704	struct drm_device *dev = crtc->dev;
705	const intel_limit_t *limit;	705	const intel_limit_t *limit;
706		706
707	if (HAS_PCH_SPLIT(dev))	707	if (HAS_PCH_SPLIT(dev))
708	limit = intel_ironlake_limit(crtc, refclk);	708	limit = intel_ironlake_limit(crtc, refclk);
709	else if (IS_G4X(dev)) {	709	else if (IS_G4X(dev)) {
710	limit = intel_g4x_limit(crtc);	710	limit = intel_g4x_limit(crtc);
711	} else if (IS_PINEVIEW(dev)) {	711	} else if (IS_PINEVIEW(dev)) {
712	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))	712	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713	limit = &intel_limits_pineview_lvds;	713	limit = &intel_limits_pineview_lvds;
714	else	714	else
715	limit = &intel_limits_pineview_sdvo;	715	limit = &intel_limits_pineview_sdvo;
716	} else if (!IS_GEN2(dev)) {	716	} else if (!IS_GEN2(dev)) {
717	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))	717	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718	limit = &intel_limits_i9xx_lvds;	718	limit = &intel_limits_i9xx_lvds;
719	else	719	else
720	limit = &intel_limits_i9xx_sdvo;	720	limit = &intel_limits_i9xx_sdvo;
721	} else {	721	} else {
722	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))	722	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723	limit = &intel_limits_i8xx_lvds;	723	limit = &intel_limits_i8xx_lvds;
724	else	724	else
725	limit = &intel_limits_i8xx_dvo;	725	limit = &intel_limits_i8xx_dvo;
726	}	726	}
727	return limit;	727	return limit;
728	}	728	}
729		729
730	/* m1 is reserved as 0 in Pineview, n is a ring counter */	730	/* m1 is reserved as 0 in Pineview, n is a ring counter */
731	static void pineview_clock(int refclk, intel_clock_t *clock)	731	static void pineview_clock(int refclk, intel_clock_t *clock)
732	{	732	{
733	clock->m = clock->m2 + 2;	733	clock->m = clock->m2 + 2;
734	clock->p = clock->p1 * clock->p2;	734	clock->p = clock->p1 * clock->p2;
735	clock->vco = refclk * clock->m / clock->n;	735	clock->vco = refclk * clock->m / clock->n;
736	clock->dot = clock->vco / clock->p;	736	clock->dot = clock->vco / clock->p;
737	}	737	}
738		738
739	static void intel_clock(struct drm_device dev, int refclk, intel_clock_t clock)	739	static void intel_clock(struct drm_device dev, int refclk, intel_clock_t clock)
740	{	740	{
741	if (IS_PINEVIEW(dev)) {	741	if (IS_PINEVIEW(dev)) {
742	pineview_clock(refclk, clock);	742	pineview_clock(refclk, clock);
743	return;	743	return;
744	}	744	}
745	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);	745	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746	clock->p = clock->p1 * clock->p2;	746	clock->p = clock->p1 * clock->p2;
747	clock->vco = refclk * clock->m / (clock->n + 2);	747	clock->vco = refclk * clock->m / (clock->n + 2);
748	clock->dot = clock->vco / clock->p;	748	clock->dot = clock->vco / clock->p;
749	}	749	}
750		750
751	/**	751	/**
752	* Returns whether any output on the specified pipe is of the specified type	752	* Returns whether any output on the specified pipe is of the specified type
753	*/	753	*/
754	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)	754	bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
755	{	755	{
756	struct drm_device *dev = crtc->dev;	756	struct drm_device *dev = crtc->dev;
757	struct drm_mode_config *mode_config = &dev->mode_config;	757	struct drm_mode_config *mode_config = &dev->mode_config;
758	struct intel_encoder *encoder;	758	struct intel_encoder *encoder;
759		759
760	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)	760	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761	if (encoder->base.crtc == crtc && encoder->type == type)	761	if (encoder->base.crtc == crtc && encoder->type == type)
762	return true;	762	return true;
763		763
764	return false;	764	return false;
765	}	765	}
766		766
767	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)	767	#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
768	/**	768	/**
769	* Returns whether the given set of divisors are valid for a given refclk with	769	* Returns whether the given set of divisors are valid for a given refclk with
770	* the given connectors.	770	* the given connectors.
771	*/	771	*/
772		772
773	static bool intel_PLL_is_valid(struct drm_device *dev,	773	static bool intel_PLL_is_valid(struct drm_device *dev,
774	const intel_limit_t *limit,	774	const intel_limit_t *limit,
775	const intel_clock_t *clock)	775	const intel_clock_t *clock)
776	{	776	{
777	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)	777	if (clock->p1 < limit->p1.min \|\| limit->p1.max < clock->p1)
778	INTELPllInvalid ("p1 out of range\n");	778	INTELPllInvalid ("p1 out of range\n");
779	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)	779	if (clock->p < limit->p.min \|\| limit->p.max < clock->p)
780	INTELPllInvalid ("p out of range\n");	780	INTELPllInvalid ("p out of range\n");
781	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)	781	if (clock->m2 < limit->m2.min \|\| limit->m2.max < clock->m2)
782	INTELPllInvalid ("m2 out of range\n");	782	INTELPllInvalid ("m2 out of range\n");
783	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)	783	if (clock->m1 < limit->m1.min \|\| limit->m1.max < clock->m1)
784	INTELPllInvalid ("m1 out of range\n");	784	INTELPllInvalid ("m1 out of range\n");
785	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))	785	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
786	INTELPllInvalid ("m1 <= m2\n");	786	INTELPllInvalid ("m1 <= m2\n");
787	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)	787	if (clock->m < limit->m.min \|\| limit->m.max < clock->m)
788	INTELPllInvalid ("m out of range\n");	788	INTELPllInvalid ("m out of range\n");
789	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)	789	if (clock->n < limit->n.min \|\| limit->n.max < clock->n)
790	INTELPllInvalid ("n out of range\n");	790	INTELPllInvalid ("n out of range\n");
791	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)	791	if (clock->vco < limit->vco.min \|\| limit->vco.max < clock->vco)
792	INTELPllInvalid ("vco out of range\n");	792	INTELPllInvalid ("vco out of range\n");
793	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,	793	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794	* connector, etc., rather than just a single range.	794	* connector, etc., rather than just a single range.
795	*/	795	*/
796	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)	796	if (clock->dot < limit->dot.min \|\| limit->dot.max < clock->dot)
797	INTELPllInvalid ("dot out of range\n");	797	INTELPllInvalid ("dot out of range\n");
798		798
799	return true;	799	return true;
800	}	800	}
801		801
802	static bool	802	static bool
803	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,	803	intel_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
804	int target, int refclk, intel_clock_t *best_clock)	804	int target, int refclk, intel_clock_t *best_clock)
805		805
806	{	806	{
807	struct drm_device *dev = crtc->dev;	807	struct drm_device *dev = crtc->dev;
808	struct drm_i915_private *dev_priv = dev->dev_private;	808	struct drm_i915_private *dev_priv = dev->dev_private;
809	intel_clock_t clock;	809	intel_clock_t clock;
810	int err = target;	810	int err = target;
811		811
812	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&	812	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
813	(I915_READ(LVDS)) != 0) {	813	(I915_READ(LVDS)) != 0) {
814	/*	814	/*
815	* For LVDS, if the panel is on, just rely on its current	815	* For LVDS, if the panel is on, just rely on its current
816	* settings for dual-channel. We haven't figured out how to	816	* settings for dual-channel. We haven't figured out how to
817	* reliably set up different single/dual channel state, if we	817	* reliably set up different single/dual channel state, if we
818	* even can.	818	* even can.
819	*/	819	*/
820	if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==	820	if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
821	LVDS_CLKB_POWER_UP)	821	LVDS_CLKB_POWER_UP)
822	clock.p2 = limit->p2.p2_fast;	822	clock.p2 = limit->p2.p2_fast;
823	else	823	else
824	clock.p2 = limit->p2.p2_slow;	824	clock.p2 = limit->p2.p2_slow;
825	} else {	825	} else {
826	if (target < limit->p2.dot_limit)	826	if (target < limit->p2.dot_limit)
827	clock.p2 = limit->p2.p2_slow;	827	clock.p2 = limit->p2.p2_slow;
828	else	828	else
829	clock.p2 = limit->p2.p2_fast;	829	clock.p2 = limit->p2.p2_fast;
830	}	830	}
831		831
832	memset (best_clock, 0, sizeof (*best_clock));	832	memset (best_clock, 0, sizeof (*best_clock));
833		833
834	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;	834	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
835	clock.m1++) {	835	clock.m1++) {
836	for (clock.m2 = limit->m2.min;	836	for (clock.m2 = limit->m2.min;
837	clock.m2 <= limit->m2.max; clock.m2++) {	837	clock.m2 <= limit->m2.max; clock.m2++) {
838	/* m1 is always 0 in Pineview */	838	/* m1 is always 0 in Pineview */
839	if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))	839	if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
840	break;	840	break;
841	for (clock.n = limit->n.min;	841	for (clock.n = limit->n.min;
842	clock.n <= limit->n.max; clock.n++) {	842	clock.n <= limit->n.max; clock.n++) {
843	for (clock.p1 = limit->p1.min;	843	for (clock.p1 = limit->p1.min;
844	clock.p1 <= limit->p1.max; clock.p1++) {	844	clock.p1 <= limit->p1.max; clock.p1++) {
845	int this_err;	845	int this_err;
846		846
847	intel_clock(dev, refclk, &clock);	847	intel_clock(dev, refclk, &clock);
848	if (!intel_PLL_is_valid(dev, limit,	848	if (!intel_PLL_is_valid(dev, limit,
849	&clock))	849	&clock))
850	continue;	850	continue;
851		851
852	this_err = abs(clock.dot - target);	852	this_err = abs(clock.dot - target);
853	if (this_err < err) {	853	if (this_err < err) {
854	*best_clock = clock;	854	*best_clock = clock;
855	err = this_err;	855	err = this_err;
856	}	856	}
857	}	857	}
858	}	858	}
859	}	859	}
860	}	860	}
861		861
862	return (err != target);	862	return (err != target);
863	}	863	}
864		864
865	static bool	865	static bool
866	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,	866	intel_g4x_find_best_PLL(const intel_limit_t limit, struct drm_crtc crtc,
867	int target, int refclk, intel_clock_t *best_clock)	867	int target, int refclk, intel_clock_t *best_clock)
868	{	868	{
869	struct drm_device *dev = crtc->dev;	869	struct drm_device *dev = crtc->dev;
870	struct drm_i915_private *dev_priv = dev->dev_private;	870	struct drm_i915_private *dev_priv = dev->dev_private;
871	intel_clock_t clock;	871	intel_clock_t clock;
872	int max_n;	872	int max_n;
873	bool found;	873	bool found;
874	/* approximately equals target * 0.00585 */	874	/* approximately equals target * 0.00585 */
875	int err_most = (target >> 8) + (target >> 9);	875	int err_most = (target >> 8) + (target >> 9);
876	found = false;	876	found = false;
877		877
878	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {	878	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
879	int lvds_reg;	879	int lvds_reg;
880		880
881	if (HAS_PCH_SPLIT(dev))	881	if (HAS_PCH_SPLIT(dev))
882	lvds_reg = PCH_LVDS;	882	lvds_reg = PCH_LVDS;
883	else	883	else
884	lvds_reg = LVDS;	884	lvds_reg = LVDS;
885	if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==	885	if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
886	LVDS_CLKB_POWER_UP)	886	LVDS_CLKB_POWER_UP)
887	clock.p2 = limit->p2.p2_fast;	887	clock.p2 = limit->p2.p2_fast;
888	else	888	else
889	clock.p2 = limit->p2.p2_slow;	889	clock.p2 = limit->p2.p2_slow;
890	} else {	890	} else {
891	if (target < limit->p2.dot_limit)	891	if (target < limit->p2.dot_limit)
892	clock.p2 = limit->p2.p2_slow;	892	clock.p2 = limit->p2.p2_slow;
893	else	893	else
894	clock.p2 = limit->p2.p2_fast;	894	clock.p2 = limit->p2.p2_fast;
895	}	895	}
896		896
897	memset(best_clock, 0, sizeof(*best_clock));	897	memset(best_clock, 0, sizeof(*best_clock));
898	max_n = limit->n.max;	898	max_n = limit->n.max;
899	/* based on hardware requirement, prefer smaller n to precision */	899	/* based on hardware requirement, prefer smaller n to precision */
900	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {	900	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
901	/* based on hardware requirement, prefere larger m1,m2 */	901	/* based on hardware requirement, prefere larger m1,m2 */
902	for (clock.m1 = limit->m1.max;	902	for (clock.m1 = limit->m1.max;
903	clock.m1 >= limit->m1.min; clock.m1--) {	903	clock.m1 >= limit->m1.min; clock.m1--) {
904	for (clock.m2 = limit->m2.max;	904	for (clock.m2 = limit->m2.max;
905	clock.m2 >= limit->m2.min; clock.m2--) {	905	clock.m2 >= limit->m2.min; clock.m2--) {
906	for (clock.p1 = limit->p1.max;	906	for (clock.p1 = limit->p1.max;
907	clock.p1 >= limit->p1.min; clock.p1--) {	907	clock.p1 >= limit->p1.min; clock.p1--) {
908	int this_err;	908	int this_err;
909		909
910	intel_clock(dev, refclk, &clock);	910	intel_clock(dev, refclk, &clock);
911	if (!intel_PLL_is_valid(dev, limit,	911	if (!intel_PLL_is_valid(dev, limit,
912	&clock))	912	&clock))
913	continue;	913	continue;
914		914
915	this_err = abs(clock.dot - target);	915	this_err = abs(clock.dot - target);
916	if (this_err < err_most) {	916	if (this_err < err_most) {
917	*best_clock = clock;	917	*best_clock = clock;
918	err_most = this_err;	918	err_most = this_err;
919	max_n = clock.n;	919	max_n = clock.n;
920	found = true;	920	found = true;
921	}	921	}
922	}	922	}
923	}	923	}
924	}	924	}
925	}	925	}
926	return found;	926	return found;
927	}	927	}
928		928
929	static bool	929	static bool
930	intel_find_pll_ironlake_dp(const intel_limit_t limit, struct drm_crtc crtc,	930	intel_find_pll_ironlake_dp(const intel_limit_t limit, struct drm_crtc crtc,
931	int target, int refclk, intel_clock_t *best_clock)	931	int target, int refclk, intel_clock_t *best_clock)
932	{	932	{
933	struct drm_device *dev = crtc->dev;	933	struct drm_device *dev = crtc->dev;
934	intel_clock_t clock;	934	intel_clock_t clock;
935		935
936	if (target < 200000) {	936	if (target < 200000) {
937	clock.n = 1;	937	clock.n = 1;
938	clock.p1 = 2;	938	clock.p1 = 2;
939	clock.p2 = 10;	939	clock.p2 = 10;
940	clock.m1 = 12;	940	clock.m1 = 12;
941	clock.m2 = 9;	941	clock.m2 = 9;
942	} else {	942	} else {
943	clock.n = 2;	943	clock.n = 2;
944	clock.p1 = 1;	944	clock.p1 = 1;
945	clock.p2 = 10;	945	clock.p2 = 10;
946	clock.m1 = 14;	946	clock.m1 = 14;
947	clock.m2 = 8;	947	clock.m2 = 8;
948	}	948	}
949	intel_clock(dev, refclk, &clock);	949	intel_clock(dev, refclk, &clock);
950	memcpy(best_clock, &clock, sizeof(intel_clock_t));	950	memcpy(best_clock, &clock, sizeof(intel_clock_t));
951	return true;	951	return true;
952	}	952	}
953		953
954	/* DisplayPort has only two frequencies, 162MHz and 270MHz */	954	/* DisplayPort has only two frequencies, 162MHz and 270MHz */
955	static bool	955	static bool
956	intel_find_pll_g4x_dp(const intel_limit_t limit, struct drm_crtc crtc,	956	intel_find_pll_g4x_dp(const intel_limit_t limit, struct drm_crtc crtc,
957	int target, int refclk, intel_clock_t *best_clock)	957	int target, int refclk, intel_clock_t *best_clock)
958	{	958	{
959	intel_clock_t clock;	959	intel_clock_t clock;
960	if (target < 200000) {	960	if (target < 200000) {
961	clock.p1 = 2;	961	clock.p1 = 2;
962	clock.p2 = 10;	962	clock.p2 = 10;
963	clock.n = 2;	963	clock.n = 2;
964	clock.m1 = 23;	964	clock.m1 = 23;
965	clock.m2 = 8;	965	clock.m2 = 8;
966	} else {	966	} else {
967	clock.p1 = 1;	967	clock.p1 = 1;
968	clock.p2 = 10;	968	clock.p2 = 10;
969	clock.n = 1;	969	clock.n = 1;
970	clock.m1 = 14;	970	clock.m1 = 14;
971	clock.m2 = 2;	971	clock.m2 = 2;
972	}	972	}
973	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);	973	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974	clock.p = (clock.p1 * clock.p2);	974	clock.p = (clock.p1 * clock.p2);
975	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;	975	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976	clock.vco = 0;	976	clock.vco = 0;
977	memcpy(best_clock, &clock, sizeof(intel_clock_t));	977	memcpy(best_clock, &clock, sizeof(intel_clock_t));
978	return true;	978	return true;
979	}	979	}
980		980
981	/**	981	/**
982	* intel_wait_for_vblank - wait for vblank on a given pipe	982	* intel_wait_for_vblank - wait for vblank on a given pipe
983	* @dev: drm device	983	* @dev: drm device
984	* @pipe: pipe to wait for	984	* @pipe: pipe to wait for
985	*	985	*
986	* Wait for vblank to occur on a given pipe. Needed for various bits of	986	* Wait for vblank to occur on a given pipe. Needed for various bits of
987	* mode setting code.	987	* mode setting code.
988	*/	988	*/
989	void intel_wait_for_vblank(struct drm_device *dev, int pipe)	989	void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990	{	990	{
991	struct drm_i915_private *dev_priv = dev->dev_private;	991	struct drm_i915_private *dev_priv = dev->dev_private;
992	int pipestat_reg = PIPESTAT(pipe);	992	int pipestat_reg = PIPESTAT(pipe);
993		993
994	/* Clear existing vblank status. Note this will clear any other	994	/* Clear existing vblank status. Note this will clear any other
995	* sticky status fields as well.	995	* sticky status fields as well.
996	*	996	*
997	* This races with i915_driver_irq_handler() with the result	997	* This races with i915_driver_irq_handler() with the result
998	* that either function could miss a vblank event. Here it is not	998	* that either function could miss a vblank event. Here it is not
999	* fatal, as we will either wait upon the next vblank interrupt or	999	* fatal, as we will either wait upon the next vblank interrupt or
1000	* timeout. Generally speaking intel_wait_for_vblank() is only	1000	* timeout. Generally speaking intel_wait_for_vblank() is only
1001	* called during modeset at which time the GPU should be idle and	1001	* called during modeset at which time the GPU should be idle and
1002	* should not be performing page flips and thus not waiting on	1002	* should not be performing page flips and thus not waiting on
1003	* vblanks...	1003	* vblanks...
1004	* Currently, the result of us stealing a vblank from the irq	1004	* Currently, the result of us stealing a vblank from the irq
1005	* handler is that a single frame will be skipped during swapbuffers.	1005	* handler is that a single frame will be skipped during swapbuffers.
1006	*/	1006	*/
1007	I915_WRITE(pipestat_reg,	1007	I915_WRITE(pipestat_reg,
1008	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);	1008	I915_READ(pipestat_reg) \| PIPE_VBLANK_INTERRUPT_STATUS);
1009		1009
1010	/* Wait for vblank interrupt bit to set */	1010	/* Wait for vblank interrupt bit to set */
1011	if (wait_for(I915_READ(pipestat_reg) &	1011	if (wait_for(I915_READ(pipestat_reg) &
1012	PIPE_VBLANK_INTERRUPT_STATUS,	1012	PIPE_VBLANK_INTERRUPT_STATUS,
1013	50))	1013	50))
1014	DRM_DEBUG_KMS("vblank wait timed out\n");	1014	DRM_DEBUG_KMS("vblank wait timed out\n");
1015	}	1015	}
1016		1016
1017	/*	1017	/*
1018	* intel_wait_for_pipe_off - wait for pipe to turn off	1018	* intel_wait_for_pipe_off - wait for pipe to turn off
1019	* @dev: drm device	1019	* @dev: drm device
1020	* @pipe: pipe to wait for	1020	* @pipe: pipe to wait for
1021	*	1021	*
1022	* After disabling a pipe, we can't wait for vblank in the usual way,	1022	* After disabling a pipe, we can't wait for vblank in the usual way,
1023	* spinning on the vblank interrupt status bit, since we won't actually	1023	* spinning on the vblank interrupt status bit, since we won't actually
1024	* see an interrupt when the pipe is disabled.	1024	* see an interrupt when the pipe is disabled.
1025	*	1025	*
1026	* On Gen4 and above:	1026	* On Gen4 and above:
1027	* wait for the pipe register state bit to turn off	1027	* wait for the pipe register state bit to turn off
1028	*	1028	*
1029	* Otherwise:	1029	* Otherwise:
1030	* wait for the display line value to settle (it usually	1030	* wait for the display line value to settle (it usually
1031	* ends up stopping at the start of the next frame).	1031	* ends up stopping at the start of the next frame).
1032	*	1032	*
1033	*/	1033	*/
1034	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)	1034	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035	{	1035	{
1036	struct drm_i915_private *dev_priv = dev->dev_private;	1036	struct drm_i915_private *dev_priv = dev->dev_private;
1037		1037
1038	if (INTEL_INFO(dev)->gen >= 4) {	1038	if (INTEL_INFO(dev)->gen >= 4) {
1039	int reg = PIPECONF(pipe);	1039	int reg = PIPECONF(pipe);
1040		1040
1041	/* Wait for the Pipe State to go off */	1041	/* Wait for the Pipe State to go off */
1042	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,	1042	if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043	100))	1043	100))
1044	DRM_DEBUG_KMS("pipe_off wait timed out\n");	1044	DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045	} else {	1045	} else {
1046	u32 last_line;	1046	u32 last_line;
1047	int reg = PIPEDSL(pipe);	1047	int reg = PIPEDSL(pipe);
1048	unsigned long timeout = jiffies + msecs_to_jiffies(100);	1048	unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049		1049
1050	/* Wait for the display line to settle */	1050	/* Wait for the display line to settle */
1051	do {	1051	do {
1052	last_line = I915_READ(reg) & DSL_LINEMASK;	1052	last_line = I915_READ(reg) & DSL_LINEMASK;
1053	mdelay(5);	1053	mdelay(5);
1054	} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&	1054	} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055	time_after(timeout, jiffies));	1055	time_after(timeout, jiffies));
1056	if (time_after(jiffies, timeout))	1056	if (time_after(jiffies, timeout))
1057	DRM_DEBUG_KMS("pipe_off wait timed out\n");	1057	DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058	}	1058	}
1059	}	1059	}
1060		1060
1061	static const char *state_string(bool enabled)	1061	static const char *state_string(bool enabled)
1062	{	1062	{
1063	return enabled ? "on" : "off";	1063	return enabled ? "on" : "off";
1064	}	1064	}
1065		1065
1066	/* Only for pre-ILK configs */	1066	/* Only for pre-ILK configs */
1067	static void assert_pll(struct drm_i915_private *dev_priv,	1067	static void assert_pll(struct drm_i915_private *dev_priv,
1068	enum pipe pipe, bool state)	1068	enum pipe pipe, bool state)
1069	{	1069	{
1070	int reg;	1070	int reg;
1071	u32 val;	1071	u32 val;
1072	bool cur_state;	1072	bool cur_state;
1073		1073
1074	reg = DPLL(pipe);	1074	reg = DPLL(pipe);
1075	val = I915_READ(reg);	1075	val = I915_READ(reg);
1076	cur_state = !!(val & DPLL_VCO_ENABLE);	1076	cur_state = !!(val & DPLL_VCO_ENABLE);
1077	WARN(cur_state != state,	1077	WARN(cur_state != state,
1078	"PLL state assertion failure (expected %s, current %s)\n",	1078	"PLL state assertion failure (expected %s, current %s)\n",
1079	state_string(state), state_string(cur_state));	1079	state_string(state), state_string(cur_state));
1080	}	1080	}
1081	#define assert_pll_enabled(d, p) assert_pll(d, p, true)	1081	#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082	#define assert_pll_disabled(d, p) assert_pll(d, p, false)	1082	#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083		1083
1084	/* For ILK+ */	1084	/* For ILK+ */
1085	static void assert_pch_pll(struct drm_i915_private *dev_priv,	1085	static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086	enum pipe pipe, bool state)	1086	enum pipe pipe, bool state)
1087	{	1087	{
1088	int reg;	1088	int reg;
1089	u32 val;	1089	u32 val;
1090	bool cur_state;	1090	bool cur_state;
1091		1091
1092	reg = PCH_DPLL(pipe);	1092	reg = PCH_DPLL(pipe);
1093	val = I915_READ(reg);	1093	val = I915_READ(reg);
1094	cur_state = !!(val & DPLL_VCO_ENABLE);	1094	cur_state = !!(val & DPLL_VCO_ENABLE);
1095	WARN(cur_state != state,	1095	WARN(cur_state != state,
1096	"PCH PLL state assertion failure (expected %s, current %s)\n",	1096	"PCH PLL state assertion failure (expected %s, current %s)\n",
1097	state_string(state), state_string(cur_state));	1097	state_string(state), state_string(cur_state));
1098	}	1098	}
1099	#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)	1099	#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100	#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)	1100	#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101		1101
1102	static void assert_fdi_tx(struct drm_i915_private *dev_priv,	1102	static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103	enum pipe pipe, bool state)	1103	enum pipe pipe, bool state)
1104	{	1104	{
1105	int reg;	1105	int reg;
1106	u32 val;	1106	u32 val;
1107	bool cur_state;	1107	bool cur_state;
1108		1108
1109	reg = FDI_TX_CTL(pipe);	1109	reg = FDI_TX_CTL(pipe);
1110	val = I915_READ(reg);	1110	val = I915_READ(reg);
1111	cur_state = !!(val & FDI_TX_ENABLE);	1111	cur_state = !!(val & FDI_TX_ENABLE);
1112	WARN(cur_state != state,	1112	WARN(cur_state != state,
1113	"FDI TX state assertion failure (expected %s, current %s)\n",	1113	"FDI TX state assertion failure (expected %s, current %s)\n",
1114	state_string(state), state_string(cur_state));	1114	state_string(state), state_string(cur_state));
1115	}	1115	}
1116	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)	1116	#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)	1117	#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118		1118
1119	static void assert_fdi_rx(struct drm_i915_private *dev_priv,	1119	static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120	enum pipe pipe, bool state)	1120	enum pipe pipe, bool state)
1121	{	1121	{
1122	int reg;	1122	int reg;
1123	u32 val;	1123	u32 val;
1124	bool cur_state;	1124	bool cur_state;
1125		1125
1126	reg = FDI_RX_CTL(pipe);	1126	reg = FDI_RX_CTL(pipe);
1127	val = I915_READ(reg);	1127	val = I915_READ(reg);
1128	cur_state = !!(val & FDI_RX_ENABLE);	1128	cur_state = !!(val & FDI_RX_ENABLE);
1129	WARN(cur_state != state,	1129	WARN(cur_state != state,
1130	"FDI RX state assertion failure (expected %s, current %s)\n",	1130	"FDI RX state assertion failure (expected %s, current %s)\n",
1131	state_string(state), state_string(cur_state));	1131	state_string(state), state_string(cur_state));
1132	}	1132	}
1133	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)	1133	#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)	1134	#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135		1135
1136	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,	1136	static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137	enum pipe pipe)	1137	enum pipe pipe)
1138	{	1138	{
1139	int reg;	1139	int reg;
1140	u32 val;	1140	u32 val;
1141		1141
1142	/* ILK FDI PLL is always enabled */	1142	/* ILK FDI PLL is always enabled */
1143	if (dev_priv->info->gen == 5)	1143	if (dev_priv->info->gen == 5)
1144	return;	1144	return;
1145		1145
1146	reg = FDI_TX_CTL(pipe);	1146	reg = FDI_TX_CTL(pipe);
1147	val = I915_READ(reg);	1147	val = I915_READ(reg);
1148	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");	1148	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149	}	1149	}
1150		1150
1151	static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,	1151	static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152	enum pipe pipe)	1152	enum pipe pipe)
1153	{	1153	{
1154	int reg;	1154	int reg;
1155	u32 val;	1155	u32 val;
1156		1156
1157	reg = FDI_RX_CTL(pipe);	1157	reg = FDI_RX_CTL(pipe);
1158	val = I915_READ(reg);	1158	val = I915_READ(reg);
1159	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");	1159	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160	}	1160	}
1161		1161
1162	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,	1162	static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163	enum pipe pipe)	1163	enum pipe pipe)
1164	{	1164	{
1165	int pp_reg, lvds_reg;	1165	int pp_reg, lvds_reg;
1166	u32 val;	1166	u32 val;
1167	enum pipe panel_pipe = PIPE_A;	1167	enum pipe panel_pipe = PIPE_A;
1168	bool locked = locked;	1168	bool locked = locked;
1169		1169
1170	if (HAS_PCH_SPLIT(dev_priv->dev)) {	1170	if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171	pp_reg = PCH_PP_CONTROL;	1171	pp_reg = PCH_PP_CONTROL;
1172	lvds_reg = PCH_LVDS;	1172	lvds_reg = PCH_LVDS;
1173	} else {	1173	} else {
1174	pp_reg = PP_CONTROL;	1174	pp_reg = PP_CONTROL;
1175	lvds_reg = LVDS;	1175	lvds_reg = LVDS;
1176	}	1176	}
1177		1177
1178	val = I915_READ(pp_reg);	1178	val = I915_READ(pp_reg);
1179	if (!(val & PANEL_POWER_ON) \|\|	1179	if (!(val & PANEL_POWER_ON) \|\|
1180	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))	1180	((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181	locked = false;	1181	locked = false;
1182		1182
1183	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)	1183	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184	panel_pipe = PIPE_B;	1184	panel_pipe = PIPE_B;
1185		1185
1186	WARN(panel_pipe == pipe && locked,	1186	WARN(panel_pipe == pipe && locked,
1187	"panel assertion failure, pipe %c regs locked\n",	1187	"panel assertion failure, pipe %c regs locked\n",
1188	pipe_name(pipe));	1188	pipe_name(pipe));
1189	}	1189	}
1190		1190
1191	static void assert_pipe(struct drm_i915_private *dev_priv,	1191	static void assert_pipe(struct drm_i915_private *dev_priv,
1192	enum pipe pipe, bool state)	1192	enum pipe pipe, bool state)
1193	{	1193	{
1194	int reg;	1194	int reg;
1195	u32 val;	1195	u32 val;
1196	bool cur_state;	1196	bool cur_state;
1197		1197
1198	reg = PIPECONF(pipe);	1198	reg = PIPECONF(pipe);
1199	val = I915_READ(reg);	1199	val = I915_READ(reg);
1200	cur_state = !!(val & PIPECONF_ENABLE);	1200	cur_state = !!(val & PIPECONF_ENABLE);
1201	WARN(cur_state != state,	1201	WARN(cur_state != state,
1202	"pipe %c assertion failure (expected %s, current %s)\n",	1202	"pipe %c assertion failure (expected %s, current %s)\n",
1203	pipe_name(pipe), state_string(state), state_string(cur_state));	1203	pipe_name(pipe), state_string(state), state_string(cur_state));
1204	}	1204	}
1205	#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)	1205	#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206	#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)	1206	#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1207		1207
1208	static void assert_plane_enabled(struct drm_i915_private *dev_priv,	1208	static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209	enum plane plane)	1209	enum plane plane)
1210	{	1210	{
1211	int reg;	1211	int reg;
1212	u32 val;	1212	u32 val;
1213		1213
1214	reg = DSPCNTR(plane);	1214	reg = DSPCNTR(plane);
1215	val = I915_READ(reg);	1215	val = I915_READ(reg);
1216	WARN(!(val & DISPLAY_PLANE_ENABLE),	1216	WARN(!(val & DISPLAY_PLANE_ENABLE),
1217	"plane %c assertion failure, should be active but is disabled\n",	1217	"plane %c assertion failure, should be active but is disabled\n",
1218	plane_name(plane));	1218	plane_name(plane));
1219	}	1219	}
1220		1220
1221	static void assert_planes_disabled(struct drm_i915_private *dev_priv,	1221	static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222	enum pipe pipe)	1222	enum pipe pipe)
1223	{	1223	{
1224	int reg, i;	1224	int reg, i;
1225	u32 val;	1225	u32 val;
1226	int cur_pipe;	1226	int cur_pipe;
1227		1227
1228	/* Planes are fixed to pipes on ILK+ */	1228	/* Planes are fixed to pipes on ILK+ */
1229	if (HAS_PCH_SPLIT(dev_priv->dev))	1229	if (HAS_PCH_SPLIT(dev_priv->dev))
1230	return;	1230	return;
1231		1231
1232	/* Need to check both planes against the pipe */	1232	/* Need to check both planes against the pipe */
1233	for (i = 0; i < 2; i++) {	1233	for (i = 0; i < 2; i++) {
1234	reg = DSPCNTR(i);	1234	reg = DSPCNTR(i);
1235	val = I915_READ(reg);	1235	val = I915_READ(reg);
1236	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>	1236	cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1237	DISPPLANE_SEL_PIPE_SHIFT;	1237	DISPPLANE_SEL_PIPE_SHIFT;
1238	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,	1238	WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1239	"plane %c assertion failure, should be off on pipe %c but is still active\n",	1239	"plane %c assertion failure, should be off on pipe %c but is still active\n",
1240	plane_name(i), pipe_name(pipe));	1240	plane_name(i), pipe_name(pipe));
1241	}	1241	}
1242	}	1242	}
1243		1243
1244	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)	1244	static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1245	{	1245	{
1246	u32 val;	1246	u32 val;
1247	bool enabled;	1247	bool enabled;
1248		1248
1249	val = I915_READ(PCH_DREF_CONTROL);	1249	val = I915_READ(PCH_DREF_CONTROL);
1250	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|	1250	enabled = !!(val & (DREF_SSC_SOURCE_MASK \| DREF_NONSPREAD_SOURCE_MASK \|
1251	DREF_SUPERSPREAD_SOURCE_MASK));	1251	DREF_SUPERSPREAD_SOURCE_MASK));
1252	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");	1252	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1253	}	1253	}
1254		1254
1255	static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,	1255	static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1256	enum pipe pipe)	1256	enum pipe pipe)
1257	{	1257	{
1258	int reg;	1258	int reg;
1259	u32 val;	1259	u32 val;
1260	bool enabled;	1260	bool enabled;
1261		1261
1262	reg = TRANSCONF(pipe);	1262	reg = TRANSCONF(pipe);
1263	val = I915_READ(reg);	1263	val = I915_READ(reg);
1264	enabled = !!(val & TRANS_ENABLE);	1264	enabled = !!(val & TRANS_ENABLE);
1265	WARN(enabled,	1265	WARN(enabled,
1266	"transcoder assertion failed, should be off on pipe %c but is still active\n",	1266	"transcoder assertion failed, should be off on pipe %c but is still active\n",
1267	pipe_name(pipe));	1267	pipe_name(pipe));
1268	}	1268	}
1269		1269
1270	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,	1270	static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271	enum pipe pipe, int reg)	1271	enum pipe pipe, int reg)
1272	{	1272	{
1273	u32 val = I915_READ(reg);	1273	u32 val = I915_READ(reg);
1274	WARN(DP_PIPE_ENABLED(val, pipe),	1274	WARN(DP_PIPE_ENABLED(val, pipe),
1275	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",	1275	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276	reg, pipe_name(pipe));	1276	reg, pipe_name(pipe));
1277	}	1277	}
1278		1278
1279	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,	1279	static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1280	enum pipe pipe, int reg)	1280	enum pipe pipe, int reg)
1281	{	1281	{
1282	u32 val = I915_READ(reg);	1282	u32 val = I915_READ(reg);
1283	WARN(HDMI_PIPE_ENABLED(val, pipe),	1283	WARN(HDMI_PIPE_ENABLED(val, pipe),
1284	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",	1284	"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1285	reg, pipe_name(pipe));	1285	reg, pipe_name(pipe));
1286	}	1286	}
1287		1287
1288	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,	1288	static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1289	enum pipe pipe)	1289	enum pipe pipe)
1290	{	1290	{
1291	int reg;	1291	int reg;
1292	u32 val;	1292	u32 val;
1293		1293
1294	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);	1294	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1295	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);	1295	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1296	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);	1296	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1297		1297
1298	reg = PCH_ADPA;	1298	reg = PCH_ADPA;
1299	val = I915_READ(reg);	1299	val = I915_READ(reg);
1300	WARN(ADPA_PIPE_ENABLED(val, pipe),	1300	WARN(ADPA_PIPE_ENABLED(val, pipe),
1301	"PCH VGA enabled on transcoder %c, should be disabled\n",	1301	"PCH VGA enabled on transcoder %c, should be disabled\n",
1302	pipe_name(pipe));	1302	pipe_name(pipe));
1303		1303
1304	reg = PCH_LVDS;	1304	reg = PCH_LVDS;
1305	val = I915_READ(reg);	1305	val = I915_READ(reg);
1306	WARN(LVDS_PIPE_ENABLED(val, pipe),	1306	WARN(LVDS_PIPE_ENABLED(val, pipe),
1307	"PCH LVDS enabled on transcoder %c, should be disabled\n",	1307	"PCH LVDS enabled on transcoder %c, should be disabled\n",
1308	pipe_name(pipe));	1308	pipe_name(pipe));
1309		1309
1310	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);	1310	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1311	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);	1311	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1312	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);	1312	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1313	}	1313	}
1314		1314
1315	/**	1315	/**
1316	* intel_enable_pll - enable a PLL	1316	* intel_enable_pll - enable a PLL
1317	* @dev_priv: i915 private structure	1317	* @dev_priv: i915 private structure
1318	* @pipe: pipe PLL to enable	1318	* @pipe: pipe PLL to enable
1319	*	1319	*
1320	* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to	1320	* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1321	* make sure the PLL reg is writable first though, since the panel write	1321	* make sure the PLL reg is writable first though, since the panel write
1322	* protect mechanism may be enabled.	1322	* protect mechanism may be enabled.
1323	*	1323	*
1324	* Note! This is for pre-ILK only.	1324	* Note! This is for pre-ILK only.
1325	*/	1325	*/
1326	static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)	1326	static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1327	{	1327	{
1328	int reg;	1328	int reg;
1329	u32 val;	1329	u32 val;
1330		1330
1331	/* No really, not for ILK+ */	1331	/* No really, not for ILK+ */
1332	BUG_ON(dev_priv->info->gen >= 5);	1332	BUG_ON(dev_priv->info->gen >= 5);
1333		1333
1334	/* PLL is protected by panel, make sure we can write it */	1334	/* PLL is protected by panel, make sure we can write it */
1335	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))	1335	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1336	assert_panel_unlocked(dev_priv, pipe);	1336	assert_panel_unlocked(dev_priv, pipe);
1337		1337
1338	reg = DPLL(pipe);	1338	reg = DPLL(pipe);
1339	val = I915_READ(reg);	1339	val = I915_READ(reg);
1340	val \|= DPLL_VCO_ENABLE;	1340	val \|= DPLL_VCO_ENABLE;
1341		1341
1342	/* We do this three times for luck */	1342	/* We do this three times for luck */
1343	I915_WRITE(reg, val);	1343	I915_WRITE(reg, val);
1344	POSTING_READ(reg);	1344	POSTING_READ(reg);
1345	udelay(150); /* wait for warmup */	1345	udelay(150); /* wait for warmup */
1346	I915_WRITE(reg, val);	1346	I915_WRITE(reg, val);
1347	POSTING_READ(reg);	1347	POSTING_READ(reg);
1348	udelay(150); /* wait for warmup */	1348	udelay(150); /* wait for warmup */
1349	I915_WRITE(reg, val);	1349	I915_WRITE(reg, val);
1350	POSTING_READ(reg);	1350	POSTING_READ(reg);
1351	udelay(150); /* wait for warmup */	1351	udelay(150); /* wait for warmup */
1352	}	1352	}
1353		1353
1354	/**	1354	/**
1355	* intel_disable_pll - disable a PLL	1355	* intel_disable_pll - disable a PLL
1356	* @dev_priv: i915 private structure	1356	* @dev_priv: i915 private structure
1357	* @pipe: pipe PLL to disable	1357	* @pipe: pipe PLL to disable
1358	*	1358	*
1359	* Disable the PLL for @pipe, making sure the pipe is off first.	1359	* Disable the PLL for @pipe, making sure the pipe is off first.
1360	*	1360	*
1361	* Note! This is for pre-ILK only.	1361	* Note! This is for pre-ILK only.
1362	*/	1362	*/
1363	static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)	1363	static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1364	{	1364	{
1365	int reg;	1365	int reg;
1366	u32 val;	1366	u32 val;
1367		1367
1368	/* Don't disable pipe A or pipe A PLLs if needed */	1368	/* Don't disable pipe A or pipe A PLLs if needed */
1369	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))	1369	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1370	return;	1370	return;
1371		1371
1372	/* Make sure the pipe isn't still relying on us */	1372	/* Make sure the pipe isn't still relying on us */
1373	assert_pipe_disabled(dev_priv, pipe);	1373	assert_pipe_disabled(dev_priv, pipe);
1374		1374
1375	reg = DPLL(pipe);	1375	reg = DPLL(pipe);
1376	val = I915_READ(reg);	1376	val = I915_READ(reg);
1377	val &= ~DPLL_VCO_ENABLE;	1377	val &= ~DPLL_VCO_ENABLE;
1378	I915_WRITE(reg, val);	1378	I915_WRITE(reg, val);
1379	POSTING_READ(reg);	1379	POSTING_READ(reg);
1380	}	1380	}
1381		1381
1382	/**	1382	/**
1383	* intel_enable_pch_pll - enable PCH PLL	1383	* intel_enable_pch_pll - enable PCH PLL
1384	* @dev_priv: i915 private structure	1384	* @dev_priv: i915 private structure
1385	* @pipe: pipe PLL to enable	1385	* @pipe: pipe PLL to enable
1386	*	1386	*
1387	* The PCH PLL needs to be enabled before the PCH transcoder, since it	1387	* The PCH PLL needs to be enabled before the PCH transcoder, since it
1388	* drives the transcoder clock.	1388	* drives the transcoder clock.
1389	*/	1389	*/
1390	static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,	1390	static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1391	enum pipe pipe)	1391	enum pipe pipe)
1392	{	1392	{
1393	int reg;	1393	int reg;
1394	u32 val;	1394	u32 val;
1395		1395
1396	/* PCH only available on ILK+ */	1396	/* PCH only available on ILK+ */
1397	BUG_ON(dev_priv->info->gen < 5);	1397	BUG_ON(dev_priv->info->gen < 5);
1398		1398
1399	/* PCH refclock must be enabled first */	1399	/* PCH refclock must be enabled first */
1400	assert_pch_refclk_enabled(dev_priv);	1400	assert_pch_refclk_enabled(dev_priv);
1401		1401
1402	reg = PCH_DPLL(pipe);	1402	reg = PCH_DPLL(pipe);
1403	val = I915_READ(reg);	1403	val = I915_READ(reg);
1404	val \|= DPLL_VCO_ENABLE;	1404	val \|= DPLL_VCO_ENABLE;
1405	I915_WRITE(reg, val);	1405	I915_WRITE(reg, val);
1406	POSTING_READ(reg);	1406	POSTING_READ(reg);
1407	udelay(200);	1407	udelay(200);
1408	}	1408	}
1409		1409
1410	static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,	1410	static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1411	enum pipe pipe)	1411	enum pipe pipe)
1412	{	1412	{
1413	int reg;	1413	int reg;
1414	u32 val;	1414	u32 val;
1415		1415
1416	/* PCH only available on ILK+ */	1416	/* PCH only available on ILK+ */
1417	BUG_ON(dev_priv->info->gen < 5);	1417	BUG_ON(dev_priv->info->gen < 5);
1418		1418
1419	/* Make sure transcoder isn't still depending on us */	1419	/* Make sure transcoder isn't still depending on us */
1420	assert_transcoder_disabled(dev_priv, pipe);	1420	assert_transcoder_disabled(dev_priv, pipe);
1421		1421
1422	reg = PCH_DPLL(pipe);	1422	reg = PCH_DPLL(pipe);
1423	val = I915_READ(reg);	1423	val = I915_READ(reg);
1424	val &= ~DPLL_VCO_ENABLE;	1424	val &= ~DPLL_VCO_ENABLE;
1425	I915_WRITE(reg, val);	1425	I915_WRITE(reg, val);
1426	POSTING_READ(reg);	1426	POSTING_READ(reg);
1427	udelay(200);	1427	udelay(200);
1428	}	1428	}
1429		1429
1430	static void intel_enable_transcoder(struct drm_i915_private *dev_priv,	1430	static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1431	enum pipe pipe)	1431	enum pipe pipe)
1432	{	1432	{
1433	int reg;	1433	int reg;
1434	u32 val;	1434	u32 val;
1435		1435
1436	/* PCH only available on ILK+ */	1436	/* PCH only available on ILK+ */
1437	BUG_ON(dev_priv->info->gen < 5);	1437	BUG_ON(dev_priv->info->gen < 5);
1438		1438
1439	/* Make sure PCH DPLL is enabled */	1439	/* Make sure PCH DPLL is enabled */
1440	assert_pch_pll_enabled(dev_priv, pipe);	1440	assert_pch_pll_enabled(dev_priv, pipe);
1441		1441
1442	/* FDI must be feeding us bits for PCH ports */	1442	/* FDI must be feeding us bits for PCH ports */
1443	assert_fdi_tx_enabled(dev_priv, pipe);	1443	assert_fdi_tx_enabled(dev_priv, pipe);
1444	assert_fdi_rx_enabled(dev_priv, pipe);	1444	assert_fdi_rx_enabled(dev_priv, pipe);
1445		1445
1446	reg = TRANSCONF(pipe);	1446	reg = TRANSCONF(pipe);
1447	val = I915_READ(reg);	1447	val = I915_READ(reg);
1448	/*	1448	/*
1449	* make the BPC in transcoder be consistent with	1449	* make the BPC in transcoder be consistent with
1450	* that in pipeconf reg.	1450	* that in pipeconf reg.
1451	*/	1451	*/
1452	val &= ~PIPE_BPC_MASK;	1452	val &= ~PIPE_BPC_MASK;
1453	val \|= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;	1453	val \|= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1454	I915_WRITE(reg, val \| TRANS_ENABLE);	1454	I915_WRITE(reg, val \| TRANS_ENABLE);
1455	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))	1455	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1456	DRM_ERROR("failed to enable transcoder %d\n", pipe);	1456	DRM_ERROR("failed to enable transcoder %d\n", pipe);
1457	}	1457	}
1458		1458
1459	static void intel_disable_transcoder(struct drm_i915_private *dev_priv,	1459	static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1460	enum pipe pipe)	1460	enum pipe pipe)
1461	{	1461	{
1462	int reg;	1462	int reg;
1463	u32 val;	1463	u32 val;
1464		1464
1465	/* FDI relies on the transcoder */	1465	/* FDI relies on the transcoder */
1466	assert_fdi_tx_disabled(dev_priv, pipe);	1466	assert_fdi_tx_disabled(dev_priv, pipe);
1467	assert_fdi_rx_disabled(dev_priv, pipe);	1467	assert_fdi_rx_disabled(dev_priv, pipe);
1468		1468
1469	/* Ports must be off as well */	1469	/* Ports must be off as well */
1470	assert_pch_ports_disabled(dev_priv, pipe);	1470	assert_pch_ports_disabled(dev_priv, pipe);
1471		1471
1472	reg = TRANSCONF(pipe);	1472	reg = TRANSCONF(pipe);
1473	val = I915_READ(reg);	1473	val = I915_READ(reg);
1474	val &= ~TRANS_ENABLE;	1474	val &= ~TRANS_ENABLE;
1475	I915_WRITE(reg, val);	1475	I915_WRITE(reg, val);
1476	/* wait for PCH transcoder off, transcoder state */	1476	/* wait for PCH transcoder off, transcoder state */
1477	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))	1477	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1478	DRM_ERROR("failed to disable transcoder\n");	1478	DRM_ERROR("failed to disable transcoder\n");
1479	}	1479	}
1480		1480
1481	/**	1481	/**
1482	* intel_enable_pipe - enable a pipe, asserting requirements	1482	* intel_enable_pipe - enable a pipe, asserting requirements
1483	* @dev_priv: i915 private structure	1483	* @dev_priv: i915 private structure
1484	* @pipe: pipe to enable	1484	* @pipe: pipe to enable
1485	* @pch_port: on ILK+, is this pipe driving a PCH port or not	1485	* @pch_port: on ILK+, is this pipe driving a PCH port or not
1486	*	1486	*
1487	* Enable @pipe, making sure that various hardware specific requirements	1487	* Enable @pipe, making sure that various hardware specific requirements
1488	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.	1488	* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1489	*	1489	*
1490	* @pipe should be %PIPE_A or %PIPE_B.	1490	* @pipe should be %PIPE_A or %PIPE_B.
1491	*	1491	*
1492	* Will wait until the pipe is actually running (i.e. first vblank) before	1492	* Will wait until the pipe is actually running (i.e. first vblank) before
1493	* returning.	1493	* returning.
1494	*/	1494	*/
1495	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,	1495	static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1496	bool pch_port)	1496	bool pch_port)
1497	{	1497	{
1498	int reg;	1498	int reg;
1499	u32 val;	1499	u32 val;
1500		1500
1501	/*	1501	/*
1502	* A pipe without a PLL won't actually be able to drive bits from	1502	* A pipe without a PLL won't actually be able to drive bits from
1503	* a plane. On ILK+ the pipe PLLs are integrated, so we don't	1503	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
1504	* need the check.	1504	* need the check.
1505	*/	1505	*/
1506	if (!HAS_PCH_SPLIT(dev_priv->dev))	1506	if (!HAS_PCH_SPLIT(dev_priv->dev))
1507	assert_pll_enabled(dev_priv, pipe);	1507	assert_pll_enabled(dev_priv, pipe);
1508	else {	1508	else {
1509	if (pch_port) {	1509	if (pch_port) {
1510	/* if driving the PCH, we need FDI enabled */	1510	/* if driving the PCH, we need FDI enabled */
1511	assert_fdi_rx_pll_enabled(dev_priv, pipe);	1511	assert_fdi_rx_pll_enabled(dev_priv, pipe);
1512	assert_fdi_tx_pll_enabled(dev_priv, pipe);	1512	assert_fdi_tx_pll_enabled(dev_priv, pipe);
1513	}	1513	}
1514	/* FIXME: assert CPU port conditions for SNB+ */	1514	/* FIXME: assert CPU port conditions for SNB+ */
1515	}	1515	}
1516		1516
1517	reg = PIPECONF(pipe);	1517	reg = PIPECONF(pipe);
1518	val = I915_READ(reg);	1518	val = I915_READ(reg);
1519	if (val & PIPECONF_ENABLE)	1519	if (val & PIPECONF_ENABLE)
1520	return;	1520	return;
1521		1521
1522	I915_WRITE(reg, val \| PIPECONF_ENABLE);	1522	I915_WRITE(reg, val \| PIPECONF_ENABLE);
1523	intel_wait_for_vblank(dev_priv->dev, pipe);	1523	intel_wait_for_vblank(dev_priv->dev, pipe);
1524	}	1524	}
1525		1525
1526	/**	1526	/**
1527	* intel_disable_pipe - disable a pipe, asserting requirements	1527	* intel_disable_pipe - disable a pipe, asserting requirements
1528	* @dev_priv: i915 private structure	1528	* @dev_priv: i915 private structure
1529	* @pipe: pipe to disable	1529	* @pipe: pipe to disable
1530	*	1530	*
1531	* Disable @pipe, making sure that various hardware specific requirements	1531	* Disable @pipe, making sure that various hardware specific requirements
1532	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.	1532	* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1533	*	1533	*
1534	* @pipe should be %PIPE_A or %PIPE_B.	1534	* @pipe should be %PIPE_A or %PIPE_B.
1535	*	1535	*
1536	* Will wait until the pipe has shut down before returning.	1536	* Will wait until the pipe has shut down before returning.
1537	*/	1537	*/
1538	static void intel_disable_pipe(struct drm_i915_private *dev_priv,	1538	static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1539	enum pipe pipe)	1539	enum pipe pipe)
1540	{	1540	{
1541	int reg;	1541	int reg;
1542	u32 val;	1542	u32 val;
1543		1543
1544	/*	1544	/*
1545	* Make sure planes won't keep trying to pump pixels to us,	1545	* Make sure planes won't keep trying to pump pixels to us,
1546	* or we might hang the display.	1546	* or we might hang the display.
1547	*/	1547	*/
1548	assert_planes_disabled(dev_priv, pipe);	1548	assert_planes_disabled(dev_priv, pipe);
1549		1549
1550	/* Don't disable pipe A or pipe A PLLs if needed */	1550	/* Don't disable pipe A or pipe A PLLs if needed */
1551	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))	1551	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1552	return;	1552	return;
1553		1553
1554	reg = PIPECONF(pipe);	1554	reg = PIPECONF(pipe);
1555	val = I915_READ(reg);	1555	val = I915_READ(reg);
1556	if ((val & PIPECONF_ENABLE) == 0)	1556	if ((val & PIPECONF_ENABLE) == 0)
1557	return;	1557	return;
1558		1558
1559	I915_WRITE(reg, val & ~PIPECONF_ENABLE);	1559	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1560	intel_wait_for_pipe_off(dev_priv->dev, pipe);	1560	intel_wait_for_pipe_off(dev_priv->dev, pipe);
1561	}	1561	}
1562		1562
1563	/**	1563	/**
1564	* intel_enable_plane - enable a display plane on a given pipe	1564	* intel_enable_plane - enable a display plane on a given pipe
1565	* @dev_priv: i915 private structure	1565	* @dev_priv: i915 private structure
1566	* @plane: plane to enable	1566	* @plane: plane to enable
1567	* @pipe: pipe being fed	1567	* @pipe: pipe being fed
1568	*	1568	*
1569	* Enable @plane on @pipe, making sure that @pipe is running first.	1569	* Enable @plane on @pipe, making sure that @pipe is running first.
1570	*/	1570	*/
1571	static void intel_enable_plane(struct drm_i915_private *dev_priv,	1571	static void intel_enable_plane(struct drm_i915_private *dev_priv,
1572	enum plane plane, enum pipe pipe)	1572	enum plane plane, enum pipe pipe)
1573	{	1573	{
1574	int reg;	1574	int reg;
1575	u32 val;	1575	u32 val;
1576		1576
1577	/* If the pipe isn't enabled, we can't pump pixels and may hang */	1577	/* If the pipe isn't enabled, we can't pump pixels and may hang */
1578	assert_pipe_enabled(dev_priv, pipe);	1578	assert_pipe_enabled(dev_priv, pipe);
1579		1579
1580	reg = DSPCNTR(plane);	1580	reg = DSPCNTR(plane);
1581	val = I915_READ(reg);	1581	val = I915_READ(reg);
1582	if (val & DISPLAY_PLANE_ENABLE)	1582	if (val & DISPLAY_PLANE_ENABLE)
1583	return;	1583	return;
1584		1584
1585	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);	1585	I915_WRITE(reg, val \| DISPLAY_PLANE_ENABLE);
1586	intel_wait_for_vblank(dev_priv->dev, pipe);	1586	intel_wait_for_vblank(dev_priv->dev, pipe);
1587	}	1587	}
1588		1588
1589	/*	1589	/*
1590	* Plane regs are double buffered, going from enabled->disabled needs a	1590	* Plane regs are double buffered, going from enabled->disabled needs a
1591	* trigger in order to latch. The display address reg provides this.	1591	* trigger in order to latch. The display address reg provides this.
1592	*/	1592	*/
1593	static void intel_flush_display_plane(struct drm_i915_private *dev_priv,	1593	static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1594	enum plane plane)	1594	enum plane plane)
1595	{	1595	{
1596	u32 reg = DSPADDR(plane);	1596	u32 reg = DSPADDR(plane);
1597	I915_WRITE(reg, I915_READ(reg));	1597	I915_WRITE(reg, I915_READ(reg));
1598	}	1598	}
1599		1599
1600	/**	1600	/**
1601	* intel_disable_plane - disable a display plane	1601	* intel_disable_plane - disable a display plane
1602	* @dev_priv: i915 private structure	1602	* @dev_priv: i915 private structure
1603	* @plane: plane to disable	1603	* @plane: plane to disable
1604	* @pipe: pipe consuming the data	1604	* @pipe: pipe consuming the data
1605	*	1605	*
1606	* Disable @plane; should be an independent operation.	1606	* Disable @plane; should be an independent operation.
1607	*/	1607	*/
1608	static void intel_disable_plane(struct drm_i915_private *dev_priv,	1608	static void intel_disable_plane(struct drm_i915_private *dev_priv,
1609	enum plane plane, enum pipe pipe)	1609	enum plane plane, enum pipe pipe)
1610	{	1610	{
1611	int reg;	1611	int reg;
1612	u32 val;	1612	u32 val;
1613		1613
1614	reg = DSPCNTR(plane);	1614	reg = DSPCNTR(plane);
1615	val = I915_READ(reg);	1615	val = I915_READ(reg);
1616	if ((val & DISPLAY_PLANE_ENABLE) == 0)	1616	if ((val & DISPLAY_PLANE_ENABLE) == 0)
1617	return;	1617	return;
1618		1618
1619	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);	1619	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1620	intel_flush_display_plane(dev_priv, plane);	1620	intel_flush_display_plane(dev_priv, plane);
1621	intel_wait_for_vblank(dev_priv->dev, pipe);	1621	intel_wait_for_vblank(dev_priv->dev, pipe);
1622	}	1622	}
1623		1623
1624	static void disable_pch_dp(struct drm_i915_private *dev_priv,	1624	static void disable_pch_dp(struct drm_i915_private *dev_priv,
1625	enum pipe pipe, int reg)	1625	enum pipe pipe, int reg)
1626	{	1626	{
1627	u32 val = I915_READ(reg);	1627	u32 val = I915_READ(reg);
1628	if (DP_PIPE_ENABLED(val, pipe))	1628	if (DP_PIPE_ENABLED(val, pipe))
1629	I915_WRITE(reg, val & ~DP_PORT_EN);	1629	I915_WRITE(reg, val & ~DP_PORT_EN);
1630	}	1630	}
1631		1631
1632	static void disable_pch_hdmi(struct drm_i915_private *dev_priv,	1632	static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1633	enum pipe pipe, int reg)	1633	enum pipe pipe, int reg)
1634	{	1634	{
1635	u32 val = I915_READ(reg);	1635	u32 val = I915_READ(reg);
1636	if (HDMI_PIPE_ENABLED(val, pipe))	1636	if (HDMI_PIPE_ENABLED(val, pipe))
1637	I915_WRITE(reg, val & ~PORT_ENABLE);	1637	I915_WRITE(reg, val & ~PORT_ENABLE);
1638	}	1638	}
1639		1639
1640	/* Disable any ports connected to this transcoder */	1640	/* Disable any ports connected to this transcoder */
1641	static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,	1641	static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1642	enum pipe pipe)	1642	enum pipe pipe)
1643	{	1643	{
1644	u32 reg, val;	1644	u32 reg, val;
1645		1645
1646	val = I915_READ(PCH_PP_CONTROL);	1646	val = I915_READ(PCH_PP_CONTROL);
1647	I915_WRITE(PCH_PP_CONTROL, val \| PANEL_UNLOCK_REGS);	1647	I915_WRITE(PCH_PP_CONTROL, val \| PANEL_UNLOCK_REGS);
1648		1648
1649	disable_pch_dp(dev_priv, pipe, PCH_DP_B);	1649	disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1650	disable_pch_dp(dev_priv, pipe, PCH_DP_C);	1650	disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1651	disable_pch_dp(dev_priv, pipe, PCH_DP_D);	1651	disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1652		1652
1653	reg = PCH_ADPA;	1653	reg = PCH_ADPA;
1654	val = I915_READ(reg);	1654	val = I915_READ(reg);
1655	if (ADPA_PIPE_ENABLED(val, pipe))	1655	if (ADPA_PIPE_ENABLED(val, pipe))
1656	I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);	1656	I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1657		1657
1658	reg = PCH_LVDS;	1658	reg = PCH_LVDS;
1659	val = I915_READ(reg);	1659	val = I915_READ(reg);
1660	if (LVDS_PIPE_ENABLED(val, pipe)) {	1660	if (LVDS_PIPE_ENABLED(val, pipe)) {
1661	I915_WRITE(reg, val & ~LVDS_PORT_EN);	1661	I915_WRITE(reg, val & ~LVDS_PORT_EN);
1662	POSTING_READ(reg);	1662	POSTING_READ(reg);
1663	udelay(100);	1663	udelay(100);
1664	}	1664	}
1665		1665
1666	disable_pch_hdmi(dev_priv, pipe, HDMIB);	1666	disable_pch_hdmi(dev_priv, pipe, HDMIB);
1667	disable_pch_hdmi(dev_priv, pipe, HDMIC);	1667	disable_pch_hdmi(dev_priv, pipe, HDMIC);
1668	disable_pch_hdmi(dev_priv, pipe, HDMID);	1668	disable_pch_hdmi(dev_priv, pipe, HDMID);
1669	}	1669	}
1670		1670
1671	static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)	1671	static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1672	{	1672	{
1673	struct drm_device *dev = crtc->dev;	1673	struct drm_device *dev = crtc->dev;
1674	struct drm_i915_private *dev_priv = dev->dev_private;	1674	struct drm_i915_private *dev_priv = dev->dev_private;
1675	struct drm_framebuffer *fb = crtc->fb;	1675	struct drm_framebuffer *fb = crtc->fb;
1676	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);	1676	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1677	struct drm_i915_gem_object *obj = intel_fb->obj;	1677	struct drm_i915_gem_object *obj = intel_fb->obj;
1678	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	1678	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1679	int plane, i;	1679	int plane, i;
1680	u32 fbc_ctl, fbc_ctl2;	1680	u32 fbc_ctl, fbc_ctl2;
1681		1681
1682	if (fb->pitch == dev_priv->cfb_pitch &&	1682	if (fb->pitch == dev_priv->cfb_pitch &&
1683	obj->fence_reg == dev_priv->cfb_fence &&	1683	obj->fence_reg == dev_priv->cfb_fence &&
1684	intel_crtc->plane == dev_priv->cfb_plane &&	1684	intel_crtc->plane == dev_priv->cfb_plane &&
1685	I915_READ(FBC_CONTROL) & FBC_CTL_EN)	1685	I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1686	return;	1686	return;
1687		1687
1688	i8xx_disable_fbc(dev);	1688	i8xx_disable_fbc(dev);
1689		1689
1690	dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;	1690	dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1691		1691
1692	if (fb->pitch < dev_priv->cfb_pitch)	1692	if (fb->pitch < dev_priv->cfb_pitch)
1693	dev_priv->cfb_pitch = fb->pitch;	1693	dev_priv->cfb_pitch = fb->pitch;
1694		1694
1695	/* FBC_CTL wants 64B units */	1695	/* FBC_CTL wants 64B units */
1696	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;	1696	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1697	dev_priv->cfb_fence = obj->fence_reg;	1697	dev_priv->cfb_fence = obj->fence_reg;
1698	dev_priv->cfb_plane = intel_crtc->plane;	1698	dev_priv->cfb_plane = intel_crtc->plane;
1699	plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;	1699	plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1700		1700
1701	/* Clear old tags */	1701	/* Clear old tags */
1702	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)	1702	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1703	I915_WRITE(FBC_TAG + (i * 4), 0);	1703	I915_WRITE(FBC_TAG + (i * 4), 0);
1704		1704
1705	/* Set it up... */	1705	/* Set it up... */
1706	fbc_ctl2 = FBC_CTL_FENCE_DBL \| FBC_CTL_IDLE_IMM \| plane;	1706	fbc_ctl2 = FBC_CTL_FENCE_DBL \| FBC_CTL_IDLE_IMM \| plane;
1707	if (obj->tiling_mode != I915_TILING_NONE)	1707	if (obj->tiling_mode != I915_TILING_NONE)
1708	fbc_ctl2 \|= FBC_CTL_CPU_FENCE;	1708	fbc_ctl2 \|= FBC_CTL_CPU_FENCE;
1709	I915_WRITE(FBC_CONTROL2, fbc_ctl2);	1709	I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1710	I915_WRITE(FBC_FENCE_OFF, crtc->y);	1710	I915_WRITE(FBC_FENCE_OFF, crtc->y);
1711		1711
1712	/* enable it... */	1712	/* enable it... */
1713	fbc_ctl = FBC_CTL_EN \| FBC_CTL_PERIODIC;	1713	fbc_ctl = FBC_CTL_EN \| FBC_CTL_PERIODIC;
1714	if (IS_I945GM(dev))	1714	if (IS_I945GM(dev))
1715	fbc_ctl \|= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */	1715	fbc_ctl \|= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1716	fbc_ctl \|= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;	1716	fbc_ctl \|= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1717	fbc_ctl \|= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;	1717	fbc_ctl \|= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1718	if (obj->tiling_mode != I915_TILING_NONE)	1718	if (obj->tiling_mode != I915_TILING_NONE)
1719	fbc_ctl \|= dev_priv->cfb_fence;	1719	fbc_ctl \|= dev_priv->cfb_fence;
1720	I915_WRITE(FBC_CONTROL, fbc_ctl);	1720	I915_WRITE(FBC_CONTROL, fbc_ctl);
1721		1721
1722	DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",	1722	DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1723	dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);	1723	dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1724	}	1724	}
1725		1725
1726	void i8xx_disable_fbc(struct drm_device *dev)	1726	void i8xx_disable_fbc(struct drm_device *dev)
1727	{	1727	{
1728	struct drm_i915_private *dev_priv = dev->dev_private;	1728	struct drm_i915_private *dev_priv = dev->dev_private;
1729	u32 fbc_ctl;	1729	u32 fbc_ctl;
1730		1730
1731	/* Disable compression */	1731	/* Disable compression */
1732	fbc_ctl = I915_READ(FBC_CONTROL);	1732	fbc_ctl = I915_READ(FBC_CONTROL);
1733	if ((fbc_ctl & FBC_CTL_EN) == 0)	1733	if ((fbc_ctl & FBC_CTL_EN) == 0)
1734	return;	1734	return;
1735		1735
1736	fbc_ctl &= ~FBC_CTL_EN;	1736	fbc_ctl &= ~FBC_CTL_EN;
1737	I915_WRITE(FBC_CONTROL, fbc_ctl);	1737	I915_WRITE(FBC_CONTROL, fbc_ctl);
1738		1738
1739	/* Wait for compressing bit to clear */	1739	/* Wait for compressing bit to clear */
1740	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {	1740	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1741	DRM_DEBUG_KMS("FBC idle timed out\n");	1741	DRM_DEBUG_KMS("FBC idle timed out\n");
1742	return;	1742	return;
1743	}	1743	}
1744		1744
1745	DRM_DEBUG_KMS("disabled FBC\n");	1745	DRM_DEBUG_KMS("disabled FBC\n");
1746	}	1746	}
1747		1747
1748	static bool i8xx_fbc_enabled(struct drm_device *dev)	1748	static bool i8xx_fbc_enabled(struct drm_device *dev)
1749	{	1749	{
1750	struct drm_i915_private *dev_priv = dev->dev_private;	1750	struct drm_i915_private *dev_priv = dev->dev_private;
1751		1751
1752	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;	1752	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1753	}	1753	}
1754		1754
1755	static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)	1755	static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1756	{	1756	{
1757	struct drm_device *dev = crtc->dev;	1757	struct drm_device *dev = crtc->dev;
1758	struct drm_i915_private *dev_priv = dev->dev_private;	1758	struct drm_i915_private *dev_priv = dev->dev_private;
1759	struct drm_framebuffer *fb = crtc->fb;	1759	struct drm_framebuffer *fb = crtc->fb;
1760	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);	1760	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1761	struct drm_i915_gem_object *obj = intel_fb->obj;	1761	struct drm_i915_gem_object *obj = intel_fb->obj;
1762	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	1762	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1763	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;	1763	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1764	unsigned long stall_watermark = 200;	1764	unsigned long stall_watermark = 200;
1765	u32 dpfc_ctl;	1765	u32 dpfc_ctl;
1766		1766
1767	dpfc_ctl = I915_READ(DPFC_CONTROL);	1767	dpfc_ctl = I915_READ(DPFC_CONTROL);
1768	if (dpfc_ctl & DPFC_CTL_EN) {	1768	if (dpfc_ctl & DPFC_CTL_EN) {
1769	if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&	1769	if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1770	dev_priv->cfb_fence == obj->fence_reg &&	1770	dev_priv->cfb_fence == obj->fence_reg &&
1771	dev_priv->cfb_plane == intel_crtc->plane &&	1771	dev_priv->cfb_plane == intel_crtc->plane &&
1772	dev_priv->cfb_y == crtc->y)	1772	dev_priv->cfb_y == crtc->y)
1773	return;	1773	return;
1774		1774
1775	I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);	1775	I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1776	intel_wait_for_vblank(dev, intel_crtc->pipe);	1776	intel_wait_for_vblank(dev, intel_crtc->pipe);
1777	}	1777	}
1778		1778
1779	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;	1779	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1780	dev_priv->cfb_fence = obj->fence_reg;	1780	dev_priv->cfb_fence = obj->fence_reg;
1781	dev_priv->cfb_plane = intel_crtc->plane;	1781	dev_priv->cfb_plane = intel_crtc->plane;
1782	dev_priv->cfb_y = crtc->y;	1782	dev_priv->cfb_y = crtc->y;
1783		1783
1784	dpfc_ctl = plane \| DPFC_SR_EN \| DPFC_CTL_LIMIT_1X;	1784	dpfc_ctl = plane \| DPFC_SR_EN \| DPFC_CTL_LIMIT_1X;
1785	if (obj->tiling_mode != I915_TILING_NONE) {	1785	if (obj->tiling_mode != I915_TILING_NONE) {
1786	dpfc_ctl \|= DPFC_CTL_FENCE_EN \| dev_priv->cfb_fence;	1786	dpfc_ctl \|= DPFC_CTL_FENCE_EN \| dev_priv->cfb_fence;
1787	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);	1787	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1788	} else {	1788	} else {
1789	I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);	1789	I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1790	}	1790	}
1791		1791
1792	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN \|	1792	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN \|
1793	(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) \|	1793	(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) \|
1794	(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));	1794	(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1795	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);	1795	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1796		1796
1797	/* enable it... */	1797	/* enable it... */
1798	I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) \| DPFC_CTL_EN);	1798	I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) \| DPFC_CTL_EN);
1799		1799
1800	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);	1800	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1801	}	1801	}
1802		1802
1803	void g4x_disable_fbc(struct drm_device *dev)	1803	void g4x_disable_fbc(struct drm_device *dev)
1804	{	1804	{
1805	struct drm_i915_private *dev_priv = dev->dev_private;	1805	struct drm_i915_private *dev_priv = dev->dev_private;
1806	u32 dpfc_ctl;	1806	u32 dpfc_ctl;
1807		1807
1808	/* Disable compression */	1808	/* Disable compression */
1809	dpfc_ctl = I915_READ(DPFC_CONTROL);	1809	dpfc_ctl = I915_READ(DPFC_CONTROL);
1810	if (dpfc_ctl & DPFC_CTL_EN) {	1810	if (dpfc_ctl & DPFC_CTL_EN) {
1811	dpfc_ctl &= ~DPFC_CTL_EN;	1811	dpfc_ctl &= ~DPFC_CTL_EN;
1812	I915_WRITE(DPFC_CONTROL, dpfc_ctl);	1812	I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1813		1813
1814	DRM_DEBUG_KMS("disabled FBC\n");	1814	DRM_DEBUG_KMS("disabled FBC\n");
1815	}	1815	}
1816	}	1816	}
1817		1817
1818	static bool g4x_fbc_enabled(struct drm_device *dev)	1818	static bool g4x_fbc_enabled(struct drm_device *dev)
1819	{	1819	{
1820	struct drm_i915_private *dev_priv = dev->dev_private;	1820	struct drm_i915_private *dev_priv = dev->dev_private;
1821		1821
1822	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;	1822	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1823	}	1823	}
1824		1824
1825	static void sandybridge_blit_fbc_update(struct drm_device *dev)	1825	static void sandybridge_blit_fbc_update(struct drm_device *dev)
1826	{	1826	{
1827	struct drm_i915_private *dev_priv = dev->dev_private;	1827	struct drm_i915_private *dev_priv = dev->dev_private;
1828	u32 blt_ecoskpd;	1828	u32 blt_ecoskpd;
1829		1829
1830	/* Make sure blitter notifies FBC of writes */	1830	/* Make sure blitter notifies FBC of writes */
1831	__gen6_gt_force_wake_get(dev_priv);	1831	__gen6_gt_force_wake_get(dev_priv);
1832	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);	1832	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1833	blt_ecoskpd \|= GEN6_BLITTER_FBC_NOTIFY <<	1833	blt_ecoskpd \|= GEN6_BLITTER_FBC_NOTIFY <<
1834	GEN6_BLITTER_LOCK_SHIFT;	1834	GEN6_BLITTER_LOCK_SHIFT;
1835	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);	1835	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1836	blt_ecoskpd \|= GEN6_BLITTER_FBC_NOTIFY;	1836	blt_ecoskpd \|= GEN6_BLITTER_FBC_NOTIFY;
1837	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);	1837	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1838	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<	1838	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1839	GEN6_BLITTER_LOCK_SHIFT);	1839	GEN6_BLITTER_LOCK_SHIFT);
1840	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);	1840	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1841	POSTING_READ(GEN6_BLITTER_ECOSKPD);	1841	POSTING_READ(GEN6_BLITTER_ECOSKPD);
1842	__gen6_gt_force_wake_put(dev_priv);	1842	__gen6_gt_force_wake_put(dev_priv);
1843	}	1843	}
1844		1844
1845	static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)	1845	static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1846	{	1846	{
1847	struct drm_device *dev = crtc->dev;	1847	struct drm_device *dev = crtc->dev;
1848	struct drm_i915_private *dev_priv = dev->dev_private;	1848	struct drm_i915_private *dev_priv = dev->dev_private;
1849	struct drm_framebuffer *fb = crtc->fb;	1849	struct drm_framebuffer *fb = crtc->fb;
1850	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);	1850	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1851	struct drm_i915_gem_object *obj = intel_fb->obj;	1851	struct drm_i915_gem_object *obj = intel_fb->obj;
1852	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	1852	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;	1853	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1854	unsigned long stall_watermark = 200;	1854	unsigned long stall_watermark = 200;
1855	u32 dpfc_ctl;	1855	u32 dpfc_ctl;
1856		1856
1857	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);	1857	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1858	if (dpfc_ctl & DPFC_CTL_EN) {	1858	if (dpfc_ctl & DPFC_CTL_EN) {
1859	if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&	1859	if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1860	dev_priv->cfb_fence == obj->fence_reg &&	1860	dev_priv->cfb_fence == obj->fence_reg &&
1861	dev_priv->cfb_plane == intel_crtc->plane &&	1861	dev_priv->cfb_plane == intel_crtc->plane &&
1862	dev_priv->cfb_offset == obj->gtt_offset &&	1862	dev_priv->cfb_offset == obj->gtt_offset &&
1863	dev_priv->cfb_y == crtc->y)	1863	dev_priv->cfb_y == crtc->y)
1864	return;	1864	return;
1865		1865
1866	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);	1866	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1867	intel_wait_for_vblank(dev, intel_crtc->pipe);	1867	intel_wait_for_vblank(dev, intel_crtc->pipe);
1868	}	1868	}
1869		1869
1870	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;	1870	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1871	dev_priv->cfb_fence = obj->fence_reg;	1871	dev_priv->cfb_fence = obj->fence_reg;
1872	dev_priv->cfb_plane = intel_crtc->plane;	1872	dev_priv->cfb_plane = intel_crtc->plane;
1873	dev_priv->cfb_offset = obj->gtt_offset;	1873	dev_priv->cfb_offset = obj->gtt_offset;
1874	dev_priv->cfb_y = crtc->y;	1874	dev_priv->cfb_y = crtc->y;
1875		1875
1876	dpfc_ctl &= DPFC_RESERVED;	1876	dpfc_ctl &= DPFC_RESERVED;
1877	dpfc_ctl \|= (plane \| DPFC_CTL_LIMIT_1X);	1877	dpfc_ctl \|= (plane \| DPFC_CTL_LIMIT_1X);
1878	if (obj->tiling_mode != I915_TILING_NONE) {	1878	if (obj->tiling_mode != I915_TILING_NONE) {
1879	dpfc_ctl \|= (DPFC_CTL_FENCE_EN \| dev_priv->cfb_fence);	1879	dpfc_ctl \|= (DPFC_CTL_FENCE_EN \| dev_priv->cfb_fence);
1880	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);	1880	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1881	} else {	1881	} else {
1882	I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);	1882	I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1883	}	1883	}
1884		1884
1885	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN \|	1885	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN \|
1886	(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) \|	1886	(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) \|
1887	(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));	1887	(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1888	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);	1888	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1889	I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset \| ILK_FBC_RT_VALID);	1889	I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset \| ILK_FBC_RT_VALID);
1890	/* enable it... */	1890	/* enable it... */
1891	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl \| DPFC_CTL_EN);	1891	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl \| DPFC_CTL_EN);
1892		1892
1893	if (IS_GEN6(dev)) {	1893	if (IS_GEN6(dev)) {
1894	I915_WRITE(SNB_DPFC_CTL_SA,	1894	I915_WRITE(SNB_DPFC_CTL_SA,
1895	SNB_CPU_FENCE_ENABLE \| dev_priv->cfb_fence);	1895	SNB_CPU_FENCE_ENABLE \| dev_priv->cfb_fence);
1896	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);	1896	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1897	sandybridge_blit_fbc_update(dev);	1897	sandybridge_blit_fbc_update(dev);
1898	}	1898	}
1899		1899
1900	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);	1900	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1901	}	1901	}
1902		1902
1903	void ironlake_disable_fbc(struct drm_device *dev)	1903	void ironlake_disable_fbc(struct drm_device *dev)
1904	{	1904	{
1905	struct drm_i915_private *dev_priv = dev->dev_private;	1905	struct drm_i915_private *dev_priv = dev->dev_private;
1906	u32 dpfc_ctl;	1906	u32 dpfc_ctl;
1907		1907
1908	/* Disable compression */	1908	/* Disable compression */
1909	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);	1909	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1910	if (dpfc_ctl & DPFC_CTL_EN) {	1910	if (dpfc_ctl & DPFC_CTL_EN) {
1911	dpfc_ctl &= ~DPFC_CTL_EN;	1911	dpfc_ctl &= ~DPFC_CTL_EN;
1912	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);	1912	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1913		1913
1914	DRM_DEBUG_KMS("disabled FBC\n");	1914	DRM_DEBUG_KMS("disabled FBC\n");
1915	}	1915	}
1916	}	1916	}
1917		1917
1918	static bool ironlake_fbc_enabled(struct drm_device *dev)	1918	static bool ironlake_fbc_enabled(struct drm_device *dev)
1919	{	1919	{
1920	struct drm_i915_private *dev_priv = dev->dev_private;	1920	struct drm_i915_private *dev_priv = dev->dev_private;
1921		1921
1922	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;	1922	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1923	}	1923	}
1924		1924
1925	bool intel_fbc_enabled(struct drm_device *dev)	1925	bool intel_fbc_enabled(struct drm_device *dev)
1926	{	1926	{
1927	struct drm_i915_private *dev_priv = dev->dev_private;	1927	struct drm_i915_private *dev_priv = dev->dev_private;
1928		1928
1929	if (!dev_priv->display.fbc_enabled)	1929	if (!dev_priv->display.fbc_enabled)
1930	return false;	1930	return false;
1931		1931
1932	return dev_priv->display.fbc_enabled(dev);	1932	return dev_priv->display.fbc_enabled(dev);
1933	}	1933	}
1934		1934
1935	void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)	1935	void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1936	{	1936	{
1937	struct drm_i915_private *dev_priv = crtc->dev->dev_private;	1937	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1938		1938
1939	if (!dev_priv->display.enable_fbc)	1939	if (!dev_priv->display.enable_fbc)
1940	return;	1940	return;
1941		1941
1942	dev_priv->display.enable_fbc(crtc, interval);	1942	dev_priv->display.enable_fbc(crtc, interval);
1943	}	1943	}
1944		1944
1945	void intel_disable_fbc(struct drm_device *dev)	1945	void intel_disable_fbc(struct drm_device *dev)
1946	{	1946	{
1947	struct drm_i915_private *dev_priv = dev->dev_private;	1947	struct drm_i915_private *dev_priv = dev->dev_private;
1948		1948
1949	if (!dev_priv->display.disable_fbc)	1949	if (!dev_priv->display.disable_fbc)
1950	return;	1950	return;
1951		1951
1952	dev_priv->display.disable_fbc(dev);	1952	dev_priv->display.disable_fbc(dev);
1953	}	1953	}
1954		1954
1955	/**	1955	/**
1956	* intel_update_fbc - enable/disable FBC as needed	1956	* intel_update_fbc - enable/disable FBC as needed
1957	* @dev: the drm_device	1957	* @dev: the drm_device
1958	*	1958	*
1959	* Set up the framebuffer compression hardware at mode set time. We	1959	* Set up the framebuffer compression hardware at mode set time. We
1960	* enable it if possible:	1960	* enable it if possible:
1961	* - plane A only (on pre-965)	1961	* - plane A only (on pre-965)
1962	* - no pixel mulitply/line duplication	1962	* - no pixel mulitply/line duplication
1963	* - no alpha buffer discard	1963	* - no alpha buffer discard
1964	* - no dual wide	1964	* - no dual wide
1965	* - framebuffer <= 2048 in width, 1536 in height	1965	* - framebuffer <= 2048 in width, 1536 in height
1966	*	1966	*
1967	* We can't assume that any compression will take place (worst case),	1967	* We can't assume that any compression will take place (worst case),
1968	* so the compressed buffer has to be the same size as the uncompressed	1968	* so the compressed buffer has to be the same size as the uncompressed
1969	* one. It also must reside (along with the line length buffer) in	1969	* one. It also must reside (along with the line length buffer) in
1970	* stolen memory.	1970	* stolen memory.
1971	*	1971	*
1972	* We need to enable/disable FBC on a global basis.	1972	* We need to enable/disable FBC on a global basis.
1973	*/	1973	*/
1974	static void intel_update_fbc(struct drm_device *dev)	1974	static void intel_update_fbc(struct drm_device *dev)
1975	{	1975	{
1976	struct drm_i915_private *dev_priv = dev->dev_private;	1976	struct drm_i915_private *dev_priv = dev->dev_private;
1977	struct drm_crtc crtc = NULL, tmp_crtc;	1977	struct drm_crtc crtc = NULL, tmp_crtc;
1978	struct intel_crtc *intel_crtc;	1978	struct intel_crtc *intel_crtc;
1979	struct drm_framebuffer *fb;	1979	struct drm_framebuffer *fb;
1980	struct intel_framebuffer *intel_fb;	1980	struct intel_framebuffer *intel_fb;
1981	struct drm_i915_gem_object *obj;	1981	struct drm_i915_gem_object *obj;
1982		1982
1983	DRM_DEBUG_KMS("\n");	1983	DRM_DEBUG_KMS("\n");
1984		1984
1985	if (!i915_powersave)	1985	if (!i915_powersave)
1986	return;	1986	return;
1987		1987
1988	if (!I915_HAS_FBC(dev))	1988	if (!I915_HAS_FBC(dev))
1989	return;	1989	return;
1990		1990
1991	/*	1991	/*
1992	* If FBC is already on, we just have to verify that we can	1992	* If FBC is already on, we just have to verify that we can
1993	* keep it that way...	1993	* keep it that way...
1994	* Need to disable if:	1994	* Need to disable if:
1995	* - more than one pipe is active	1995	* - more than one pipe is active
1996	* - changing FBC params (stride, fence, mode)	1996	* - changing FBC params (stride, fence, mode)
1997	* - new fb is too large to fit in compressed buffer	1997	* - new fb is too large to fit in compressed buffer
1998	* - going to an unsupported config (interlace, pixel multiply, etc.)	1998	* - going to an unsupported config (interlace, pixel multiply, etc.)
1999	*/	1999	*/
2000	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {	2000	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
2001	if (tmp_crtc->enabled && tmp_crtc->fb) {	2001	if (tmp_crtc->enabled && tmp_crtc->fb) {
2002	if (crtc) {	2002	if (crtc) {
2003	DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");	2003	DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
2004	dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;	2004	dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
2005	goto out_disable;	2005	goto out_disable;
2006	}	2006	}
2007	crtc = tmp_crtc;	2007	crtc = tmp_crtc;
2008	}	2008	}
2009	}	2009	}
2010		2010
2011	if (!crtc \|\| crtc->fb == NULL) {	2011	if (!crtc \|\| crtc->fb == NULL) {
2012	DRM_DEBUG_KMS("no output, disabling\n");	2012	DRM_DEBUG_KMS("no output, disabling\n");
2013	dev_priv->no_fbc_reason = FBC_NO_OUTPUT;	2013	dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2014	goto out_disable;	2014	goto out_disable;
2015	}	2015	}
2016		2016
2017	intel_crtc = to_intel_crtc(crtc);	2017	intel_crtc = to_intel_crtc(crtc);
2018	fb = crtc->fb;	2018	fb = crtc->fb;
2019	intel_fb = to_intel_framebuffer(fb);	2019	intel_fb = to_intel_framebuffer(fb);
2020	obj = intel_fb->obj;	2020	obj = intel_fb->obj;
2021		2021
2022	if (intel_fb->obj->base.size > dev_priv->cfb_size) {	2022	if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2023	DRM_DEBUG_KMS("framebuffer too large, disabling "	2023	DRM_DEBUG_KMS("framebuffer too large, disabling "
2024	"compression\n");	2024	"compression\n");
2025	dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;	2025	dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2026	goto out_disable;	2026	goto out_disable;
2027	}	2027	}
2028	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) \|\|	2028	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) \|\|
2029	(crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {	2029	(crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
2030	DRM_DEBUG_KMS("mode incompatible with compression, "	2030	DRM_DEBUG_KMS("mode incompatible with compression, "
2031	"disabling\n");	2031	"disabling\n");
2032	dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;	2032	dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2033	goto out_disable;	2033	goto out_disable;
2034	}	2034	}
2035	if ((crtc->mode.hdisplay > 2048) \|\|	2035	if ((crtc->mode.hdisplay > 2048) \|\|
2036	(crtc->mode.vdisplay > 1536)) {	2036	(crtc->mode.vdisplay > 1536)) {
2037	DRM_DEBUG_KMS("mode too large for compression, disabling\n");	2037	DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2038	dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;	2038	dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2039	goto out_disable;	2039	goto out_disable;
2040	}	2040	}
2041	if ((IS_I915GM(dev) \|\| IS_I945GM(dev)) && intel_crtc->plane != 0) {	2041	if ((IS_I915GM(dev) \|\| IS_I945GM(dev)) && intel_crtc->plane != 0) {
2042	DRM_DEBUG_KMS("plane not 0, disabling compression\n");	2042	DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2043	dev_priv->no_fbc_reason = FBC_BAD_PLANE;	2043	dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2044	goto out_disable;	2044	goto out_disable;
2045	}	2045	}
2046	if (obj->tiling_mode != I915_TILING_X) {	2046	if (obj->tiling_mode != I915_TILING_X) {
2047	DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");	2047	DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
2048	dev_priv->no_fbc_reason = FBC_NOT_TILED;	2048	dev_priv->no_fbc_reason = FBC_NOT_TILED;
2049	goto out_disable;	2049	goto out_disable;
2050	}	2050	}
2051		2051
2052	/* If the kernel debugger is active, always disable compression */	2052	/* If the kernel debugger is active, always disable compression */
2053	if (in_dbg_master())	2053	if (in_dbg_master())
2054	goto out_disable;	2054	goto out_disable;
2055		2055
2056	intel_enable_fbc(crtc, 500);	2056	intel_enable_fbc(crtc, 500);
2057	return;	2057	return;
2058		2058
2059	out_disable:	2059	out_disable:
2060	/* Multiple disables should be harmless */	2060	/* Multiple disables should be harmless */
2061	if (intel_fbc_enabled(dev)) {	2061	if (intel_fbc_enabled(dev)) {
2062	DRM_DEBUG_KMS("unsupported config, disabling FBC\n");	2062	DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2063	intel_disable_fbc(dev);	2063	intel_disable_fbc(dev);
2064	}	2064	}
2065	}	2065	}
2066		2066
2067	int	2067	int
2068	intel_pin_and_fence_fb_obj(struct drm_device *dev,	2068	intel_pin_and_fence_fb_obj(struct drm_device *dev,
2069	struct drm_i915_gem_object *obj,	2069	struct drm_i915_gem_object *obj,
2070	struct intel_ring_buffer *pipelined)	2070	struct intel_ring_buffer *pipelined)
2071	{	2071	{
2072	struct drm_i915_private *dev_priv = dev->dev_private;	2072	struct drm_i915_private *dev_priv = dev->dev_private;
2073	u32 alignment;	2073	u32 alignment;
2074	int ret;	2074	int ret;
2075		2075
2076	switch (obj->tiling_mode) {	2076	switch (obj->tiling_mode) {
2077	case I915_TILING_NONE:	2077	case I915_TILING_NONE:
2078	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))	2078	if (IS_BROADWATER(dev) \|\| IS_CRESTLINE(dev))
2079	alignment = 128 * 1024;	2079	alignment = 128 * 1024;
2080	else if (INTEL_INFO(dev)->gen >= 4)	2080	else if (INTEL_INFO(dev)->gen >= 4)
2081	alignment = 4 * 1024;	2081	alignment = 4 * 1024;
2082	else	2082	else
2083	alignment = 64 * 1024;	2083	alignment = 64 * 1024;
2084	break;	2084	break;
2085	case I915_TILING_X:	2085	case I915_TILING_X:
2086	/* pin() will align the object as required by fence */	2086	/* pin() will align the object as required by fence */
2087	alignment = 0;	2087	alignment = 0;
2088	break;	2088	break;
2089	case I915_TILING_Y:	2089	case I915_TILING_Y:
2090	/* FIXME: Is this true? */	2090	/* FIXME: Is this true? */
2091	DRM_ERROR("Y tiled not allowed for scan out buffers\n");	2091	DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2092	return -EINVAL;	2092	return -EINVAL;
2093	default:	2093	default:
2094	BUG();	2094	BUG();
2095	}	2095	}
2096		2096
2097	dev_priv->mm.interruptible = false;	2097	dev_priv->mm.interruptible = false;
2098	ret = i915_gem_object_pin(obj, alignment, true);	2098	ret = i915_gem_object_pin(obj, alignment, true);
2099	if (ret)	2099	if (ret)
2100	goto err_interruptible;	2100	goto err_interruptible;
2101		2101
2102	ret = i915_gem_object_set_to_display_plane(obj, pipelined);	2102	ret = i915_gem_object_set_to_display_plane(obj, pipelined);
2103	if (ret)	2103	if (ret)
2104	goto err_unpin;	2104	goto err_unpin;
2105		2105
2106	/* Install a fence for tiled scan-out. Pre-i965 always needs a	2106	/* Install a fence for tiled scan-out. Pre-i965 always needs a
2107	* fence, whereas 965+ only requires a fence if using	2107	* fence, whereas 965+ only requires a fence if using
2108	* framebuffer compression. For simplicity, we always install	2108	* framebuffer compression. For simplicity, we always install
2109	* a fence as the cost is not that onerous.	2109	* a fence as the cost is not that onerous.
2110	*/	2110	*/
2111	if (obj->tiling_mode != I915_TILING_NONE) {	2111	if (obj->tiling_mode != I915_TILING_NONE) {
2112	ret = i915_gem_object_get_fence(obj, pipelined);	2112	ret = i915_gem_object_get_fence(obj, pipelined);
2113	if (ret)	2113	if (ret)
2114	goto err_unpin;	2114	goto err_unpin;
2115	}	2115	}
2116		2116
2117	dev_priv->mm.interruptible = true;	2117	dev_priv->mm.interruptible = true;
2118	return 0;	2118	return 0;
2119		2119
2120	err_unpin:	2120	err_unpin:
2121	i915_gem_object_unpin(obj);	2121	i915_gem_object_unpin(obj);
2122	err_interruptible:	2122	err_interruptible:
2123	dev_priv->mm.interruptible = true;	2123	dev_priv->mm.interruptible = true;
2124	return ret;	2124	return ret;
2125	}	2125	}
2126		2126
2127	/* Assume fb object is pinned & idle & fenced and just update base pointers */	2127	/* Assume fb object is pinned & idle & fenced and just update base pointers */
2128	static int	2128	static int
2129	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,	2129	intel_pipe_set_base_atomic(struct drm_crtc crtc, struct drm_framebuffer fb,
2130	int x, int y, enum mode_set_atomic state)	2130	int x, int y, enum mode_set_atomic state)
2131	{	2131	{
2132	struct drm_device *dev = crtc->dev;	2132	struct drm_device *dev = crtc->dev;
2133	struct drm_i915_private *dev_priv = dev->dev_private;	2133	struct drm_i915_private *dev_priv = dev->dev_private;
2134	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2134	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2135	struct intel_framebuffer *intel_fb;	2135	struct intel_framebuffer *intel_fb;
2136	struct drm_i915_gem_object *obj;	2136	struct drm_i915_gem_object *obj;
2137	int plane = intel_crtc->plane;	2137	int plane = intel_crtc->plane;
2138	unsigned long Start, Offset;	2138	unsigned long Start, Offset;
2139	u32 dspcntr;	2139	u32 dspcntr;
2140	u32 reg;	2140	u32 reg;
2141		2141
2142	switch (plane) {	2142	switch (plane) {
2143	case 0:	2143	case 0:
2144	case 1:	2144	case 1:
2145	break;	2145	break;
2146	default:	2146	default:
2147	DRM_ERROR("Can't update plane %d in SAREA\n", plane);	2147	DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2148	return -EINVAL;	2148	return -EINVAL;
2149	}	2149	}
2150		2150
2151	intel_fb = to_intel_framebuffer(fb);	2151	intel_fb = to_intel_framebuffer(fb);
2152	obj = intel_fb->obj;	2152	obj = intel_fb->obj;
2153		2153
2154	reg = DSPCNTR(plane);	2154	reg = DSPCNTR(plane);
2155	dspcntr = I915_READ(reg);	2155	dspcntr = I915_READ(reg);
2156	/* Mask out pixel format bits in case we change it */	2156	/* Mask out pixel format bits in case we change it */
2157	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;	2157	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2158	switch (fb->bits_per_pixel) {	2158	switch (fb->bits_per_pixel) {
2159	case 8:	2159	case 8:
2160	dspcntr \|= DISPPLANE_8BPP;	2160	dspcntr \|= DISPPLANE_8BPP;
2161	break;	2161	break;
2162	case 16:	2162	case 16:
2163	if (fb->depth == 15)	2163	if (fb->depth == 15)
2164	dspcntr \|= DISPPLANE_15_16BPP;	2164	dspcntr \|= DISPPLANE_15_16BPP;
2165	else	2165	else
2166	dspcntr \|= DISPPLANE_16BPP;	2166	dspcntr \|= DISPPLANE_16BPP;
2167	break;	2167	break;
2168	case 24:	2168	case 24:
2169	case 32:	2169	case 32:
2170	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;	2170	dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
2171	break;	2171	break;
2172	default:	2172	default:
2173	DRM_ERROR("Unknown color depth\n");	2173	DRM_ERROR("Unknown color depth\n");
2174	return -EINVAL;	2174	return -EINVAL;
2175	}	2175	}
2176	if (INTEL_INFO(dev)->gen >= 4) {	2176	if (INTEL_INFO(dev)->gen >= 4) {
2177	if (obj->tiling_mode != I915_TILING_NONE)	2177	if (obj->tiling_mode != I915_TILING_NONE)
2178	dspcntr \|= DISPPLANE_TILED;	2178	dspcntr \|= DISPPLANE_TILED;
2179	else	2179	else
2180	dspcntr &= ~DISPPLANE_TILED;	2180	dspcntr &= ~DISPPLANE_TILED;
2181	}	2181	}
2182		2182
2183	if (HAS_PCH_SPLIT(dev))	2183	if (HAS_PCH_SPLIT(dev))
2184	/* must disable */	2184	/* must disable */
2185	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;	2185	dspcntr \|= DISPPLANE_TRICKLE_FEED_DISABLE;
2186		2186
2187	I915_WRITE(reg, dspcntr);	2187	I915_WRITE(reg, dspcntr);
2188		2188
2189	Start = obj->gtt_offset;	2189	Start = obj->gtt_offset;
2190	Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);	2190	Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2191		2191
2192	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",	2192	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2193	Start, Offset, x, y, fb->pitch);	2193	Start, Offset, x, y, fb->pitch);
2194	I915_WRITE(DSPSTRIDE(plane), fb->pitch);	2194	I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2195	if (INTEL_INFO(dev)->gen >= 4) {	2195	if (INTEL_INFO(dev)->gen >= 4) {
2196	I915_WRITE(DSPSURF(plane), Start);	2196	I915_WRITE(DSPSURF(plane), Start);
2197	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);	2197	I915_WRITE(DSPTILEOFF(plane), (y << 16) \| x);
2198	I915_WRITE(DSPADDR(plane), Offset);	2198	I915_WRITE(DSPADDR(plane), Offset);
2199	} else	2199	} else
2200	I915_WRITE(DSPADDR(plane), Start + Offset);	2200	I915_WRITE(DSPADDR(plane), Start + Offset);
2201	POSTING_READ(reg);	2201	POSTING_READ(reg);
2202		2202
2203	intel_update_fbc(dev);	2203	intel_update_fbc(dev);
2204	intel_increase_pllclock(crtc);	2204	intel_increase_pllclock(crtc);
2205		2205
2206	return 0;	2206	return 0;
2207	}	2207	}
2208		2208
2209	static int	2209	static int
2210	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,	2210	intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2211	struct drm_framebuffer *old_fb)	2211	struct drm_framebuffer *old_fb)
2212	{	2212	{
2213	struct drm_device *dev = crtc->dev;	2213	struct drm_device *dev = crtc->dev;
2214	struct drm_i915_master_private *master_priv;	2214	struct drm_i915_master_private *master_priv;
2215	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2215	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216	int ret;	2216	int ret;
2217		2217
2218	/* no fb bound */	2218	/* no fb bound */
2219	if (!crtc->fb) {	2219	if (!crtc->fb) {
2220	DRM_DEBUG_KMS("No FB bound\n");	2220	DRM_DEBUG_KMS("No FB bound\n");
2221	return 0;	2221	return 0;
2222	}	2222	}
2223		2223
2224	switch (intel_crtc->plane) {	2224	switch (intel_crtc->plane) {
2225	case 0:	2225	case 0:
2226	case 1:	2226	case 1:
2227	break;	2227	break;
2228	default:	2228	default:
2229	return -EINVAL;	2229	return -EINVAL;
2230	}	2230	}
2231		2231
2232	mutex_lock(&dev->struct_mutex);	2232	mutex_lock(&dev->struct_mutex);
2233	ret = intel_pin_and_fence_fb_obj(dev,	2233	ret = intel_pin_and_fence_fb_obj(dev,
2234	to_intel_framebuffer(crtc->fb)->obj,	2234	to_intel_framebuffer(crtc->fb)->obj,
2235	NULL);	2235	NULL);
2236	if (ret != 0) {	2236	if (ret != 0) {
2237	mutex_unlock(&dev->struct_mutex);	2237	mutex_unlock(&dev->struct_mutex);
2238	return ret;	2238	return ret;
2239	}	2239	}
2240		2240
2241	if (old_fb) {	2241	if (old_fb) {
2242	struct drm_i915_private *dev_priv = dev->dev_private;	2242	struct drm_i915_private *dev_priv = dev->dev_private;
2243	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;	2243	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2244		2244
2245	wait_event(dev_priv->pending_flip_queue,	2245	wait_event(dev_priv->pending_flip_queue,
2246	atomic_read(&dev_priv->mm.wedged) \|\|	2246	atomic_read(&dev_priv->mm.wedged) \|\|
2247	atomic_read(&obj->pending_flip) == 0);	2247	atomic_read(&obj->pending_flip) == 0);
2248		2248
2249	/* Big Hammer, we also need to ensure that any pending	2249	/* Big Hammer, we also need to ensure that any pending
2250	* MI_WAIT_FOR_EVENT inside a user batch buffer on the	2250	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251	* current scanout is retired before unpinning the old	2251	* current scanout is retired before unpinning the old
2252	* framebuffer.	2252	* framebuffer.
2253	*	2253	*
2254	* This should only fail upon a hung GPU, in which case we	2254	* This should only fail upon a hung GPU, in which case we
2255	* can safely continue.	2255	* can safely continue.
2256	*/	2256	*/
2257	ret = i915_gem_object_flush_gpu(obj);	2257	ret = i915_gem_object_flush_gpu(obj);
2258	(void) ret;	2258	(void) ret;
2259	}	2259	}
2260		2260
2261	ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,	2261	ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2262	LEAVE_ATOMIC_MODE_SET);	2262	LEAVE_ATOMIC_MODE_SET);
2263	if (ret) {	2263	if (ret) {
2264	i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);	2264	i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2265	mutex_unlock(&dev->struct_mutex);	2265	mutex_unlock(&dev->struct_mutex);
2266	return ret;	2266	return ret;
2267	}	2267	}
2268		2268
2269	if (old_fb) {	2269	if (old_fb) {
2270	intel_wait_for_vblank(dev, intel_crtc->pipe);	2270	intel_wait_for_vblank(dev, intel_crtc->pipe);
2271	i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);	2271	i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2272	}	2272	}
2273		2273
2274	mutex_unlock(&dev->struct_mutex);	2274	mutex_unlock(&dev->struct_mutex);
2275		2275
2276	if (!dev->primary->master)	2276	if (!dev->primary->master)
2277	return 0;	2277	return 0;
2278		2278
2279	master_priv = dev->primary->master->driver_priv;	2279	master_priv = dev->primary->master->driver_priv;
2280	if (!master_priv->sarea_priv)	2280	if (!master_priv->sarea_priv)
2281	return 0;	2281	return 0;
2282		2282
2283	if (intel_crtc->pipe) {	2283	if (intel_crtc->pipe) {
2284	master_priv->sarea_priv->pipeB_x = x;	2284	master_priv->sarea_priv->pipeB_x = x;
2285	master_priv->sarea_priv->pipeB_y = y;	2285	master_priv->sarea_priv->pipeB_y = y;
2286	} else {	2286	} else {
2287	master_priv->sarea_priv->pipeA_x = x;	2287	master_priv->sarea_priv->pipeA_x = x;
2288	master_priv->sarea_priv->pipeA_y = y;	2288	master_priv->sarea_priv->pipeA_y = y;
2289	}	2289	}
2290		2290
2291	return 0;	2291	return 0;
2292	}	2292	}
2293		2293
2294	static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)	2294	static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2295	{	2295	{
2296	struct drm_device *dev = crtc->dev;	2296	struct drm_device *dev = crtc->dev;
2297	struct drm_i915_private *dev_priv = dev->dev_private;	2297	struct drm_i915_private *dev_priv = dev->dev_private;
2298	u32 dpa_ctl;	2298	u32 dpa_ctl;
2299		2299
2300	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);	2300	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2301	dpa_ctl = I915_READ(DP_A);	2301	dpa_ctl = I915_READ(DP_A);
2302	dpa_ctl &= ~DP_PLL_FREQ_MASK;	2302	dpa_ctl &= ~DP_PLL_FREQ_MASK;
2303		2303
2304	if (clock < 200000) {	2304	if (clock < 200000) {
2305	u32 temp;	2305	u32 temp;
2306	dpa_ctl \|= DP_PLL_FREQ_160MHZ;	2306	dpa_ctl \|= DP_PLL_FREQ_160MHZ;
2307	/* workaround for 160Mhz:	2307	/* workaround for 160Mhz:
2308	1) program 0x4600c bits 15:0 = 0x8124	2308	1) program 0x4600c bits 15:0 = 0x8124
2309	2) program 0x46010 bit 0 = 1	2309	2) program 0x46010 bit 0 = 1
2310	3) program 0x46034 bit 24 = 1	2310	3) program 0x46034 bit 24 = 1
2311	4) program 0x64000 bit 14 = 1	2311	4) program 0x64000 bit 14 = 1
2312	*/	2312	*/
2313	temp = I915_READ(0x4600c);	2313	temp = I915_READ(0x4600c);
2314	temp &= 0xffff0000;	2314	temp &= 0xffff0000;
2315	I915_WRITE(0x4600c, temp \| 0x8124);	2315	I915_WRITE(0x4600c, temp \| 0x8124);
2316		2316
2317	temp = I915_READ(0x46010);	2317	temp = I915_READ(0x46010);
2318	I915_WRITE(0x46010, temp \| 1);	2318	I915_WRITE(0x46010, temp \| 1);
2319		2319
2320	temp = I915_READ(0x46034);	2320	temp = I915_READ(0x46034);
2321	I915_WRITE(0x46034, temp \| (1 << 24));	2321	I915_WRITE(0x46034, temp \| (1 << 24));
2322	} else {	2322	} else {
2323	dpa_ctl \|= DP_PLL_FREQ_270MHZ;	2323	dpa_ctl \|= DP_PLL_FREQ_270MHZ;
2324	}	2324	}
2325	I915_WRITE(DP_A, dpa_ctl);	2325	I915_WRITE(DP_A, dpa_ctl);
2326		2326
2327	POSTING_READ(DP_A);	2327	POSTING_READ(DP_A);
2328	udelay(500);	2328	udelay(500);
2329	}	2329	}
2330		2330
2331	static void intel_fdi_normal_train(struct drm_crtc *crtc)	2331	static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332	{	2332	{
2333	struct drm_device *dev = crtc->dev;	2333	struct drm_device *dev = crtc->dev;
2334	struct drm_i915_private *dev_priv = dev->dev_private;	2334	struct drm_i915_private *dev_priv = dev->dev_private;
2335	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2335	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336	int pipe = intel_crtc->pipe;	2336	int pipe = intel_crtc->pipe;
2337	u32 reg, temp;	2337	u32 reg, temp;
2338		2338
2339	/* enable normal train */	2339	/* enable normal train */
2340	reg = FDI_TX_CTL(pipe);	2340	reg = FDI_TX_CTL(pipe);
2341	temp = I915_READ(reg);	2341	temp = I915_READ(reg);
2342	temp &= ~FDI_LINK_TRAIN_NONE;	2342	temp &= ~FDI_LINK_TRAIN_NONE;
2343	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;	2343	temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
2344	I915_WRITE(reg, temp);	2344	I915_WRITE(reg, temp);
2345		2345
2346	reg = FDI_RX_CTL(pipe);	2346	reg = FDI_RX_CTL(pipe);
2347	temp = I915_READ(reg);	2347	temp = I915_READ(reg);
2348	if (HAS_PCH_CPT(dev)) {	2348	if (HAS_PCH_CPT(dev)) {
2349	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;	2349	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2350	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;	2350	temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
2351	} else {	2351	} else {
2352	temp &= ~FDI_LINK_TRAIN_NONE;	2352	temp &= ~FDI_LINK_TRAIN_NONE;
2353	temp \|= FDI_LINK_TRAIN_NONE;	2353	temp \|= FDI_LINK_TRAIN_NONE;
2354	}	2354	}
2355	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);	2355	I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);
2356		2356
2357	/* wait one idle pattern time */	2357	/* wait one idle pattern time */
2358	POSTING_READ(reg);	2358	POSTING_READ(reg);
2359	udelay(1000);	2359	udelay(1000);
2360	}	2360	}
2361		2361
2362	/* The FDI link training functions for ILK/Ibexpeak. */	2362	/* The FDI link training functions for ILK/Ibexpeak. */
2363	static void ironlake_fdi_link_train(struct drm_crtc *crtc)	2363	static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364	{	2364	{
2365	struct drm_device *dev = crtc->dev;	2365	struct drm_device *dev = crtc->dev;
2366	struct drm_i915_private *dev_priv = dev->dev_private;	2366	struct drm_i915_private *dev_priv = dev->dev_private;
2367	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2367	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368	int pipe = intel_crtc->pipe;	2368	int pipe = intel_crtc->pipe;
2369	int plane = intel_crtc->plane;	2369	int plane = intel_crtc->plane;
2370	u32 reg, temp, tries;	2370	u32 reg, temp, tries;
2371		2371
2372	/* FDI needs bits from pipe & plane first */	2372	/* FDI needs bits from pipe & plane first */
2373	assert_pipe_enabled(dev_priv, pipe);	2373	assert_pipe_enabled(dev_priv, pipe);
2374	assert_plane_enabled(dev_priv, plane);	2374	assert_plane_enabled(dev_priv, plane);
2375		2375
2376	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit	2376	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377	for train result */	2377	for train result */
2378	reg = FDI_RX_IMR(pipe);	2378	reg = FDI_RX_IMR(pipe);
2379	temp = I915_READ(reg);	2379	temp = I915_READ(reg);
2380	temp &= ~FDI_RX_SYMBOL_LOCK;	2380	temp &= ~FDI_RX_SYMBOL_LOCK;
2381	temp &= ~FDI_RX_BIT_LOCK;	2381	temp &= ~FDI_RX_BIT_LOCK;
2382	I915_WRITE(reg, temp);	2382	I915_WRITE(reg, temp);
2383	I915_READ(reg);	2383	I915_READ(reg);
2384	udelay(150);	2384	udelay(150);
2385		2385
2386	/* enable CPU FDI TX and PCH FDI RX */	2386	/* enable CPU FDI TX and PCH FDI RX */
2387	reg = FDI_TX_CTL(pipe);	2387	reg = FDI_TX_CTL(pipe);
2388	temp = I915_READ(reg);	2388	temp = I915_READ(reg);
2389	temp &= ~(7 << 19);	2389	temp &= ~(7 << 19);
2390	temp \|= (intel_crtc->fdi_lanes - 1) << 19;	2390	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
2391	temp &= ~FDI_LINK_TRAIN_NONE;	2391	temp &= ~FDI_LINK_TRAIN_NONE;
2392	temp \|= FDI_LINK_TRAIN_PATTERN_1;	2392	temp \|= FDI_LINK_TRAIN_PATTERN_1;
2393	I915_WRITE(reg, temp \| FDI_TX_ENABLE);	2393	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
2394		2394
2395	reg = FDI_RX_CTL(pipe);	2395	reg = FDI_RX_CTL(pipe);
2396	temp = I915_READ(reg);	2396	temp = I915_READ(reg);
2397	temp &= ~FDI_LINK_TRAIN_NONE;	2397	temp &= ~FDI_LINK_TRAIN_NONE;
2398	temp \|= FDI_LINK_TRAIN_PATTERN_1;	2398	temp \|= FDI_LINK_TRAIN_PATTERN_1;
2399	I915_WRITE(reg, temp \| FDI_RX_ENABLE);	2399	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
2400		2400
2401	POSTING_READ(reg);	2401	POSTING_READ(reg);
2402	udelay(150);	2402	udelay(150);
2403		2403
2404	/* Ironlake workaround, enable clock pointer after FDI enable*/	2404	/* Ironlake workaround, enable clock pointer after FDI enable*/
2405	if (HAS_PCH_IBX(dev)) {	2405	if (HAS_PCH_IBX(dev)) {
2406	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);	2406	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|	2407	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR \|
2408	FDI_RX_PHASE_SYNC_POINTER_EN);	2408	FDI_RX_PHASE_SYNC_POINTER_EN);
2409	}	2409	}
2410		2410
2411	reg = FDI_RX_IIR(pipe);	2411	reg = FDI_RX_IIR(pipe);
2412	for (tries = 0; tries < 5; tries++) {	2412	for (tries = 0; tries < 5; tries++) {
2413	temp = I915_READ(reg);	2413	temp = I915_READ(reg);
2414	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);	2414	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415		2415
2416	if ((temp & FDI_RX_BIT_LOCK)) {	2416	if ((temp & FDI_RX_BIT_LOCK)) {
2417	DRM_DEBUG_KMS("FDI train 1 done.\n");	2417	DRM_DEBUG_KMS("FDI train 1 done.\n");
2418	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);	2418	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
2419	break;	2419	break;
2420	}	2420	}
2421	}	2421	}
2422	if (tries == 5)	2422	if (tries == 5)
2423	DRM_ERROR("FDI train 1 fail!\n");	2423	DRM_ERROR("FDI train 1 fail!\n");
2424		2424
2425	/* Train 2 */	2425	/* Train 2 */
2426	reg = FDI_TX_CTL(pipe);	2426	reg = FDI_TX_CTL(pipe);
2427	temp = I915_READ(reg);	2427	temp = I915_READ(reg);
2428	temp &= ~FDI_LINK_TRAIN_NONE;	2428	temp &= ~FDI_LINK_TRAIN_NONE;
2429	temp \|= FDI_LINK_TRAIN_PATTERN_2;	2429	temp \|= FDI_LINK_TRAIN_PATTERN_2;
2430	I915_WRITE(reg, temp);	2430	I915_WRITE(reg, temp);
2431		2431
2432	reg = FDI_RX_CTL(pipe);	2432	reg = FDI_RX_CTL(pipe);
2433	temp = I915_READ(reg);	2433	temp = I915_READ(reg);
2434	temp &= ~FDI_LINK_TRAIN_NONE;	2434	temp &= ~FDI_LINK_TRAIN_NONE;
2435	temp \|= FDI_LINK_TRAIN_PATTERN_2;	2435	temp \|= FDI_LINK_TRAIN_PATTERN_2;
2436	I915_WRITE(reg, temp);	2436	I915_WRITE(reg, temp);
2437		2437
2438	POSTING_READ(reg);	2438	POSTING_READ(reg);
2439	udelay(150);	2439	udelay(150);
2440		2440
2441	reg = FDI_RX_IIR(pipe);	2441	reg = FDI_RX_IIR(pipe);
2442	for (tries = 0; tries < 5; tries++) {	2442	for (tries = 0; tries < 5; tries++) {
2443	temp = I915_READ(reg);	2443	temp = I915_READ(reg);
2444	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);	2444	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445		2445
2446	if (temp & FDI_RX_SYMBOL_LOCK) {	2446	if (temp & FDI_RX_SYMBOL_LOCK) {
2447	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);	2447	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
2448	DRM_DEBUG_KMS("FDI train 2 done.\n");	2448	DRM_DEBUG_KMS("FDI train 2 done.\n");
2449	break;	2449	break;
2450	}	2450	}
2451	}	2451	}
2452	if (tries == 5)	2452	if (tries == 5)
2453	DRM_ERROR("FDI train 2 fail!\n");	2453	DRM_ERROR("FDI train 2 fail!\n");
2454		2454
2455	DRM_DEBUG_KMS("FDI train done\n");	2455	DRM_DEBUG_KMS("FDI train done\n");
2456		2456
2457	}	2457	}
2458		2458
2459	static const int snb_b_fdi_train_param [] = {	2459	static const int snb_b_fdi_train_param [] = {
2460	FDI_LINK_TRAIN_400MV_0DB_SNB_B,	2460	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461	FDI_LINK_TRAIN_400MV_6DB_SNB_B,	2461	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,	2462	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463	FDI_LINK_TRAIN_800MV_0DB_SNB_B,	2463	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464	};	2464	};
2465		2465
2466	/* The FDI link training functions for SNB/Cougarpoint. */	2466	/* The FDI link training functions for SNB/Cougarpoint. */
2467	static void gen6_fdi_link_train(struct drm_crtc *crtc)	2467	static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468	{	2468	{
2469	struct drm_device *dev = crtc->dev;	2469	struct drm_device *dev = crtc->dev;
2470	struct drm_i915_private *dev_priv = dev->dev_private;	2470	struct drm_i915_private *dev_priv = dev->dev_private;
2471	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2471	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472	int pipe = intel_crtc->pipe;	2472	int pipe = intel_crtc->pipe;
2473	u32 reg, temp, i;	2473	u32 reg, temp, i;
2474		2474
2475	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit	2475	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476	for train result */	2476	for train result */
2477	reg = FDI_RX_IMR(pipe);	2477	reg = FDI_RX_IMR(pipe);
2478	temp = I915_READ(reg);	2478	temp = I915_READ(reg);
2479	temp &= ~FDI_RX_SYMBOL_LOCK;	2479	temp &= ~FDI_RX_SYMBOL_LOCK;
2480	temp &= ~FDI_RX_BIT_LOCK;	2480	temp &= ~FDI_RX_BIT_LOCK;
2481	I915_WRITE(reg, temp);	2481	I915_WRITE(reg, temp);
2482		2482
2483	POSTING_READ(reg);	2483	POSTING_READ(reg);
2484	udelay(150);	2484	udelay(150);
2485		2485
2486	/* enable CPU FDI TX and PCH FDI RX */	2486	/* enable CPU FDI TX and PCH FDI RX */
2487	reg = FDI_TX_CTL(pipe);	2487	reg = FDI_TX_CTL(pipe);
2488	temp = I915_READ(reg);	2488	temp = I915_READ(reg);
2489	temp &= ~(7 << 19);	2489	temp &= ~(7 << 19);
2490	temp \|= (intel_crtc->fdi_lanes - 1) << 19;	2490	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
2491	temp &= ~FDI_LINK_TRAIN_NONE;	2491	temp &= ~FDI_LINK_TRAIN_NONE;
2492	temp \|= FDI_LINK_TRAIN_PATTERN_1;	2492	temp \|= FDI_LINK_TRAIN_PATTERN_1;
2493	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;	2493	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494	/* SNB-B */	2494	/* SNB-B */
2495	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;	2495	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496	I915_WRITE(reg, temp \| FDI_TX_ENABLE);	2496	I915_WRITE(reg, temp \| FDI_TX_ENABLE);
2497		2497
2498	reg = FDI_RX_CTL(pipe);	2498	reg = FDI_RX_CTL(pipe);
2499	temp = I915_READ(reg);	2499	temp = I915_READ(reg);
2500	if (HAS_PCH_CPT(dev)) {	2500	if (HAS_PCH_CPT(dev)) {
2501	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;	2501	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;	2502	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503	} else {	2503	} else {
2504	temp &= ~FDI_LINK_TRAIN_NONE;	2504	temp &= ~FDI_LINK_TRAIN_NONE;
2505	temp \|= FDI_LINK_TRAIN_PATTERN_1;	2505	temp \|= FDI_LINK_TRAIN_PATTERN_1;
2506	}	2506	}
2507	I915_WRITE(reg, temp \| FDI_RX_ENABLE);	2507	I915_WRITE(reg, temp \| FDI_RX_ENABLE);
2508		2508
2509	POSTING_READ(reg);	2509	POSTING_READ(reg);
2510	udelay(150);	2510	udelay(150);
2511		2511
2512	for (i = 0; i < 4; i++ ) {	2512	for (i = 0; i < 4; i++ ) {
2513	reg = FDI_TX_CTL(pipe);	2513	reg = FDI_TX_CTL(pipe);
2514	temp = I915_READ(reg);	2514	temp = I915_READ(reg);
2515	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;	2515	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516	temp \|= snb_b_fdi_train_param[i];	2516	temp \|= snb_b_fdi_train_param[i];
2517	I915_WRITE(reg, temp);	2517	I915_WRITE(reg, temp);
2518		2518
2519	POSTING_READ(reg);	2519	POSTING_READ(reg);
2520	udelay(500);	2520	udelay(500);
2521		2521
2522	reg = FDI_RX_IIR(pipe);	2522	reg = FDI_RX_IIR(pipe);
2523	temp = I915_READ(reg);	2523	temp = I915_READ(reg);
2524	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);	2524	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2525		2525
2526	if (temp & FDI_RX_BIT_LOCK) {	2526	if (temp & FDI_RX_BIT_LOCK) {
2527	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);	2527	I915_WRITE(reg, temp \| FDI_RX_BIT_LOCK);
2528	DRM_DEBUG_KMS("FDI train 1 done.\n");	2528	DRM_DEBUG_KMS("FDI train 1 done.\n");
2529	break;	2529	break;
2530	}	2530	}
2531	}	2531	}
2532	if (i == 4)	2532	if (i == 4)
2533	DRM_ERROR("FDI train 1 fail!\n");	2533	DRM_ERROR("FDI train 1 fail!\n");
2534		2534
2535	/* Train 2 */	2535	/* Train 2 */
2536	reg = FDI_TX_CTL(pipe);	2536	reg = FDI_TX_CTL(pipe);
2537	temp = I915_READ(reg);	2537	temp = I915_READ(reg);
2538	temp &= ~FDI_LINK_TRAIN_NONE;	2538	temp &= ~FDI_LINK_TRAIN_NONE;
2539	temp \|= FDI_LINK_TRAIN_PATTERN_2;	2539	temp \|= FDI_LINK_TRAIN_PATTERN_2;
2540	if (IS_GEN6(dev)) {	2540	if (IS_GEN6(dev)) {
2541	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;	2541	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2542	/* SNB-B */	2542	/* SNB-B */
2543	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;	2543	temp \|= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2544	}	2544	}
2545	I915_WRITE(reg, temp);	2545	I915_WRITE(reg, temp);
2546		2546
2547	reg = FDI_RX_CTL(pipe);	2547	reg = FDI_RX_CTL(pipe);
2548	temp = I915_READ(reg);	2548	temp = I915_READ(reg);
2549	if (HAS_PCH_CPT(dev)) {	2549	if (HAS_PCH_CPT(dev)) {
2550	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;	2550	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2551	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;	2551	temp \|= FDI_LINK_TRAIN_PATTERN_2_CPT;
2552	} else {	2552	} else {
2553	temp &= ~FDI_LINK_TRAIN_NONE;	2553	temp &= ~FDI_LINK_TRAIN_NONE;
2554	temp \|= FDI_LINK_TRAIN_PATTERN_2;	2554	temp \|= FDI_LINK_TRAIN_PATTERN_2;
2555	}	2555	}
2556	I915_WRITE(reg, temp);	2556	I915_WRITE(reg, temp);
2557		2557
2558	POSTING_READ(reg);	2558	POSTING_READ(reg);
2559	udelay(150);	2559	udelay(150);
2560		2560
2561	for (i = 0; i < 4; i++ ) {	2561	for (i = 0; i < 4; i++ ) {
2562	reg = FDI_TX_CTL(pipe);	2562	reg = FDI_TX_CTL(pipe);
2563	temp = I915_READ(reg);	2563	temp = I915_READ(reg);
2564	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;	2564	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565	temp \|= snb_b_fdi_train_param[i];	2565	temp \|= snb_b_fdi_train_param[i];
2566	I915_WRITE(reg, temp);	2566	I915_WRITE(reg, temp);
2567		2567
2568	POSTING_READ(reg);	2568	POSTING_READ(reg);
2569	udelay(500);	2569	udelay(500);
2570		2570
2571	reg = FDI_RX_IIR(pipe);	2571	reg = FDI_RX_IIR(pipe);
2572	temp = I915_READ(reg);	2572	temp = I915_READ(reg);
2573	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);	2573	DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574		2574
2575	if (temp & FDI_RX_SYMBOL_LOCK) {	2575	if (temp & FDI_RX_SYMBOL_LOCK) {
2576	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);	2576	I915_WRITE(reg, temp \| FDI_RX_SYMBOL_LOCK);
2577	DRM_DEBUG_KMS("FDI train 2 done.\n");	2577	DRM_DEBUG_KMS("FDI train 2 done.\n");
2578	break;	2578	break;
2579	}	2579	}
2580	}	2580	}
2581	if (i == 4)	2581	if (i == 4)
2582	DRM_ERROR("FDI train 2 fail!\n");	2582	DRM_ERROR("FDI train 2 fail!\n");
2583		2583
2584	DRM_DEBUG_KMS("FDI train done.\n");	2584	DRM_DEBUG_KMS("FDI train done.\n");
2585	}	2585	}
2586		2586
2587	static void ironlake_fdi_enable(struct drm_crtc *crtc)	2587	static void ironlake_fdi_enable(struct drm_crtc *crtc)
2588	{	2588	{
2589	struct drm_device *dev = crtc->dev;	2589	struct drm_device *dev = crtc->dev;
2590	struct drm_i915_private *dev_priv = dev->dev_private;	2590	struct drm_i915_private *dev_priv = dev->dev_private;
2591	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2591	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2592	int pipe = intel_crtc->pipe;	2592	int pipe = intel_crtc->pipe;
2593	u32 reg, temp;	2593	u32 reg, temp;
2594		2594
2595	/* Write the TU size bits so error detection works */	2595	/* Write the TU size bits so error detection works */
2596	I915_WRITE(FDI_RX_TUSIZE1(pipe),	2596	I915_WRITE(FDI_RX_TUSIZE1(pipe),
2597	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);	2597	I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2598		2598
2599	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */	2599	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2600	reg = FDI_RX_CTL(pipe);	2600	reg = FDI_RX_CTL(pipe);
2601	temp = I915_READ(reg);	2601	temp = I915_READ(reg);
2602	temp &= ~((0x7 << 19) \| (0x7 << 16));	2602	temp &= ~((0x7 << 19) \| (0x7 << 16));
2603	temp \|= (intel_crtc->fdi_lanes - 1) << 19;	2603	temp \|= (intel_crtc->fdi_lanes - 1) << 19;
2604	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;	2604	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2605	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);	2605	I915_WRITE(reg, temp \| FDI_RX_PLL_ENABLE);
2606		2606
2607	POSTING_READ(reg);	2607	POSTING_READ(reg);
2608	udelay(200);	2608	udelay(200);
2609		2609
2610	/* Switch from Rawclk to PCDclk */	2610	/* Switch from Rawclk to PCDclk */
2611	temp = I915_READ(reg);	2611	temp = I915_READ(reg);
2612	I915_WRITE(reg, temp \| FDI_PCDCLK);	2612	I915_WRITE(reg, temp \| FDI_PCDCLK);
2613		2613
2614	POSTING_READ(reg);	2614	POSTING_READ(reg);
2615	udelay(200);	2615	udelay(200);
2616		2616
2617	/* Enable CPU FDI TX PLL, always on for Ironlake */	2617	/* Enable CPU FDI TX PLL, always on for Ironlake */
2618	reg = FDI_TX_CTL(pipe);	2618	reg = FDI_TX_CTL(pipe);
2619	temp = I915_READ(reg);	2619	temp = I915_READ(reg);
2620	if ((temp & FDI_TX_PLL_ENABLE) == 0) {	2620	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2621	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);	2621	I915_WRITE(reg, temp \| FDI_TX_PLL_ENABLE);
2622		2622
2623	POSTING_READ(reg);	2623	POSTING_READ(reg);
2624	udelay(100);	2624	udelay(100);
2625	}	2625	}
2626	}	2626	}
2627		2627
2628	static void ironlake_fdi_disable(struct drm_crtc *crtc)	2628	static void ironlake_fdi_disable(struct drm_crtc *crtc)
2629	{	2629	{
2630	struct drm_device *dev = crtc->dev;	2630	struct drm_device *dev = crtc->dev;
2631	struct drm_i915_private *dev_priv = dev->dev_private;	2631	struct drm_i915_private *dev_priv = dev->dev_private;
2632	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2632	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2633	int pipe = intel_crtc->pipe;	2633	int pipe = intel_crtc->pipe;
2634	u32 reg, temp;	2634	u32 reg, temp;
2635		2635
2636	/* disable CPU FDI tx and PCH FDI rx */	2636	/* disable CPU FDI tx and PCH FDI rx */
2637	reg = FDI_TX_CTL(pipe);	2637	reg = FDI_TX_CTL(pipe);
2638	temp = I915_READ(reg);	2638	temp = I915_READ(reg);
2639	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);	2639	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2640	POSTING_READ(reg);	2640	POSTING_READ(reg);
2641		2641
2642	reg = FDI_RX_CTL(pipe);	2642	reg = FDI_RX_CTL(pipe);
2643	temp = I915_READ(reg);	2643	temp = I915_READ(reg);
2644	temp &= ~(0x7 << 16);	2644	temp &= ~(0x7 << 16);
2645	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;	2645	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2646	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);	2646	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2647		2647
2648	POSTING_READ(reg);	2648	POSTING_READ(reg);
2649	udelay(100);	2649	udelay(100);
2650		2650
2651	/* Ironlake workaround, disable clock pointer after downing FDI */	2651	/* Ironlake workaround, disable clock pointer after downing FDI */
2652	if (HAS_PCH_IBX(dev)) {	2652	if (HAS_PCH_IBX(dev)) {
2653	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);	2653	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2654	I915_WRITE(FDI_RX_CHICKEN(pipe),	2654	I915_WRITE(FDI_RX_CHICKEN(pipe),
2655	I915_READ(FDI_RX_CHICKEN(pipe) &	2655	I915_READ(FDI_RX_CHICKEN(pipe) &
2656	~FDI_RX_PHASE_SYNC_POINTER_EN));	2656	~FDI_RX_PHASE_SYNC_POINTER_EN));
2657	}	2657	}
2658		2658
2659	/* still set train pattern 1 */	2659	/* still set train pattern 1 */
2660	reg = FDI_TX_CTL(pipe);	2660	reg = FDI_TX_CTL(pipe);
2661	temp = I915_READ(reg);	2661	temp = I915_READ(reg);
2662	temp &= ~FDI_LINK_TRAIN_NONE;	2662	temp &= ~FDI_LINK_TRAIN_NONE;
2663	temp \|= FDI_LINK_TRAIN_PATTERN_1;	2663	temp \|= FDI_LINK_TRAIN_PATTERN_1;
2664	I915_WRITE(reg, temp);	2664	I915_WRITE(reg, temp);
2665		2665
2666	reg = FDI_RX_CTL(pipe);	2666	reg = FDI_RX_CTL(pipe);
2667	temp = I915_READ(reg);	2667	temp = I915_READ(reg);
2668	if (HAS_PCH_CPT(dev)) {	2668	if (HAS_PCH_CPT(dev)) {
2669	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;	2669	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2670	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;	2670	temp \|= FDI_LINK_TRAIN_PATTERN_1_CPT;
2671	} else {	2671	} else {
2672	temp &= ~FDI_LINK_TRAIN_NONE;	2672	temp &= ~FDI_LINK_TRAIN_NONE;
2673	temp \|= FDI_LINK_TRAIN_PATTERN_1;	2673	temp \|= FDI_LINK_TRAIN_PATTERN_1;
2674	}	2674	}
2675	/* BPC in FDI rx is consistent with that in PIPECONF */	2675	/* BPC in FDI rx is consistent with that in PIPECONF */
2676	temp &= ~(0x07 << 16);	2676	temp &= ~(0x07 << 16);
2677	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;	2677	temp \|= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2678	I915_WRITE(reg, temp);	2678	I915_WRITE(reg, temp);
2679		2679
2680	POSTING_READ(reg);	2680	POSTING_READ(reg);
2681	udelay(100);	2681	udelay(100);
2682	}	2682	}
2683		2683
2684	/*	2684	/*
2685	* When we disable a pipe, we need to clear any pending scanline wait events	2685	* When we disable a pipe, we need to clear any pending scanline wait events
2686	* to avoid hanging the ring, which we assume we are waiting on.	2686	* to avoid hanging the ring, which we assume we are waiting on.
2687	*/	2687	*/
2688	static void intel_clear_scanline_wait(struct drm_device *dev)	2688	static void intel_clear_scanline_wait(struct drm_device *dev)
2689	{	2689	{
2690	struct drm_i915_private *dev_priv = dev->dev_private;	2690	struct drm_i915_private *dev_priv = dev->dev_private;
2691	struct intel_ring_buffer *ring;	2691	struct intel_ring_buffer *ring;
2692	u32 tmp;	2692	u32 tmp;
2693		2693
2694	if (IS_GEN2(dev))	2694	if (IS_GEN2(dev))
2695	/* Can't break the hang on i8xx */	2695	/* Can't break the hang on i8xx */
2696	return;	2696	return;
2697		2697
2698	ring = LP_RING(dev_priv);	2698	ring = LP_RING(dev_priv);
2699	tmp = I915_READ_CTL(ring);	2699	tmp = I915_READ_CTL(ring);
2700	if (tmp & RING_WAIT)	2700	if (tmp & RING_WAIT)
2701	I915_WRITE_CTL(ring, tmp);	2701	I915_WRITE_CTL(ring, tmp);
2702	}	2702	}
2703		2703
2704	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)	2704	static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2705	{	2705	{
2706	struct drm_i915_gem_object *obj;	2706	struct drm_i915_gem_object *obj;
2707	struct drm_i915_private *dev_priv;	2707	struct drm_i915_private *dev_priv;
2708		2708
2709	if (crtc->fb == NULL)	2709	if (crtc->fb == NULL)
2710	return;	2710	return;
2711		2711
2712	obj = to_intel_framebuffer(crtc->fb)->obj;	2712	obj = to_intel_framebuffer(crtc->fb)->obj;
2713	dev_priv = crtc->dev->dev_private;	2713	dev_priv = crtc->dev->dev_private;
2714	wait_event(dev_priv->pending_flip_queue,	2714	wait_event(dev_priv->pending_flip_queue,
2715	atomic_read(&obj->pending_flip) == 0);	2715	atomic_read(&obj->pending_flip) == 0);
2716	}	2716	}
2717		2717
2718	static bool intel_crtc_driving_pch(struct drm_crtc *crtc)	2718	static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2719	{	2719	{
2720	struct drm_device *dev = crtc->dev;	2720	struct drm_device *dev = crtc->dev;
2721	struct drm_mode_config *mode_config = &dev->mode_config;	2721	struct drm_mode_config *mode_config = &dev->mode_config;
2722	struct intel_encoder *encoder;	2722	struct intel_encoder *encoder;
2723		2723
2724	/*	2724	/*
2725	* If there's a non-PCH eDP on this crtc, it must be DP_A, and that	2725	* If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2726	* must be driven by its own crtc; no sharing is possible.	2726	* must be driven by its own crtc; no sharing is possible.
2727	*/	2727	*/
2728	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {	2728	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2729	if (encoder->base.crtc != crtc)	2729	if (encoder->base.crtc != crtc)
2730	continue;	2730	continue;
2731		2731
2732	switch (encoder->type) {	2732	switch (encoder->type) {
2733	case INTEL_OUTPUT_EDP:	2733	case INTEL_OUTPUT_EDP:
2734	if (!intel_encoder_is_pch_edp(&encoder->base))	2734	if (!intel_encoder_is_pch_edp(&encoder->base))
2735	return false;	2735	return false;
2736	continue;	2736	continue;
2737	}	2737	}
2738	}	2738	}
2739		2739
2740	return true;	2740	return true;
2741	}	2741	}
2742		2742
2743	/*	2743	/*
2744	* Enable PCH resources required for PCH ports:	2744	* Enable PCH resources required for PCH ports:
2745	* - PCH PLLs	2745	* - PCH PLLs
2746	* - FDI training & RX/TX	2746	* - FDI training & RX/TX
2747	* - update transcoder timings	2747	* - update transcoder timings
2748	* - DP transcoding bits	2748	* - DP transcoding bits
2749	* - transcoder	2749	* - transcoder
2750	*/	2750	*/
2751	static void ironlake_pch_enable(struct drm_crtc *crtc)	2751	static void ironlake_pch_enable(struct drm_crtc *crtc)
2752	{	2752	{
2753	struct drm_device *dev = crtc->dev;	2753	struct drm_device *dev = crtc->dev;
2754	struct drm_i915_private *dev_priv = dev->dev_private;	2754	struct drm_i915_private *dev_priv = dev->dev_private;
2755	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2755	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756	int pipe = intel_crtc->pipe;	2756	int pipe = intel_crtc->pipe;
2757	u32 reg, temp;	2757	u32 reg, temp;
2758		2758
2759	/* For PCH output, training FDI link */	2759	/* For PCH output, training FDI link */
2760	if (IS_GEN6(dev))	2760	if (IS_GEN6(dev))
2761	gen6_fdi_link_train(crtc);	2761	gen6_fdi_link_train(crtc);
2762	else	2762	else
2763	ironlake_fdi_link_train(crtc);	2763	ironlake_fdi_link_train(crtc);
2764		2764
2765	intel_enable_pch_pll(dev_priv, pipe);	2765	intel_enable_pch_pll(dev_priv, pipe);
2766		2766
2767	if (HAS_PCH_CPT(dev)) {	2767	if (HAS_PCH_CPT(dev)) {
2768	/* Be sure PCH DPLL SEL is set */	2768	/* Be sure PCH DPLL SEL is set */
2769	temp = I915_READ(PCH_DPLL_SEL);	2769	temp = I915_READ(PCH_DPLL_SEL);
2770	if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)	2770	if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2771	temp \|= (TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL);	2771	temp \|= (TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL);
2772	else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)	2772	else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2773	temp \|= (TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);	2773	temp \|= (TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
2774	I915_WRITE(PCH_DPLL_SEL, temp);	2774	I915_WRITE(PCH_DPLL_SEL, temp);
2775	}	2775	}
2776		2776
2777	/* set transcoder timing, panel must allow it */	2777	/* set transcoder timing, panel must allow it */
2778	assert_panel_unlocked(dev_priv, pipe);	2778	assert_panel_unlocked(dev_priv, pipe);
2779	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));	2779	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2780	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));	2780	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2781	I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));	2781	I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2782		2782
2783	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));	2783	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2784	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));	2784	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2785	I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));	2785	I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2786		2786
2787	intel_fdi_normal_train(crtc);	2787	intel_fdi_normal_train(crtc);
2788		2788
2789	/* For PCH DP, enable TRANS_DP_CTL */	2789	/* For PCH DP, enable TRANS_DP_CTL */
2790	if (HAS_PCH_CPT(dev) &&	2790	if (HAS_PCH_CPT(dev) &&
2791	intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {	2791	intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2792	reg = TRANS_DP_CTL(pipe);	2792	reg = TRANS_DP_CTL(pipe);
2793	temp = I915_READ(reg);	2793	temp = I915_READ(reg);
2794	temp &= ~(TRANS_DP_PORT_SEL_MASK \|	2794	temp &= ~(TRANS_DP_PORT_SEL_MASK \|
2795	TRANS_DP_SYNC_MASK \|	2795	TRANS_DP_SYNC_MASK \|
2796	TRANS_DP_BPC_MASK);	2796	TRANS_DP_BPC_MASK);
2797	temp \|= (TRANS_DP_OUTPUT_ENABLE \|	2797	temp \|= (TRANS_DP_OUTPUT_ENABLE \|
2798	TRANS_DP_ENH_FRAMING);	2798	TRANS_DP_ENH_FRAMING);
2799	temp \|= TRANS_DP_8BPC;	2799	temp \|= TRANS_DP_8BPC;
2800		2800
2801	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)	2801	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2802	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;	2802	temp \|= TRANS_DP_HSYNC_ACTIVE_HIGH;
2803	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)	2803	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2804	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;	2804	temp \|= TRANS_DP_VSYNC_ACTIVE_HIGH;
2805		2805
2806	switch (intel_trans_dp_port_sel(crtc)) {	2806	switch (intel_trans_dp_port_sel(crtc)) {
2807	case PCH_DP_B:	2807	case PCH_DP_B:
2808	temp \|= TRANS_DP_PORT_SEL_B;	2808	temp \|= TRANS_DP_PORT_SEL_B;
2809	break;	2809	break;
2810	case PCH_DP_C:	2810	case PCH_DP_C:
2811	temp \|= TRANS_DP_PORT_SEL_C;	2811	temp \|= TRANS_DP_PORT_SEL_C;
2812	break;	2812	break;
2813	case PCH_DP_D:	2813	case PCH_DP_D:
2814	temp \|= TRANS_DP_PORT_SEL_D;	2814	temp \|= TRANS_DP_PORT_SEL_D;
2815	break;	2815	break;
2816	default:	2816	default:
2817	DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");	2817	DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2818	temp \|= TRANS_DP_PORT_SEL_B;	2818	temp \|= TRANS_DP_PORT_SEL_B;
2819	break;	2819	break;
2820	}	2820	}
2821		2821
2822	I915_WRITE(reg, temp);	2822	I915_WRITE(reg, temp);
2823	}	2823	}
2824		2824
2825	intel_enable_transcoder(dev_priv, pipe);	2825	intel_enable_transcoder(dev_priv, pipe);
2826	}	2826	}
2827		2827
2828	static void ironlake_crtc_enable(struct drm_crtc *crtc)	2828	static void ironlake_crtc_enable(struct drm_crtc *crtc)
2829	{	2829	{
2830	struct drm_device *dev = crtc->dev;	2830	struct drm_device *dev = crtc->dev;
2831	struct drm_i915_private *dev_priv = dev->dev_private;	2831	struct drm_i915_private *dev_priv = dev->dev_private;
2832	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2832	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2833	int pipe = intel_crtc->pipe;	2833	int pipe = intel_crtc->pipe;
2834	int plane = intel_crtc->plane;	2834	int plane = intel_crtc->plane;
2835	u32 temp;	2835	u32 temp;
2836	bool is_pch_port;	2836	bool is_pch_port;
2837		2837
2838	if (intel_crtc->active)	2838	if (intel_crtc->active)
2839	return;	2839	return;
2840		2840
2841	intel_crtc->active = true;	2841	intel_crtc->active = true;
2842	intel_update_watermarks(dev);	2842	intel_update_watermarks(dev);
2843		2843
2844	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {	2844	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2845	temp = I915_READ(PCH_LVDS);	2845	temp = I915_READ(PCH_LVDS);
2846	if ((temp & LVDS_PORT_EN) == 0)	2846	if ((temp & LVDS_PORT_EN) == 0)
2847	I915_WRITE(PCH_LVDS, temp \| LVDS_PORT_EN);	2847	I915_WRITE(PCH_LVDS, temp \| LVDS_PORT_EN);
2848	}	2848	}
2849		2849
2850	is_pch_port = intel_crtc_driving_pch(crtc);	2850	is_pch_port = intel_crtc_driving_pch(crtc);
2851		2851
2852	if (is_pch_port)	2852	if (is_pch_port)
2853	ironlake_fdi_enable(crtc);	2853	ironlake_fdi_enable(crtc);
2854	else	2854	else
2855	ironlake_fdi_disable(crtc);	2855	ironlake_fdi_disable(crtc);
2856		2856
2857	/* Enable panel fitting for LVDS */	2857	/* Enable panel fitting for LVDS */
2858	if (dev_priv->pch_pf_size &&	2858	if (dev_priv->pch_pf_size &&
2859	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\| HAS_eDP)) {	2859	(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) \|\| HAS_eDP)) {
2860	/* Force use of hard-coded filter coefficients	2860	/* Force use of hard-coded filter coefficients
2861	* as some pre-programmed values are broken,	2861	* as some pre-programmed values are broken,
2862	* e.g. x201.	2862	* e.g. x201.
2863	*/	2863	*/
2864	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);	2864	I915_WRITE(PF_CTL(pipe), PF_ENABLE \| PF_FILTER_MED_3x3);
2865	I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);	2865	I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2866	I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);	2866	I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2867	}	2867	}
2868		2868
2869	intel_enable_pipe(dev_priv, pipe, is_pch_port);	2869	intel_enable_pipe(dev_priv, pipe, is_pch_port);
2870	intel_enable_plane(dev_priv, plane, pipe);	2870	intel_enable_plane(dev_priv, plane, pipe);
2871		2871
2872	if (is_pch_port)	2872	if (is_pch_port)
2873	ironlake_pch_enable(crtc);	2873	ironlake_pch_enable(crtc);
2874		2874
2875	intel_crtc_load_lut(crtc);	2875	intel_crtc_load_lut(crtc);
2876	intel_update_fbc(dev);	2876	intel_update_fbc(dev);
2877	intel_crtc_update_cursor(crtc, true);	2877	intel_crtc_update_cursor(crtc, true);
2878	}	2878	}
2879		2879
2880	static void ironlake_crtc_disable(struct drm_crtc *crtc)	2880	static void ironlake_crtc_disable(struct drm_crtc *crtc)
2881	{	2881	{
2882	struct drm_device *dev = crtc->dev;	2882	struct drm_device *dev = crtc->dev;
2883	struct drm_i915_private *dev_priv = dev->dev_private;	2883	struct drm_i915_private *dev_priv = dev->dev_private;
2884	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2884	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885	int pipe = intel_crtc->pipe;	2885	int pipe = intel_crtc->pipe;
2886	int plane = intel_crtc->plane;	2886	int plane = intel_crtc->plane;
2887	u32 reg, temp;	2887	u32 reg, temp;
2888		2888
2889	if (!intel_crtc->active)	2889	if (!intel_crtc->active)
2890	return;	2890	return;
2891		2891
2892	intel_crtc_wait_for_pending_flips(crtc);	2892	intel_crtc_wait_for_pending_flips(crtc);
2893	drm_vblank_off(dev, pipe);	2893	drm_vblank_off(dev, pipe);
2894	intel_crtc_update_cursor(crtc, false);	2894	intel_crtc_update_cursor(crtc, false);
2895		2895
2896	intel_disable_plane(dev_priv, plane, pipe);	2896	intel_disable_plane(dev_priv, plane, pipe);
2897		2897
2898	if (dev_priv->cfb_plane == plane &&	2898	if (dev_priv->cfb_plane == plane &&
2899	dev_priv->display.disable_fbc)	2899	dev_priv->display.disable_fbc)
2900	dev_priv->display.disable_fbc(dev);	2900	dev_priv->display.disable_fbc(dev);
2901		2901
2902	intel_disable_pipe(dev_priv, pipe);	2902	intel_disable_pipe(dev_priv, pipe);
2903		2903
2904	/* Disable PF */	2904	/* Disable PF */
2905	I915_WRITE(PF_CTL(pipe), 0);	2905	I915_WRITE(PF_CTL(pipe), 0);
2906	I915_WRITE(PF_WIN_SZ(pipe), 0);	2906	I915_WRITE(PF_WIN_SZ(pipe), 0);
2907		2907
2908	ironlake_fdi_disable(crtc);	2908	ironlake_fdi_disable(crtc);
2909		2909
2910	/* This is a horrible layering violation; we should be doing this in	2910	/* This is a horrible layering violation; we should be doing this in
2911	* the connector/encoder ->prepare instead, but we don't always have	2911	* the connector/encoder ->prepare instead, but we don't always have
2912	* enough information there about the config to know whether it will	2912	* enough information there about the config to know whether it will
2913	* actually be necessary or just cause undesired flicker.	2913	* actually be necessary or just cause undesired flicker.
2914	*/	2914	*/
2915	intel_disable_pch_ports(dev_priv, pipe);	2915	intel_disable_pch_ports(dev_priv, pipe);
2916		2916
2917	intel_disable_transcoder(dev_priv, pipe);	2917	intel_disable_transcoder(dev_priv, pipe);
2918		2918
2919	if (HAS_PCH_CPT(dev)) {	2919	if (HAS_PCH_CPT(dev)) {
2920	/* disable TRANS_DP_CTL */	2920	/* disable TRANS_DP_CTL */
2921	reg = TRANS_DP_CTL(pipe);	2921	reg = TRANS_DP_CTL(pipe);
2922	temp = I915_READ(reg);	2922	temp = I915_READ(reg);
2923	temp &= ~(TRANS_DP_OUTPUT_ENABLE \| TRANS_DP_PORT_SEL_MASK);	2923	temp &= ~(TRANS_DP_OUTPUT_ENABLE \| TRANS_DP_PORT_SEL_MASK);
2924	temp \|= TRANS_DP_PORT_SEL_NONE;	2924	temp \|= TRANS_DP_PORT_SEL_NONE;
2925	I915_WRITE(reg, temp);	2925	I915_WRITE(reg, temp);
2926		2926
2927	/* disable DPLL_SEL */	2927	/* disable DPLL_SEL */
2928	temp = I915_READ(PCH_DPLL_SEL);	2928	temp = I915_READ(PCH_DPLL_SEL);
2929	switch (pipe) {	2929	switch (pipe) {
2930	case 0:	2930	case 0:
2931	temp &= ~(TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL);	2931	temp &= ~(TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL);
2932	break;	2932	break;
2933	case 1:	2933	case 1:
2934	temp &= ~(TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);	2934	temp &= ~(TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL);
2935	break;	2935	break;
2936	case 2:	2936	case 2:
2937	/* FIXME: manage transcoder PLLs? */	2937	/* FIXME: manage transcoder PLLs? */
2938	temp &= ~(TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL);	2938	temp &= ~(TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL);
2939	break;	2939	break;
2940	default:	2940	default:
2941	BUG(); /* wtf */	2941	BUG(); /* wtf */
2942	}	2942	}
2943	I915_WRITE(PCH_DPLL_SEL, temp);	2943	I915_WRITE(PCH_DPLL_SEL, temp);
2944	}	2944	}
2945		2945
2946	/* disable PCH DPLL */	2946	/* disable PCH DPLL */
2947	intel_disable_pch_pll(dev_priv, pipe);	2947	intel_disable_pch_pll(dev_priv, pipe);
2948		2948
2949	/* Switch from PCDclk to Rawclk */	2949	/* Switch from PCDclk to Rawclk */
2950	reg = FDI_RX_CTL(pipe);	2950	reg = FDI_RX_CTL(pipe);
2951	temp = I915_READ(reg);	2951	temp = I915_READ(reg);
2952	I915_WRITE(reg, temp & ~FDI_PCDCLK);	2952	I915_WRITE(reg, temp & ~FDI_PCDCLK);
2953		2953
2954	/* Disable CPU FDI TX PLL */	2954	/* Disable CPU FDI TX PLL */
2955	reg = FDI_TX_CTL(pipe);	2955	reg = FDI_TX_CTL(pipe);
2956	temp = I915_READ(reg);	2956	temp = I915_READ(reg);
2957	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);	2957	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2958		2958
2959	POSTING_READ(reg);	2959	POSTING_READ(reg);
2960	udelay(100);	2960	udelay(100);
2961		2961
2962	reg = FDI_RX_CTL(pipe);	2962	reg = FDI_RX_CTL(pipe);
2963	temp = I915_READ(reg);	2963	temp = I915_READ(reg);
2964	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);	2964	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2965		2965
2966	/* Wait for the clocks to turn off. */	2966	/* Wait for the clocks to turn off. */
2967	POSTING_READ(reg);	2967	POSTING_READ(reg);
2968	udelay(100);	2968	udelay(100);
2969		2969
2970	intel_crtc->active = false;	2970	intel_crtc->active = false;
2971	intel_update_watermarks(dev);	2971	intel_update_watermarks(dev);
2972	intel_update_fbc(dev);	2972	intel_update_fbc(dev);
2973	intel_clear_scanline_wait(dev);	2973	intel_clear_scanline_wait(dev);
2974	}	2974	}
2975		2975
2976	static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)	2976	static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2977	{	2977	{
2978	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	2978	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2979	int pipe = intel_crtc->pipe;	2979	int pipe = intel_crtc->pipe;
2980	int plane = intel_crtc->plane;	2980	int plane = intel_crtc->plane;
2981		2981
2982	/* XXX: When our outputs are all unaware of DPMS modes other than off	2982	/* XXX: When our outputs are all unaware of DPMS modes other than off
2983	* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.	2983	* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2984	*/	2984	*/
2985	switch (mode) {	2985	switch (mode) {
2986	case DRM_MODE_DPMS_ON:	2986	case DRM_MODE_DPMS_ON:
2987	case DRM_MODE_DPMS_STANDBY:	2987	case DRM_MODE_DPMS_STANDBY:
2988	case DRM_MODE_DPMS_SUSPEND:	2988	case DRM_MODE_DPMS_SUSPEND:
2989	DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);	2989	DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2990	ironlake_crtc_enable(crtc);	2990	ironlake_crtc_enable(crtc);
2991	break;	2991	break;
2992		2992
2993	case DRM_MODE_DPMS_OFF:	2993	case DRM_MODE_DPMS_OFF:
2994	DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);	2994	DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2995	ironlake_crtc_disable(crtc);	2995	ironlake_crtc_disable(crtc);
2996	break;	2996	break;
2997	}	2997	}
2998	}	2998	}
2999		2999
3000	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)	3000	static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3001	{	3001	{
3002	if (!enable && intel_crtc->overlay) {	3002	if (!enable && intel_crtc->overlay) {
3003	struct drm_device *dev = intel_crtc->base.dev;	3003	struct drm_device *dev = intel_crtc->base.dev;
3004	struct drm_i915_private *dev_priv = dev->dev_private;	3004	struct drm_i915_private *dev_priv = dev->dev_private;
3005		3005
3006	mutex_lock(&dev->struct_mutex);	3006	mutex_lock(&dev->struct_mutex);
3007	dev_priv->mm.interruptible = false;	3007	dev_priv->mm.interruptible = false;
3008	(void) intel_overlay_switch_off(intel_crtc->overlay);	3008	(void) intel_overlay_switch_off(intel_crtc->overlay);
3009	dev_priv->mm.interruptible = true;	3009	dev_priv->mm.interruptible = true;
3010	mutex_unlock(&dev->struct_mutex);	3010	mutex_unlock(&dev->struct_mutex);
3011	}	3011	}
3012		3012
3013	/* Let userspace switch the overlay on again. In most cases userspace	3013	/* Let userspace switch the overlay on again. In most cases userspace
3014	* has to recompute where to put it anyway.	3014	* has to recompute where to put it anyway.
3015	*/	3015	*/
3016	}	3016	}
3017		3017
3018	static void i9xx_crtc_enable(struct drm_crtc *crtc)	3018	static void i9xx_crtc_enable(struct drm_crtc *crtc)
3019	{	3019	{
3020	struct drm_device *dev = crtc->dev;	3020	struct drm_device *dev = crtc->dev;
3021	struct drm_i915_private *dev_priv = dev->dev_private;	3021	struct drm_i915_private *dev_priv = dev->dev_private;
3022	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3022	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3023	int pipe = intel_crtc->pipe;	3023	int pipe = intel_crtc->pipe;
3024	int plane = intel_crtc->plane;	3024	int plane = intel_crtc->plane;
3025		3025
3026	if (intel_crtc->active)	3026	if (intel_crtc->active)
3027	return;	3027	return;
3028		3028
3029	intel_crtc->active = true;	3029	intel_crtc->active = true;
3030	intel_update_watermarks(dev);	3030	intel_update_watermarks(dev);
3031		3031
3032	intel_enable_pll(dev_priv, pipe);	3032	intel_enable_pll(dev_priv, pipe);
3033	intel_enable_pipe(dev_priv, pipe, false);	3033	intel_enable_pipe(dev_priv, pipe, false);
3034	intel_enable_plane(dev_priv, plane, pipe);	3034	intel_enable_plane(dev_priv, plane, pipe);
3035		3035
3036	intel_crtc_load_lut(crtc);	3036	intel_crtc_load_lut(crtc);
3037	intel_update_fbc(dev);	3037	intel_update_fbc(dev);
3038		3038
3039	/* Give the overlay scaler a chance to enable if it's on this pipe */	3039	/* Give the overlay scaler a chance to enable if it's on this pipe */
3040	intel_crtc_dpms_overlay(intel_crtc, true);	3040	intel_crtc_dpms_overlay(intel_crtc, true);
3041	intel_crtc_update_cursor(crtc, true);	3041	intel_crtc_update_cursor(crtc, true);
3042	}	3042	}
3043		3043
3044	static void i9xx_crtc_disable(struct drm_crtc *crtc)	3044	static void i9xx_crtc_disable(struct drm_crtc *crtc)
3045	{	3045	{
3046	struct drm_device *dev = crtc->dev;	3046	struct drm_device *dev = crtc->dev;
3047	struct drm_i915_private *dev_priv = dev->dev_private;	3047	struct drm_i915_private *dev_priv = dev->dev_private;
3048	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3048	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3049	int pipe = intel_crtc->pipe;	3049	int pipe = intel_crtc->pipe;
3050	int plane = intel_crtc->plane;	3050	int plane = intel_crtc->plane;
3051		3051
3052	if (!intel_crtc->active)	3052	if (!intel_crtc->active)
3053	return;	3053	return;
3054		3054
3055	/* Give the overlay scaler a chance to disable if it's on this pipe */	3055	/* Give the overlay scaler a chance to disable if it's on this pipe */
3056	intel_crtc_wait_for_pending_flips(crtc);	3056	intel_crtc_wait_for_pending_flips(crtc);
3057	drm_vblank_off(dev, pipe);	3057	drm_vblank_off(dev, pipe);
3058	intel_crtc_dpms_overlay(intel_crtc, false);	3058	intel_crtc_dpms_overlay(intel_crtc, false);
3059	intel_crtc_update_cursor(crtc, false);	3059	intel_crtc_update_cursor(crtc, false);
3060		3060
3061	if (dev_priv->cfb_plane == plane &&	3061	if (dev_priv->cfb_plane == plane &&
3062	dev_priv->display.disable_fbc)	3062	dev_priv->display.disable_fbc)
3063	dev_priv->display.disable_fbc(dev);	3063	dev_priv->display.disable_fbc(dev);
3064		3064
3065	intel_disable_plane(dev_priv, plane, pipe);	3065	intel_disable_plane(dev_priv, plane, pipe);
3066	intel_disable_pipe(dev_priv, pipe);	3066	intel_disable_pipe(dev_priv, pipe);
3067	intel_disable_pll(dev_priv, pipe);	3067	intel_disable_pll(dev_priv, pipe);
3068		3068
3069	intel_crtc->active = false;	3069	intel_crtc->active = false;
3070	intel_update_fbc(dev);	3070	intel_update_fbc(dev);
3071	intel_update_watermarks(dev);	3071	intel_update_watermarks(dev);
3072	intel_clear_scanline_wait(dev);	3072	intel_clear_scanline_wait(dev);
3073	}	3073	}
3074		3074
3075	static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)	3075	static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3076	{	3076	{
3077	/* XXX: When our outputs are all unaware of DPMS modes other than off	3077	/* XXX: When our outputs are all unaware of DPMS modes other than off
3078	* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.	3078	* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3079	*/	3079	*/
3080	switch (mode) {	3080	switch (mode) {
3081	case DRM_MODE_DPMS_ON:	3081	case DRM_MODE_DPMS_ON:
3082	case DRM_MODE_DPMS_STANDBY:	3082	case DRM_MODE_DPMS_STANDBY:
3083	case DRM_MODE_DPMS_SUSPEND:	3083	case DRM_MODE_DPMS_SUSPEND:
3084	i9xx_crtc_enable(crtc);	3084	i9xx_crtc_enable(crtc);
3085	break;	3085	break;
3086	case DRM_MODE_DPMS_OFF:	3086	case DRM_MODE_DPMS_OFF:
3087	i9xx_crtc_disable(crtc);	3087	i9xx_crtc_disable(crtc);
3088	break;	3088	break;
3089	}	3089	}
3090	}	3090	}
3091		3091
3092	/**	3092	/**
3093	* Sets the power management mode of the pipe and plane.	3093	* Sets the power management mode of the pipe and plane.
3094	*/	3094	*/
3095	static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)	3095	static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3096	{	3096	{
3097	struct drm_device *dev = crtc->dev;	3097	struct drm_device *dev = crtc->dev;
3098	struct drm_i915_private *dev_priv = dev->dev_private;	3098	struct drm_i915_private *dev_priv = dev->dev_private;
3099	struct drm_i915_master_private *master_priv;	3099	struct drm_i915_master_private *master_priv;
3100	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	3100	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101	int pipe = intel_crtc->pipe;	3101	int pipe = intel_crtc->pipe;
3102	bool enabled;	3102	bool enabled;
3103		3103
3104	if (intel_crtc->dpms_mode == mode)	3104	if (intel_crtc->dpms_mode == mode)
3105	return;	3105	return;
3106		3106
3107	intel_crtc->dpms_mode = mode;	3107	intel_crtc->dpms_mode = mode;
3108		3108
3109	dev_priv->display.dpms(crtc, mode);	3109	dev_priv->display.dpms(crtc, mode);
3110		3110
3111	if (!dev->primary->master)	3111	if (!dev->primary->master)
3112	return;	3112	return;
3113		3113
3114	master_priv = dev->primary->master->driver_priv;	3114	master_priv = dev->primary->master->driver_priv;
3115	if (!master_priv->sarea_priv)	3115	if (!master_priv->sarea_priv)
3116	return;	3116	return;
3117		3117
3118	enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;	3118	enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3119		3119
3120	switch (pipe) {	3120	switch (pipe) {
3121	case 0:	3121	case 0:
3122	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;	3122	master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3123	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;	3123	master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3124	break;	3124	break;
3125	case 1:	3125	case 1:
3126	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;	3126	master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3127	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;	3127	master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3128	break;	3128	break;
3129	default:	3129	default:
3130	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));	3130	DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3131	break;	3131	break;
3132	}	3132	}
3133	}	3133	}
3134		3134
3135	static void intel_crtc_disable(struct drm_crtc *crtc)	3135	static void intel_crtc_disable(struct drm_crtc *crtc)
3136	{	3136	{
3137	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;	3137	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3138	struct drm_device *dev = crtc->dev;	3138	struct drm_device *dev = crtc->dev;
3139		3139
3140	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);	3140	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3141		3141
3142	if (crtc->fb) {	3142	if (crtc->fb) {
3143	mutex_lock(&dev->struct_mutex);	3143	mutex_lock(&dev->struct_mutex);
3144	i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);	3144	i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3145	mutex_unlock(&dev->struct_mutex);	3145	mutex_unlock(&dev->struct_mutex);
3146	}	3146	}
3147	}	3147	}
3148		3148
3149	/* Prepare for a mode set.	3149	/* Prepare for a mode set.
3150	*	3150	*
3151	* Note we could be a lot smarter here. We need to figure out which outputs	3151	* Note we could be a lot smarter here. We need to figure out which outputs
3152	* will be enabled, which disabled (in short, how the config will changes)	3152	* will be enabled, which disabled (in short, how the config will changes)
3153	* and perform the minimum necessary steps to accomplish that, e.g. updating	3153	* and perform the minimum necessary steps to accomplish that, e.g. updating
3154	* watermarks, FBC configuration, making sure PLLs are programmed correctly,	3154	* watermarks, FBC configuration, making sure PLLs are programmed correctly,
3155	* panel fitting is in the proper state, etc.	3155	* panel fitting is in the proper state, etc.
3156	*/	3156	*/
3157	static void i9xx_crtc_prepare(struct drm_crtc *crtc)	3157	static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3158	{	3158	{
3159	i9xx_crtc_disable(crtc);	3159	i9xx_crtc_disable(crtc);
3160	}	3160	}
3161		3161
3162	static void i9xx_crtc_commit(struct drm_crtc *crtc)	3162	static void i9xx_crtc_commit(struct drm_crtc *crtc)
3163	{	3163	{
3164	i9xx_crtc_enable(crtc);	3164	i9xx_crtc_enable(crtc);
3165	}	3165	}
3166		3166
3167	static void ironlake_crtc_prepare(struct drm_crtc *crtc)	3167	static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3168	{	3168	{
3169	ironlake_crtc_disable(crtc);	3169	ironlake_crtc_disable(crtc);
3170	}	3170	}
3171		3171
3172	static void ironlake_crtc_commit(struct drm_crtc *crtc)	3172	static void ironlake_crtc_commit(struct drm_crtc *crtc)
3173	{	3173	{
3174	ironlake_crtc_enable(crtc);	3174	ironlake_crtc_enable(crtc);
3175	}	3175	}
3176		3176
3177	void intel_encoder_prepare (struct drm_encoder *encoder)	3177	void intel_encoder_prepare (struct drm_encoder *encoder)
3178	{	3178	{
3179	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;	3179	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3180	/* lvds has its own version of prepare see intel_lvds_prepare */	3180	/* lvds has its own version of prepare see intel_lvds_prepare */
3181	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);	3181	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3182	}	3182	}
3183		3183
3184	void intel_encoder_commit (struct drm_encoder *encoder)	3184	void intel_encoder_commit (struct drm_encoder *encoder)
3185	{	3185	{
3186	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;	3186	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3187	/* lvds has its own version of commit see intel_lvds_commit */	3187	/* lvds has its own version of commit see intel_lvds_commit */
3188	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);	3188	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3189	}	3189	}
3190		3190
3191	void intel_encoder_destroy(struct drm_encoder *encoder)	3191	void intel_encoder_destroy(struct drm_encoder *encoder)
3192	{	3192	{
3193	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);	3193	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3194		3194
3195	drm_encoder_cleanup(encoder);	3195	drm_encoder_cleanup(encoder);
3196	kfree(intel_encoder);	3196	kfree(intel_encoder);
3197	}	3197	}
3198		3198
3199	static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,	3199	static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3200	struct drm_display_mode *mode,	3200	struct drm_display_mode *mode,
3201	struct drm_display_mode *adjusted_mode)	3201	struct drm_display_mode *adjusted_mode)
3202	{	3202	{
3203	struct drm_device *dev = crtc->dev;	3203	struct drm_device *dev = crtc->dev;
3204		3204
3205	if (HAS_PCH_SPLIT(dev)) {	3205	if (HAS_PCH_SPLIT(dev)) {
3206	/* FDI link clock is fixed at 2.7G */	3206	/* FDI link clock is fixed at 2.7G */
3207	if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)	3207	if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3208	return false;	3208	return false;
3209	}	3209	}
3210		3210
3211	/* XXX some encoders set the crtcinfo, others don't.	3211	/* XXX some encoders set the crtcinfo, others don't.
3212	* Obviously we need some form of conflict resolution here...	3212	* Obviously we need some form of conflict resolution here...
3213	*/	3213	*/
3214	if (adjusted_mode->crtc_htotal == 0)	3214	if (adjusted_mode->crtc_htotal == 0)
3215	drm_mode_set_crtcinfo(adjusted_mode, 0);	3215	drm_mode_set_crtcinfo(adjusted_mode, 0);
3216		3216
3217	return true;	3217	return true;
3218	}	3218	}
3219		3219
3220	static int i945_get_display_clock_speed(struct drm_device *dev)	3220	static int i945_get_display_clock_speed(struct drm_device *dev)
3221	{	3221	{
3222	return 400000;	3222	return 400000;
3223	}	3223	}
3224		3224
3225	static int i915_get_display_clock_speed(struct drm_device *dev)	3225	static int i915_get_display_clock_speed(struct drm_device *dev)
3226	{	3226	{
3227	return 333000;	3227	return 333000;
3228	}	3228	}
3229		3229
3230	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)	3230	static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3231	{	3231	{
3232	return 200000;	3232	return 200000;
3233	}	3233	}
3234		3234
3235	static int i915gm_get_display_clock_speed(struct drm_device *dev)	3235	static int i915gm_get_display_clock_speed(struct drm_device *dev)
3236	{	3236	{
3237	u16 gcfgc = 0;	3237	u16 gcfgc = 0;
3238		3238
3239	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);	3239	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3240		3240
3241	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)	3241	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3242	return 133000;	3242	return 133000;
3243	else {	3243	else {
3244	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {	3244	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3245	case GC_DISPLAY_CLOCK_333_MHZ:	3245	case GC_DISPLAY_CLOCK_333_MHZ:
3246	return 333000;	3246	return 333000;
3247	default:	3247	default:
3248	case GC_DISPLAY_CLOCK_190_200_MHZ:	3248	case GC_DISPLAY_CLOCK_190_200_MHZ:
3249	return 190000;	3249	return 190000;
3250	}	3250	}
3251	}	3251	}
3252	}	3252	}
3253		3253
3254	static int i865_get_display_clock_speed(struct drm_device *dev)	3254	static int i865_get_display_clock_speed(struct drm_device *dev)
3255	{	3255	{
3256	return 266000;	3256	return 266000;
3257	}	3257	}
3258		3258
3259	static int i855_get_display_clock_speed(struct drm_device *dev)	3259	static int i855_get_display_clock_speed(struct drm_device *dev)
3260	{	3260	{
3261	u16 hpllcc = 0;	3261	u16 hpllcc = 0;
3262	/* Assume that the hardware is in the high speed state. This	3262	/* Assume that the hardware is in the high speed state. This
3263	* should be the default.	3263	* should be the default.
3264	*/	3264	*/
3265	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {	3265	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3266	case GC_CLOCK_133_200:	3266	case GC_CLOCK_133_200:
3267	case GC_CLOCK_100_200:	3267	case GC_CLOCK_100_200:
3268	return 200000;	3268	return 200000;
3269	case GC_CLOCK_166_250:	3269	case GC_CLOCK_166_250:
3270	return 250000;	3270	return 250000;
3271	case GC_CLOCK_100_133:	3271	case GC_CLOCK_100_133:
3272	return 133000;	3272	return 133000;
3273	}	3273	}
3274		3274
3275	/* Shouldn't happen */	3275	/* Shouldn't happen */
3276	return 0;	3276	return 0;
3277	}	3277	}
3278		3278
3279	static int i830_get_display_clock_speed(struct drm_device *dev)	3279	static int i830_get_display_clock_speed(struct drm_device *dev)
3280	{	3280	{
3281	return 133000;	3281	return 133000;
3282	}	3282	}
3283		3283
3284	struct fdi_m_n {	3284	struct fdi_m_n {
3285	u32 tu;	3285	u32 tu;
3286	u32 gmch_m;	3286	u32 gmch_m;
3287	u32 gmch_n;	3287	u32 gmch_n;
3288	u32 link_m;	3288	u32 link_m;
3289	u32 link_n;	3289	u32 link_n;
3290	};	3290	};
3291		3291
3292	static void	3292	static void
3293	fdi_reduce_ratio(u32 num, u32 den)	3293	fdi_reduce_ratio(u32 num, u32 den)
3294	{	3294	{
3295	while (num > 0xffffff \|\| den > 0xffffff) {	3295	while (num > 0xffffff \|\| den > 0xffffff) {
3296	*num >>= 1;	3296	*num >>= 1;
3297	*den >>= 1;	3297	*den >>= 1;
3298	}	3298	}
3299	}	3299	}
3300		3300
3301	static void	3301	static void
3302	ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,	3302	ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3303	int link_clock, struct fdi_m_n *m_n)	3303	int link_clock, struct fdi_m_n *m_n)
3304	{	3304	{
3305	m_n->tu = 64; /* default size */	3305	m_n->tu = 64; /* default size */
3306		3306
3307	/* BUG_ON(pixel_clock > INT_MAX / 36); */	3307	/* BUG_ON(pixel_clock > INT_MAX / 36); */
3308	m_n->gmch_m = bits_per_pixel * pixel_clock;	3308	m_n->gmch_m = bits_per_pixel * pixel_clock;
3309	m_n->gmch_n = link_clock * nlanes * 8;	3309	m_n->gmch_n = link_clock * nlanes * 8;
3310	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);	3310	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3311		3311
3312	m_n->link_m = pixel_clock;	3312	m_n->link_m = pixel_clock;
3313	m_n->link_n = link_clock;	3313	m_n->link_n = link_clock;
3314	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);	3314	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3315	}	3315	}
3316		3316
3317		3317
3318	struct intel_watermark_params {	3318	struct intel_watermark_params {
3319	unsigned long fifo_size;	3319	unsigned long fifo_size;
3320	unsigned long max_wm;	3320	unsigned long max_wm;
3321	unsigned long default_wm;	3321	unsigned long default_wm;
3322	unsigned long guard_size;	3322	unsigned long guard_size;
3323	unsigned long cacheline_size;	3323	unsigned long cacheline_size;
3324	};	3324	};
3325		3325
3326	/* Pineview has different values for various configs */	3326	/* Pineview has different values for various configs */
3327	static const struct intel_watermark_params pineview_display_wm = {	3327	static const struct intel_watermark_params pineview_display_wm = {
3328	PINEVIEW_DISPLAY_FIFO,	3328	PINEVIEW_DISPLAY_FIFO,
3329	PINEVIEW_MAX_WM,	3329	PINEVIEW_MAX_WM,
3330	PINEVIEW_DFT_WM,	3330	PINEVIEW_DFT_WM,
3331	PINEVIEW_GUARD_WM,	3331	PINEVIEW_GUARD_WM,
3332	PINEVIEW_FIFO_LINE_SIZE	3332	PINEVIEW_FIFO_LINE_SIZE
3333	};	3333	};
3334	static const struct intel_watermark_params pineview_display_hplloff_wm = {	3334	static const struct intel_watermark_params pineview_display_hplloff_wm = {
3335	PINEVIEW_DISPLAY_FIFO,	3335	PINEVIEW_DISPLAY_FIFO,
3336	PINEVIEW_MAX_WM,	3336	PINEVIEW_MAX_WM,
3337	PINEVIEW_DFT_HPLLOFF_WM,	3337	PINEVIEW_DFT_HPLLOFF_WM,
3338	PINEVIEW_GUARD_WM,	3338	PINEVIEW_GUARD_WM,
3339	PINEVIEW_FIFO_LINE_SIZE	3339	PINEVIEW_FIFO_LINE_SIZE
3340	};	3340	};
3341	static const struct intel_watermark_params pineview_cursor_wm = {	3341	static const struct intel_watermark_params pineview_cursor_wm = {
3342	PINEVIEW_CURSOR_FIFO,	3342	PINEVIEW_CURSOR_FIFO,
3343	PINEVIEW_CURSOR_MAX_WM,	3343	PINEVIEW_CURSOR_MAX_WM,
3344	PINEVIEW_CURSOR_DFT_WM,	3344	PINEVIEW_CURSOR_DFT_WM,
3345	PINEVIEW_CURSOR_GUARD_WM,	3345	PINEVIEW_CURSOR_GUARD_WM,
3346	PINEVIEW_FIFO_LINE_SIZE,	3346	PINEVIEW_FIFO_LINE_SIZE,
3347	};	3347	};
3348	static const struct intel_watermark_params pineview_cursor_hplloff_wm = {	3348	static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3349	PINEVIEW_CURSOR_FIFO,	3349	PINEVIEW_CURSOR_FIFO,
3350	PINEVIEW_CURSOR_MAX_WM,	3350	PINEVIEW_CURSOR_MAX_WM,
3351	PINEVIEW_CURSOR_DFT_WM,	3351	PINEVIEW_CURSOR_DFT_WM,
3352	PINEVIEW_CURSOR_GUARD_WM,	3352	PINEVIEW_CURSOR_GUARD_WM,
3353	PINEVIEW_FIFO_LINE_SIZE	3353	PINEVIEW_FIFO_LINE_SIZE
3354	};	3354	};
3355	static const struct intel_watermark_params g4x_wm_info = {	3355	static const struct intel_watermark_params g4x_wm_info = {
3356	G4X_FIFO_SIZE,	3356	G4X_FIFO_SIZE,
3357	G4X_MAX_WM,	3357	G4X_MAX_WM,
3358	G4X_MAX_WM,	3358	G4X_MAX_WM,
3359	2,	3359	2,
3360	G4X_FIFO_LINE_SIZE,	3360	G4X_FIFO_LINE_SIZE,
3361	};	3361	};
3362	static const struct intel_watermark_params g4x_cursor_wm_info = {	3362	static const struct intel_watermark_params g4x_cursor_wm_info = {
3363	I965_CURSOR_FIFO,	3363	I965_CURSOR_FIFO,
3364	I965_CURSOR_MAX_WM,	3364	I965_CURSOR_MAX_WM,
3365	I965_CURSOR_DFT_WM,	3365	I965_CURSOR_DFT_WM,
3366	2,	3366	2,
3367	G4X_FIFO_LINE_SIZE,	3367	G4X_FIFO_LINE_SIZE,
3368	};	3368	};
3369	static const struct intel_watermark_params i965_cursor_wm_info = {	3369	static const struct intel_watermark_params i965_cursor_wm_info = {
3370	I965_CURSOR_FIFO,	3370	I965_CURSOR_FIFO,
3371	I965_CURSOR_MAX_WM,	3371	I965_CURSOR_MAX_WM,
3372	I965_CURSOR_DFT_WM,	3372	I965_CURSOR_DFT_WM,
3373	2,	3373	2,
3374	I915_FIFO_LINE_SIZE,	3374	I915_FIFO_LINE_SIZE,
3375	};	3375	};
3376	static const struct intel_watermark_params i945_wm_info = {	3376	static const struct intel_watermark_params i945_wm_info = {
3377	I945_FIFO_SIZE,	3377	I945_FIFO_SIZE,
3378	I915_MAX_WM,	3378	I915_MAX_WM,
3379	1,	3379	1,
3380	2,	3380	2,
3381	I915_FIFO_LINE_SIZE	3381	I915_FIFO_LINE_SIZE
3382	};	3382	};
3383	static const struct intel_watermark_params i915_wm_info = {	3383	static const struct intel_watermark_params i915_wm_info = {
3384	I915_FIFO_SIZE,	3384	I915_FIFO_SIZE,
3385	I915_MAX_WM,	3385	I915_MAX_WM,
3386	1,	3386	1,
3387	2,	3387	2,
3388	I915_FIFO_LINE_SIZE	3388	I915_FIFO_LINE_SIZE
3389	};	3389	};
3390	static const struct intel_watermark_params i855_wm_info = {	3390	static const struct intel_watermark_params i855_wm_info = {
3391	I855GM_FIFO_SIZE,	3391	I855GM_FIFO_SIZE,
3392	I915_MAX_WM,	3392	I915_MAX_WM,
3393	1,	3393	1,
3394	2,	3394	2,
3395	I830_FIFO_LINE_SIZE	3395	I830_FIFO_LINE_SIZE
3396	};	3396	};
3397	static const struct intel_watermark_params i830_wm_info = {	3397	static const struct intel_watermark_params i830_wm_info = {
3398	I830_FIFO_SIZE,	3398	I830_FIFO_SIZE,
3399	I915_MAX_WM,	3399	I915_MAX_WM,
3400	1,	3400	1,
3401	2,	3401	2,
3402	I830_FIFO_LINE_SIZE	3402	I830_FIFO_LINE_SIZE
3403	};	3403	};
3404		3404
3405	static const struct intel_watermark_params ironlake_display_wm_info = {	3405	static const struct intel_watermark_params ironlake_display_wm_info = {
3406	ILK_DISPLAY_FIFO,	3406	ILK_DISPLAY_FIFO,
3407	ILK_DISPLAY_MAXWM,	3407	ILK_DISPLAY_MAXWM,
3408	ILK_DISPLAY_DFTWM,	3408	ILK_DISPLAY_DFTWM,
3409	2,	3409	2,
3410	ILK_FIFO_LINE_SIZE	3410	ILK_FIFO_LINE_SIZE
3411	};	3411	};
3412	static const struct intel_watermark_params ironlake_cursor_wm_info = {	3412	static const struct intel_watermark_params ironlake_cursor_wm_info = {
3413	ILK_CURSOR_FIFO,	3413	ILK_CURSOR_FIFO,
3414	ILK_CURSOR_MAXWM,	3414	ILK_CURSOR_MAXWM,
3415	ILK_CURSOR_DFTWM,	3415	ILK_CURSOR_DFTWM,
3416	2,	3416	2,
3417	ILK_FIFO_LINE_SIZE	3417	ILK_FIFO_LINE_SIZE
3418	};	3418	};
3419	static const struct intel_watermark_params ironlake_display_srwm_info = {	3419	static const struct intel_watermark_params ironlake_display_srwm_info = {
3420	ILK_DISPLAY_SR_FIFO,	3420	ILK_DISPLAY_SR_FIFO,
3421	ILK_DISPLAY_MAX_SRWM,	3421	ILK_DISPLAY_MAX_SRWM,
3422	ILK_DISPLAY_DFT_SRWM,	3422	ILK_DISPLAY_DFT_SRWM,
3423	2,	3423	2,
3424	ILK_FIFO_LINE_SIZE	3424	ILK_FIFO_LINE_SIZE
3425	};	3425	};
3426	static const struct intel_watermark_params ironlake_cursor_srwm_info = {	3426	static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3427	ILK_CURSOR_SR_FIFO,	3427	ILK_CURSOR_SR_FIFO,
3428	ILK_CURSOR_MAX_SRWM,	3428	ILK_CURSOR_MAX_SRWM,
3429	ILK_CURSOR_DFT_SRWM,	3429	ILK_CURSOR_DFT_SRWM,
3430	2,	3430	2,
3431	ILK_FIFO_LINE_SIZE	3431	ILK_FIFO_LINE_SIZE
3432	};	3432	};
3433		3433
3434	static const struct intel_watermark_params sandybridge_display_wm_info = {	3434	static const struct intel_watermark_params sandybridge_display_wm_info = {
3435	SNB_DISPLAY_FIFO,	3435	SNB_DISPLAY_FIFO,
3436	SNB_DISPLAY_MAXWM,	3436	SNB_DISPLAY_MAXWM,
3437	SNB_DISPLAY_DFTWM,	3437	SNB_DISPLAY_DFTWM,
3438	2,	3438	2,
3439	SNB_FIFO_LINE_SIZE	3439	SNB_FIFO_LINE_SIZE
3440	};	3440	};
3441	static const struct intel_watermark_params sandybridge_cursor_wm_info = {	3441	static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3442	SNB_CURSOR_FIFO,	3442	SNB_CURSOR_FIFO,
3443	SNB_CURSOR_MAXWM,	3443	SNB_CURSOR_MAXWM,
3444	SNB_CURSOR_DFTWM,	3444	SNB_CURSOR_DFTWM,
3445	2,	3445	2,
3446	SNB_FIFO_LINE_SIZE	3446	SNB_FIFO_LINE_SIZE
3447	};	3447	};
3448	static const struct intel_watermark_params sandybridge_display_srwm_info = {	3448	static const struct intel_watermark_params sandybridge_display_srwm_info = {
3449	SNB_DISPLAY_SR_FIFO,	3449	SNB_DISPLAY_SR_FIFO,
3450	SNB_DISPLAY_MAX_SRWM,	3450	SNB_DISPLAY_MAX_SRWM,
3451	SNB_DISPLAY_DFT_SRWM,	3451	SNB_DISPLAY_DFT_SRWM,
3452	2,	3452	2,
3453	SNB_FIFO_LINE_SIZE	3453	SNB_FIFO_LINE_SIZE
3454	};	3454	};
3455	static const struct intel_watermark_params sandybridge_cursor_srwm_info = {	3455	static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3456	SNB_CURSOR_SR_FIFO,	3456	SNB_CURSOR_SR_FIFO,
3457	SNB_CURSOR_MAX_SRWM,	3457	SNB_CURSOR_MAX_SRWM,
3458	SNB_CURSOR_DFT_SRWM,	3458	SNB_CURSOR_DFT_SRWM,
3459	2,	3459	2,
3460	SNB_FIFO_LINE_SIZE	3460	SNB_FIFO_LINE_SIZE
3461	};	3461	};
3462		3462
3463		3463
3464	/**	3464	/**
3465	* intel_calculate_wm - calculate watermark level	3465	* intel_calculate_wm - calculate watermark level
3466	* @clock_in_khz: pixel clock	3466	* @clock_in_khz: pixel clock
3467	* @wm: chip FIFO params	3467	* @wm: chip FIFO params
3468	* @pixel_size: display pixel size	3468	* @pixel_size: display pixel size
3469	* @latency_ns: memory latency for the platform	3469	* @latency_ns: memory latency for the platform
3470	*	3470	*
3471	* Calculate the watermark level (the level at which the display plane will	3471	* Calculate the watermark level (the level at which the display plane will
3472	* start fetching from memory again). Each chip has a different display	3472	* start fetching from memory again). Each chip has a different display
3473	* FIFO size and allocation, so the caller needs to figure that out and pass	3473	* FIFO size and allocation, so the caller needs to figure that out and pass
3474	* in the correct intel_watermark_params structure.	3474	* in the correct intel_watermark_params structure.
3475	*	3475	*
3476	* As the pixel clock runs, the FIFO will be drained at a rate that depends	3476	* As the pixel clock runs, the FIFO will be drained at a rate that depends
3477	* on the pixel size. When it reaches the watermark level, it'll start	3477	* on the pixel size. When it reaches the watermark level, it'll start
3478	* fetching FIFO line sized based chunks from memory until the FIFO fills	3478	* fetching FIFO line sized based chunks from memory until the FIFO fills
3479	* past the watermark point. If the FIFO drains completely, a FIFO underrun	3479	* past the watermark point. If the FIFO drains completely, a FIFO underrun
3480	* will occur, and a display engine hang could result.	3480	* will occur, and a display engine hang could result.
3481	*/	3481	*/
3482	static unsigned long intel_calculate_wm(unsigned long clock_in_khz,	3482	static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3483	const struct intel_watermark_params *wm,	3483	const struct intel_watermark_params *wm,
3484	int fifo_size,	3484	int fifo_size,
3485	int pixel_size,	3485	int pixel_size,
3486	unsigned long latency_ns)	3486	unsigned long latency_ns)
3487	{	3487	{
3488	long entries_required, wm_size;	3488	long entries_required, wm_size;
3489		3489
3490	/*	3490	/*
3491	* Note: we need to make sure we don't overflow for various clock &	3491	* Note: we need to make sure we don't overflow for various clock &
3492	* latency values.	3492	* latency values.
3493	* clocks go from a few thousand to several hundred thousand.	3493	* clocks go from a few thousand to several hundred thousand.
3494	* latency is usually a few thousand	3494	* latency is usually a few thousand
3495	*/	3495	*/
3496	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /	3496	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3497	1000;	3497	1000;
3498	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);	3498	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3499		3499
3500	DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);	3500	DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3501		3501
3502	wm_size = fifo_size - (entries_required + wm->guard_size);	3502	wm_size = fifo_size - (entries_required + wm->guard_size);
3503		3503
3504	DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);	3504	DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3505		3505
3506	/* Don't promote wm_size to unsigned... */	3506	/* Don't promote wm_size to unsigned... */
3507	if (wm_size > (long)wm->max_wm)	3507	if (wm_size > (long)wm->max_wm)
3508	wm_size = wm->max_wm;	3508	wm_size = wm->max_wm;
3509	if (wm_size <= 0)	3509	if (wm_size <= 0)
3510	wm_size = wm->default_wm;	3510	wm_size = wm->default_wm;
3511	return wm_size;	3511	return wm_size;
3512	}	3512	}
3513		3513
3514	struct cxsr_latency {	3514	struct cxsr_latency {
3515	int is_desktop;	3515	int is_desktop;
3516	int is_ddr3;	3516	int is_ddr3;
3517	unsigned long fsb_freq;	3517	unsigned long fsb_freq;
3518	unsigned long mem_freq;	3518	unsigned long mem_freq;
3519	unsigned long display_sr;	3519	unsigned long display_sr;
3520	unsigned long display_hpll_disable;	3520	unsigned long display_hpll_disable;
3521	unsigned long cursor_sr;	3521	unsigned long cursor_sr;
3522	unsigned long cursor_hpll_disable;	3522	unsigned long cursor_hpll_disable;
3523	};	3523	};
3524		3524
3525	static const struct cxsr_latency cxsr_latency_table[] = {	3525	static const struct cxsr_latency cxsr_latency_table[] = {
3526	{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */	3526	{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3527	{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */	3527	{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3528	{1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */	3528	{1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3529	{1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */	3529	{1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3530	{1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */	3530	{1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3531		3531
3532	{1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */	3532	{1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3533	{1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */	3533	{1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3534	{1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */	3534	{1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3535	{1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */	3535	{1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3536	{1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */	3536	{1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3537		3537
3538	{1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */	3538	{1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3539	{1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */	3539	{1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3540	{1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */	3540	{1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3541	{1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */	3541	{1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3542	{1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */	3542	{1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3543		3543
3544	{0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */	3544	{0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3545	{0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */	3545	{0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3546	{0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */	3546	{0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3547	{0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */	3547	{0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3548	{0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */	3548	{0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3549		3549
3550	{0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */	3550	{0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3551	{0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */	3551	{0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3552	{0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */	3552	{0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3553	{0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */	3553	{0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3554	{0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */	3554	{0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3555		3555
3556	{0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */	3556	{0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3557	{0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */	3557	{0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3558	{0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */	3558	{0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3559	{0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */	3559	{0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3560	{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */	3560	{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3561	};	3561	};
3562		3562
3563	static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,	3563	static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3564	int is_ddr3,	3564	int is_ddr3,
3565	int fsb,	3565	int fsb,
3566	int mem)	3566	int mem)
3567	{	3567	{
3568	const struct cxsr_latency *latency;	3568	const struct cxsr_latency *latency;
3569	int i;	3569	int i;
3570		3570
3571	if (fsb == 0 \|\| mem == 0)	3571	if (fsb == 0 \|\| mem == 0)
3572	return NULL;	3572	return NULL;
3573		3573
3574	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {	3574	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3575	latency = &cxsr_latency_table[i];	3575	latency = &cxsr_latency_table[i];
3576	if (is_desktop == latency->is_desktop &&	3576	if (is_desktop == latency->is_desktop &&
3577	is_ddr3 == latency->is_ddr3 &&	3577	is_ddr3 == latency->is_ddr3 &&
3578	fsb == latency->fsb_freq && mem == latency->mem_freq)	3578	fsb == latency->fsb_freq && mem == latency->mem_freq)
3579	return latency;	3579	return latency;
3580	}	3580	}
3581		3581
3582	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");	3582	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3583		3583
3584	return NULL;	3584	return NULL;
3585	}	3585	}
3586		3586
3587	static void pineview_disable_cxsr(struct drm_device *dev)	3587	static void pineview_disable_cxsr(struct drm_device *dev)
3588	{	3588	{
3589	struct drm_i915_private *dev_priv = dev->dev_private;	3589	struct drm_i915_private *dev_priv = dev->dev_private;
3590		3590
3591	/* deactivate cxsr */	3591	/* deactivate cxsr */
3592	I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);	3592	I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3593	}	3593	}
3594		3594
3595	/*	3595	/*
3596	* Latency for FIFO fetches is dependent on several factors:	3596	* Latency for FIFO fetches is dependent on several factors:
3597	* - memory configuration (speed, channels)	3597	* - memory configuration (speed, channels)
3598	* - chipset	3598	* - chipset
3599	* - current MCH state	3599	* - current MCH state
3600	* It can be fairly high in some situations, so here we assume a fairly	3600	* It can be fairly high in some situations, so here we assume a fairly
3601	* pessimal value. It's a tradeoff between extra memory fetches (if we	3601	* pessimal value. It's a tradeoff between extra memory fetches (if we
3602	* set this value too high, the FIFO will fetch frequently to stay full)	3602	* set this value too high, the FIFO will fetch frequently to stay full)
3603	* and power consumption (set it too low to save power and we might see	3603	* and power consumption (set it too low to save power and we might see
3604	* FIFO underruns and display "flicker").	3604	* FIFO underruns and display "flicker").
3605	*	3605	*
3606	* A value of 5us seems to be a good balance; safe for very low end	3606	* A value of 5us seems to be a good balance; safe for very low end
3607	* platforms but not overly aggressive on lower latency configs.	3607	* platforms but not overly aggressive on lower latency configs.
3608	*/	3608	*/
3609	static const int latency_ns = 5000;	3609	static const int latency_ns = 5000;
3610		3610
3611	static int i9xx_get_fifo_size(struct drm_device *dev, int plane)	3611	static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3612	{	3612	{
3613	struct drm_i915_private *dev_priv = dev->dev_private;	3613	struct drm_i915_private *dev_priv = dev->dev_private;
3614	uint32_t dsparb = I915_READ(DSPARB);	3614	uint32_t dsparb = I915_READ(DSPARB);
3615	int size;	3615	int size;
3616		3616
3617	size = dsparb & 0x7f;	3617	size = dsparb & 0x7f;
3618	if (plane)	3618	if (plane)
3619	size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;	3619	size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3620		3620
3621	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,	3621	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3622	plane ? "B" : "A", size);	3622	plane ? "B" : "A", size);
3623		3623
3624	return size;	3624	return size;
3625	}	3625	}
3626		3626
3627	static int i85x_get_fifo_size(struct drm_device *dev, int plane)	3627	static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3628	{	3628	{
3629	struct drm_i915_private *dev_priv = dev->dev_private;	3629	struct drm_i915_private *dev_priv = dev->dev_private;
3630	uint32_t dsparb = I915_READ(DSPARB);	3630	uint32_t dsparb = I915_READ(DSPARB);
3631	int size;	3631	int size;
3632		3632
3633	size = dsparb & 0x1ff;	3633	size = dsparb & 0x1ff;
3634	if (plane)	3634	if (plane)
3635	size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;	3635	size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3636	size >>= 1; /* Convert to cachelines */	3636	size >>= 1; /* Convert to cachelines */
3637		3637
3638	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,	3638	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3639	plane ? "B" : "A", size);	3639	plane ? "B" : "A", size);
3640		3640
3641	return size;	3641	return size;
3642	}	3642	}
3643		3643
3644	static int i845_get_fifo_size(struct drm_device *dev, int plane)	3644	static int i845_get_fifo_size(struct drm_device *dev, int plane)
3645	{	3645	{
3646	struct drm_i915_private *dev_priv = dev->dev_private;	3646	struct drm_i915_private *dev_priv = dev->dev_private;
3647	uint32_t dsparb = I915_READ(DSPARB);	3647	uint32_t dsparb = I915_READ(DSPARB);
3648	int size;	3648	int size;
3649		3649
3650	size = dsparb & 0x7f;	3650	size = dsparb & 0x7f;
3651	size >>= 2; /* Convert to cachelines */	3651	size >>= 2; /* Convert to cachelines */
3652		3652
3653	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,	3653	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3654	plane ? "B" : "A",	3654	plane ? "B" : "A",
3655	size);	3655	size);
3656		3656
3657	return size;	3657	return size;
3658	}	3658	}
3659		3659
3660	static int i830_get_fifo_size(struct drm_device *dev, int plane)	3660	static int i830_get_fifo_size(struct drm_device *dev, int plane)
3661	{	3661	{
3662	struct drm_i915_private *dev_priv = dev->dev_private;	3662	struct drm_i915_private *dev_priv = dev->dev_private;
3663	uint32_t dsparb = I915_READ(DSPARB);	3663	uint32_t dsparb = I915_READ(DSPARB);
3664	int size;	3664	int size;
3665		3665
3666	size = dsparb & 0x7f;	3666	size = dsparb & 0x7f;
3667	size >>= 1; /* Convert to cachelines */	3667	size >>= 1; /* Convert to cachelines */
3668		3668
3669	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,	3669	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3670	plane ? "B" : "A", size);	3670	plane ? "B" : "A", size);
3671		3671
3672	return size;	3672	return size;
3673	}	3673	}
3674		3674
3675	static struct drm_crtc single_enabled_crtc(struct drm_device dev)	3675	static struct drm_crtc single_enabled_crtc(struct drm_device dev)
3676	{	3676	{
3677	struct drm_crtc crtc, enabled = NULL;	3677	struct drm_crtc crtc, enabled = NULL;
3678		3678
3679	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {	3679	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3680	if (crtc->enabled && crtc->fb) {	3680	if (crtc->enabled && crtc->fb) {
3681	if (enabled)	3681	if (enabled)
3682	return NULL;	3682	return NULL;
3683	enabled = crtc;	3683	enabled = crtc;
3684	}	3684	}
3685	}	3685	}
3686		3686
3687	return enabled;	3687	return enabled;
3688	}	3688	}
3689		3689
3690	static void pineview_update_wm(struct drm_device *dev)	3690	static void pineview_update_wm(struct drm_device *dev)
3691	{	3691	{
3692	struct drm_i915_private *dev_priv = dev->dev_private;	3692	struct drm_i915_private *dev_priv = dev->dev_private;
3693	struct drm_crtc *crtc;	3693	struct drm_crtc *crtc;
3694	const struct cxsr_latency *latency;	3694	const struct cxsr_latency *latency;
3695	u32 reg;	3695	u32 reg;
3696	unsigned long wm;	3696	unsigned long wm;
3697		3697
3698	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,	3698	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3699	dev_priv->fsb_freq, dev_priv->mem_freq);	3699	dev_priv->fsb_freq, dev_priv->mem_freq);
3700	if (!latency) {	3700	if (!latency) {
3701	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");	3701	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3702	pineview_disable_cxsr(dev);	3702	pineview_disable_cxsr(dev);
3703	return;	3703	return;
3704	}	3704	}
3705		3705
3706	crtc = single_enabled_crtc(dev);	3706	crtc = single_enabled_crtc(dev);
3707	if (crtc) {	3707	if (crtc) {
3708	int clock = crtc->mode.clock;	3708	int clock = crtc->mode.clock;
3709	int pixel_size = crtc->fb->bits_per_pixel / 8;	3709	int pixel_size = crtc->fb->bits_per_pixel / 8;
3710		3710
3711	/* Display SR */	3711	/* Display SR */
3712	wm = intel_calculate_wm(clock, &pineview_display_wm,	3712	wm = intel_calculate_wm(clock, &pineview_display_wm,
3713	pineview_display_wm.fifo_size,	3713	pineview_display_wm.fifo_size,
3714	pixel_size, latency->display_sr);	3714	pixel_size, latency->display_sr);
3715	reg = I915_READ(DSPFW1);	3715	reg = I915_READ(DSPFW1);
3716	reg &= ~DSPFW_SR_MASK;	3716	reg &= ~DSPFW_SR_MASK;
3717	reg \|= wm << DSPFW_SR_SHIFT;	3717	reg \|= wm << DSPFW_SR_SHIFT;
3718	I915_WRITE(DSPFW1, reg);	3718	I915_WRITE(DSPFW1, reg);
3719	DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);	3719	DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3720		3720
3721	/* cursor SR */	3721	/* cursor SR */
3722	wm = intel_calculate_wm(clock, &pineview_cursor_wm,	3722	wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3723	pineview_display_wm.fifo_size,	3723	pineview_display_wm.fifo_size,
3724	pixel_size, latency->cursor_sr);	3724	pixel_size, latency->cursor_sr);
3725	reg = I915_READ(DSPFW3);	3725	reg = I915_READ(DSPFW3);
3726	reg &= ~DSPFW_CURSOR_SR_MASK;	3726	reg &= ~DSPFW_CURSOR_SR_MASK;
3727	reg \|= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;	3727	reg \|= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3728	I915_WRITE(DSPFW3, reg);	3728	I915_WRITE(DSPFW3, reg);
3729		3729
3730	/* Display HPLL off SR */	3730	/* Display HPLL off SR */
3731	wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,	3731	wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3732	pineview_display_hplloff_wm.fifo_size,	3732	pineview_display_hplloff_wm.fifo_size,
3733	pixel_size, latency->display_hpll_disable);	3733	pixel_size, latency->display_hpll_disable);
3734	reg = I915_READ(DSPFW3);	3734	reg = I915_READ(DSPFW3);
3735	reg &= ~DSPFW_HPLL_SR_MASK;	3735	reg &= ~DSPFW_HPLL_SR_MASK;
3736	reg \|= wm & DSPFW_HPLL_SR_MASK;	3736	reg \|= wm & DSPFW_HPLL_SR_MASK;
3737	I915_WRITE(DSPFW3, reg);	3737	I915_WRITE(DSPFW3, reg);
3738		3738
3739	/* cursor HPLL off SR */	3739	/* cursor HPLL off SR */
3740	wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,	3740	wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3741	pineview_display_hplloff_wm.fifo_size,	3741	pineview_display_hplloff_wm.fifo_size,
3742	pixel_size, latency->cursor_hpll_disable);	3742	pixel_size, latency->cursor_hpll_disable);
3743	reg = I915_READ(DSPFW3);	3743	reg = I915_READ(DSPFW3);
3744	reg &= ~DSPFW_HPLL_CURSOR_MASK;	3744	reg &= ~DSPFW_HPLL_CURSOR_MASK;
3745	reg \|= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;	3745	reg \|= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3746	I915_WRITE(DSPFW3, reg);	3746	I915_WRITE(DSPFW3, reg);
3747	DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);	3747	DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3748		3748
3749	/* activate cxsr */	3749	/* activate cxsr */
3750	I915_WRITE(DSPFW3,	3750	I915_WRITE(DSPFW3,
3751	I915_READ(DSPFW3) \| PINEVIEW_SELF_REFRESH_EN);	3751	I915_READ(DSPFW3) \| PINEVIEW_SELF_REFRESH_EN);
3752	DRM_DEBUG_KMS("Self-refresh is enabled\n");	3752	DRM_DEBUG_KMS("Self-refresh is enabled\n");
3753	} else {	3753	} else {
3754	pineview_disable_cxsr(dev);	3754	pineview_disable_cxsr(dev);
3755	DRM_DEBUG_KMS("Self-refresh is disabled\n");	3755	DRM_DEBUG_KMS("Self-refresh is disabled\n");
3756	}	3756	}
3757	}	3757	}
3758		3758
3759	static bool g4x_compute_wm0(struct drm_device *dev,	3759	static bool g4x_compute_wm0(struct drm_device *dev,
3760	int plane,	3760	int plane,
3761	const struct intel_watermark_params *display,	3761	const struct intel_watermark_params *display,
3762	int display_latency_ns,	3762	int display_latency_ns,
3763	const struct intel_watermark_params *cursor,	3763	const struct intel_watermark_params *cursor,
3764	int cursor_latency_ns,	3764	int cursor_latency_ns,
3765	int *plane_wm,	3765	int *plane_wm,
3766	int *cursor_wm)	3766	int *cursor_wm)
3767	{	3767	{
3768	struct drm_crtc *crtc;	3768	struct drm_crtc *crtc;
3769	int htotal, hdisplay, clock, pixel_size;	3769	int htotal, hdisplay, clock, pixel_size;
3770	int line_time_us, line_count;	3770	int line_time_us, line_count;
3771	int entries, tlb_miss;	3771	int entries, tlb_miss;
3772		3772
3773	crtc = intel_get_crtc_for_plane(dev, plane);	3773	crtc = intel_get_crtc_for_plane(dev, plane);
3774	if (crtc->fb == NULL \|\| !crtc->enabled) {	3774	if (crtc->fb == NULL \|\| !crtc->enabled) {
3775	*cursor_wm = cursor->guard_size;	3775	*cursor_wm = cursor->guard_size;
3776	*plane_wm = display->guard_size;	3776	*plane_wm = display->guard_size;
3777	return false;	3777	return false;
3778	}	3778	}
3779		3779
3780	htotal = crtc->mode.htotal;	3780	htotal = crtc->mode.htotal;
3781	hdisplay = crtc->mode.hdisplay;	3781	hdisplay = crtc->mode.hdisplay;
3782	clock = crtc->mode.clock;	3782	clock = crtc->mode.clock;
3783	pixel_size = crtc->fb->bits_per_pixel / 8;	3783	pixel_size = crtc->fb->bits_per_pixel / 8;
3784		3784
3785	/* Use the small buffer method to calculate plane watermark */	3785	/* Use the small buffer method to calculate plane watermark */
3786	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;	3786	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3787	tlb_miss = display->fifo_sizedisplay->cacheline_size - hdisplay 8;	3787	tlb_miss = display->fifo_sizedisplay->cacheline_size - hdisplay 8;
3788	if (tlb_miss > 0)	3788	if (tlb_miss > 0)
3789	entries += tlb_miss;	3789	entries += tlb_miss;
3790	entries = DIV_ROUND_UP(entries, display->cacheline_size);	3790	entries = DIV_ROUND_UP(entries, display->cacheline_size);
3791	*plane_wm = entries + display->guard_size;	3791	*plane_wm = entries + display->guard_size;
3792	if (*plane_wm > (int)display->max_wm)	3792	if (*plane_wm > (int)display->max_wm)
3793	*plane_wm = display->max_wm;	3793	*plane_wm = display->max_wm;
3794		3794
3795	/* Use the large buffer method to calculate cursor watermark */	3795	/* Use the large buffer method to calculate cursor watermark */
3796	line_time_us = ((htotal * 1000) / clock);	3796	line_time_us = ((htotal * 1000) / clock);
3797	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;	3797	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3798	entries = line_count * 64 * pixel_size;	3798	entries = line_count * 64 * pixel_size;
3799	tlb_miss = cursor->fifo_sizecursor->cacheline_size - hdisplay 8;	3799	tlb_miss = cursor->fifo_sizecursor->cacheline_size - hdisplay 8;
3800	if (tlb_miss > 0)	3800	if (tlb_miss > 0)
3801	entries += tlb_miss;	3801	entries += tlb_miss;
3802	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);	3802	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3803	*cursor_wm = entries + cursor->guard_size;	3803	*cursor_wm = entries + cursor->guard_size;
3804	if (*cursor_wm > (int)cursor->max_wm)	3804	if (*cursor_wm > (int)cursor->max_wm)
3805	*cursor_wm = (int)cursor->max_wm;	3805	*cursor_wm = (int)cursor->max_wm;
3806		3806
3807	return true;	3807	return true;
3808	}	3808	}
3809		3809
3810	/*	3810	/*
3811	* Check the wm result.	3811	* Check the wm result.
3812	*	3812	*
3813	* If any calculated watermark values is larger than the maximum value that	3813	* If any calculated watermark values is larger than the maximum value that
3814	* can be programmed into the associated watermark register, that watermark	3814	* can be programmed into the associated watermark register, that watermark
3815	* must be disabled.	3815	* must be disabled.
3816	*/	3816	*/
3817	static bool g4x_check_srwm(struct drm_device *dev,	3817	static bool g4x_check_srwm(struct drm_device *dev,
3818	int display_wm, int cursor_wm,	3818	int display_wm, int cursor_wm,
3819	const struct intel_watermark_params *display,	3819	const struct intel_watermark_params *display,
3820	const struct intel_watermark_params *cursor)	3820	const struct intel_watermark_params *cursor)
3821	{	3821	{
3822	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",	3822	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3823	display_wm, cursor_wm);	3823	display_wm, cursor_wm);
3824		3824
3825	if (display_wm > display->max_wm) {	3825	if (display_wm > display->max_wm) {
3826	DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",	3826	DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3827	display_wm, display->max_wm);	3827	display_wm, display->max_wm);
3828	return false;	3828	return false;
3829	}	3829	}
3830		3830
3831	if (cursor_wm > cursor->max_wm) {	3831	if (cursor_wm > cursor->max_wm) {
3832	DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",	3832	DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3833	cursor_wm, cursor->max_wm);	3833	cursor_wm, cursor->max_wm);
3834	return false;	3834	return false;
3835	}	3835	}
3836		3836
3837	if (!(display_wm \|\| cursor_wm)) {	3837	if (!(display_wm \|\| cursor_wm)) {
3838	DRM_DEBUG_KMS("SR latency is 0, disabling\n");	3838	DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3839	return false;	3839	return false;
3840	}	3840	}
3841		3841
3842	return true;	3842	return true;
3843	}	3843	}
3844		3844
3845	static bool g4x_compute_srwm(struct drm_device *dev,	3845	static bool g4x_compute_srwm(struct drm_device *dev,
3846	int plane,	3846	int plane,
3847	int latency_ns,	3847	int latency_ns,
3848	const struct intel_watermark_params *display,	3848	const struct intel_watermark_params *display,
3849	const struct intel_watermark_params *cursor,	3849	const struct intel_watermark_params *cursor,
3850	int display_wm, int cursor_wm)	3850	int display_wm, int cursor_wm)
3851	{	3851	{
3852	struct drm_crtc *crtc;	3852	struct drm_crtc *crtc;
3853	int hdisplay, htotal, pixel_size, clock;	3853	int hdisplay, htotal, pixel_size, clock;
3854	unsigned long line_time_us;	3854	unsigned long line_time_us;
3855	int line_count, line_size;	3855	int line_count, line_size;
3856	int small, large;	3856	int small, large;
3857	int entries;	3857	int entries;
3858		3858
3859	if (!latency_ns) {	3859	if (!latency_ns) {
3860	display_wm = cursor_wm = 0;	3860	display_wm = cursor_wm = 0;
3861	return false;	3861	return false;
3862	}	3862	}
3863		3863
3864	crtc = intel_get_crtc_for_plane(dev, plane);	3864	crtc = intel_get_crtc_for_plane(dev, plane);
3865	hdisplay = crtc->mode.hdisplay;	3865	hdisplay = crtc->mode.hdisplay;
3866	htotal = crtc->mode.htotal;	3866	htotal = crtc->mode.htotal;
3867	clock = crtc->mode.clock;	3867	clock = crtc->mode.clock;
3868	pixel_size = crtc->fb->bits_per_pixel / 8;	3868	pixel_size = crtc->fb->bits_per_pixel / 8;
3869		3869
3870	line_time_us = (htotal * 1000) / clock;	3870	line_time_us = (htotal * 1000) / clock;
3871	line_count = (latency_ns / line_time_us + 1000) / 1000;	3871	line_count = (latency_ns / line_time_us + 1000) / 1000;
3872	line_size = hdisplay * pixel_size;	3872	line_size = hdisplay * pixel_size;
3873		3873
3874	/* Use the minimum of the small and large buffer method for primary */	3874	/* Use the minimum of the small and large buffer method for primary */
3875	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;	3875	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3876	large = line_count * line_size;	3876	large = line_count * line_size;
3877		3877
3878	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);	3878	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3879	*display_wm = entries + display->guard_size;	3879	*display_wm = entries + display->guard_size;
3880		3880
3881	/* calculate the self-refresh watermark for display cursor */	3881	/* calculate the self-refresh watermark for display cursor */
3882	entries = line_count * pixel_size * 64;	3882	entries = line_count * pixel_size * 64;
3883	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);	3883	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3884	*cursor_wm = entries + cursor->guard_size;	3884	*cursor_wm = entries + cursor->guard_size;
3885		3885
3886	return g4x_check_srwm(dev,	3886	return g4x_check_srwm(dev,
3887	display_wm, cursor_wm,	3887	display_wm, cursor_wm,
3888	display, cursor);	3888	display, cursor);
3889	}	3889	}
3890		3890
3891	#define single_plane_enabled(mask) is_power_of_2(mask)	3891	#define single_plane_enabled(mask) is_power_of_2(mask)
3892		3892
3893	static void g4x_update_wm(struct drm_device *dev)	3893	static void g4x_update_wm(struct drm_device *dev)
3894	{	3894	{
3895	static const int sr_latency_ns = 12000;	3895	static const int sr_latency_ns = 12000;
3896	struct drm_i915_private *dev_priv = dev->dev_private;	3896	struct drm_i915_private *dev_priv = dev->dev_private;
3897	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;	3897	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3898	int plane_sr, cursor_sr;	3898	int plane_sr, cursor_sr;
3899	unsigned int enabled = 0;	3899	unsigned int enabled = 0;
3900		3900
3901	if (g4x_compute_wm0(dev, 0,	3901	if (g4x_compute_wm0(dev, 0,
3902	&g4x_wm_info, latency_ns,	3902	&g4x_wm_info, latency_ns,
3903	&g4x_cursor_wm_info, latency_ns,	3903	&g4x_cursor_wm_info, latency_ns,
3904	&planea_wm, &cursora_wm))	3904	&planea_wm, &cursora_wm))
3905	enabled \|= 1;	3905	enabled \|= 1;
3906		3906
3907	if (g4x_compute_wm0(dev, 1,	3907	if (g4x_compute_wm0(dev, 1,
3908	&g4x_wm_info, latency_ns,	3908	&g4x_wm_info, latency_ns,
3909	&g4x_cursor_wm_info, latency_ns,	3909	&g4x_cursor_wm_info, latency_ns,
3910	&planeb_wm, &cursorb_wm))	3910	&planeb_wm, &cursorb_wm))
3911	enabled \|= 2;	3911	enabled \|= 2;
3912		3912
3913	plane_sr = cursor_sr = 0;	3913	plane_sr = cursor_sr = 0;
3914	if (single_plane_enabled(enabled) &&	3914	if (single_plane_enabled(enabled) &&
3915	g4x_compute_srwm(dev, ffs(enabled) - 1,	3915	g4x_compute_srwm(dev, ffs(enabled) - 1,
3916	sr_latency_ns,	3916	sr_latency_ns,
3917	&g4x_wm_info,	3917	&g4x_wm_info,
3918	&g4x_cursor_wm_info,	3918	&g4x_cursor_wm_info,
3919	&plane_sr, &cursor_sr))	3919	&plane_sr, &cursor_sr))
3920	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);	3920	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3921	else	3921	else
3922	I915_WRITE(FW_BLC_SELF,	3922	I915_WRITE(FW_BLC_SELF,
3923	I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);	3923	I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3924		3924
3925	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",	3925	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3926	planea_wm, cursora_wm,	3926	planea_wm, cursora_wm,
3927	planeb_wm, cursorb_wm,	3927	planeb_wm, cursorb_wm,
3928	plane_sr, cursor_sr);	3928	plane_sr, cursor_sr);
3929		3929
3930	I915_WRITE(DSPFW1,	3930	I915_WRITE(DSPFW1,
3931	(plane_sr << DSPFW_SR_SHIFT) \|	3931	(plane_sr << DSPFW_SR_SHIFT) \|
3932	(cursorb_wm << DSPFW_CURSORB_SHIFT) \|	3932	(cursorb_wm << DSPFW_CURSORB_SHIFT) \|
3933	(planeb_wm << DSPFW_PLANEB_SHIFT) \|	3933	(planeb_wm << DSPFW_PLANEB_SHIFT) \|
3934	planea_wm);	3934	planea_wm);
3935	I915_WRITE(DSPFW2,	3935	I915_WRITE(DSPFW2,
3936	(I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) \|	3936	(I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) \|
3937	(cursora_wm << DSPFW_CURSORA_SHIFT));	3937	(cursora_wm << DSPFW_CURSORA_SHIFT));
3938	/* HPLL off in SR has some issues on G4x... disable it */	3938	/* HPLL off in SR has some issues on G4x... disable it */
3939	I915_WRITE(DSPFW3,	3939	I915_WRITE(DSPFW3,
3940	(I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) \|	3940	(I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) \|
3941	(cursor_sr << DSPFW_CURSOR_SR_SHIFT));	3941	(cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3942	}	3942	}
3943		3943
3944	static void i965_update_wm(struct drm_device *dev)	3944	static void i965_update_wm(struct drm_device *dev)
3945	{	3945	{
3946	struct drm_i915_private *dev_priv = dev->dev_private;	3946	struct drm_i915_private *dev_priv = dev->dev_private;
3947	struct drm_crtc *crtc;	3947	struct drm_crtc *crtc;
3948	int srwm = 1;	3948	int srwm = 1;
3949	int cursor_sr = 16;	3949	int cursor_sr = 16;
3950		3950
3951	/* Calc sr entries for one plane configs */	3951	/* Calc sr entries for one plane configs */
3952	crtc = single_enabled_crtc(dev);	3952	crtc = single_enabled_crtc(dev);
3953	if (crtc) {	3953	if (crtc) {
3954	/* self-refresh has much higher latency */	3954	/* self-refresh has much higher latency */
3955	static const int sr_latency_ns = 12000;	3955	static const int sr_latency_ns = 12000;
3956	int clock = crtc->mode.clock;	3956	int clock = crtc->mode.clock;
3957	int htotal = crtc->mode.htotal;	3957	int htotal = crtc->mode.htotal;
3958	int hdisplay = crtc->mode.hdisplay;	3958	int hdisplay = crtc->mode.hdisplay;
3959	int pixel_size = crtc->fb->bits_per_pixel / 8;	3959	int pixel_size = crtc->fb->bits_per_pixel / 8;
3960	unsigned long line_time_us;	3960	unsigned long line_time_us;
3961	int entries;	3961	int entries;
3962		3962
3963	line_time_us = ((htotal * 1000) / clock);	3963	line_time_us = ((htotal * 1000) / clock);
3964		3964
3965	/* Use ns/us then divide to preserve precision */	3965	/* Use ns/us then divide to preserve precision */
3966	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *	3966	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3967	pixel_size * hdisplay;	3967	pixel_size * hdisplay;
3968	entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);	3968	entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3969	srwm = I965_FIFO_SIZE - entries;	3969	srwm = I965_FIFO_SIZE - entries;
3970	if (srwm < 0)	3970	if (srwm < 0)
3971	srwm = 1;	3971	srwm = 1;
3972	srwm &= 0x1ff;	3972	srwm &= 0x1ff;
3973	DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",	3973	DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3974	entries, srwm);	3974	entries, srwm);
3975		3975
3976	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *	3976	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3977	pixel_size * 64;	3977	pixel_size * 64;
3978	entries = DIV_ROUND_UP(entries,	3978	entries = DIV_ROUND_UP(entries,
3979	i965_cursor_wm_info.cacheline_size);	3979	i965_cursor_wm_info.cacheline_size);
3980	cursor_sr = i965_cursor_wm_info.fifo_size -	3980	cursor_sr = i965_cursor_wm_info.fifo_size -
3981	(entries + i965_cursor_wm_info.guard_size);	3981	(entries + i965_cursor_wm_info.guard_size);
3982		3982
3983	if (cursor_sr > i965_cursor_wm_info.max_wm)	3983	if (cursor_sr > i965_cursor_wm_info.max_wm)
3984	cursor_sr = i965_cursor_wm_info.max_wm;	3984	cursor_sr = i965_cursor_wm_info.max_wm;
3985		3985
3986	DRM_DEBUG_KMS("self-refresh watermark: display plane %d "	3986	DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3987	"cursor %d\n", srwm, cursor_sr);	3987	"cursor %d\n", srwm, cursor_sr);
3988		3988
3989	if (IS_CRESTLINE(dev))	3989	if (IS_CRESTLINE(dev))
3990	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);	3990	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3991	} else {	3991	} else {
3992	/* Turn off self refresh if both pipes are enabled */	3992	/* Turn off self refresh if both pipes are enabled */
3993	if (IS_CRESTLINE(dev))	3993	if (IS_CRESTLINE(dev))
3994	I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)	3994	I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3995	& ~FW_BLC_SELF_EN);	3995	& ~FW_BLC_SELF_EN);
3996	}	3996	}
3997		3997
3998	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",	3998	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3999	srwm);	3999	srwm);
4000		4000
4001	/* 965 has limitations... */	4001	/* 965 has limitations... */
4002	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) \|	4002	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) \|
4003	(8 << 16) \| (8 << 8) \| (8 << 0));	4003	(8 << 16) \| (8 << 8) \| (8 << 0));
4004	I915_WRITE(DSPFW2, (8 << 8) \| (8 << 0));	4004	I915_WRITE(DSPFW2, (8 << 8) \| (8 << 0));
4005	/* update cursor SR watermark */	4005	/* update cursor SR watermark */
4006	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));	4006	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4007	}	4007	}
4008		4008
4009	static void i9xx_update_wm(struct drm_device *dev)	4009	static void i9xx_update_wm(struct drm_device *dev)
4010	{	4010	{
4011	struct drm_i915_private *dev_priv = dev->dev_private;	4011	struct drm_i915_private *dev_priv = dev->dev_private;
4012	const struct intel_watermark_params *wm_info;	4012	const struct intel_watermark_params *wm_info;
4013	uint32_t fwater_lo;	4013	uint32_t fwater_lo;
4014	uint32_t fwater_hi;	4014	uint32_t fwater_hi;
4015	int cwm, srwm = 1;	4015	int cwm, srwm = 1;
4016	int fifo_size;	4016	int fifo_size;
4017	int planea_wm, planeb_wm;	4017	int planea_wm, planeb_wm;
4018	struct drm_crtc crtc, enabled = NULL;	4018	struct drm_crtc crtc, enabled = NULL;
4019		4019
4020	if (IS_I945GM(dev))	4020	if (IS_I945GM(dev))
4021	wm_info = &i945_wm_info;	4021	wm_info = &i945_wm_info;
4022	else if (!IS_GEN2(dev))	4022	else if (!IS_GEN2(dev))
4023	wm_info = &i915_wm_info;	4023	wm_info = &i915_wm_info;
4024	else	4024	else
4025	wm_info = &i855_wm_info;	4025	wm_info = &i855_wm_info;
4026		4026
4027	fifo_size = dev_priv->display.get_fifo_size(dev, 0);	4027	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4028	crtc = intel_get_crtc_for_plane(dev, 0);	4028	crtc = intel_get_crtc_for_plane(dev, 0);
4029	if (crtc->enabled && crtc->fb) {	4029	if (crtc->enabled && crtc->fb) {
4030	planea_wm = intel_calculate_wm(crtc->mode.clock,	4030	planea_wm = intel_calculate_wm(crtc->mode.clock,
4031	wm_info, fifo_size,	4031	wm_info, fifo_size,
4032	crtc->fb->bits_per_pixel / 8,	4032	crtc->fb->bits_per_pixel / 8,
4033	latency_ns);	4033	latency_ns);
4034	enabled = crtc;	4034	enabled = crtc;
4035	} else	4035	} else
4036	planea_wm = fifo_size - wm_info->guard_size;	4036	planea_wm = fifo_size - wm_info->guard_size;
4037		4037
4038	fifo_size = dev_priv->display.get_fifo_size(dev, 1);	4038	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4039	crtc = intel_get_crtc_for_plane(dev, 1);	4039	crtc = intel_get_crtc_for_plane(dev, 1);
4040	if (crtc->enabled && crtc->fb) {	4040	if (crtc->enabled && crtc->fb) {
4041	planeb_wm = intel_calculate_wm(crtc->mode.clock,	4041	planeb_wm = intel_calculate_wm(crtc->mode.clock,
4042	wm_info, fifo_size,	4042	wm_info, fifo_size,
4043	crtc->fb->bits_per_pixel / 8,	4043	crtc->fb->bits_per_pixel / 8,
4044	latency_ns);	4044	latency_ns);
4045	if (enabled == NULL)	4045	if (enabled == NULL)
4046	enabled = crtc;	4046	enabled = crtc;
4047	else	4047	else
4048	enabled = NULL;	4048	enabled = NULL;
4049	} else	4049	} else
4050	planeb_wm = fifo_size - wm_info->guard_size;	4050	planeb_wm = fifo_size - wm_info->guard_size;
4051		4051
4052	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);	4052	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4053		4053
4054	/*	4054	/*
4055	* Overlay gets an aggressive default since video jitter is bad.	4055	* Overlay gets an aggressive default since video jitter is bad.
4056	*/	4056	*/
4057	cwm = 2;	4057	cwm = 2;
4058		4058
4059	/* Play safe and disable self-refresh before adjusting watermarks. */	4059	/* Play safe and disable self-refresh before adjusting watermarks. */
4060	if (IS_I945G(dev) \|\| IS_I945GM(dev))	4060	if (IS_I945G(dev) \|\| IS_I945GM(dev))
4061	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK \| 0);	4061	I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK \| 0);
4062	else if (IS_I915GM(dev))	4062	else if (IS_I915GM(dev))
4063	I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);	4063	I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4064		4064
4065	/* Calc sr entries for one plane configs */	4065	/* Calc sr entries for one plane configs */
4066	if (HAS_FW_BLC(dev) && enabled) {	4066	if (HAS_FW_BLC(dev) && enabled) {
4067	/* self-refresh has much higher latency */	4067	/* self-refresh has much higher latency */
4068	static const int sr_latency_ns = 6000;	4068	static const int sr_latency_ns = 6000;
4069	int clock = enabled->mode.clock;	4069	int clock = enabled->mode.clock;
4070	int htotal = enabled->mode.htotal;	4070	int htotal = enabled->mode.htotal;
4071	int hdisplay = enabled->mode.hdisplay;	4071	int hdisplay = enabled->mode.hdisplay;
4072	int pixel_size = enabled->fb->bits_per_pixel / 8;	4072	int pixel_size = enabled->fb->bits_per_pixel / 8;
4073	unsigned long line_time_us;	4073	unsigned long line_time_us;
4074	int entries;	4074	int entries;
4075		4075
4076	line_time_us = (htotal * 1000) / clock;	4076	line_time_us = (htotal * 1000) / clock;
4077		4077
4078	/* Use ns/us then divide to preserve precision */	4078	/* Use ns/us then divide to preserve precision */
4079	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *	4079	entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4080	pixel_size * hdisplay;	4080	pixel_size * hdisplay;
4081	entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);	4081	entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4082	DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);	4082	DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4083	srwm = wm_info->fifo_size - entries;	4083	srwm = wm_info->fifo_size - entries;
4084	if (srwm < 0)	4084	if (srwm < 0)
4085	srwm = 1;	4085	srwm = 1;
4086		4086
4087	if (IS_I945G(dev) \|\| IS_I945GM(dev))	4087	if (IS_I945G(dev) \|\| IS_I945GM(dev))
4088	I915_WRITE(FW_BLC_SELF,	4088	I915_WRITE(FW_BLC_SELF,
4089	FW_BLC_SELF_FIFO_MASK \| (srwm & 0xff));	4089	FW_BLC_SELF_FIFO_MASK \| (srwm & 0xff));
4090	else if (IS_I915GM(dev))	4090	else if (IS_I915GM(dev))
4091	I915_WRITE(FW_BLC_SELF, srwm & 0x3f);	4091	I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4092	}	4092	}
4093		4093
4094	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",	4094	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4095	planea_wm, planeb_wm, cwm, srwm);	4095	planea_wm, planeb_wm, cwm, srwm);
4096		4096
4097	fwater_lo = ((planeb_wm & 0x3f) << 16) \| (planea_wm & 0x3f);	4097	fwater_lo = ((planeb_wm & 0x3f) << 16) \| (planea_wm & 0x3f);
4098	fwater_hi = (cwm & 0x1f);	4098	fwater_hi = (cwm & 0x1f);
4099		4099
4100	/* Set request length to 8 cachelines per fetch */	4100	/* Set request length to 8 cachelines per fetch */
4101	fwater_lo = fwater_lo \| (1 << 24) \| (1 << 8);	4101	fwater_lo = fwater_lo \| (1 << 24) \| (1 << 8);
4102	fwater_hi = fwater_hi \| (1 << 8);	4102	fwater_hi = fwater_hi \| (1 << 8);
4103		4103
4104	I915_WRITE(FW_BLC, fwater_lo);	4104	I915_WRITE(FW_BLC, fwater_lo);
4105	I915_WRITE(FW_BLC2, fwater_hi);	4105	I915_WRITE(FW_BLC2, fwater_hi);
4106		4106
4107	if (HAS_FW_BLC(dev)) {	4107	if (HAS_FW_BLC(dev)) {
4108	if (enabled) {	4108	if (enabled) {
4109	if (IS_I945G(dev) \|\| IS_I945GM(dev))	4109	if (IS_I945G(dev) \|\| IS_I945GM(dev))
4110	I915_WRITE(FW_BLC_SELF,	4110	I915_WRITE(FW_BLC_SELF,
4111	FW_BLC_SELF_EN_MASK \| FW_BLC_SELF_EN);	4111	FW_BLC_SELF_EN_MASK \| FW_BLC_SELF_EN);
4112	else if (IS_I915GM(dev))	4112	else if (IS_I915GM(dev))
4113	I915_WRITE(INSTPM, I915_READ(INSTPM) \| INSTPM_SELF_EN);	4113	I915_WRITE(INSTPM, I915_READ(INSTPM) \| INSTPM_SELF_EN);
4114	DRM_DEBUG_KMS("memory self refresh enabled\n");	4114	DRM_DEBUG_KMS("memory self refresh enabled\n");
4115	} else	4115	} else
4116	DRM_DEBUG_KMS("memory self refresh disabled\n");	4116	DRM_DEBUG_KMS("memory self refresh disabled\n");
4117	}	4117	}
4118	}	4118	}
4119		4119
4120	static void i830_update_wm(struct drm_device *dev)	4120	static void i830_update_wm(struct drm_device *dev)
4121	{	4121	{
4122	struct drm_i915_private *dev_priv = dev->dev_private;	4122	struct drm_i915_private *dev_priv = dev->dev_private;
4123	struct drm_crtc *crtc;	4123	struct drm_crtc *crtc;
4124	uint32_t fwater_lo;	4124	uint32_t fwater_lo;
4125	int planea_wm;	4125	int planea_wm;
4126		4126
4127	crtc = single_enabled_crtc(dev);	4127	crtc = single_enabled_crtc(dev);
4128	if (crtc == NULL)	4128	if (crtc == NULL)
4129	return;	4129	return;
4130		4130
4131	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,	4131	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4132	dev_priv->display.get_fifo_size(dev, 0),	4132	dev_priv->display.get_fifo_size(dev, 0),
4133	crtc->fb->bits_per_pixel / 8,	4133	crtc->fb->bits_per_pixel / 8,
4134	latency_ns);	4134	latency_ns);
4135	fwater_lo = I915_READ(FW_BLC) & ~0xfff;	4135	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4136	fwater_lo \|= (3<<8) \| planea_wm;	4136	fwater_lo \|= (3<<8) \| planea_wm;
4137		4137
4138	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);	4138	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4139		4139
4140	I915_WRITE(FW_BLC, fwater_lo);	4140	I915_WRITE(FW_BLC, fwater_lo);
4141	}	4141	}
4142		4142
4143	#define ILK_LP0_PLANE_LATENCY 700	4143	#define ILK_LP0_PLANE_LATENCY 700
4144	#define ILK_LP0_CURSOR_LATENCY 1300	4144	#define ILK_LP0_CURSOR_LATENCY 1300
4145		4145
4146	static bool ironlake_compute_wm0(struct drm_device *dev,	4146	static bool ironlake_compute_wm0(struct drm_device *dev,
4147	int pipe,	4147	int pipe,
4148	const struct intel_watermark_params *display,	4148	const struct intel_watermark_params *display,
4149	int display_latency_ns,	4149	int display_latency_ns,
4150	const struct intel_watermark_params *cursor,	4150	const struct intel_watermark_params *cursor,
4151	int cursor_latency_ns,	4151	int cursor_latency_ns,
4152	int *plane_wm,	4152	int *plane_wm,
4153	int *cursor_wm)	4153	int *cursor_wm)
4154	{	4154	{
4155	struct drm_crtc *crtc;	4155	struct drm_crtc *crtc;
4156	int htotal, hdisplay, clock, pixel_size;	4156	int htotal, hdisplay, clock, pixel_size;
4157	int line_time_us, line_count;	4157	int line_time_us, line_count;
4158	int entries, tlb_miss;	4158	int entries, tlb_miss;
4159		4159
4160	crtc = intel_get_crtc_for_pipe(dev, pipe);	4160	crtc = intel_get_crtc_for_pipe(dev, pipe);
4161	if (crtc->fb == NULL \|\| !crtc->enabled)	4161	if (crtc->fb == NULL \|\| !crtc->enabled)
4162	return false;	4162	return false;
4163		4163
4164	htotal = crtc->mode.htotal;	4164	htotal = crtc->mode.htotal;
4165	hdisplay = crtc->mode.hdisplay;	4165	hdisplay = crtc->mode.hdisplay;
4166	clock = crtc->mode.clock;	4166	clock = crtc->mode.clock;
4167	pixel_size = crtc->fb->bits_per_pixel / 8;	4167	pixel_size = crtc->fb->bits_per_pixel / 8;
4168		4168
4169	/* Use the small buffer method to calculate plane watermark */	4169	/* Use the small buffer method to calculate plane watermark */
4170	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;	4170	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4171	tlb_miss = display->fifo_sizedisplay->cacheline_size - hdisplay 8;	4171	tlb_miss = display->fifo_sizedisplay->cacheline_size - hdisplay 8;
4172	if (tlb_miss > 0)	4172	if (tlb_miss > 0)
4173	entries += tlb_miss;	4173	entries += tlb_miss;
4174	entries = DIV_ROUND_UP(entries, display->cacheline_size);	4174	entries = DIV_ROUND_UP(entries, display->cacheline_size);
4175	*plane_wm = entries + display->guard_size;	4175	*plane_wm = entries + display->guard_size;
4176	if (*plane_wm > (int)display->max_wm)	4176	if (*plane_wm > (int)display->max_wm)
4177	*plane_wm = display->max_wm;	4177	*plane_wm = display->max_wm;
4178		4178
4179	/* Use the large buffer method to calculate cursor watermark */	4179	/* Use the large buffer method to calculate cursor watermark */
4180	line_time_us = ((htotal * 1000) / clock);	4180	line_time_us = ((htotal * 1000) / clock);
4181	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;	4181	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4182	entries = line_count * 64 * pixel_size;	4182	entries = line_count * 64 * pixel_size;
4183	tlb_miss = cursor->fifo_sizecursor->cacheline_size - hdisplay 8;	4183	tlb_miss = cursor->fifo_sizecursor->cacheline_size - hdisplay 8;
4184	if (tlb_miss > 0)	4184	if (tlb_miss > 0)
4185	entries += tlb_miss;	4185	entries += tlb_miss;
4186	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);	4186	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4187	*cursor_wm = entries + cursor->guard_size;	4187	*cursor_wm = entries + cursor->guard_size;
4188	if (*cursor_wm > (int)cursor->max_wm)	4188	if (*cursor_wm > (int)cursor->max_wm)
4189	*cursor_wm = (int)cursor->max_wm;	4189	*cursor_wm = (int)cursor->max_wm;
4190		4190
4191	return true;	4191	return true;
4192	}	4192	}
4193		4193
4194	/*	4194	/*
4195	* Check the wm result.	4195	* Check the wm result.
4196	*	4196	*
4197	* If any calculated watermark values is larger than the maximum value that	4197	* If any calculated watermark values is larger than the maximum value that
4198	* can be programmed into the associated watermark register, that watermark	4198	* can be programmed into the associated watermark register, that watermark
4199	* must be disabled.	4199	* must be disabled.
4200	*/	4200	*/
4201	static bool ironlake_check_srwm(struct drm_device *dev, int level,	4201	static bool ironlake_check_srwm(struct drm_device *dev, int level,
4202	int fbc_wm, int display_wm, int cursor_wm,	4202	int fbc_wm, int display_wm, int cursor_wm,
4203	const struct intel_watermark_params *display,	4203	const struct intel_watermark_params *display,
4204	const struct intel_watermark_params *cursor)	4204	const struct intel_watermark_params *cursor)
4205	{	4205	{
4206	struct drm_i915_private *dev_priv = dev->dev_private;	4206	struct drm_i915_private *dev_priv = dev->dev_private;
4207		4207
4208	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"	4208	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4209	" cursor %d\n", level, display_wm, fbc_wm, cursor_wm);	4209	" cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4210		4210
4211	if (fbc_wm > SNB_FBC_MAX_SRWM) {	4211	if (fbc_wm > SNB_FBC_MAX_SRWM) {
4212	DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",	4212	DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4213	fbc_wm, SNB_FBC_MAX_SRWM, level);	4213	fbc_wm, SNB_FBC_MAX_SRWM, level);
4214		4214
4215	/* fbc has it's own way to disable FBC WM */	4215	/* fbc has it's own way to disable FBC WM */
4216	I915_WRITE(DISP_ARB_CTL,	4216	I915_WRITE(DISP_ARB_CTL,
4217	I915_READ(DISP_ARB_CTL) \| DISP_FBC_WM_DIS);	4217	I915_READ(DISP_ARB_CTL) \| DISP_FBC_WM_DIS);
4218	return false;	4218	return false;
4219	}	4219	}
4220		4220
4221	if (display_wm > display->max_wm) {	4221	if (display_wm > display->max_wm) {
4222	DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",	4222	DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4223	display_wm, SNB_DISPLAY_MAX_SRWM, level);	4223	display_wm, SNB_DISPLAY_MAX_SRWM, level);
4224	return false;	4224	return false;
4225	}	4225	}
4226		4226
4227	if (cursor_wm > cursor->max_wm) {	4227	if (cursor_wm > cursor->max_wm) {
4228	DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",	4228	DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4229	cursor_wm, SNB_CURSOR_MAX_SRWM, level);	4229	cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4230	return false;	4230	return false;
4231	}	4231	}
4232		4232
4233	if (!(fbc_wm \|\| display_wm \|\| cursor_wm)) {	4233	if (!(fbc_wm \|\| display_wm \|\| cursor_wm)) {
4234	DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);	4234	DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4235	return false;	4235	return false;
4236	}	4236	}
4237		4237
4238	return true;	4238	return true;
4239	}	4239	}
4240		4240
4241	/*	4241	/*
4242	* Compute watermark values of WM[1-3],	4242	* Compute watermark values of WM[1-3],
4243	*/	4243	*/
4244	static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,	4244	static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4245	int latency_ns,	4245	int latency_ns,
4246	const struct intel_watermark_params *display,	4246	const struct intel_watermark_params *display,
4247	const struct intel_watermark_params *cursor,	4247	const struct intel_watermark_params *cursor,
4248	int fbc_wm, int display_wm, int *cursor_wm)	4248	int fbc_wm, int display_wm, int *cursor_wm)
4249	{	4249	{
4250	struct drm_crtc *crtc;	4250	struct drm_crtc *crtc;
4251	unsigned long line_time_us;	4251	unsigned long line_time_us;
4252	int hdisplay, htotal, pixel_size, clock;	4252	int hdisplay, htotal, pixel_size, clock;
4253	int line_count, line_size;	4253	int line_count, line_size;
4254	int small, large;	4254	int small, large;
4255	int entries;	4255	int entries;
4256		4256
4257	if (!latency_ns) {	4257	if (!latency_ns) {
4258	fbc_wm = display_wm = *cursor_wm = 0;	4258	fbc_wm = display_wm = *cursor_wm = 0;
4259	return false;	4259	return false;
4260	}	4260	}
4261		4261
4262	crtc = intel_get_crtc_for_plane(dev, plane);	4262	crtc = intel_get_crtc_for_plane(dev, plane);
4263	hdisplay = crtc->mode.hdisplay;	4263	hdisplay = crtc->mode.hdisplay;
4264	htotal = crtc->mode.htotal;	4264	htotal = crtc->mode.htotal;
4265	clock = crtc->mode.clock;	4265	clock = crtc->mode.clock;
4266	pixel_size = crtc->fb->bits_per_pixel / 8;	4266	pixel_size = crtc->fb->bits_per_pixel / 8;
4267		4267
4268	line_time_us = (htotal * 1000) / clock;	4268	line_time_us = (htotal * 1000) / clock;
4269	line_count = (latency_ns / line_time_us + 1000) / 1000;	4269	line_count = (latency_ns / line_time_us + 1000) / 1000;
4270	line_size = hdisplay * pixel_size;	4270	line_size = hdisplay * pixel_size;
4271		4271
4272	/* Use the minimum of the small and large buffer method for primary */	4272	/* Use the minimum of the small and large buffer method for primary */
4273	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;	4273	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4274	large = line_count * line_size;	4274	large = line_count * line_size;
4275		4275
4276	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);	4276	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4277	*display_wm = entries + display->guard_size;	4277	*display_wm = entries + display->guard_size;
4278		4278
4279	/*	4279	/*
4280	* Spec says:	4280	* Spec says:
4281	* FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2	4281	* FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4282	*/	4282	*/
4283	fbc_wm = DIV_ROUND_UP(display_wm * 64, line_size) + 2;	4283	fbc_wm = DIV_ROUND_UP(display_wm * 64, line_size) + 2;
4284		4284
4285	/* calculate the self-refresh watermark for display cursor */	4285	/* calculate the self-refresh watermark for display cursor */
4286	entries = line_count * pixel_size * 64;	4286	entries = line_count * pixel_size * 64;
4287	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);	4287	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4288	*cursor_wm = entries + cursor->guard_size;	4288	*cursor_wm = entries + cursor->guard_size;
4289		4289
4290	return ironlake_check_srwm(dev, level,	4290	return ironlake_check_srwm(dev, level,
4291	fbc_wm, display_wm, *cursor_wm,	4291	fbc_wm, display_wm, *cursor_wm,
4292	display, cursor);	4292	display, cursor);
4293	}	4293	}
4294		4294
4295	static void ironlake_update_wm(struct drm_device *dev)	4295	static void ironlake_update_wm(struct drm_device *dev)
4296	{	4296	{
4297	struct drm_i915_private *dev_priv = dev->dev_private;	4297	struct drm_i915_private *dev_priv = dev->dev_private;
4298	int fbc_wm, plane_wm, cursor_wm;	4298	int fbc_wm, plane_wm, cursor_wm;
4299	unsigned int enabled;	4299	unsigned int enabled;
4300		4300
4301	enabled = 0;	4301	enabled = 0;
4302	if (ironlake_compute_wm0(dev, 0,	4302	if (ironlake_compute_wm0(dev, 0,
4303	&ironlake_display_wm_info,	4303	&ironlake_display_wm_info,
4304	ILK_LP0_PLANE_LATENCY,	4304	ILK_LP0_PLANE_LATENCY,
4305	&ironlake_cursor_wm_info,	4305	&ironlake_cursor_wm_info,
4306	ILK_LP0_CURSOR_LATENCY,	4306	ILK_LP0_CURSOR_LATENCY,
4307	&plane_wm, &cursor_wm)) {	4307	&plane_wm, &cursor_wm)) {
4308	I915_WRITE(WM0_PIPEA_ILK,	4308	I915_WRITE(WM0_PIPEA_ILK,
4309	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);	4309	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
4310	DRM_DEBUG_KMS("FIFO watermarks For pipe A -"	4310	DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4311	" plane %d, " "cursor: %d\n",	4311	" plane %d, " "cursor: %d\n",
4312	plane_wm, cursor_wm);	4312	plane_wm, cursor_wm);
4313	enabled \|= 1;	4313	enabled \|= 1;
4314	}	4314	}
4315		4315
4316	if (ironlake_compute_wm0(dev, 1,	4316	if (ironlake_compute_wm0(dev, 1,
4317	&ironlake_display_wm_info,	4317	&ironlake_display_wm_info,
4318	ILK_LP0_PLANE_LATENCY,	4318	ILK_LP0_PLANE_LATENCY,
4319	&ironlake_cursor_wm_info,	4319	&ironlake_cursor_wm_info,
4320	ILK_LP0_CURSOR_LATENCY,	4320	ILK_LP0_CURSOR_LATENCY,
4321	&plane_wm, &cursor_wm)) {	4321	&plane_wm, &cursor_wm)) {
4322	I915_WRITE(WM0_PIPEB_ILK,	4322	I915_WRITE(WM0_PIPEB_ILK,
4323	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);	4323	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
4324	DRM_DEBUG_KMS("FIFO watermarks For pipe B -"	4324	DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4325	" plane %d, cursor: %d\n",	4325	" plane %d, cursor: %d\n",
4326	plane_wm, cursor_wm);	4326	plane_wm, cursor_wm);
4327	enabled \|= 2;	4327	enabled \|= 2;
4328	}	4328	}
4329		4329
4330	/*	4330	/*
4331	* Calculate and update the self-refresh watermark only when one	4331	* Calculate and update the self-refresh watermark only when one
4332	* display plane is used.	4332	* display plane is used.
4333	*/	4333	*/
4334	I915_WRITE(WM3_LP_ILK, 0);	4334	I915_WRITE(WM3_LP_ILK, 0);
4335	I915_WRITE(WM2_LP_ILK, 0);	4335	I915_WRITE(WM2_LP_ILK, 0);
4336	I915_WRITE(WM1_LP_ILK, 0);	4336	I915_WRITE(WM1_LP_ILK, 0);
4337		4337
4338	if (!single_plane_enabled(enabled))	4338	if (!single_plane_enabled(enabled))
4339	return;	4339	return;
4340	enabled = ffs(enabled) - 1;	4340	enabled = ffs(enabled) - 1;
4341		4341
4342	/* WM1 */	4342	/* WM1 */
4343	if (!ironlake_compute_srwm(dev, 1, enabled,	4343	if (!ironlake_compute_srwm(dev, 1, enabled,
4344	ILK_READ_WM1_LATENCY() * 500,	4344	ILK_READ_WM1_LATENCY() * 500,
4345	&ironlake_display_srwm_info,	4345	&ironlake_display_srwm_info,
4346	&ironlake_cursor_srwm_info,	4346	&ironlake_cursor_srwm_info,
4347	&fbc_wm, &plane_wm, &cursor_wm))	4347	&fbc_wm, &plane_wm, &cursor_wm))
4348	return;	4348	return;
4349		4349
4350	I915_WRITE(WM1_LP_ILK,	4350	I915_WRITE(WM1_LP_ILK,
4351	WM1_LP_SR_EN \|	4351	WM1_LP_SR_EN \|
4352	(ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) \|	4352	(ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
4353	(fbc_wm << WM1_LP_FBC_SHIFT) \|	4353	(fbc_wm << WM1_LP_FBC_SHIFT) \|
4354	(plane_wm << WM1_LP_SR_SHIFT) \|	4354	(plane_wm << WM1_LP_SR_SHIFT) \|
4355	cursor_wm);	4355	cursor_wm);
4356		4356
4357	/* WM2 */	4357	/* WM2 */
4358	if (!ironlake_compute_srwm(dev, 2, enabled,	4358	if (!ironlake_compute_srwm(dev, 2, enabled,
4359	ILK_READ_WM2_LATENCY() * 500,	4359	ILK_READ_WM2_LATENCY() * 500,
4360	&ironlake_display_srwm_info,	4360	&ironlake_display_srwm_info,
4361	&ironlake_cursor_srwm_info,	4361	&ironlake_cursor_srwm_info,
4362	&fbc_wm, &plane_wm, &cursor_wm))	4362	&fbc_wm, &plane_wm, &cursor_wm))
4363	return;	4363	return;
4364		4364
4365	I915_WRITE(WM2_LP_ILK,	4365	I915_WRITE(WM2_LP_ILK,
4366	WM2_LP_EN \|	4366	WM2_LP_EN \|
4367	(ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) \|	4367	(ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
4368	(fbc_wm << WM1_LP_FBC_SHIFT) \|	4368	(fbc_wm << WM1_LP_FBC_SHIFT) \|
4369	(plane_wm << WM1_LP_SR_SHIFT) \|	4369	(plane_wm << WM1_LP_SR_SHIFT) \|
4370	cursor_wm);	4370	cursor_wm);
4371		4371
4372	/*	4372	/*
4373	* WM3 is unsupported on ILK, probably because we don't have latency	4373	* WM3 is unsupported on ILK, probably because we don't have latency
4374	* data for that power state	4374	* data for that power state
4375	*/	4375	*/
4376	}	4376	}
4377		4377
4378	static void sandybridge_update_wm(struct drm_device *dev)	4378	static void sandybridge_update_wm(struct drm_device *dev)
4379	{	4379	{
4380	struct drm_i915_private *dev_priv = dev->dev_private;	4380	struct drm_i915_private *dev_priv = dev->dev_private;
4381	int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */	4381	int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4382	int fbc_wm, plane_wm, cursor_wm;	4382	int fbc_wm, plane_wm, cursor_wm;
4383	unsigned int enabled;	4383	unsigned int enabled;
4384		4384
4385	enabled = 0;	4385	enabled = 0;
4386	if (ironlake_compute_wm0(dev, 0,	4386	if (ironlake_compute_wm0(dev, 0,
4387	&sandybridge_display_wm_info, latency,	4387	&sandybridge_display_wm_info, latency,
4388	&sandybridge_cursor_wm_info, latency,	4388	&sandybridge_cursor_wm_info, latency,
4389	&plane_wm, &cursor_wm)) {	4389	&plane_wm, &cursor_wm)) {
4390	I915_WRITE(WM0_PIPEA_ILK,	4390	I915_WRITE(WM0_PIPEA_ILK,
4391	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);	4391	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
4392	DRM_DEBUG_KMS("FIFO watermarks For pipe A -"	4392	DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4393	" plane %d, " "cursor: %d\n",	4393	" plane %d, " "cursor: %d\n",
4394	plane_wm, cursor_wm);	4394	plane_wm, cursor_wm);
4395	enabled \|= 1;	4395	enabled \|= 1;
4396	}	4396	}
4397		4397
4398	if (ironlake_compute_wm0(dev, 1,	4398	if (ironlake_compute_wm0(dev, 1,
4399	&sandybridge_display_wm_info, latency,	4399	&sandybridge_display_wm_info, latency,
4400	&sandybridge_cursor_wm_info, latency,	4400	&sandybridge_cursor_wm_info, latency,
4401	&plane_wm, &cursor_wm)) {	4401	&plane_wm, &cursor_wm)) {
4402	I915_WRITE(WM0_PIPEB_ILK,	4402	I915_WRITE(WM0_PIPEB_ILK,
4403	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);	4403	(plane_wm << WM0_PIPE_PLANE_SHIFT) \| cursor_wm);
4404	DRM_DEBUG_KMS("FIFO watermarks For pipe B -"	4404	DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4405	" plane %d, cursor: %d\n",	4405	" plane %d, cursor: %d\n",
4406	plane_wm, cursor_wm);	4406	plane_wm, cursor_wm);
4407	enabled \|= 2;	4407	enabled \|= 2;
4408	}	4408	}
4409		4409
4410	/*	4410	/*
4411	* Calculate and update the self-refresh watermark only when one	4411	* Calculate and update the self-refresh watermark only when one
4412	* display plane is used.	4412	* display plane is used.
4413	*	4413	*
4414	* SNB support 3 levels of watermark.	4414	* SNB support 3 levels of watermark.
4415	*	4415	*
4416	* WM1/WM2/WM2 watermarks have to be enabled in the ascending order,	4416	* WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4417	* and disabled in the descending order	4417	* and disabled in the descending order
4418	*	4418	*
4419	*/	4419	*/
4420	I915_WRITE(WM3_LP_ILK, 0);	4420	I915_WRITE(WM3_LP_ILK, 0);
4421	I915_WRITE(WM2_LP_ILK, 0);	4421	I915_WRITE(WM2_LP_ILK, 0);
4422	I915_WRITE(WM1_LP_ILK, 0);	4422	I915_WRITE(WM1_LP_ILK, 0);
4423		4423
4424	if (!single_plane_enabled(enabled))	4424	if (!single_plane_enabled(enabled))
4425	return;	4425	return;
4426	enabled = ffs(enabled) - 1;	4426	enabled = ffs(enabled) - 1;
4427		4427
4428	/* WM1 */	4428	/* WM1 */
4429	if (!ironlake_compute_srwm(dev, 1, enabled,	4429	if (!ironlake_compute_srwm(dev, 1, enabled,
4430	SNB_READ_WM1_LATENCY() * 500,	4430	SNB_READ_WM1_LATENCY() * 500,
4431	&sandybridge_display_srwm_info,	4431	&sandybridge_display_srwm_info,
4432	&sandybridge_cursor_srwm_info,	4432	&sandybridge_cursor_srwm_info,
4433	&fbc_wm, &plane_wm, &cursor_wm))	4433	&fbc_wm, &plane_wm, &cursor_wm))
4434	return;	4434	return;
4435		4435
4436	I915_WRITE(WM1_LP_ILK,	4436	I915_WRITE(WM1_LP_ILK,
4437	WM1_LP_SR_EN \|	4437	WM1_LP_SR_EN \|
4438	(SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) \|	4438	(SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
4439	(fbc_wm << WM1_LP_FBC_SHIFT) \|	4439	(fbc_wm << WM1_LP_FBC_SHIFT) \|
4440	(plane_wm << WM1_LP_SR_SHIFT) \|	4440	(plane_wm << WM1_LP_SR_SHIFT) \|
4441	cursor_wm);	4441	cursor_wm);
4442		4442
4443	/* WM2 */	4443	/* WM2 */
4444	if (!ironlake_compute_srwm(dev, 2, enabled,	4444	if (!ironlake_compute_srwm(dev, 2, enabled,
4445	SNB_READ_WM2_LATENCY() * 500,	4445	SNB_READ_WM2_LATENCY() * 500,
4446	&sandybridge_display_srwm_info,	4446	&sandybridge_display_srwm_info,
4447	&sandybridge_cursor_srwm_info,	4447	&sandybridge_cursor_srwm_info,
4448	&fbc_wm, &plane_wm, &cursor_wm))	4448	&fbc_wm, &plane_wm, &cursor_wm))
4449	return;	4449	return;
4450		4450
4451	I915_WRITE(WM2_LP_ILK,	4451	I915_WRITE(WM2_LP_ILK,
4452	WM2_LP_EN \|	4452	WM2_LP_EN \|
4453	(SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) \|	4453	(SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
4454	(fbc_wm << WM1_LP_FBC_SHIFT) \|	4454	(fbc_wm << WM1_LP_FBC_SHIFT) \|
4455	(plane_wm << WM1_LP_SR_SHIFT) \|	4455	(plane_wm << WM1_LP_SR_SHIFT) \|
4456	cursor_wm);	4456	cursor_wm);
4457		4457
4458	/* WM3 */	4458	/* WM3 */
4459	if (!ironlake_compute_srwm(dev, 3, enabled,	4459	if (!ironlake_compute_srwm(dev, 3, enabled,
4460	SNB_READ_WM3_LATENCY() * 500,	4460	SNB_READ_WM3_LATENCY() * 500,
4461	&sandybridge_display_srwm_info,	4461	&sandybridge_display_srwm_info,
4462	&sandybridge_cursor_srwm_info,	4462	&sandybridge_cursor_srwm_info,
4463	&fbc_wm, &plane_wm, &cursor_wm))	4463	&fbc_wm, &plane_wm, &cursor_wm))
4464	return;	4464	return;
4465		4465
4466	I915_WRITE(WM3_LP_ILK,	4466	I915_WRITE(WM3_LP_ILK,
4467	WM3_LP_EN \|	4467	WM3_LP_EN \|
4468	(SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) \|	4468	(SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) \|
4469	(fbc_wm << WM1_LP_FBC_SHIFT) \|	4469	(fbc_wm << WM1_LP_FBC_SHIFT) \|
4470	(plane_wm << WM1_LP_SR_SHIFT) \|	4470	(plane_wm << WM1_LP_SR_SHIFT) \|
4471	cursor_wm);	4471	cursor_wm);
4472	}	4472	}
4473		4473
4474	/**	4474	/**
4475	* intel_update_watermarks - update FIFO watermark values based on current modes	4475	* intel_update_watermarks - update FIFO watermark values based on current modes
4476	*	4476	*
4477	* Calculate watermark values for the various WM regs based on current mode	4477	* Calculate watermark values for the various WM regs based on current mode
4478	* and plane configuration.	4478	* and plane configuration.
4479	*	4479	*
4480	* There are several cases to deal with here:	4480	* There are several cases to deal with here:
4481	* - normal (i.e. non-self-refresh)	4481	* - normal (i.e. non-self-refresh)
4482	* - self-refresh (SR) mode	4482	* - self-refresh (SR) mode
4483	* - lines are large relative to FIFO size (buffer can hold up to 2)	4483	* - lines are large relative to FIFO size (buffer can hold up to 2)
4484	* - lines are small relative to FIFO size (buffer can hold more than 2	4484	* - lines are small relative to FIFO size (buffer can hold more than 2
4485	* lines), so need to account for TLB latency	4485	* lines), so need to account for TLB latency
4486	*	4486	*
4487	* The normal calculation is:	4487	* The normal calculation is:
4488	* watermark = dotclock * bytes per pixel * latency	4488	* watermark = dotclock * bytes per pixel * latency
4489	* where latency is platform & configuration dependent (we assume pessimal	4489	* where latency is platform & configuration dependent (we assume pessimal
4490	* values here).	4490	* values here).
4491	*	4491	*
4492	* The SR calculation is:	4492	* The SR calculation is:
4493	* watermark = (trunc(latency/line time)+1) * surface width *	4493	* watermark = (trunc(latency/line time)+1) * surface width *
4494	* bytes per pixel	4494	* bytes per pixel
4495	* where	4495	* where
4496	* line time = htotal / dotclock	4496	* line time = htotal / dotclock
4497	* surface width = hdisplay for normal plane and 64 for cursor	4497	* surface width = hdisplay for normal plane and 64 for cursor
4498	* and latency is assumed to be high, as above.	4498	* and latency is assumed to be high, as above.
4499	*	4499	*
4500	* The final value programmed to the register should always be rounded up,	4500	* The final value programmed to the register should always be rounded up,
4501	* and include an extra 2 entries to account for clock crossings.	4501	* and include an extra 2 entries to account for clock crossings.
4502	*	4502	*
4503	* We don't use the sprite, so we can ignore that. And on Crestline we have	4503	* We don't use the sprite, so we can ignore that. And on Crestline we have
4504	* to set the non-SR watermarks to 8.	4504	* to set the non-SR watermarks to 8.
4505	*/	4505	*/
4506	static void intel_update_watermarks(struct drm_device *dev)	4506	static void intel_update_watermarks(struct drm_device *dev)
4507	{	4507	{
4508	struct drm_i915_private *dev_priv = dev->dev_private;	4508	struct drm_i915_private *dev_priv = dev->dev_private;
4509		4509
4510	if (dev_priv->display.update_wm)	4510	if (dev_priv->display.update_wm)
4511	dev_priv->display.update_wm(dev);	4511	dev_priv->display.update_wm(dev);
4512	}	4512	}
4513		4513
4514	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)	4514	static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4515	{	4515	{
4516	return dev_priv->lvds_use_ssc && i915_panel_use_ssc;	4516	return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4517	}	4517	}
4518		4518
4519	static int intel_crtc_mode_set(struct drm_crtc *crtc,	4519	static int intel_crtc_mode_set(struct drm_crtc *crtc,
4520	struct drm_display_mode *mode,	4520	struct drm_display_mode *mode,
4521	struct drm_display_mode *adjusted_mode,	4521	struct drm_display_mode *adjusted_mode,
4522	int x, int y,	4522	int x, int y,
4523	struct drm_framebuffer *old_fb)	4523	struct drm_framebuffer *old_fb)
4524	{	4524	{
4525	struct drm_device *dev = crtc->dev;	4525	struct drm_device *dev = crtc->dev;
4526	struct drm_i915_private *dev_priv = dev->dev_private;	4526	struct drm_i915_private *dev_priv = dev->dev_private;
4527	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	4527	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4528	int pipe = intel_crtc->pipe;	4528	int pipe = intel_crtc->pipe;
4529	int plane = intel_crtc->plane;	4529	int plane = intel_crtc->plane;
4530	u32 fp_reg, dpll_reg;	4530	u32 fp_reg, dpll_reg;
4531	int refclk, num_connectors = 0;	4531	int refclk, num_connectors = 0;
4532	intel_clock_t clock, reduced_clock;	4532	intel_clock_t clock, reduced_clock;
4533	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;	4533	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4534	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;	4534	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4535	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;	4535	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4536	struct intel_encoder *has_edp_encoder = NULL;	4536	struct intel_encoder *has_edp_encoder = NULL;
4537	struct drm_mode_config *mode_config = &dev->mode_config;	4537	struct drm_mode_config *mode_config = &dev->mode_config;
4538	struct intel_encoder *encoder;	4538	struct intel_encoder *encoder;
4539	const intel_limit_t *limit;	4539	const intel_limit_t *limit;
4540	int ret;	4540	int ret;
4541	struct fdi_m_n m_n = {0};	4541	struct fdi_m_n m_n = {0};
4542	u32 reg, temp;	4542	u32 reg, temp;
4543	u32 lvds_sync = 0;	4543	u32 lvds_sync = 0;
4544	int target_clock;	4544	int target_clock;
4545		4545
4546	drm_vblank_pre_modeset(dev, pipe);	4546	drm_vblank_pre_modeset(dev, pipe);
4547		4547
4548	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {	4548	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4549	if (encoder->base.crtc != crtc)	4549	if (encoder->base.crtc != crtc)
4550	continue;	4550	continue;
4551		4551
4552	switch (encoder->type) {	4552	switch (encoder->type) {
4553	case INTEL_OUTPUT_LVDS:	4553	case INTEL_OUTPUT_LVDS:
4554	is_lvds = true;	4554	is_lvds = true;
4555	break;	4555	break;
4556	case INTEL_OUTPUT_SDVO:	4556	case INTEL_OUTPUT_SDVO:
4557	case INTEL_OUTPUT_HDMI:	4557	case INTEL_OUTPUT_HDMI:
4558	is_sdvo = true;	4558	is_sdvo = true;
4559	if (encoder->needs_tv_clock)	4559	if (encoder->needs_tv_clock)
4560	is_tv = true;	4560	is_tv = true;
4561	break;	4561	break;
4562	case INTEL_OUTPUT_DVO:	4562	case INTEL_OUTPUT_DVO:
4563	is_dvo = true;	4563	is_dvo = true;
4564	break;	4564	break;
4565	case INTEL_OUTPUT_TVOUT:	4565	case INTEL_OUTPUT_TVOUT:
4566	is_tv = true;	4566	is_tv = true;
4567	break;	4567	break;
4568	case INTEL_OUTPUT_ANALOG:	4568	case INTEL_OUTPUT_ANALOG:
4569	is_crt = true;	4569	is_crt = true;
4570	break;	4570	break;
4571	case INTEL_OUTPUT_DISPLAYPORT:	4571	case INTEL_OUTPUT_DISPLAYPORT:
4572	is_dp = true;	4572	is_dp = true;
4573	break;	4573	break;
4574	case INTEL_OUTPUT_EDP:	4574	case INTEL_OUTPUT_EDP:
4575	has_edp_encoder = encoder;	4575	has_edp_encoder = encoder;
4576	break;	4576	break;
4577	}	4577	}
4578		4578
4579	num_connectors++;	4579	num_connectors++;
4580	}	4580	}
4581		4581
4582	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {	4582	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4583	refclk = dev_priv->lvds_ssc_freq * 1000;	4583	refclk = dev_priv->lvds_ssc_freq * 1000;
4584	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",	4584	DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4585	refclk / 1000);	4585	refclk / 1000);
4586	} else if (!IS_GEN2(dev)) {	4586	} else if (!IS_GEN2(dev)) {
4587	refclk = 96000;	4587	refclk = 96000;
4588	if (HAS_PCH_SPLIT(dev) &&	4588	if (HAS_PCH_SPLIT(dev) &&
4589	(!has_edp_encoder \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)))	4589	(!has_edp_encoder \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4590	refclk = 120000; /* 120Mhz refclk */	4590	refclk = 120000; /* 120Mhz refclk */
4591	} else {	4591	} else {
4592	refclk = 48000;	4592	refclk = 48000;
4593	}	4593	}
4594		4594
4595	/*	4595	/*
4596	* Returns a set of divisors for the desired target clock with the given	4596	* Returns a set of divisors for the desired target clock with the given
4597	* refclk, or FALSE. The returned values represent the clock equation:	4597	* refclk, or FALSE. The returned values represent the clock equation:
4598	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.	4598	* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4599	*/	4599	*/
4600	limit = intel_limit(crtc, refclk);	4600	limit = intel_limit(crtc, refclk);
4601	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);	4601	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4602	if (!ok) {	4602	if (!ok) {
4603	DRM_ERROR("Couldn't find PLL settings for mode!\n");	4603	DRM_ERROR("Couldn't find PLL settings for mode!\n");
4604	drm_vblank_post_modeset(dev, pipe);	4604	drm_vblank_post_modeset(dev, pipe);
4605	return -EINVAL;	4605	return -EINVAL;
4606	}	4606	}
4607		4607
4608	/* Ensure that the cursor is valid for the new mode before changing... */	4608	/* Ensure that the cursor is valid for the new mode before changing... */
4609	intel_crtc_update_cursor(crtc, true);	4609	intel_crtc_update_cursor(crtc, true);
4610		4610
4611	if (is_lvds && dev_priv->lvds_downclock_avail) {	4611	if (is_lvds && dev_priv->lvds_downclock_avail) {
4612	has_reduced_clock = limit->find_pll(limit, crtc,	4612	has_reduced_clock = limit->find_pll(limit, crtc,
4613	dev_priv->lvds_downclock,	4613	dev_priv->lvds_downclock,
4614	refclk,	4614	refclk,
4615	&reduced_clock);	4615	&reduced_clock);
4616	if (has_reduced_clock && (clock.p != reduced_clock.p)) {	4616	if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4617	/*	4617	/*
4618	* If the different P is found, it means that we can't	4618	* If the different P is found, it means that we can't
4619	* switch the display clock by using the FP0/FP1.	4619	* switch the display clock by using the FP0/FP1.
4620	* In such case we will disable the LVDS downclock	4620	* In such case we will disable the LVDS downclock
4621	* feature.	4621	* feature.
4622	*/	4622	*/
4623	DRM_DEBUG_KMS("Different P is found for "	4623	DRM_DEBUG_KMS("Different P is found for "
4624	"LVDS clock/downclock\n");	4624	"LVDS clock/downclock\n");
4625	has_reduced_clock = 0;	4625	has_reduced_clock = 0;
4626	}	4626	}
4627	}	4627	}
4628	/* SDVO TV has fixed PLL values depend on its clock range,	4628	/* SDVO TV has fixed PLL values depend on its clock range,
4629	this mirrors vbios setting. */	4629	this mirrors vbios setting. */
4630	if (is_sdvo && is_tv) {	4630	if (is_sdvo && is_tv) {
4631	if (adjusted_mode->clock >= 100000	4631	if (adjusted_mode->clock >= 100000
4632	&& adjusted_mode->clock < 140500) {	4632	&& adjusted_mode->clock < 140500) {
4633	clock.p1 = 2;	4633	clock.p1 = 2;
4634	clock.p2 = 10;	4634	clock.p2 = 10;
4635	clock.n = 3;	4635	clock.n = 3;
4636	clock.m1 = 16;	4636	clock.m1 = 16;
4637	clock.m2 = 8;	4637	clock.m2 = 8;
4638	} else if (adjusted_mode->clock >= 140500	4638	} else if (adjusted_mode->clock >= 140500
4639	&& adjusted_mode->clock <= 200000) {	4639	&& adjusted_mode->clock <= 200000) {
4640	clock.p1 = 1;	4640	clock.p1 = 1;
4641	clock.p2 = 10;	4641	clock.p2 = 10;
4642	clock.n = 6;	4642	clock.n = 6;
4643	clock.m1 = 12;	4643	clock.m1 = 12;
4644	clock.m2 = 8;	4644	clock.m2 = 8;
4645	}	4645	}
4646	}	4646	}
4647		4647
4648	/* FDI link */	4648	/* FDI link */
4649	if (HAS_PCH_SPLIT(dev)) {	4649	if (HAS_PCH_SPLIT(dev)) {
4650	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);	4650	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4651	int lane = 0, link_bw, bpp;	4651	int lane = 0, link_bw, bpp;
4652	/* CPU eDP doesn't require FDI link, so just set DP M/N	4652	/* CPU eDP doesn't require FDI link, so just set DP M/N
4653	according to current link config */	4653	according to current link config */
4654	if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {	4654	if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4655	target_clock = mode->clock;	4655	target_clock = mode->clock;
4656	intel_edp_link_config(has_edp_encoder,	4656	intel_edp_link_config(has_edp_encoder,
4657	&lane, &link_bw);	4657	&lane, &link_bw);
4658	} else {	4658	} else {
4659	/* [e]DP over FDI requires target mode clock	4659	/* [e]DP over FDI requires target mode clock
4660	instead of link clock */	4660	instead of link clock */
4661	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base))	4661	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base))
4662	target_clock = mode->clock;	4662	target_clock = mode->clock;
4663	else	4663	else
4664	target_clock = adjusted_mode->clock;	4664	target_clock = adjusted_mode->clock;
4665		4665
4666	/* FDI is a binary signal running at ~2.7GHz, encoding	4666	/* FDI is a binary signal running at ~2.7GHz, encoding
4667	* each output octet as 10 bits. The actual frequency	4667	* each output octet as 10 bits. The actual frequency
4668	* is stored as a divider into a 100MHz clock, and the	4668	* is stored as a divider into a 100MHz clock, and the
4669	* mode pixel clock is stored in units of 1KHz.	4669	* mode pixel clock is stored in units of 1KHz.
4670	* Hence the bw of each lane in terms of the mode signal	4670	* Hence the bw of each lane in terms of the mode signal
4671	* is:	4671	* is:
4672	*/	4672	*/
4673	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;	4673	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4674	}	4674	}
4675		4675
4676	/* determine panel color depth */	4676	/* determine panel color depth */
4677	temp = I915_READ(PIPECONF(pipe));	4677	temp = I915_READ(PIPECONF(pipe));
4678	temp &= ~PIPE_BPC_MASK;	4678	temp &= ~PIPE_BPC_MASK;
4679	if (is_lvds) {	4679	if (is_lvds) {
4680	/* the BPC will be 6 if it is 18-bit LVDS panel */	4680	/* the BPC will be 6 if it is 18-bit LVDS panel */
4681	if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)	4681	if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4682	temp \|= PIPE_8BPC;	4682	temp \|= PIPE_8BPC;
4683	else	4683	else
4684	temp \|= PIPE_6BPC;	4684	temp \|= PIPE_6BPC;
4685	} else if (has_edp_encoder) {	4685	} else if (has_edp_encoder) {
4686	switch (dev_priv->edp.bpp/3) {	4686	switch (dev_priv->edp.bpp/3) {
4687	case 8:	4687	case 8:
4688	temp \|= PIPE_8BPC;	4688	temp \|= PIPE_8BPC;
4689	break;	4689	break;
4690	case 10:	4690	case 10:
4691	temp \|= PIPE_10BPC;	4691	temp \|= PIPE_10BPC;
4692	break;	4692	break;
4693	case 6:	4693	case 6:
4694	temp \|= PIPE_6BPC;	4694	temp \|= PIPE_6BPC;
4695	break;	4695	break;
4696	case 12:	4696	case 12:
4697	temp \|= PIPE_12BPC;	4697	temp \|= PIPE_12BPC;
4698	break;	4698	break;
4699	}	4699	}
4700	} else	4700	} else
4701	temp \|= PIPE_8BPC;	4701	temp \|= PIPE_8BPC;
4702	I915_WRITE(PIPECONF(pipe), temp);	4702	I915_WRITE(PIPECONF(pipe), temp);
4703		4703
4704	switch (temp & PIPE_BPC_MASK) {	4704	switch (temp & PIPE_BPC_MASK) {
4705	case PIPE_8BPC:	4705	case PIPE_8BPC:
4706	bpp = 24;	4706	bpp = 24;
4707	break;	4707	break;
4708	case PIPE_10BPC:	4708	case PIPE_10BPC:
4709	bpp = 30;	4709	bpp = 30;
4710	break;	4710	break;
4711	case PIPE_6BPC:	4711	case PIPE_6BPC:
4712	bpp = 18;	4712	bpp = 18;
4713	break;	4713	break;
4714	case PIPE_12BPC:	4714	case PIPE_12BPC:
4715	bpp = 36;	4715	bpp = 36;
4716	break;	4716	break;
4717	default:	4717	default:
4718	DRM_ERROR("unknown pipe bpc value\n");	4718	DRM_ERROR("unknown pipe bpc value\n");
4719	bpp = 24;	4719	bpp = 24;
4720	}	4720	}
4721		4721
4722	if (!lane) {	4722	if (!lane) {
4723	/*	4723	/*
4724	* Account for spread spectrum to avoid	4724	* Account for spread spectrum to avoid
4725	* oversubscribing the link. Max center spread	4725	* oversubscribing the link. Max center spread
4726	* is 2.5%; use 5% for safety's sake.	4726	* is 2.5%; use 5% for safety's sake.
4727	*/	4727	*/
4728	u32 bps = target_clock * bpp * 21 / 20;	4728	u32 bps = target_clock * bpp * 21 / 20;
4729	lane = bps / (link_bw * 8) + 1;	4729	lane = bps / (link_bw * 8) + 1;
4730	}	4730	}
4731		4731
4732	intel_crtc->fdi_lanes = lane;	4732	intel_crtc->fdi_lanes = lane;
4733		4733
4734	if (pixel_multiplier > 1)	4734	if (pixel_multiplier > 1)
4735	link_bw *= pixel_multiplier;	4735	link_bw *= pixel_multiplier;
4736	ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);	4736	ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4737	}	4737	}
4738		4738
4739	/* Ironlake: try to setup display ref clock before DPLL	4739	/* Ironlake: try to setup display ref clock before DPLL
4740	* enabling. This is only under driver's control after	4740	* enabling. This is only under driver's control after
4741	* PCH B stepping, previous chipset stepping should be	4741	* PCH B stepping, previous chipset stepping should be
4742	* ignoring this setting.	4742	* ignoring this setting.
4743	*/	4743	*/
4744	if (HAS_PCH_SPLIT(dev)) {	4744	if (HAS_PCH_SPLIT(dev)) {
4745	temp = I915_READ(PCH_DREF_CONTROL);	4745	temp = I915_READ(PCH_DREF_CONTROL);
4746	/* Always enable nonspread source */	4746	/* Always enable nonspread source */
4747	temp &= ~DREF_NONSPREAD_SOURCE_MASK;	4747	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4748	temp \|= DREF_NONSPREAD_SOURCE_ENABLE;	4748	temp \|= DREF_NONSPREAD_SOURCE_ENABLE;
4749	temp &= ~DREF_SSC_SOURCE_MASK;	4749	temp &= ~DREF_SSC_SOURCE_MASK;
4750	temp \|= DREF_SSC_SOURCE_ENABLE;	4750	temp \|= DREF_SSC_SOURCE_ENABLE;
4751	I915_WRITE(PCH_DREF_CONTROL, temp);	4751	I915_WRITE(PCH_DREF_CONTROL, temp);
4752		4752
4753	POSTING_READ(PCH_DREF_CONTROL);	4753	POSTING_READ(PCH_DREF_CONTROL);
4754	udelay(200);	4754	udelay(200);
4755		4755
4756	if (has_edp_encoder) {	4756	if (has_edp_encoder) {
4757	if (intel_panel_use_ssc(dev_priv)) {	4757	if (intel_panel_use_ssc(dev_priv)) {
4758	temp \|= DREF_SSC1_ENABLE;	4758	temp \|= DREF_SSC1_ENABLE;
4759	I915_WRITE(PCH_DREF_CONTROL, temp);	4759	I915_WRITE(PCH_DREF_CONTROL, temp);
4760		4760
4761	POSTING_READ(PCH_DREF_CONTROL);	4761	POSTING_READ(PCH_DREF_CONTROL);
4762	udelay(200);	4762	udelay(200);
4763	}	4763	}
4764	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;	4764	temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4765		4765
4766	/* Enable CPU source on CPU attached eDP */	4766	/* Enable CPU source on CPU attached eDP */
4767	if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {	4767	if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4768	if (intel_panel_use_ssc(dev_priv))	4768	if (intel_panel_use_ssc(dev_priv))
4769	temp \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;	4769	temp \|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4770	else	4770	else
4771	temp \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;	4771	temp \|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4772	} else {	4772	} else {
4773	/* Enable SSC on PCH eDP if needed */	4773	/* Enable SSC on PCH eDP if needed */
4774	if (intel_panel_use_ssc(dev_priv)) {	4774	if (intel_panel_use_ssc(dev_priv)) {
4775	DRM_ERROR("enabling SSC on PCH\n");	4775	DRM_ERROR("enabling SSC on PCH\n");
4776	temp \|= DREF_SUPERSPREAD_SOURCE_ENABLE;	4776	temp \|= DREF_SUPERSPREAD_SOURCE_ENABLE;
4777	}	4777	}
4778	}	4778	}
4779	I915_WRITE(PCH_DREF_CONTROL, temp);	4779	I915_WRITE(PCH_DREF_CONTROL, temp);
4780	POSTING_READ(PCH_DREF_CONTROL);	4780	POSTING_READ(PCH_DREF_CONTROL);
4781	udelay(200);	4781	udelay(200);
4782	}	4782	}
4783	}	4783	}
4784		4784
4785	if (IS_PINEVIEW(dev)) {	4785	if (IS_PINEVIEW(dev)) {
4786	fp = (1 << clock.n) << 16 \| clock.m1 << 8 \| clock.m2;	4786	fp = (1 << clock.n) << 16 \| clock.m1 << 8 \| clock.m2;
4787	if (has_reduced_clock)	4787	if (has_reduced_clock)
4788	fp2 = (1 << reduced_clock.n) << 16 \|	4788	fp2 = (1 << reduced_clock.n) << 16 \|
4789	reduced_clock.m1 << 8 \| reduced_clock.m2;	4789	reduced_clock.m1 << 8 \| reduced_clock.m2;
4790	} else {	4790	} else {
4791	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;	4791	fp = clock.n << 16 \| clock.m1 << 8 \| clock.m2;
4792	if (has_reduced_clock)	4792	if (has_reduced_clock)
4793	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|	4793	fp2 = reduced_clock.n << 16 \| reduced_clock.m1 << 8 \|
4794	reduced_clock.m2;	4794	reduced_clock.m2;
4795	}	4795	}
4796		4796
4797	/* Enable autotuning of the PLL clock (if permissible) */	4797	/* Enable autotuning of the PLL clock (if permissible) */
4798	if (HAS_PCH_SPLIT(dev)) {	4798	if (HAS_PCH_SPLIT(dev)) {
4799	int factor = 21;	4799	int factor = 21;
4800		4800
4801	if (is_lvds) {	4801	if (is_lvds) {
4802	if ((intel_panel_use_ssc(dev_priv) &&	4802	if ((intel_panel_use_ssc(dev_priv) &&
4803	dev_priv->lvds_ssc_freq == 100) \|\|	4803	dev_priv->lvds_ssc_freq == 100) \|\|
4804	(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)	4804	(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4805	factor = 25;	4805	factor = 25;
4806	} else if (is_sdvo && is_tv)	4806	} else if (is_sdvo && is_tv)
4807	factor = 20;	4807	factor = 20;
4808		4808
4809	if (clock.m1 < factor * clock.n)	4809	if (clock.m1 < factor * clock.n)
4810	fp \|= FP_CB_TUNE;	4810	fp \|= FP_CB_TUNE;
4811	}	4811	}
4812		4812
4813	dpll = 0;	4813	dpll = 0;
4814	if (!HAS_PCH_SPLIT(dev))	4814	if (!HAS_PCH_SPLIT(dev))
4815	dpll = DPLL_VGA_MODE_DIS;	4815	dpll = DPLL_VGA_MODE_DIS;
4816		4816
4817	if (!IS_GEN2(dev)) {	4817	if (!IS_GEN2(dev)) {
4818	if (is_lvds)	4818	if (is_lvds)
4819	dpll \|= DPLLB_MODE_LVDS;	4819	dpll \|= DPLLB_MODE_LVDS;
4820	else	4820	else
4821	dpll \|= DPLLB_MODE_DAC_SERIAL;	4821	dpll \|= DPLLB_MODE_DAC_SERIAL;
4822	if (is_sdvo) {	4822	if (is_sdvo) {
4823	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);	4823	int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4824	if (pixel_multiplier > 1) {	4824	if (pixel_multiplier > 1) {
4825	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev))	4825	if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev))
4826	dpll \|= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;	4826	dpll \|= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4827	else if (HAS_PCH_SPLIT(dev))	4827	else if (HAS_PCH_SPLIT(dev))
4828	dpll \|= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;	4828	dpll \|= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4829	}	4829	}
4830	dpll \|= DPLL_DVO_HIGH_SPEED;	4830	dpll \|= DPLL_DVO_HIGH_SPEED;
4831	}	4831	}
4832	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base))	4832	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base))
4833	dpll \|= DPLL_DVO_HIGH_SPEED;	4833	dpll \|= DPLL_DVO_HIGH_SPEED;
4834		4834
4835	/* compute bitmask from p1 value */	4835	/* compute bitmask from p1 value */
4836	if (IS_PINEVIEW(dev))	4836	if (IS_PINEVIEW(dev))
4837	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;	4837	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4838	else {	4838	else {
4839	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;	4839	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4840	/* also FPA1 */	4840	/* also FPA1 */
4841	if (HAS_PCH_SPLIT(dev))	4841	if (HAS_PCH_SPLIT(dev))
4842	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;	4842	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4843	if (IS_G4X(dev) && has_reduced_clock)	4843	if (IS_G4X(dev) && has_reduced_clock)
4844	dpll \|= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;	4844	dpll \|= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4845	}	4845	}
4846	switch (clock.p2) {	4846	switch (clock.p2) {
4847	case 5:	4847	case 5:
4848	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;	4848	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4849	break;	4849	break;
4850	case 7:	4850	case 7:
4851	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;	4851	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_7;
4852	break;	4852	break;
4853	case 10:	4853	case 10:
4854	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;	4854	dpll \|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4855	break;	4855	break;
4856	case 14:	4856	case 14:
4857	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;	4857	dpll \|= DPLLB_LVDS_P2_CLOCK_DIV_14;
4858	break;	4858	break;
4859	}	4859	}
4860	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))	4860	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4861	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);	4861	dpll \|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4862	} else {	4862	} else {
4863	if (is_lvds) {	4863	if (is_lvds) {
4864	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;	4864	dpll \|= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4865	} else {	4865	} else {
4866	if (clock.p1 == 2)	4866	if (clock.p1 == 2)
4867	dpll \|= PLL_P1_DIVIDE_BY_TWO;	4867	dpll \|= PLL_P1_DIVIDE_BY_TWO;
4868	else	4868	else
4869	dpll \|= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;	4869	dpll \|= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4870	if (clock.p2 == 4)	4870	if (clock.p2 == 4)
4871	dpll \|= PLL_P2_DIVIDE_BY_4;	4871	dpll \|= PLL_P2_DIVIDE_BY_4;
4872	}	4872	}
4873	}	4873	}
4874		4874
4875	if (is_sdvo && is_tv)	4875	if (is_sdvo && is_tv)
4876	dpll \|= PLL_REF_INPUT_TVCLKINBC;	4876	dpll \|= PLL_REF_INPUT_TVCLKINBC;
4877	else if (is_tv)	4877	else if (is_tv)
4878	/* XXX: just matching BIOS for now */	4878	/* XXX: just matching BIOS for now */
4879	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */	4879	/* dpll \|= PLL_REF_INPUT_TVCLKINBC; */
4880	dpll \|= 3;	4880	dpll \|= 3;
4881	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)	4881	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4882	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;	4882	dpll \|= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4883	else	4883	else
4884	dpll \|= PLL_REF_INPUT_DREFCLK;	4884	dpll \|= PLL_REF_INPUT_DREFCLK;
4885		4885
4886	/* setup pipeconf */	4886	/* setup pipeconf */
4887	pipeconf = I915_READ(PIPECONF(pipe));	4887	pipeconf = I915_READ(PIPECONF(pipe));
4888		4888
4889	/* Set up the display plane register */	4889	/* Set up the display plane register */
4890	dspcntr = DISPPLANE_GAMMA_ENABLE;	4890	dspcntr = DISPPLANE_GAMMA_ENABLE;
4891		4891
4892	/* Ironlake's plane is forced to pipe, bit 24 is to	4892	/* Ironlake's plane is forced to pipe, bit 24 is to
4893	enable color space conversion */	4893	enable color space conversion */
4894	if (!HAS_PCH_SPLIT(dev)) {	4894	if (!HAS_PCH_SPLIT(dev)) {
4895	if (pipe == 0)	4895	if (pipe == 0)
4896	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;	4896	dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4897	else	4897	else
4898	dspcntr \|= DISPPLANE_SEL_PIPE_B;	4898	dspcntr \|= DISPPLANE_SEL_PIPE_B;
4899	}	4899	}
4900		4900
4901	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {	4901	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4902	/* Enable pixel doubling when the dot clock is > 90% of the (display)	4902	/* Enable pixel doubling when the dot clock is > 90% of the (display)
4903	* core speed.	4903	* core speed.
4904	*	4904	*
4905	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the	4905	* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4906	* pipe == 0 check?	4906	* pipe == 0 check?
4907	*/	4907	*/
4908	if (mode->clock >	4908	if (mode->clock >
4909	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)	4909	dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4910	pipeconf \|= PIPECONF_DOUBLE_WIDE;	4910	pipeconf \|= PIPECONF_DOUBLE_WIDE;
4911	else	4911	else
4912	pipeconf &= ~PIPECONF_DOUBLE_WIDE;	4912	pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4913	}	4913	}
4914		4914
4915	if (!HAS_PCH_SPLIT(dev))	4915	if (!HAS_PCH_SPLIT(dev))
4916	dpll \|= DPLL_VCO_ENABLE;	4916	dpll \|= DPLL_VCO_ENABLE;
4917		4917
4918	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');	4918	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4919	drm_mode_debug_printmodeline(mode);	4919	drm_mode_debug_printmodeline(mode);
4920		4920
4921	/* assign to Ironlake registers */	4921	/* assign to Ironlake registers */
4922	if (HAS_PCH_SPLIT(dev)) {	4922	if (HAS_PCH_SPLIT(dev)) {
4923	fp_reg = PCH_FP0(pipe);	4923	fp_reg = PCH_FP0(pipe);
4924	dpll_reg = PCH_DPLL(pipe);	4924	dpll_reg = PCH_DPLL(pipe);
4925	} else {	4925	} else {
4926	fp_reg = FP0(pipe);	4926	fp_reg = FP0(pipe);
4927	dpll_reg = DPLL(pipe);	4927	dpll_reg = DPLL(pipe);
4928	}	4928	}
4929		4929
4930	/* PCH eDP needs FDI, but CPU eDP does not */	4930	/* PCH eDP needs FDI, but CPU eDP does not */
4931	if (!has_edp_encoder \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {	4931	if (!has_edp_encoder \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4932	I915_WRITE(fp_reg, fp);	4932	I915_WRITE(fp_reg, fp);
4933	I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);	4933	I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4934		4934
4935	POSTING_READ(dpll_reg);	4935	POSTING_READ(dpll_reg);
4936	udelay(150);	4936	udelay(150);
4937	}	4937	}
4938		4938
4939	/* enable transcoder DPLL */	4939	/* enable transcoder DPLL */
4940	if (HAS_PCH_CPT(dev)) {	4940	if (HAS_PCH_CPT(dev)) {
4941	temp = I915_READ(PCH_DPLL_SEL);	4941	temp = I915_READ(PCH_DPLL_SEL);
4942	switch (pipe) {	4942	switch (pipe) {
4943	case 0:	4943	case 0:
4944	temp \|= TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL;	4944	temp \|= TRANSA_DPLL_ENABLE \| TRANSA_DPLLA_SEL;
4945	break;	4945	break;
4946	case 1:	4946	case 1:
4947	temp \|= TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL;	4947	temp \|= TRANSB_DPLL_ENABLE \| TRANSB_DPLLB_SEL;
4948	break;	4948	break;
4949	case 2:	4949	case 2:
4950	/* FIXME: manage transcoder PLLs? */	4950	/* FIXME: manage transcoder PLLs? */
4951	temp \|= TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL;	4951	temp \|= TRANSC_DPLL_ENABLE \| TRANSC_DPLLB_SEL;
4952	break;	4952	break;
4953	default:	4953	default:
4954	BUG();	4954	BUG();
4955	}	4955	}
4956	I915_WRITE(PCH_DPLL_SEL, temp);	4956	I915_WRITE(PCH_DPLL_SEL, temp);
4957		4957
4958	POSTING_READ(PCH_DPLL_SEL);	4958	POSTING_READ(PCH_DPLL_SEL);
4959	udelay(150);	4959	udelay(150);
4960	}	4960	}
4961		4961
4962	/* The LVDS pin pair needs to be on before the DPLLs are enabled.	4962	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
4963	* This is an exception to the general rule that mode_set doesn't turn	4963	* This is an exception to the general rule that mode_set doesn't turn
4964	* things on.	4964	* things on.
4965	*/	4965	*/
4966	if (is_lvds) {	4966	if (is_lvds) {
4967	reg = LVDS;	4967	reg = LVDS;
4968	if (HAS_PCH_SPLIT(dev))	4968	if (HAS_PCH_SPLIT(dev))
4969	reg = PCH_LVDS;	4969	reg = PCH_LVDS;
4970		4970
4971	temp = I915_READ(reg);	4971	temp = I915_READ(reg);
4972	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;	4972	temp \|= LVDS_PORT_EN \| LVDS_A0A2_CLKA_POWER_UP;
4973	if (pipe == 1) {	4973	if (pipe == 1) {
4974	if (HAS_PCH_CPT(dev))	4974	if (HAS_PCH_CPT(dev))
4975	temp \|= PORT_TRANS_B_SEL_CPT;	4975	temp \|= PORT_TRANS_B_SEL_CPT;
4976	else	4976	else
4977	temp \|= LVDS_PIPEB_SELECT;	4977	temp \|= LVDS_PIPEB_SELECT;
4978	} else {	4978	} else {
4979	if (HAS_PCH_CPT(dev))	4979	if (HAS_PCH_CPT(dev))
4980	temp &= ~PORT_TRANS_SEL_MASK;	4980	temp &= ~PORT_TRANS_SEL_MASK;
4981	else	4981	else
4982	temp &= ~LVDS_PIPEB_SELECT;	4982	temp &= ~LVDS_PIPEB_SELECT;
4983	}	4983	}
4984	/* set the corresponsding LVDS_BORDER bit */	4984	/* set the corresponsding LVDS_BORDER bit */
4985	temp \|= dev_priv->lvds_border_bits;	4985	temp \|= dev_priv->lvds_border_bits;
4986	/* Set the B0-B3 data pairs corresponding to whether we're going to	4986	/* Set the B0-B3 data pairs corresponding to whether we're going to
4987	* set the DPLLs for dual-channel mode or not.	4987	* set the DPLLs for dual-channel mode or not.
4988	*/	4988	*/
4989	if (clock.p2 == 7)	4989	if (clock.p2 == 7)
4990	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;	4990	temp \|= LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP;
4991	else	4991	else
4992	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);	4992	temp &= ~(LVDS_B0B3_POWER_UP \| LVDS_CLKB_POWER_UP);
4993		4993
4994	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)	4994	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4995	* appropriately here, but we need to look more thoroughly into how	4995	* appropriately here, but we need to look more thoroughly into how
4996	* panels behave in the two modes.	4996	* panels behave in the two modes.
4997	*/	4997	*/
4998	/* set the dithering flag on non-PCH LVDS as needed */	4998	/* set the dithering flag on non-PCH LVDS as needed */
4999	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {	4999	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
5000	if (dev_priv->lvds_dither)	5000	if (dev_priv->lvds_dither)
5001	temp \|= LVDS_ENABLE_DITHER;	5001	temp \|= LVDS_ENABLE_DITHER;
5002	else	5002	else
5003	temp &= ~LVDS_ENABLE_DITHER;	5003	temp &= ~LVDS_ENABLE_DITHER;
5004	}	5004	}
5005	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)	5005	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5006	lvds_sync \|= LVDS_HSYNC_POLARITY;	5006	lvds_sync \|= LVDS_HSYNC_POLARITY;
5007	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)	5007	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5008	lvds_sync \|= LVDS_VSYNC_POLARITY;	5008	lvds_sync \|= LVDS_VSYNC_POLARITY;
5009	if ((temp & (LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY))	5009	if ((temp & (LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY))
5010	!= lvds_sync) {	5010	!= lvds_sync) {
5011	char flags[2] = "-+";	5011	char flags[2] = "-+";
5012	DRM_INFO("Changing LVDS panel from "	5012	DRM_INFO("Changing LVDS panel from "
5013	"(%chsync, %cvsync) to (%chsync, %cvsync)\n",	5013	"(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5014	flags[!(temp & LVDS_HSYNC_POLARITY)],	5014	flags[!(temp & LVDS_HSYNC_POLARITY)],
5015	flags[!(temp & LVDS_VSYNC_POLARITY)],	5015	flags[!(temp & LVDS_VSYNC_POLARITY)],
5016	flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],	5016	flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5017	flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);	5017	flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5018	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);	5018	temp &= ~(LVDS_HSYNC_POLARITY \| LVDS_VSYNC_POLARITY);
5019	temp \|= lvds_sync;	5019	temp \|= lvds_sync;
5020	}	5020	}
5021	I915_WRITE(reg, temp);	5021	I915_WRITE(reg, temp);
5022	}	5022	}
5023		5023
5024	/* set the dithering flag and clear for anything other than a panel. */	5024	/* set the dithering flag and clear for anything other than a panel. */
5025	if (HAS_PCH_SPLIT(dev)) {	5025	if (HAS_PCH_SPLIT(dev)) {
5026	pipeconf &= ~PIPECONF_DITHER_EN;	5026	pipeconf &= ~PIPECONF_DITHER_EN;
5027	pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;	5027	pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5028	if (dev_priv->lvds_dither && (is_lvds \|\| has_edp_encoder)) {	5028	if (dev_priv->lvds_dither && (is_lvds \|\| has_edp_encoder)) {
5029	pipeconf \|= PIPECONF_DITHER_EN;	5029	pipeconf \|= PIPECONF_DITHER_EN;
5030	pipeconf \|= PIPECONF_DITHER_TYPE_ST1;	5030	pipeconf \|= PIPECONF_DITHER_TYPE_ST1;
5031	}	5031	}
5032	}	5032	}
5033		5033
5034	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {	5034	if (is_dp \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5035	intel_dp_set_m_n(crtc, mode, adjusted_mode);	5035	intel_dp_set_m_n(crtc, mode, adjusted_mode);
5036	} else if (HAS_PCH_SPLIT(dev)) {	5036	} else if (HAS_PCH_SPLIT(dev)) {
5037	/* For non-DP output, clear any trans DP clock recovery setting.*/	5037	/* For non-DP output, clear any trans DP clock recovery setting.*/
5038	I915_WRITE(TRANSDATA_M1(pipe), 0);	5038	I915_WRITE(TRANSDATA_M1(pipe), 0);
5039	I915_WRITE(TRANSDATA_N1(pipe), 0);	5039	I915_WRITE(TRANSDATA_N1(pipe), 0);
5040	I915_WRITE(TRANSDPLINK_M1(pipe), 0);	5040	I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5041	I915_WRITE(TRANSDPLINK_N1(pipe), 0);	5041	I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5042	}	5042	}
5043		5043
5044	if (!has_edp_encoder \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {	5044	if (!has_edp_encoder \|\| intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5045	I915_WRITE(dpll_reg, dpll);	5045	I915_WRITE(dpll_reg, dpll);
5046		5046
5047	/* Wait for the clocks to stabilize. */	5047	/* Wait for the clocks to stabilize. */
5048	POSTING_READ(dpll_reg);	5048	POSTING_READ(dpll_reg);
5049	udelay(150);	5049	udelay(150);
5050		5050
5051	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {	5051	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
5052	temp = 0;	5052	temp = 0;
5053	if (is_sdvo) {	5053	if (is_sdvo) {
5054	temp = intel_mode_get_pixel_multiplier(adjusted_mode);	5054	temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5055	if (temp > 1)	5055	if (temp > 1)
5056	temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;	5056	temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5057	else	5057	else
5058	temp = 0;	5058	temp = 0;
5059	}	5059	}
5060	I915_WRITE(DPLL_MD(pipe), temp);	5060	I915_WRITE(DPLL_MD(pipe), temp);
5061	} else {	5061	} else {
5062	/* The pixel multiplier can only be updated once the	5062	/* The pixel multiplier can only be updated once the
5063	* DPLL is enabled and the clocks are stable.	5063	* DPLL is enabled and the clocks are stable.
5064	*	5064	*
5065	* So write it again.	5065	* So write it again.
5066	*/	5066	*/
5067	I915_WRITE(dpll_reg, dpll);	5067	I915_WRITE(dpll_reg, dpll);
5068	}	5068	}
5069	}	5069	}
5070		5070
5071	intel_crtc->lowfreq_avail = false;	5071	intel_crtc->lowfreq_avail = false;
5072	if (is_lvds && has_reduced_clock && i915_powersave) {	5072	if (is_lvds && has_reduced_clock && i915_powersave) {
5073	I915_WRITE(fp_reg + 4, fp2);	5073	I915_WRITE(fp_reg + 4, fp2);
5074	intel_crtc->lowfreq_avail = true;	5074	intel_crtc->lowfreq_avail = true;
5075	if (HAS_PIPE_CXSR(dev)) {	5075	if (HAS_PIPE_CXSR(dev)) {
5076	DRM_DEBUG_KMS("enabling CxSR downclocking\n");	5076	DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5077	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;	5077	pipeconf \|= PIPECONF_CXSR_DOWNCLOCK;
5078	}	5078	}
5079	} else {	5079	} else {
5080	I915_WRITE(fp_reg + 4, fp);	5080	I915_WRITE(fp_reg + 4, fp);
5081	if (HAS_PIPE_CXSR(dev)) {	5081	if (HAS_PIPE_CXSR(dev)) {
5082	DRM_DEBUG_KMS("disabling CxSR downclocking\n");	5082	DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5083	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;	5083	pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5084	}	5084	}
5085	}	5085	}
5086		5086
5087	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {	5087	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5088	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;	5088	pipeconf \|= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5089	/* the chip adds 2 halflines automatically */	5089	/* the chip adds 2 halflines automatically */
5090	adjusted_mode->crtc_vdisplay -= 1;	5090	adjusted_mode->crtc_vdisplay -= 1;
5091	adjusted_mode->crtc_vtotal -= 1;	5091	adjusted_mode->crtc_vtotal -= 1;
5092	adjusted_mode->crtc_vblank_start -= 1;	5092	adjusted_mode->crtc_vblank_start -= 1;
5093	adjusted_mode->crtc_vblank_end -= 1;	5093	adjusted_mode->crtc_vblank_end -= 1;
5094	adjusted_mode->crtc_vsync_end -= 1;	5094	adjusted_mode->crtc_vsync_end -= 1;
5095	adjusted_mode->crtc_vsync_start -= 1;	5095	adjusted_mode->crtc_vsync_start -= 1;
5096	} else	5096	} else
5097	pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */	5097	pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5098		5098
5099	I915_WRITE(HTOTAL(pipe),	5099	I915_WRITE(HTOTAL(pipe),
5100	(adjusted_mode->crtc_hdisplay - 1) \|	5100	(adjusted_mode->crtc_hdisplay - 1) \|
5101	((adjusted_mode->crtc_htotal - 1) << 16));	5101	((adjusted_mode->crtc_htotal - 1) << 16));
5102	I915_WRITE(HBLANK(pipe),	5102	I915_WRITE(HBLANK(pipe),
5103	(adjusted_mode->crtc_hblank_start - 1) \|	5103	(adjusted_mode->crtc_hblank_start - 1) \|
5104	((adjusted_mode->crtc_hblank_end - 1) << 16));	5104	((adjusted_mode->crtc_hblank_end - 1) << 16));
5105	I915_WRITE(HSYNC(pipe),	5105	I915_WRITE(HSYNC(pipe),
5106	(adjusted_mode->crtc_hsync_start - 1) \|	5106	(adjusted_mode->crtc_hsync_start - 1) \|
5107	((adjusted_mode->crtc_hsync_end - 1) << 16));	5107	((adjusted_mode->crtc_hsync_end - 1) << 16));
5108		5108
5109	I915_WRITE(VTOTAL(pipe),	5109	I915_WRITE(VTOTAL(pipe),
5110	(adjusted_mode->crtc_vdisplay - 1) \|	5110	(adjusted_mode->crtc_vdisplay - 1) \|
5111	((adjusted_mode->crtc_vtotal - 1) << 16));	5111	((adjusted_mode->crtc_vtotal - 1) << 16));
5112	I915_WRITE(VBLANK(pipe),	5112	I915_WRITE(VBLANK(pipe),
5113	(adjusted_mode->crtc_vblank_start - 1) \|	5113	(adjusted_mode->crtc_vblank_start - 1) \|
5114	((adjusted_mode->crtc_vblank_end - 1) << 16));	5114	((adjusted_mode->crtc_vblank_end - 1) << 16));
5115	I915_WRITE(VSYNC(pipe),	5115	I915_WRITE(VSYNC(pipe),
5116	(adjusted_mode->crtc_vsync_start - 1) \|	5116	(adjusted_mode->crtc_vsync_start - 1) \|
5117	((adjusted_mode->crtc_vsync_end - 1) << 16));	5117	((adjusted_mode->crtc_vsync_end - 1) << 16));
5118		5118
5119	/* pipesrc and dspsize control the size that is scaled from,	5119	/* pipesrc and dspsize control the size that is scaled from,
5120	* which should always be the user's requested size.	5120	* which should always be the user's requested size.
5121	*/	5121	*/
5122	if (!HAS_PCH_SPLIT(dev)) {	5122	if (!HAS_PCH_SPLIT(dev)) {
5123	I915_WRITE(DSPSIZE(plane),	5123	I915_WRITE(DSPSIZE(plane),
5124	((mode->vdisplay - 1) << 16) \|	5124	((mode->vdisplay - 1) << 16) \|
5125	(mode->hdisplay - 1));	5125	(mode->hdisplay - 1));
5126	I915_WRITE(DSPPOS(plane), 0);	5126	I915_WRITE(DSPPOS(plane), 0);
5127	}	5127	}
5128	I915_WRITE(PIPESRC(pipe),	5128	I915_WRITE(PIPESRC(pipe),
5129	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));	5129	((mode->hdisplay - 1) << 16) \| (mode->vdisplay - 1));
5130		5130
5131	if (HAS_PCH_SPLIT(dev)) {	5131	if (HAS_PCH_SPLIT(dev)) {
5132	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) \| m_n.gmch_m);	5132	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) \| m_n.gmch_m);
5133	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);	5133	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5134	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);	5134	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5135	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);	5135	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5136		5136
5137	if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {	5137	if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5138	ironlake_set_pll_edp(crtc, adjusted_mode->clock);	5138	ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5139	}	5139	}
5140	}	5140	}
5141		5141
5142	I915_WRITE(PIPECONF(pipe), pipeconf);	5142	I915_WRITE(PIPECONF(pipe), pipeconf);
5143	POSTING_READ(PIPECONF(pipe));	5143	POSTING_READ(PIPECONF(pipe));
5144	if (!HAS_PCH_SPLIT(dev))	5144	if (!HAS_PCH_SPLIT(dev))
5145	intel_enable_pipe(dev_priv, pipe, false);	5145	intel_enable_pipe(dev_priv, pipe, false);
5146		5146
5147	intel_wait_for_vblank(dev, pipe);	5147	intel_wait_for_vblank(dev, pipe);
5148		5148
5149	if (IS_GEN5(dev)) {	5149	if (IS_GEN5(dev)) {
5150	/* enable address swizzle for tiling buffer */	5150	/* enable address swizzle for tiling buffer */
5151	temp = I915_READ(DISP_ARB_CTL);	5151	temp = I915_READ(DISP_ARB_CTL);
5152	I915_WRITE(DISP_ARB_CTL, temp \| DISP_TILE_SURFACE_SWIZZLING);	5152	I915_WRITE(DISP_ARB_CTL, temp \| DISP_TILE_SURFACE_SWIZZLING);
5153	}	5153	}
5154		5154
5155	I915_WRITE(DSPCNTR(plane), dspcntr);	5155	I915_WRITE(DSPCNTR(plane), dspcntr);
5156	POSTING_READ(DSPCNTR(plane));	5156	POSTING_READ(DSPCNTR(plane));
5157	if (!HAS_PCH_SPLIT(dev))	5157	if (!HAS_PCH_SPLIT(dev))
5158	intel_enable_plane(dev_priv, plane, pipe);	5158	intel_enable_plane(dev_priv, plane, pipe);
5159		5159
5160	ret = intel_pipe_set_base(crtc, x, y, old_fb);	5160	ret = intel_pipe_set_base(crtc, x, y, old_fb);
5161		5161
5162	intel_update_watermarks(dev);	5162	intel_update_watermarks(dev);
5163		5163
5164	drm_vblank_post_modeset(dev, pipe);	5164	drm_vblank_post_modeset(dev, pipe);
5165		5165
5166	return ret;	5166	return ret;
5167	}	5167	}
5168		5168
5169	/** Loads the palette/gamma unit for the CRTC with the prepared values */	5169	/** Loads the palette/gamma unit for the CRTC with the prepared values */
5170	void intel_crtc_load_lut(struct drm_crtc *crtc)	5170	void intel_crtc_load_lut(struct drm_crtc *crtc)
5171	{	5171	{
5172	struct drm_device *dev = crtc->dev;	5172	struct drm_device *dev = crtc->dev;
5173	struct drm_i915_private *dev_priv = dev->dev_private;	5173	struct drm_i915_private *dev_priv = dev->dev_private;
5174	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5174	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5175	int palreg = PALETTE(intel_crtc->pipe);	5175	int palreg = PALETTE(intel_crtc->pipe);
5176	int i;	5176	int i;
5177		5177
5178	/* The clocks have to be on to load the palette. */	5178	/* The clocks have to be on to load the palette. */
5179	if (!crtc->enabled)	5179	if (!crtc->enabled)
5180	return;	5180	return;
5181		5181
5182	/* use legacy palette for Ironlake */	5182	/* use legacy palette for Ironlake */
5183	if (HAS_PCH_SPLIT(dev))	5183	if (HAS_PCH_SPLIT(dev))
5184	palreg = LGC_PALETTE(intel_crtc->pipe);	5184	palreg = LGC_PALETTE(intel_crtc->pipe);
5185		5185
5186	for (i = 0; i < 256; i++) {	5186	for (i = 0; i < 256; i++) {
5187	I915_WRITE(palreg + 4 * i,	5187	I915_WRITE(palreg + 4 * i,
5188	(intel_crtc->lut_r[i] << 16) \|	5188	(intel_crtc->lut_r[i] << 16) \|
5189	(intel_crtc->lut_g[i] << 8) \|	5189	(intel_crtc->lut_g[i] << 8) \|
5190	intel_crtc->lut_b[i]);	5190	intel_crtc->lut_b[i]);
5191	}	5191	}
5192	}	5192	}
5193		5193
5194	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)	5194	static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5195	{	5195	{
5196	struct drm_device *dev = crtc->dev;	5196	struct drm_device *dev = crtc->dev;
5197	struct drm_i915_private *dev_priv = dev->dev_private;	5197	struct drm_i915_private *dev_priv = dev->dev_private;
5198	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5198	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5199	bool visible = base != 0;	5199	bool visible = base != 0;
5200	u32 cntl;	5200	u32 cntl;
5201		5201
5202	if (intel_crtc->cursor_visible == visible)	5202	if (intel_crtc->cursor_visible == visible)
5203	return;	5203	return;
5204		5204
5205	cntl = I915_READ(_CURACNTR);	5205	cntl = I915_READ(_CURACNTR);
5206	if (visible) {	5206	if (visible) {
5207	/* On these chipsets we can only modify the base whilst	5207	/* On these chipsets we can only modify the base whilst
5208	* the cursor is disabled.	5208	* the cursor is disabled.
5209	*/	5209	*/
5210	I915_WRITE(_CURABASE, base);	5210	I915_WRITE(_CURABASE, base);
5211		5211
5212	cntl &= ~(CURSOR_FORMAT_MASK);	5212	cntl &= ~(CURSOR_FORMAT_MASK);
5213	/* XXX width must be 64, stride 256 => 0x00 << 28 */	5213	/* XXX width must be 64, stride 256 => 0x00 << 28 */
5214	cntl \|= CURSOR_ENABLE \|	5214	cntl \|= CURSOR_ENABLE \|
5215	CURSOR_GAMMA_ENABLE \|	5215	CURSOR_GAMMA_ENABLE \|
5216	CURSOR_FORMAT_ARGB;	5216	CURSOR_FORMAT_ARGB;
5217	} else	5217	} else
5218	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);	5218	cntl &= ~(CURSOR_ENABLE \| CURSOR_GAMMA_ENABLE);
5219	I915_WRITE(_CURACNTR, cntl);	5219	I915_WRITE(_CURACNTR, cntl);
5220		5220
5221	intel_crtc->cursor_visible = visible;	5221	intel_crtc->cursor_visible = visible;
5222	}	5222	}
5223		5223
5224	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)	5224	static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5225	{	5225	{
5226	struct drm_device *dev = crtc->dev;	5226	struct drm_device *dev = crtc->dev;
5227	struct drm_i915_private *dev_priv = dev->dev_private;	5227	struct drm_i915_private *dev_priv = dev->dev_private;
5228	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5228	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229	int pipe = intel_crtc->pipe;	5229	int pipe = intel_crtc->pipe;
5230	bool visible = base != 0;	5230	bool visible = base != 0;
5231		5231
5232	if (intel_crtc->cursor_visible != visible) {	5232	if (intel_crtc->cursor_visible != visible) {
5233	uint32_t cntl = I915_READ(CURCNTR(pipe));	5233	uint32_t cntl = I915_READ(CURCNTR(pipe));
5234	if (base) {	5234	if (base) {
5235	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);	5235	cntl &= ~(CURSOR_MODE \| MCURSOR_PIPE_SELECT);
5236	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;	5236	cntl \|= CURSOR_MODE_64_ARGB_AX \| MCURSOR_GAMMA_ENABLE;
5237	cntl \|= pipe << 28; /* Connect to correct pipe */	5237	cntl \|= pipe << 28; /* Connect to correct pipe */
5238	} else {	5238	} else {
5239	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);	5239	cntl &= ~(CURSOR_MODE \| MCURSOR_GAMMA_ENABLE);
5240	cntl \|= CURSOR_MODE_DISABLE;	5240	cntl \|= CURSOR_MODE_DISABLE;
5241	}	5241	}
5242	I915_WRITE(CURCNTR(pipe), cntl);	5242	I915_WRITE(CURCNTR(pipe), cntl);
5243		5243
5244	intel_crtc->cursor_visible = visible;	5244	intel_crtc->cursor_visible = visible;
5245	}	5245	}
5246	/* and commit changes on next vblank */	5246	/* and commit changes on next vblank */
5247	I915_WRITE(CURBASE(pipe), base);	5247	I915_WRITE(CURBASE(pipe), base);
5248	}	5248	}
5249		5249
5250	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */	5250	/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5251	static void intel_crtc_update_cursor(struct drm_crtc *crtc,	5251	static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5252	bool on)	5252	bool on)
5253	{	5253	{
5254	struct drm_device *dev = crtc->dev;	5254	struct drm_device *dev = crtc->dev;
5255	struct drm_i915_private *dev_priv = dev->dev_private;	5255	struct drm_i915_private *dev_priv = dev->dev_private;
5256	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5256	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5257	int pipe = intel_crtc->pipe;	5257	int pipe = intel_crtc->pipe;
5258	int x = intel_crtc->cursor_x;	5258	int x = intel_crtc->cursor_x;
5259	int y = intel_crtc->cursor_y;	5259	int y = intel_crtc->cursor_y;
5260	u32 base, pos;	5260	u32 base, pos;
5261	bool visible;	5261	bool visible;
5262		5262
5263	pos = 0;	5263	pos = 0;
5264		5264
5265	if (on && crtc->enabled && crtc->fb) {	5265	if (on && crtc->enabled && crtc->fb) {
5266	base = intel_crtc->cursor_addr;	5266	base = intel_crtc->cursor_addr;
5267	if (x > (int) crtc->fb->width)	5267	if (x > (int) crtc->fb->width)
5268	base = 0;	5268	base = 0;
5269		5269
5270	if (y > (int) crtc->fb->height)	5270	if (y > (int) crtc->fb->height)
5271	base = 0;	5271	base = 0;
5272	} else	5272	} else
5273	base = 0;	5273	base = 0;
5274		5274
5275	if (x < 0) {	5275	if (x < 0) {
5276	if (x + intel_crtc->cursor_width < 0)	5276	if (x + intel_crtc->cursor_width < 0)
5277	base = 0;	5277	base = 0;
5278		5278
5279	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;	5279	pos \|= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5280	x = -x;	5280	x = -x;
5281	}	5281	}
5282	pos \|= x << CURSOR_X_SHIFT;	5282	pos \|= x << CURSOR_X_SHIFT;
5283		5283
5284	if (y < 0) {	5284	if (y < 0) {
5285	if (y + intel_crtc->cursor_height < 0)	5285	if (y + intel_crtc->cursor_height < 0)
5286	base = 0;	5286	base = 0;
5287		5287
5288	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;	5288	pos \|= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5289	y = -y;	5289	y = -y;
5290	}	5290	}
5291	pos \|= y << CURSOR_Y_SHIFT;	5291	pos \|= y << CURSOR_Y_SHIFT;
5292		5292
5293	visible = base != 0;	5293	visible = base != 0;
5294	if (!visible && !intel_crtc->cursor_visible)	5294	if (!visible && !intel_crtc->cursor_visible)
5295	return;	5295	return;
5296		5296
5297	I915_WRITE(CURPOS(pipe), pos);	5297	I915_WRITE(CURPOS(pipe), pos);
5298	if (IS_845G(dev) \|\| IS_I865G(dev))	5298	if (IS_845G(dev) \|\| IS_I865G(dev))
5299	i845_update_cursor(crtc, base);	5299	i845_update_cursor(crtc, base);
5300	else	5300	else
5301	i9xx_update_cursor(crtc, base);	5301	i9xx_update_cursor(crtc, base);
5302		5302
5303	if (visible)	5303	if (visible)
5304	intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);	5304	intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5305	}	5305	}
5306		5306
5307	static int intel_crtc_cursor_set(struct drm_crtc *crtc,	5307	static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5308	struct drm_file *file,	5308	struct drm_file *file,
5309	uint32_t handle,	5309	uint32_t handle,
5310	uint32_t width, uint32_t height)	5310	uint32_t width, uint32_t height)
5311	{	5311	{
5312	struct drm_device *dev = crtc->dev;	5312	struct drm_device *dev = crtc->dev;
5313	struct drm_i915_private *dev_priv = dev->dev_private;	5313	struct drm_i915_private *dev_priv = dev->dev_private;
5314	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5314	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5315	struct drm_i915_gem_object *obj;	5315	struct drm_i915_gem_object *obj;
5316	uint32_t addr;	5316	uint32_t addr;
5317	int ret;	5317	int ret;
5318		5318
5319	DRM_DEBUG_KMS("\n");	5319	DRM_DEBUG_KMS("\n");
5320		5320
5321	/* if we want to turn off the cursor ignore width and height */	5321	/* if we want to turn off the cursor ignore width and height */
5322	if (!handle) {	5322	if (!handle) {
5323	DRM_DEBUG_KMS("cursor off\n");	5323	DRM_DEBUG_KMS("cursor off\n");
5324	addr = 0;	5324	addr = 0;
5325	obj = NULL;	5325	obj = NULL;
5326	mutex_lock(&dev->struct_mutex);	5326	mutex_lock(&dev->struct_mutex);
5327	goto finish;	5327	goto finish;
5328	}	5328	}
5329		5329
5330	/* Currently we only support 64x64 cursors */	5330	/* Currently we only support 64x64 cursors */
5331	if (width != 64 \|\| height != 64) {	5331	if (width != 64 \|\| height != 64) {
5332	DRM_ERROR("we currently only support 64x64 cursors\n");	5332	DRM_ERROR("we currently only support 64x64 cursors\n");
5333	return -EINVAL;	5333	return -EINVAL;
5334	}	5334	}
5335		5335
5336	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));	5336	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5337	if (&obj->base == NULL)	5337	if (&obj->base == NULL)
5338	return -ENOENT;	5338	return -ENOENT;
5339		5339
5340	if (obj->base.size < width * height * 4) {	5340	if (obj->base.size < width * height * 4) {
5341	DRM_ERROR("buffer is to small\n");	5341	DRM_ERROR("buffer is to small\n");
5342	ret = -ENOMEM;	5342	ret = -ENOMEM;
5343	goto fail;	5343	goto fail;
5344	}	5344	}
5345		5345
5346	/* we only need to pin inside GTT if cursor is non-phy */	5346	/* we only need to pin inside GTT if cursor is non-phy */
5347	mutex_lock(&dev->struct_mutex);	5347	mutex_lock(&dev->struct_mutex);
5348	if (!dev_priv->info->cursor_needs_physical) {	5348	if (!dev_priv->info->cursor_needs_physical) {
5349	if (obj->tiling_mode) {	5349	if (obj->tiling_mode) {
5350	DRM_ERROR("cursor cannot be tiled\n");	5350	DRM_ERROR("cursor cannot be tiled\n");
5351	ret = -EINVAL;	5351	ret = -EINVAL;
5352	goto fail_locked;	5352	goto fail_locked;
5353	}	5353	}
5354		5354
5355	ret = i915_gem_object_pin(obj, PAGE_SIZE, true);	5355	ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5356	if (ret) {	5356	if (ret) {
5357	DRM_ERROR("failed to pin cursor bo\n");	5357	DRM_ERROR("failed to pin cursor bo\n");
5358	goto fail_locked;	5358	goto fail_locked;
5359	}	5359	}
5360		5360
5361	ret = i915_gem_object_set_to_gtt_domain(obj, 0);	5361	ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5362	if (ret) {	5362	if (ret) {
5363	DRM_ERROR("failed to move cursor bo into the GTT\n");	5363	DRM_ERROR("failed to move cursor bo into the GTT\n");
5364	goto fail_unpin;	5364	goto fail_unpin;
5365	}	5365	}
5366		5366
5367	ret = i915_gem_object_put_fence(obj);	5367	ret = i915_gem_object_put_fence(obj);
5368	if (ret) {	5368	if (ret) {
5369	DRM_ERROR("failed to move cursor bo into the GTT\n");	5369	DRM_ERROR("failed to move cursor bo into the GTT\n");
5370	goto fail_unpin;	5370	goto fail_unpin;
5371	}	5371	}
5372		5372
5373	addr = obj->gtt_offset;	5373	addr = obj->gtt_offset;
5374	} else {	5374	} else {
5375	int align = IS_I830(dev) ? 16 * 1024 : 256;	5375	int align = IS_I830(dev) ? 16 * 1024 : 256;
5376	ret = i915_gem_attach_phys_object(dev, obj,	5376	ret = i915_gem_attach_phys_object(dev, obj,
5377	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,	5377	(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5378	align);	5378	align);
5379	if (ret) {	5379	if (ret) {
5380	DRM_ERROR("failed to attach phys object\n");	5380	DRM_ERROR("failed to attach phys object\n");
5381	goto fail_locked;	5381	goto fail_locked;
5382	}	5382	}
5383	addr = obj->phys_obj->handle->busaddr;	5383	addr = obj->phys_obj->handle->busaddr;
5384	}	5384	}
5385		5385
5386	if (IS_GEN2(dev))	5386	if (IS_GEN2(dev))
5387	I915_WRITE(CURSIZE, (height << 12) \| width);	5387	I915_WRITE(CURSIZE, (height << 12) \| width);
5388		5388
5389	finish:	5389	finish:
5390	if (intel_crtc->cursor_bo) {	5390	if (intel_crtc->cursor_bo) {
5391	if (dev_priv->info->cursor_needs_physical) {	5391	if (dev_priv->info->cursor_needs_physical) {
5392	if (intel_crtc->cursor_bo != obj)	5392	if (intel_crtc->cursor_bo != obj)
5393	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);	5393	i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5394	} else	5394	} else
5395	i915_gem_object_unpin(intel_crtc->cursor_bo);	5395	i915_gem_object_unpin(intel_crtc->cursor_bo);
5396	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);	5396	drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5397	}	5397	}
5398		5398
5399	mutex_unlock(&dev->struct_mutex);	5399	mutex_unlock(&dev->struct_mutex);
5400		5400
5401	intel_crtc->cursor_addr = addr;	5401	intel_crtc->cursor_addr = addr;
5402	intel_crtc->cursor_bo = obj;	5402	intel_crtc->cursor_bo = obj;
5403	intel_crtc->cursor_width = width;	5403	intel_crtc->cursor_width = width;
5404	intel_crtc->cursor_height = height;	5404	intel_crtc->cursor_height = height;
5405		5405
5406	intel_crtc_update_cursor(crtc, true);	5406	intel_crtc_update_cursor(crtc, true);
5407		5407
5408	return 0;	5408	return 0;
5409	fail_unpin:	5409	fail_unpin:
5410	i915_gem_object_unpin(obj);	5410	i915_gem_object_unpin(obj);
5411	fail_locked:	5411	fail_locked:
5412	mutex_unlock(&dev->struct_mutex);	5412	mutex_unlock(&dev->struct_mutex);
5413	fail:	5413	fail:
5414	drm_gem_object_unreference_unlocked(&obj->base);	5414	drm_gem_object_unreference_unlocked(&obj->base);
5415	return ret;	5415	return ret;
5416	}	5416	}
5417		5417
5418	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)	5418	static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5419	{	5419	{
5420	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5420	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5421		5421
5422	intel_crtc->cursor_x = x;	5422	intel_crtc->cursor_x = x;
5423	intel_crtc->cursor_y = y;	5423	intel_crtc->cursor_y = y;
5424		5424
5425	intel_crtc_update_cursor(crtc, true);	5425	intel_crtc_update_cursor(crtc, true);
5426		5426
5427	return 0;	5427	return 0;
5428	}	5428	}
5429		5429
5430	/** Sets the color ramps on behalf of RandR */	5430	/** Sets the color ramps on behalf of RandR */
5431	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,	5431	void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5432	u16 blue, int regno)	5432	u16 blue, int regno)
5433	{	5433	{
5434	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5434	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5435		5435
5436	intel_crtc->lut_r[regno] = red >> 8;	5436	intel_crtc->lut_r[regno] = red >> 8;
5437	intel_crtc->lut_g[regno] = green >> 8;	5437	intel_crtc->lut_g[regno] = green >> 8;
5438	intel_crtc->lut_b[regno] = blue >> 8;	5438	intel_crtc->lut_b[regno] = blue >> 8;
5439	}	5439	}
5440		5440
5441	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,	5441	void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
5442	u16 *blue, int regno)	5442	u16 *blue, int regno)
5443	{	5443	{
5444	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5444	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5445		5445
5446	*red = intel_crtc->lut_r[regno] << 8;	5446	*red = intel_crtc->lut_r[regno] << 8;
5447	*green = intel_crtc->lut_g[regno] << 8;	5447	*green = intel_crtc->lut_g[regno] << 8;
5448	*blue = intel_crtc->lut_b[regno] << 8;	5448	*blue = intel_crtc->lut_b[regno] << 8;
5449	}	5449	}
5450		5450
5451	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,	5451	static void intel_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
5452	u16 *blue, uint32_t start, uint32_t size)	5452	u16 *blue, uint32_t start, uint32_t size)
5453	{	5453	{
5454	int end = (start + size > 256) ? 256 : start + size, i;	5454	int end = (start + size > 256) ? 256 : start + size, i;
5455	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5455	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5456		5456
5457	for (i = start; i < end; i++) {	5457	for (i = start; i < end; i++) {
5458	intel_crtc->lut_r[i] = red[i] >> 8;	5458	intel_crtc->lut_r[i] = red[i] >> 8;
5459	intel_crtc->lut_g[i] = green[i] >> 8;	5459	intel_crtc->lut_g[i] = green[i] >> 8;
5460	intel_crtc->lut_b[i] = blue[i] >> 8;	5460	intel_crtc->lut_b[i] = blue[i] >> 8;
5461	}	5461	}
5462		5462
5463	intel_crtc_load_lut(crtc);	5463	intel_crtc_load_lut(crtc);
5464	}	5464	}
5465		5465
5466	/**	5466	/**
5467	* Get a pipe with a simple mode set on it for doing load-based monitor	5467	* Get a pipe with a simple mode set on it for doing load-based monitor
5468	* detection.	5468	* detection.
5469	*	5469	*
5470	* It will be up to the load-detect code to adjust the pipe as appropriate for	5470	* It will be up to the load-detect code to adjust the pipe as appropriate for
5471	* its requirements. The pipe will be connected to no other encoders.	5471	* its requirements. The pipe will be connected to no other encoders.
5472	*	5472	*
5473	* Currently this code will only succeed if there is a pipe with no encoders	5473	* Currently this code will only succeed if there is a pipe with no encoders
5474	* configured for it. In the future, it could choose to temporarily disable	5474	* configured for it. In the future, it could choose to temporarily disable
5475	* some outputs to free up a pipe for its use.	5475	* some outputs to free up a pipe for its use.
5476	*	5476	*
5477	* \return crtc, or NULL if no pipes are available.	5477	* \return crtc, or NULL if no pipes are available.
5478	*/	5478	*/
5479		5479
5480	/* VESA 640x480x72Hz mode to set on the pipe */	5480	/* VESA 640x480x72Hz mode to set on the pipe */
5481	static struct drm_display_mode load_detect_mode = {	5481	static struct drm_display_mode load_detect_mode = {
5482	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,	5482	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5483	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),	5483	704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
5484	};	5484	};
5485		5485
5486	struct drm_crtc intel_get_load_detect_pipe(struct intel_encoder intel_encoder,	5486	struct drm_crtc intel_get_load_detect_pipe(struct intel_encoder intel_encoder,
5487	struct drm_connector *connector,	5487	struct drm_connector *connector,
5488	struct drm_display_mode *mode,	5488	struct drm_display_mode *mode,
5489	int *dpms_mode)	5489	int *dpms_mode)
5490	{	5490	{
5491	struct intel_crtc *intel_crtc;	5491	struct intel_crtc *intel_crtc;
5492	struct drm_crtc *possible_crtc;	5492	struct drm_crtc *possible_crtc;
5493	struct drm_crtc *supported_crtc =NULL;	5493	struct drm_crtc *supported_crtc =NULL;
5494	struct drm_encoder *encoder = &intel_encoder->base;	5494	struct drm_encoder *encoder = &intel_encoder->base;
5495	struct drm_crtc *crtc = NULL;	5495	struct drm_crtc *crtc = NULL;
5496	struct drm_device *dev = encoder->dev;	5496	struct drm_device *dev = encoder->dev;
5497	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;	5497	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5498	struct drm_crtc_helper_funcs *crtc_funcs;	5498	struct drm_crtc_helper_funcs *crtc_funcs;
5499	int i = -1;	5499	int i = -1;
5500		5500
5501	/*	5501	/*
5502	* Algorithm gets a little messy:	5502	* Algorithm gets a little messy:
5503	* - if the connector already has an assigned crtc, use it (but make	5503	* - if the connector already has an assigned crtc, use it (but make
5504	* sure it's on first)	5504	* sure it's on first)
5505	* - try to find the first unused crtc that can drive this connector,	5505	* - try to find the first unused crtc that can drive this connector,
5506	* and use that if we find one	5506	* and use that if we find one
5507	* - if there are no unused crtcs available, try to use the first	5507	* - if there are no unused crtcs available, try to use the first
5508	* one we found that supports the connector	5508	* one we found that supports the connector
5509	*/	5509	*/
5510		5510
5511	/* See if we already have a CRTC for this connector */	5511	/* See if we already have a CRTC for this connector */
5512	if (encoder->crtc) {	5512	if (encoder->crtc) {
5513	crtc = encoder->crtc;	5513	crtc = encoder->crtc;
5514	/* Make sure the crtc and connector are running */	5514	/* Make sure the crtc and connector are running */
5515	intel_crtc = to_intel_crtc(crtc);	5515	intel_crtc = to_intel_crtc(crtc);
5516	*dpms_mode = intel_crtc->dpms_mode;	5516	*dpms_mode = intel_crtc->dpms_mode;
5517	if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {	5517	if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5518	crtc_funcs = crtc->helper_private;	5518	crtc_funcs = crtc->helper_private;
5519	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);	5519	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5520	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);	5520	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5521	}	5521	}
5522	return crtc;	5522	return crtc;
5523	}	5523	}
5524		5524
5525	/* Find an unused one (if possible) */	5525	/* Find an unused one (if possible) */
5526	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {	5526	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5527	i++;	5527	i++;
5528	if (!(encoder->possible_crtcs & (1 << i)))	5528	if (!(encoder->possible_crtcs & (1 << i)))
5529	continue;	5529	continue;
5530	if (!possible_crtc->enabled) {	5530	if (!possible_crtc->enabled) {
5531	crtc = possible_crtc;	5531	crtc = possible_crtc;
5532	break;	5532	break;
5533	}	5533	}
5534	if (!supported_crtc)	5534	if (!supported_crtc)
5535	supported_crtc = possible_crtc;	5535	supported_crtc = possible_crtc;
5536	}	5536	}
5537		5537
5538	/*	5538	/*
5539	* If we didn't find an unused CRTC, don't use any.	5539	* If we didn't find an unused CRTC, don't use any.
5540	*/	5540	*/
5541	if (!crtc) {	5541	if (!crtc) {
5542	return NULL;	5542	return NULL;
5543	}	5543	}
5544		5544
5545	encoder->crtc = crtc;	5545	encoder->crtc = crtc;
5546	connector->encoder = encoder;	5546	connector->encoder = encoder;
5547	intel_encoder->load_detect_temp = true;	5547	intel_encoder->load_detect_temp = true;
5548		5548
5549	intel_crtc = to_intel_crtc(crtc);	5549	intel_crtc = to_intel_crtc(crtc);
5550	*dpms_mode = intel_crtc->dpms_mode;	5550	*dpms_mode = intel_crtc->dpms_mode;
5551		5551
5552	if (!crtc->enabled) {	5552	if (!crtc->enabled) {
5553	if (!mode)	5553	if (!mode)
5554	mode = &load_detect_mode;	5554	mode = &load_detect_mode;
5555	drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);	5555	drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5556	} else {	5556	} else {
5557	if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {	5557	if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5558	crtc_funcs = crtc->helper_private;	5558	crtc_funcs = crtc->helper_private;
5559	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);	5559	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5560	}	5560	}
5561		5561
5562	/* Add this connector to the crtc */	5562	/* Add this connector to the crtc */
5563	encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);	5563	encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5564	encoder_funcs->commit(encoder);	5564	encoder_funcs->commit(encoder);
5565	}	5565	}
5566	/* let the connector get through one full cycle before testing */	5566	/* let the connector get through one full cycle before testing */
5567	intel_wait_for_vblank(dev, intel_crtc->pipe);	5567	intel_wait_for_vblank(dev, intel_crtc->pipe);
5568		5568
5569	return crtc;	5569	return crtc;
5570	}	5570	}
5571		5571
5572	void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,	5572	void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5573	struct drm_connector *connector, int dpms_mode)	5573	struct drm_connector *connector, int dpms_mode)
5574	{	5574	{
5575	struct drm_encoder *encoder = &intel_encoder->base;	5575	struct drm_encoder *encoder = &intel_encoder->base;
5576	struct drm_device *dev = encoder->dev;	5576	struct drm_device *dev = encoder->dev;
5577	struct drm_crtc *crtc = encoder->crtc;	5577	struct drm_crtc *crtc = encoder->crtc;
5578	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;	5578	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5579	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;	5579	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5580		5580
5581	if (intel_encoder->load_detect_temp) {	5581	if (intel_encoder->load_detect_temp) {
5582	encoder->crtc = NULL;	5582	encoder->crtc = NULL;
5583	connector->encoder = NULL;	5583	connector->encoder = NULL;
5584	intel_encoder->load_detect_temp = false;	5584	intel_encoder->load_detect_temp = false;
5585	crtc->enabled = drm_helper_crtc_in_use(crtc);	5585	crtc->enabled = drm_helper_crtc_in_use(crtc);
5586	drm_helper_disable_unused_functions(dev);	5586	drm_helper_disable_unused_functions(dev);
5587	}	5587	}
5588		5588
5589	/* Switch crtc and encoder back off if necessary */	5589	/* Switch crtc and encoder back off if necessary */
5590	if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {	5590	if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5591	if (encoder->crtc == crtc)	5591	if (encoder->crtc == crtc)
5592	encoder_funcs->dpms(encoder, dpms_mode);	5592	encoder_funcs->dpms(encoder, dpms_mode);
5593	crtc_funcs->dpms(crtc, dpms_mode);	5593	crtc_funcs->dpms(crtc, dpms_mode);
5594	}	5594	}
5595	}	5595	}
5596		5596
5597	/* Returns the clock of the currently programmed mode of the given pipe. */	5597	/* Returns the clock of the currently programmed mode of the given pipe. */
5598	static int intel_crtc_clock_get(struct drm_device dev, struct drm_crtc crtc)	5598	static int intel_crtc_clock_get(struct drm_device dev, struct drm_crtc crtc)
5599	{	5599	{
5600	struct drm_i915_private *dev_priv = dev->dev_private;	5600	struct drm_i915_private *dev_priv = dev->dev_private;
5601	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5601	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5602	int pipe = intel_crtc->pipe;	5602	int pipe = intel_crtc->pipe;
5603	u32 dpll = I915_READ(DPLL(pipe));	5603	u32 dpll = I915_READ(DPLL(pipe));
5604	u32 fp;	5604	u32 fp;
5605	intel_clock_t clock;	5605	intel_clock_t clock;
5606		5606
5607	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)	5607	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5608	fp = FP0(pipe);	5608	fp = FP0(pipe);
5609	else	5609	else
5610	fp = FP1(pipe);	5610	fp = FP1(pipe);
5611		5611
5612	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;	5612	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5613	if (IS_PINEVIEW(dev)) {	5613	if (IS_PINEVIEW(dev)) {
5614	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;	5614	clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5615	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;	5615	clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5616	} else {	5616	} else {
5617	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;	5617	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5618	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;	5618	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5619	}	5619	}
5620		5620
5621	if (!IS_GEN2(dev)) {	5621	if (!IS_GEN2(dev)) {
5622	if (IS_PINEVIEW(dev))	5622	if (IS_PINEVIEW(dev))
5623	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>	5623	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5624	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);	5624	DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5625	else	5625	else
5626	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>	5626	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5627	DPLL_FPA01_P1_POST_DIV_SHIFT);	5627	DPLL_FPA01_P1_POST_DIV_SHIFT);
5628		5628
5629	switch (dpll & DPLL_MODE_MASK) {	5629	switch (dpll & DPLL_MODE_MASK) {
5630	case DPLLB_MODE_DAC_SERIAL:	5630	case DPLLB_MODE_DAC_SERIAL:
5631	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?	5631	clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5632	5 : 10;	5632	5 : 10;
5633	break;	5633	break;
5634	case DPLLB_MODE_LVDS:	5634	case DPLLB_MODE_LVDS:
5635	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?	5635	clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5636	7 : 14;	5636	7 : 14;
5637	break;	5637	break;
5638	default:	5638	default:
5639	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "	5639	DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5640	"mode\n", (int)(dpll & DPLL_MODE_MASK));	5640	"mode\n", (int)(dpll & DPLL_MODE_MASK));
5641	return 0;	5641	return 0;
5642	}	5642	}
5643		5643
5644	/* XXX: Handle the 100Mhz refclk */	5644	/* XXX: Handle the 100Mhz refclk */
5645	intel_clock(dev, 96000, &clock);	5645	intel_clock(dev, 96000, &clock);
5646	} else {	5646	} else {
5647	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);	5647	bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5648		5648
5649	if (is_lvds) {	5649	if (is_lvds) {
5650	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>	5650	clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5651	DPLL_FPA01_P1_POST_DIV_SHIFT);	5651	DPLL_FPA01_P1_POST_DIV_SHIFT);
5652	clock.p2 = 14;	5652	clock.p2 = 14;
5653		5653
5654	if ((dpll & PLL_REF_INPUT_MASK) ==	5654	if ((dpll & PLL_REF_INPUT_MASK) ==
5655	PLLB_REF_INPUT_SPREADSPECTRUMIN) {	5655	PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5656	/* XXX: might not be 66MHz */	5656	/* XXX: might not be 66MHz */
5657	intel_clock(dev, 66000, &clock);	5657	intel_clock(dev, 66000, &clock);
5658	} else	5658	} else
5659	intel_clock(dev, 48000, &clock);	5659	intel_clock(dev, 48000, &clock);
5660	} else {	5660	} else {
5661	if (dpll & PLL_P1_DIVIDE_BY_TWO)	5661	if (dpll & PLL_P1_DIVIDE_BY_TWO)
5662	clock.p1 = 2;	5662	clock.p1 = 2;
5663	else {	5663	else {
5664	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>	5664	clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5665	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;	5665	DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5666	}	5666	}
5667	if (dpll & PLL_P2_DIVIDE_BY_4)	5667	if (dpll & PLL_P2_DIVIDE_BY_4)
5668	clock.p2 = 4;	5668	clock.p2 = 4;
5669	else	5669	else
5670	clock.p2 = 2;	5670	clock.p2 = 2;
5671		5671
5672	intel_clock(dev, 48000, &clock);	5672	intel_clock(dev, 48000, &clock);
5673	}	5673	}
5674	}	5674	}
5675		5675
5676	/* XXX: It would be nice to validate the clocks, but we can't reuse	5676	/* XXX: It would be nice to validate the clocks, but we can't reuse
5677	* i830PllIsValid() because it relies on the xf86_config connector	5677	* i830PllIsValid() because it relies on the xf86_config connector
5678	* configuration being accurate, which it isn't necessarily.	5678	* configuration being accurate, which it isn't necessarily.
5679	*/	5679	*/
5680		5680
5681	return clock.dot;	5681	return clock.dot;
5682	}	5682	}
5683		5683
5684	/** Returns the currently programmed mode of the given pipe. */	5684	/** Returns the currently programmed mode of the given pipe. */
5685	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,	5685	struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
5686	struct drm_crtc *crtc)	5686	struct drm_crtc *crtc)
5687	{	5687	{
5688	struct drm_i915_private *dev_priv = dev->dev_private;	5688	struct drm_i915_private *dev_priv = dev->dev_private;
5689	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5689	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5690	int pipe = intel_crtc->pipe;	5690	int pipe = intel_crtc->pipe;
5691	struct drm_display_mode *mode;	5691	struct drm_display_mode *mode;
5692	int htot = I915_READ(HTOTAL(pipe));	5692	int htot = I915_READ(HTOTAL(pipe));
5693	int hsync = I915_READ(HSYNC(pipe));	5693	int hsync = I915_READ(HSYNC(pipe));
5694	int vtot = I915_READ(VTOTAL(pipe));	5694	int vtot = I915_READ(VTOTAL(pipe));
5695	int vsync = I915_READ(VSYNC(pipe));	5695	int vsync = I915_READ(VSYNC(pipe));
5696		5696
5697	mode = kzalloc(sizeof(*mode), GFP_KERNEL);	5697	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5698	if (!mode)	5698	if (!mode)
5699	return NULL;	5699	return NULL;
5700		5700
5701	mode->clock = intel_crtc_clock_get(dev, crtc);	5701	mode->clock = intel_crtc_clock_get(dev, crtc);
5702	mode->hdisplay = (htot & 0xffff) + 1;	5702	mode->hdisplay = (htot & 0xffff) + 1;
5703	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;	5703	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5704	mode->hsync_start = (hsync & 0xffff) + 1;	5704	mode->hsync_start = (hsync & 0xffff) + 1;
5705	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;	5705	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5706	mode->vdisplay = (vtot & 0xffff) + 1;	5706	mode->vdisplay = (vtot & 0xffff) + 1;
5707	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;	5707	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5708	mode->vsync_start = (vsync & 0xffff) + 1;	5708	mode->vsync_start = (vsync & 0xffff) + 1;
5709	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;	5709	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5710		5710
5711	drm_mode_set_name(mode);	5711	drm_mode_set_name(mode);
5712	drm_mode_set_crtcinfo(mode, 0);	5712	drm_mode_set_crtcinfo(mode, 0);
5713		5713
5714	return mode;	5714	return mode;
5715	}	5715	}
5716		5716
5717	#define GPU_IDLE_TIMEOUT 500 /* ms */	5717	#define GPU_IDLE_TIMEOUT 500 /* ms */
5718		5718
5719	/* When this timer fires, we've been idle for awhile */	5719	/* When this timer fires, we've been idle for awhile */
5720	static void intel_gpu_idle_timer(unsigned long arg)	5720	static void intel_gpu_idle_timer(unsigned long arg)
5721	{	5721	{
5722	struct drm_device dev = (struct drm_device )arg;	5722	struct drm_device dev = (struct drm_device )arg;
5723	drm_i915_private_t *dev_priv = dev->dev_private;	5723	drm_i915_private_t *dev_priv = dev->dev_private;
5724		5724
5725	if (!list_empty(&dev_priv->mm.active_list)) {	5725	if (!list_empty(&dev_priv->mm.active_list)) {
5726	/* Still processing requests, so just re-arm the timer. */	5726	/* Still processing requests, so just re-arm the timer. */
5727	mod_timer(&dev_priv->idle_timer, jiffies +	5727	mod_timer(&dev_priv->idle_timer, jiffies +
5728	msecs_to_jiffies(GPU_IDLE_TIMEOUT));	5728	msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5729	return;	5729	return;
5730	}	5730	}
5731		5731
5732	dev_priv->busy = false;	5732	dev_priv->busy = false;
5733	queue_work(dev_priv->wq, &dev_priv->idle_work);	5733	queue_work(dev_priv->wq, &dev_priv->idle_work);
5734	}	5734	}
5735		5735
5736	#define CRTC_IDLE_TIMEOUT 1000 /* ms */	5736	#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5737		5737
5738	static void intel_crtc_idle_timer(unsigned long arg)	5738	static void intel_crtc_idle_timer(unsigned long arg)
5739	{	5739	{
5740	struct intel_crtc intel_crtc = (struct intel_crtc )arg;	5740	struct intel_crtc intel_crtc = (struct intel_crtc )arg;
5741	struct drm_crtc *crtc = &intel_crtc->base;	5741	struct drm_crtc *crtc = &intel_crtc->base;
5742	drm_i915_private_t *dev_priv = crtc->dev->dev_private;	5742	drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5743	struct intel_framebuffer *intel_fb;	5743	struct intel_framebuffer *intel_fb;
5744		5744
5745	intel_fb = to_intel_framebuffer(crtc->fb);	5745	intel_fb = to_intel_framebuffer(crtc->fb);
5746	if (intel_fb && intel_fb->obj->active) {	5746	if (intel_fb && intel_fb->obj->active) {
5747	/* The framebuffer is still being accessed by the GPU. */	5747	/* The framebuffer is still being accessed by the GPU. */
5748	mod_timer(&intel_crtc->idle_timer, jiffies +	5748	mod_timer(&intel_crtc->idle_timer, jiffies +
5749	msecs_to_jiffies(CRTC_IDLE_TIMEOUT));	5749	msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5750	return;	5750	return;
5751	}	5751	}
5752		5752
5753	intel_crtc->busy = false;	5753	intel_crtc->busy = false;
5754	queue_work(dev_priv->wq, &dev_priv->idle_work);	5754	queue_work(dev_priv->wq, &dev_priv->idle_work);
5755	}	5755	}
5756		5756
5757	static void intel_increase_pllclock(struct drm_crtc *crtc)	5757	static void intel_increase_pllclock(struct drm_crtc *crtc)
5758	{	5758	{
5759	struct drm_device *dev = crtc->dev;	5759	struct drm_device *dev = crtc->dev;
5760	drm_i915_private_t *dev_priv = dev->dev_private;	5760	drm_i915_private_t *dev_priv = dev->dev_private;
5761	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5761	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5762	int pipe = intel_crtc->pipe;	5762	int pipe = intel_crtc->pipe;
5763	int dpll_reg = DPLL(pipe);	5763	int dpll_reg = DPLL(pipe);
5764	int dpll;	5764	int dpll;
5765		5765
5766	if (HAS_PCH_SPLIT(dev))	5766	if (HAS_PCH_SPLIT(dev))
5767	return;	5767	return;
5768		5768
5769	if (!dev_priv->lvds_downclock_avail)	5769	if (!dev_priv->lvds_downclock_avail)
5770	return;	5770	return;
5771		5771
5772	dpll = I915_READ(dpll_reg);	5772	dpll = I915_READ(dpll_reg);
5773	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {	5773	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5774	DRM_DEBUG_DRIVER("upclocking LVDS\n");	5774	DRM_DEBUG_DRIVER("upclocking LVDS\n");
5775		5775
5776	/* Unlock panel regs */	5776	/* Unlock panel regs */
5777	I915_WRITE(PP_CONTROL,	5777	I915_WRITE(PP_CONTROL,
5778	I915_READ(PP_CONTROL) \| PANEL_UNLOCK_REGS);	5778	I915_READ(PP_CONTROL) \| PANEL_UNLOCK_REGS);
5779		5779
5780	dpll &= ~DISPLAY_RATE_SELECT_FPA1;	5780	dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5781	I915_WRITE(dpll_reg, dpll);	5781	I915_WRITE(dpll_reg, dpll);
5782	intel_wait_for_vblank(dev, pipe);	5782	intel_wait_for_vblank(dev, pipe);
5783		5783
5784	dpll = I915_READ(dpll_reg);	5784	dpll = I915_READ(dpll_reg);
5785	if (dpll & DISPLAY_RATE_SELECT_FPA1)	5785	if (dpll & DISPLAY_RATE_SELECT_FPA1)
5786	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");	5786	DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5787		5787
5788	/* ...and lock them again */	5788	/* ...and lock them again */
5789	I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);	5789	I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5790	}	5790	}
5791		5791
5792	/* Schedule downclock */	5792	/* Schedule downclock */
5793	mod_timer(&intel_crtc->idle_timer, jiffies +	5793	mod_timer(&intel_crtc->idle_timer, jiffies +
5794	msecs_to_jiffies(CRTC_IDLE_TIMEOUT));	5794	msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5795	}	5795	}
5796		5796
5797	static void intel_decrease_pllclock(struct drm_crtc *crtc)	5797	static void intel_decrease_pllclock(struct drm_crtc *crtc)
5798	{	5798	{
5799	struct drm_device *dev = crtc->dev;	5799	struct drm_device *dev = crtc->dev;
5800	drm_i915_private_t *dev_priv = dev->dev_private;	5800	drm_i915_private_t *dev_priv = dev->dev_private;
5801	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5801	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5802	int pipe = intel_crtc->pipe;	5802	int pipe = intel_crtc->pipe;
5803	int dpll_reg = DPLL(pipe);	5803	int dpll_reg = DPLL(pipe);
5804	int dpll = I915_READ(dpll_reg);	5804	int dpll = I915_READ(dpll_reg);
5805		5805
5806	if (HAS_PCH_SPLIT(dev))	5806	if (HAS_PCH_SPLIT(dev))
5807	return;	5807	return;
5808		5808
5809	if (!dev_priv->lvds_downclock_avail)	5809	if (!dev_priv->lvds_downclock_avail)
5810	return;	5810	return;
5811		5811
5812	/*	5812	/*
5813	* Since this is called by a timer, we should never get here in	5813	* Since this is called by a timer, we should never get here in
5814	* the manual case.	5814	* the manual case.
5815	*/	5815	*/
5816	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {	5816	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5817	DRM_DEBUG_DRIVER("downclocking LVDS\n");	5817	DRM_DEBUG_DRIVER("downclocking LVDS\n");
5818		5818
5819	/* Unlock panel regs */	5819	/* Unlock panel regs */
5820	I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) \|	5820	I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) \|
5821	PANEL_UNLOCK_REGS);	5821	PANEL_UNLOCK_REGS);
5822		5822
5823	dpll \|= DISPLAY_RATE_SELECT_FPA1;	5823	dpll \|= DISPLAY_RATE_SELECT_FPA1;
5824	I915_WRITE(dpll_reg, dpll);	5824	I915_WRITE(dpll_reg, dpll);
5825	intel_wait_for_vblank(dev, pipe);	5825	intel_wait_for_vblank(dev, pipe);
5826	dpll = I915_READ(dpll_reg);	5826	dpll = I915_READ(dpll_reg);
5827	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))	5827	if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5828	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");	5828	DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5829		5829
5830	/* ...and lock them again */	5830	/* ...and lock them again */
5831	I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);	5831	I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5832	}	5832	}
5833		5833
5834	}	5834	}
5835		5835
5836	/**	5836	/**
5837	* intel_idle_update - adjust clocks for idleness	5837	* intel_idle_update - adjust clocks for idleness
5838	* @work: work struct	5838	* @work: work struct
5839	*	5839	*
5840	* Either the GPU or display (or both) went idle. Check the busy status	5840	* Either the GPU or display (or both) went idle. Check the busy status
5841	* here and adjust the CRTC and GPU clocks as necessary.	5841	* here and adjust the CRTC and GPU clocks as necessary.
5842	*/	5842	*/
5843	static void intel_idle_update(struct work_struct *work)	5843	static void intel_idle_update(struct work_struct *work)
5844	{	5844	{
5845	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,	5845	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5846	idle_work);	5846	idle_work);
5847	struct drm_device *dev = dev_priv->dev;	5847	struct drm_device *dev = dev_priv->dev;
5848	struct drm_crtc *crtc;	5848	struct drm_crtc *crtc;
5849	struct intel_crtc *intel_crtc;	5849	struct intel_crtc *intel_crtc;
5850		5850
5851	if (!i915_powersave)	5851	if (!i915_powersave)
5852	return;	5852	return;
5853		5853
5854	mutex_lock(&dev->struct_mutex);	5854	mutex_lock(&dev->struct_mutex);
5855		5855
5856	i915_update_gfx_val(dev_priv);	5856	i915_update_gfx_val(dev_priv);
5857		5857
5858	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {	5858	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5859	/* Skip inactive CRTCs */	5859	/* Skip inactive CRTCs */
5860	if (!crtc->fb)	5860	if (!crtc->fb)
5861	continue;	5861	continue;
5862		5862
5863	intel_crtc = to_intel_crtc(crtc);	5863	intel_crtc = to_intel_crtc(crtc);
5864	if (!intel_crtc->busy)	5864	if (!intel_crtc->busy)
5865	intel_decrease_pllclock(crtc);	5865	intel_decrease_pllclock(crtc);
5866	}	5866	}
5867		5867
5868		5868
5869	mutex_unlock(&dev->struct_mutex);	5869	mutex_unlock(&dev->struct_mutex);
5870	}	5870	}
5871		5871
5872	/**	5872	/**
5873	* intel_mark_busy - mark the GPU and possibly the display busy	5873	* intel_mark_busy - mark the GPU and possibly the display busy
5874	* @dev: drm device	5874	* @dev: drm device
5875	* @obj: object we're operating on	5875	* @obj: object we're operating on
5876	*	5876	*
5877	* Callers can use this function to indicate that the GPU is busy processing	5877	* Callers can use this function to indicate that the GPU is busy processing
5878	* commands. If @obj matches one of the CRTC objects (i.e. it's a scanout	5878	* commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5879	* buffer), we'll also mark the display as busy, so we know to increase its	5879	* buffer), we'll also mark the display as busy, so we know to increase its
5880	* clock frequency.	5880	* clock frequency.
5881	*/	5881	*/
5882	void intel_mark_busy(struct drm_device dev, struct drm_i915_gem_object obj)	5882	void intel_mark_busy(struct drm_device dev, struct drm_i915_gem_object obj)
5883	{	5883	{
5884	drm_i915_private_t *dev_priv = dev->dev_private;	5884	drm_i915_private_t *dev_priv = dev->dev_private;
5885	struct drm_crtc *crtc = NULL;	5885	struct drm_crtc *crtc = NULL;
5886	struct intel_framebuffer *intel_fb;	5886	struct intel_framebuffer *intel_fb;
5887	struct intel_crtc *intel_crtc;	5887	struct intel_crtc *intel_crtc;
5888		5888
5889	if (!drm_core_check_feature(dev, DRIVER_MODESET))	5889	if (!drm_core_check_feature(dev, DRIVER_MODESET))
5890	return;	5890	return;
5891		5891
5892	if (!dev_priv->busy)	5892	if (!dev_priv->busy)
5893	dev_priv->busy = true;	5893	dev_priv->busy = true;
5894	else	5894	else
5895	mod_timer(&dev_priv->idle_timer, jiffies +	5895	mod_timer(&dev_priv->idle_timer, jiffies +
5896	msecs_to_jiffies(GPU_IDLE_TIMEOUT));	5896	msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5897		5897
5898	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {	5898	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5899	if (!crtc->fb)	5899	if (!crtc->fb)
5900	continue;	5900	continue;
5901		5901
5902	intel_crtc = to_intel_crtc(crtc);	5902	intel_crtc = to_intel_crtc(crtc);
5903	intel_fb = to_intel_framebuffer(crtc->fb);	5903	intel_fb = to_intel_framebuffer(crtc->fb);
5904	if (intel_fb->obj == obj) {	5904	if (intel_fb->obj == obj) {
5905	if (!intel_crtc->busy) {	5905	if (!intel_crtc->busy) {
5906	/* Non-busy -> busy, upclock */	5906	/* Non-busy -> busy, upclock */
5907	intel_increase_pllclock(crtc);	5907	intel_increase_pllclock(crtc);
5908	intel_crtc->busy = true;	5908	intel_crtc->busy = true;
5909	} else {	5909	} else {
5910	/* Busy -> busy, put off timer */	5910	/* Busy -> busy, put off timer */
5911	mod_timer(&intel_crtc->idle_timer, jiffies +	5911	mod_timer(&intel_crtc->idle_timer, jiffies +
5912	msecs_to_jiffies(CRTC_IDLE_TIMEOUT));	5912	msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5913	}	5913	}
5914	}	5914	}
5915	}	5915	}
5916	}	5916	}
5917		5917
5918	static void intel_crtc_destroy(struct drm_crtc *crtc)	5918	static void intel_crtc_destroy(struct drm_crtc *crtc)
5919	{	5919	{
5920	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5920	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5921	struct drm_device *dev = crtc->dev;	5921	struct drm_device *dev = crtc->dev;
5922	struct intel_unpin_work *work;	5922	struct intel_unpin_work *work;
5923	unsigned long flags;	5923	unsigned long flags;
5924		5924
5925	spin_lock_irqsave(&dev->event_lock, flags);	5925	spin_lock_irqsave(&dev->event_lock, flags);
5926	work = intel_crtc->unpin_work;	5926	work = intel_crtc->unpin_work;
5927	intel_crtc->unpin_work = NULL;	5927	intel_crtc->unpin_work = NULL;
5928	spin_unlock_irqrestore(&dev->event_lock, flags);	5928	spin_unlock_irqrestore(&dev->event_lock, flags);
5929		5929
5930	if (work) {	5930	if (work) {
5931	cancel_work_sync(&work->work);	5931	cancel_work_sync(&work->work);
5932	kfree(work);	5932	kfree(work);
5933	}	5933	}
5934		5934
5935	drm_crtc_cleanup(crtc);	5935	drm_crtc_cleanup(crtc);
5936		5936
5937	kfree(intel_crtc);	5937	kfree(intel_crtc);
5938	}	5938	}
5939		5939
5940	static void intel_unpin_work_fn(struct work_struct *__work)	5940	static void intel_unpin_work_fn(struct work_struct *__work)
5941	{	5941	{
5942	struct intel_unpin_work *work =	5942	struct intel_unpin_work *work =
5943	container_of(__work, struct intel_unpin_work, work);	5943	container_of(__work, struct intel_unpin_work, work);
5944		5944
5945	mutex_lock(&work->dev->struct_mutex);	5945	mutex_lock(&work->dev->struct_mutex);
5946	i915_gem_object_unpin(work->old_fb_obj);	5946	i915_gem_object_unpin(work->old_fb_obj);
5947	drm_gem_object_unreference(&work->pending_flip_obj->base);	5947	drm_gem_object_unreference(&work->pending_flip_obj->base);
5948	drm_gem_object_unreference(&work->old_fb_obj->base);	5948	drm_gem_object_unreference(&work->old_fb_obj->base);
5949		5949
5950	mutex_unlock(&work->dev->struct_mutex);	5950	mutex_unlock(&work->dev->struct_mutex);
5951	kfree(work);	5951	kfree(work);
5952	}	5952	}
5953		5953
5954	static void do_intel_finish_page_flip(struct drm_device *dev,	5954	static void do_intel_finish_page_flip(struct drm_device *dev,
5955	struct drm_crtc *crtc)	5955	struct drm_crtc *crtc)
5956	{	5956	{
5957	drm_i915_private_t *dev_priv = dev->dev_private;	5957	drm_i915_private_t *dev_priv = dev->dev_private;
5958	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	5958	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5959	struct intel_unpin_work *work;	5959	struct intel_unpin_work *work;
5960	struct drm_i915_gem_object *obj;	5960	struct drm_i915_gem_object *obj;
5961	struct drm_pending_vblank_event *e;	5961	struct drm_pending_vblank_event *e;
5962	struct timeval tnow, tvbl;	5962	struct timeval tnow, tvbl;
5963	unsigned long flags;	5963	unsigned long flags;
5964		5964
5965	/* Ignore early vblank irqs */	5965	/* Ignore early vblank irqs */
5966	if (intel_crtc == NULL)	5966	if (intel_crtc == NULL)
5967	return;	5967	return;
5968		5968
5969	do_gettimeofday(&tnow);	5969	do_gettimeofday(&tnow);
5970		5970
5971	spin_lock_irqsave(&dev->event_lock, flags);	5971	spin_lock_irqsave(&dev->event_lock, flags);
5972	work = intel_crtc->unpin_work;	5972	work = intel_crtc->unpin_work;
5973	if (work == NULL \|\| !work->pending) {	5973	if (work == NULL \|\| !work->pending) {
5974	spin_unlock_irqrestore(&dev->event_lock, flags);	5974	spin_unlock_irqrestore(&dev->event_lock, flags);
5975	return;	5975	return;
5976	}	5976	}
5977		5977
5978	intel_crtc->unpin_work = NULL;	5978	intel_crtc->unpin_work = NULL;
5979		5979
5980	if (work->event) {	5980	if (work->event) {
5981	e = work->event;	5981	e = work->event;
5982	e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);	5982	e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5983		5983
5984	/* Called before vblank count and timestamps have	5984	/* Called before vblank count and timestamps have
5985	* been updated for the vblank interval of flip	5985	* been updated for the vblank interval of flip
5986	* completion? Need to increment vblank count and	5986	* completion? Need to increment vblank count and
5987	* add one videorefresh duration to returned timestamp	5987	* add one videorefresh duration to returned timestamp
5988	* to account for this. We assume this happened if we	5988	* to account for this. We assume this happened if we
5989	* get called over 0.9 frame durations after the last	5989	* get called over 0.9 frame durations after the last
5990	* timestamped vblank.	5990	* timestamped vblank.
5991	*	5991	*
5992	* This calculation can not be used with vrefresh rates	5992	* This calculation can not be used with vrefresh rates
5993	* below 5Hz (10Hz to be on the safe side) without	5993	* below 5Hz (10Hz to be on the safe side) without
5994	* promoting to 64 integers.	5994	* promoting to 64 integers.
5995	*/	5995	*/
5996	if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >	5996	if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5997	9 * crtc->framedur_ns) {	5997	9 * crtc->framedur_ns) {
5998	e->event.sequence++;	5998	e->event.sequence++;
5999	tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +	5999	tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6000	crtc->framedur_ns);	6000	crtc->framedur_ns);
6001	}	6001	}
6002		6002
6003	e->event.tv_sec = tvbl.tv_sec;	6003	e->event.tv_sec = tvbl.tv_sec;
6004	e->event.tv_usec = tvbl.tv_usec;	6004	e->event.tv_usec = tvbl.tv_usec;
6005		6005
6006	list_add_tail(&e->base.link,	6006	list_add_tail(&e->base.link,
6007	&e->base.file_priv->event_list);	6007	&e->base.file_priv->event_list);
6008	wake_up_interruptible(&e->base.file_priv->event_wait);	6008	wake_up_interruptible(&e->base.file_priv->event_wait);
6009	}	6009	}
6010		6010
6011	drm_vblank_put(dev, intel_crtc->pipe);	6011	drm_vblank_put(dev, intel_crtc->pipe);
6012		6012
6013	spin_unlock_irqrestore(&dev->event_lock, flags);	6013	spin_unlock_irqrestore(&dev->event_lock, flags);
6014		6014
6015	obj = work->old_fb_obj;	6015	obj = work->old_fb_obj;
6016		6016
6017	atomic_clear_mask(1 << intel_crtc->plane,	6017	atomic_clear_mask(1 << intel_crtc->plane,
6018	&obj->pending_flip.counter);	6018	&obj->pending_flip.counter);
6019	if (atomic_read(&obj->pending_flip) == 0)	6019	if (atomic_read(&obj->pending_flip) == 0)
6020	wake_up(&dev_priv->pending_flip_queue);	6020	wake_up(&dev_priv->pending_flip_queue);
6021		6021
6022	schedule_work(&work->work);	6022	schedule_work(&work->work);
6023		6023
6024	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);	6024	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6025	}	6025	}
6026		6026
6027	void intel_finish_page_flip(struct drm_device *dev, int pipe)	6027	void intel_finish_page_flip(struct drm_device *dev, int pipe)
6028	{	6028	{
6029	drm_i915_private_t *dev_priv = dev->dev_private;	6029	drm_i915_private_t *dev_priv = dev->dev_private;
6030	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];	6030	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6031		6031
6032	do_intel_finish_page_flip(dev, crtc);	6032	do_intel_finish_page_flip(dev, crtc);
6033	}	6033	}
6034		6034
6035	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)	6035	void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6036	{	6036	{
6037	drm_i915_private_t *dev_priv = dev->dev_private;	6037	drm_i915_private_t *dev_priv = dev->dev_private;
6038	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];	6038	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6039		6039
6040	do_intel_finish_page_flip(dev, crtc);	6040	do_intel_finish_page_flip(dev, crtc);
6041	}	6041	}
6042		6042
6043	void intel_prepare_page_flip(struct drm_device *dev, int plane)	6043	void intel_prepare_page_flip(struct drm_device *dev, int plane)
6044	{	6044	{
6045	drm_i915_private_t *dev_priv = dev->dev_private;	6045	drm_i915_private_t *dev_priv = dev->dev_private;
6046	struct intel_crtc *intel_crtc =	6046	struct intel_crtc *intel_crtc =
6047	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);	6047	to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6048	unsigned long flags;	6048	unsigned long flags;
6049		6049
6050	spin_lock_irqsave(&dev->event_lock, flags);	6050	spin_lock_irqsave(&dev->event_lock, flags);
6051	if (intel_crtc->unpin_work) {	6051	if (intel_crtc->unpin_work) {
6052	if ((++intel_crtc->unpin_work->pending) > 1)	6052	if ((++intel_crtc->unpin_work->pending) > 1)
6053	DRM_ERROR("Prepared flip multiple times\n");	6053	DRM_ERROR("Prepared flip multiple times\n");
6054	} else {	6054	} else {
6055	DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");	6055	DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6056	}	6056	}
6057	spin_unlock_irqrestore(&dev->event_lock, flags);	6057	spin_unlock_irqrestore(&dev->event_lock, flags);
6058	}	6058	}
6059		6059
6060	static int intel_crtc_page_flip(struct drm_crtc *crtc,	6060	static int intel_crtc_page_flip(struct drm_crtc *crtc,
6061	struct drm_framebuffer *fb,	6061	struct drm_framebuffer *fb,
6062	struct drm_pending_vblank_event *event)	6062	struct drm_pending_vblank_event *event)
6063	{	6063	{
6064	struct drm_device *dev = crtc->dev;	6064	struct drm_device *dev = crtc->dev;
6065	struct drm_i915_private *dev_priv = dev->dev_private;	6065	struct drm_i915_private *dev_priv = dev->dev_private;
6066	struct intel_framebuffer *intel_fb;	6066	struct intel_framebuffer *intel_fb;
6067	struct drm_i915_gem_object *obj;	6067	struct drm_i915_gem_object *obj;
6068	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	6068	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6069	struct intel_unpin_work *work;	6069	struct intel_unpin_work *work;
6070	unsigned long flags, offset;	6070	unsigned long flags, offset;
6071	int pipe = intel_crtc->pipe;	6071	int pipe = intel_crtc->pipe;
6072	u32 pf, pipesrc;	6072	u32 pf, pipesrc;
6073	int ret;	6073	int ret;
6074		6074
6075	work = kzalloc(sizeof *work, GFP_KERNEL);	6075	work = kzalloc(sizeof *work, GFP_KERNEL);
6076	if (work == NULL)	6076	if (work == NULL)
6077	return -ENOMEM;	6077	return -ENOMEM;
6078		6078
6079	work->event = event;	6079	work->event = event;
6080	work->dev = crtc->dev;	6080	work->dev = crtc->dev;
6081	intel_fb = to_intel_framebuffer(crtc->fb);	6081	intel_fb = to_intel_framebuffer(crtc->fb);
6082	work->old_fb_obj = intel_fb->obj;	6082	work->old_fb_obj = intel_fb->obj;
6083	INIT_WORK(&work->work, intel_unpin_work_fn);	6083	INIT_WORK(&work->work, intel_unpin_work_fn);
6084		6084
6085	/* We borrow the event spin lock for protecting unpin_work */	6085	/* We borrow the event spin lock for protecting unpin_work */
6086	spin_lock_irqsave(&dev->event_lock, flags);	6086	spin_lock_irqsave(&dev->event_lock, flags);
6087	if (intel_crtc->unpin_work) {	6087	if (intel_crtc->unpin_work) {
6088	spin_unlock_irqrestore(&dev->event_lock, flags);	6088	spin_unlock_irqrestore(&dev->event_lock, flags);
6089	kfree(work);	6089	kfree(work);
6090		6090
6091	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");	6091	DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6092	return -EBUSY;	6092	return -EBUSY;
6093	}	6093	}
6094	intel_crtc->unpin_work = work;	6094	intel_crtc->unpin_work = work;
6095	spin_unlock_irqrestore(&dev->event_lock, flags);	6095	spin_unlock_irqrestore(&dev->event_lock, flags);
6096		6096
6097	intel_fb = to_intel_framebuffer(fb);	6097	intel_fb = to_intel_framebuffer(fb);
6098	obj = intel_fb->obj;	6098	obj = intel_fb->obj;
6099		6099
6100	mutex_lock(&dev->struct_mutex);	6100	mutex_lock(&dev->struct_mutex);
6101	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));	6101	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6102	if (ret)	6102	if (ret)
6103	goto cleanup_work;	6103	goto cleanup_work;
6104		6104
6105	/* Reference the objects for the scheduled work. */	6105	/* Reference the objects for the scheduled work. */
6106	drm_gem_object_reference(&work->old_fb_obj->base);	6106	drm_gem_object_reference(&work->old_fb_obj->base);
6107	drm_gem_object_reference(&obj->base);	6107	drm_gem_object_reference(&obj->base);
6108		6108
6109	crtc->fb = fb;	6109	crtc->fb = fb;
6110		6110
6111	ret = drm_vblank_get(dev, intel_crtc->pipe);	6111	ret = drm_vblank_get(dev, intel_crtc->pipe);
6112	if (ret)	6112	if (ret)
6113	goto cleanup_objs;	6113	goto cleanup_objs;
6114		6114
6115	if (IS_GEN3(dev) \|\| IS_GEN2(dev)) {	6115	if (IS_GEN3(dev) \|\| IS_GEN2(dev)) {
6116	u32 flip_mask;	6116	u32 flip_mask;
6117		6117
6118	/* Can't queue multiple flips, so wait for the previous	6118	/* Can't queue multiple flips, so wait for the previous
6119	* one to finish before executing the next.	6119	* one to finish before executing the next.
6120	*/	6120	*/
6121	ret = BEGIN_LP_RING(2);	6121	ret = BEGIN_LP_RING(2);
6122	if (ret)	6122	if (ret)
6123	goto cleanup_objs;	6123	goto cleanup_objs;
6124		6124
6125	if (intel_crtc->plane)	6125	if (intel_crtc->plane)
6126	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;	6126	flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6127	else	6127	else
6128	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;	6128	flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6129	OUT_RING(MI_WAIT_FOR_EVENT \| flip_mask);	6129	OUT_RING(MI_WAIT_FOR_EVENT \| flip_mask);
6130	OUT_RING(MI_NOOP);	6130	OUT_RING(MI_NOOP);
6131	ADVANCE_LP_RING();	6131	ADVANCE_LP_RING();
6132	}	6132	}
6133		6133
6134	work->pending_flip_obj = obj;	6134	work->pending_flip_obj = obj;
6135		6135
6136	work->enable_stall_check = true;	6136	work->enable_stall_check = true;
6137		6137
6138	/* Offset into the new buffer for cases of shared fbs between CRTCs */	6138	/* Offset into the new buffer for cases of shared fbs between CRTCs */
6139	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;	6139	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6140		6140
6141	ret = BEGIN_LP_RING(4);	6141	ret = BEGIN_LP_RING(4);
6142	if (ret)	6142	if (ret)
6143	goto cleanup_objs;	6143	goto cleanup_objs;
6144		6144
6145	/* Block clients from rendering to the new back buffer until	6145	/* Block clients from rendering to the new back buffer until
6146	* the flip occurs and the object is no longer visible.	6146	* the flip occurs and the object is no longer visible.
6147	*/	6147	*/
6148	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);	6148	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6149		6149
6150	switch (INTEL_INFO(dev)->gen) {	6150	switch (INTEL_INFO(dev)->gen) {
6151	case 2:	6151	case 2:
6152	OUT_RING(MI_DISPLAY_FLIP \|	6152	OUT_RING(MI_DISPLAY_FLIP \|
6153	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));	6153	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6154	OUT_RING(fb->pitch);	6154	OUT_RING(fb->pitch);
6155	OUT_RING(obj->gtt_offset + offset);	6155	OUT_RING(obj->gtt_offset + offset);
6156	OUT_RING(MI_NOOP);	6156	OUT_RING(MI_NOOP);
6157	break;	6157	break;
6158		6158
6159	case 3:	6159	case 3:
6160	OUT_RING(MI_DISPLAY_FLIP_I915 \|	6160	OUT_RING(MI_DISPLAY_FLIP_I915 \|
6161	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));	6161	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6162	OUT_RING(fb->pitch);	6162	OUT_RING(fb->pitch);
6163	OUT_RING(obj->gtt_offset + offset);	6163	OUT_RING(obj->gtt_offset + offset);
6164	OUT_RING(MI_NOOP);	6164	OUT_RING(MI_NOOP);
6165	break;	6165	break;
6166		6166
6167	case 4:	6167	case 4:
6168	case 5:	6168	case 5:
6169	/* i965+ uses the linear or tiled offsets from the	6169	/* i965+ uses the linear or tiled offsets from the
6170	* Display Registers (which do not change across a page-flip)	6170	* Display Registers (which do not change across a page-flip)
6171	* so we need only reprogram the base address.	6171	* so we need only reprogram the base address.
6172	*/	6172	*/
6173	OUT_RING(MI_DISPLAY_FLIP \|	6173	OUT_RING(MI_DISPLAY_FLIP \|
6174	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));	6174	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6175	OUT_RING(fb->pitch);	6175	OUT_RING(fb->pitch);
6176	OUT_RING(obj->gtt_offset \| obj->tiling_mode);	6176	OUT_RING(obj->gtt_offset \| obj->tiling_mode);
6177		6177
6178	/* XXX Enabling the panel-fitter across page-flip is so far	6178	/* XXX Enabling the panel-fitter across page-flip is so far
6179	* untested on non-native modes, so ignore it for now.	6179	* untested on non-native modes, so ignore it for now.
6180	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;	6180	* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6181	*/	6181	*/
6182	pf = 0;	6182	pf = 0;
6183	pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;	6183	pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6184	OUT_RING(pf \| pipesrc);	6184	OUT_RING(pf \| pipesrc);
6185	break;	6185	break;
6186		6186
6187	case 6:	6187	case 6:
6188	OUT_RING(MI_DISPLAY_FLIP \|	6188	OUT_RING(MI_DISPLAY_FLIP \|
6189	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));	6189	MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6190	OUT_RING(fb->pitch \| obj->tiling_mode);	6190	OUT_RING(fb->pitch \| obj->tiling_mode);
6191	OUT_RING(obj->gtt_offset);	6191	OUT_RING(obj->gtt_offset);
6192		6192
6193	pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;	6193	pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6194	pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;	6194	pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6195	OUT_RING(pf \| pipesrc);	6195	OUT_RING(pf \| pipesrc);
6196	break;	6196	break;
6197	}	6197	}
6198	ADVANCE_LP_RING();	6198	ADVANCE_LP_RING();
6199		6199
6200	mutex_unlock(&dev->struct_mutex);	6200	mutex_unlock(&dev->struct_mutex);
6201		6201
6202	trace_i915_flip_request(intel_crtc->plane, obj);	6202	trace_i915_flip_request(intel_crtc->plane, obj);
6203		6203
6204	return 0;	6204	return 0;
6205		6205
6206	cleanup_objs:	6206	cleanup_objs:
6207	drm_gem_object_unreference(&work->old_fb_obj->base);	6207	drm_gem_object_unreference(&work->old_fb_obj->base);
6208	drm_gem_object_unreference(&obj->base);	6208	drm_gem_object_unreference(&obj->base);
6209	cleanup_work:	6209	cleanup_work:
6210	mutex_unlock(&dev->struct_mutex);	6210	mutex_unlock(&dev->struct_mutex);
6211		6211
6212	spin_lock_irqsave(&dev->event_lock, flags);	6212	spin_lock_irqsave(&dev->event_lock, flags);
6213	intel_crtc->unpin_work = NULL;	6213	intel_crtc->unpin_work = NULL;
6214	spin_unlock_irqrestore(&dev->event_lock, flags);	6214	spin_unlock_irqrestore(&dev->event_lock, flags);
6215		6215
6216	kfree(work);	6216	kfree(work);
6217		6217
6218	return ret;	6218	return ret;
6219	}	6219	}
6220		6220
6221	static void intel_sanitize_modesetting(struct drm_device *dev,	6221	static void intel_sanitize_modesetting(struct drm_device *dev,
6222	int pipe, int plane)	6222	int pipe, int plane)
6223	{	6223	{
6224	struct drm_i915_private *dev_priv = dev->dev_private;	6224	struct drm_i915_private *dev_priv = dev->dev_private;
6225	u32 reg, val;	6225	u32 reg, val;
6226		6226
6227	if (HAS_PCH_SPLIT(dev))	6227	if (HAS_PCH_SPLIT(dev))
6228	return;	6228	return;
6229		6229
6230	/* Who knows what state these registers were left in by the BIOS or	6230	/* Who knows what state these registers were left in by the BIOS or
6231	* grub?	6231	* grub?
6232	*	6232	*
6233	* If we leave the registers in a conflicting state (e.g. with the	6233	* If we leave the registers in a conflicting state (e.g. with the
6234	* display plane reading from the other pipe than the one we intend	6234	* display plane reading from the other pipe than the one we intend
6235	* to use) then when we attempt to teardown the active mode, we will	6235	* to use) then when we attempt to teardown the active mode, we will
6236	* not disable the pipes and planes in the correct order -- leaving	6236	* not disable the pipes and planes in the correct order -- leaving
6237	* a plane reading from a disabled pipe and possibly leading to	6237	* a plane reading from a disabled pipe and possibly leading to
6238	* undefined behaviour.	6238	* undefined behaviour.
6239	*/	6239	*/
6240		6240
6241	reg = DSPCNTR(plane);	6241	reg = DSPCNTR(plane);
6242	val = I915_READ(reg);	6242	val = I915_READ(reg);
6243		6243
6244	if ((val & DISPLAY_PLANE_ENABLE) == 0)	6244	if ((val & DISPLAY_PLANE_ENABLE) == 0)
6245	return;	6245	return;
6246	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)	6246	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6247	return;	6247	return;
6248		6248
6249	/* This display plane is active and attached to the other CPU pipe. */	6249	/* This display plane is active and attached to the other CPU pipe. */
6250	pipe = !pipe;	6250	pipe = !pipe;
6251		6251
6252	/* Disable the plane and wait for it to stop reading from the pipe. */	6252	/* Disable the plane and wait for it to stop reading from the pipe. */
6253	intel_disable_plane(dev_priv, plane, pipe);	6253	intel_disable_plane(dev_priv, plane, pipe);
6254	intel_disable_pipe(dev_priv, pipe);	6254	intel_disable_pipe(dev_priv, pipe);
6255	}	6255	}
6256		6256
6257	static void intel_crtc_reset(struct drm_crtc *crtc)	6257	static void intel_crtc_reset(struct drm_crtc *crtc)
6258	{	6258	{
6259	struct drm_device *dev = crtc->dev;	6259	struct drm_device *dev = crtc->dev;
6260	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	6260	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6261		6261
6262	/* Reset flags back to the 'unknown' status so that they	6262	/* Reset flags back to the 'unknown' status so that they
6263	* will be correctly set on the initial modeset.	6263	* will be correctly set on the initial modeset.
6264	*/	6264	*/
6265	intel_crtc->dpms_mode = -1;	6265	intel_crtc->dpms_mode = -1;
6266		6266
6267	/* We need to fix up any BIOS configuration that conflicts with	6267	/* We need to fix up any BIOS configuration that conflicts with
6268	* our expectations.	6268	* our expectations.
6269	*/	6269	*/
6270	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);	6270	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6271	}	6271	}
6272		6272
6273	static struct drm_crtc_helper_funcs intel_helper_funcs = {	6273	static struct drm_crtc_helper_funcs intel_helper_funcs = {
6274	.dpms = intel_crtc_dpms,	6274	.dpms = intel_crtc_dpms,
6275	.mode_fixup = intel_crtc_mode_fixup,	6275	.mode_fixup = intel_crtc_mode_fixup,
6276	.mode_set = intel_crtc_mode_set,	6276	.mode_set = intel_crtc_mode_set,
6277	.mode_set_base = intel_pipe_set_base,	6277	.mode_set_base = intel_pipe_set_base,
6278	.mode_set_base_atomic = intel_pipe_set_base_atomic,	6278	.mode_set_base_atomic = intel_pipe_set_base_atomic,
6279	.load_lut = intel_crtc_load_lut,	6279	.load_lut = intel_crtc_load_lut,
6280	.disable = intel_crtc_disable,	6280	.disable = intel_crtc_disable,
6281	};	6281	};
6282		6282
6283	static const struct drm_crtc_funcs intel_crtc_funcs = {	6283	static const struct drm_crtc_funcs intel_crtc_funcs = {
6284	.reset = intel_crtc_reset,	6284	.reset = intel_crtc_reset,
6285	.cursor_set = intel_crtc_cursor_set,	6285	.cursor_set = intel_crtc_cursor_set,
6286	.cursor_move = intel_crtc_cursor_move,	6286	.cursor_move = intel_crtc_cursor_move,
6287	.gamma_set = intel_crtc_gamma_set,	6287	.gamma_set = intel_crtc_gamma_set,
6288	.set_config = drm_crtc_helper_set_config,	6288	.set_config = drm_crtc_helper_set_config,
6289	.destroy = intel_crtc_destroy,	6289	.destroy = intel_crtc_destroy,
6290	.page_flip = intel_crtc_page_flip,	6290	.page_flip = intel_crtc_page_flip,
6291	};	6291	};
6292		6292
6293	static void intel_crtc_init(struct drm_device *dev, int pipe)	6293	static void intel_crtc_init(struct drm_device *dev, int pipe)
6294	{	6294	{
6295	drm_i915_private_t *dev_priv = dev->dev_private;	6295	drm_i915_private_t *dev_priv = dev->dev_private;
6296	struct intel_crtc *intel_crtc;	6296	struct intel_crtc *intel_crtc;
6297	int i;	6297	int i;
6298		6298
6299	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);	6299	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6300	if (intel_crtc == NULL)	6300	if (intel_crtc == NULL)
6301	return;	6301	return;
6302		6302
6303	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);	6303	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6304		6304
6305	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);	6305	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6306	for (i = 0; i < 256; i++) {	6306	for (i = 0; i < 256; i++) {
6307	intel_crtc->lut_r[i] = i;	6307	intel_crtc->lut_r[i] = i;
6308	intel_crtc->lut_g[i] = i;	6308	intel_crtc->lut_g[i] = i;
6309	intel_crtc->lut_b[i] = i;	6309	intel_crtc->lut_b[i] = i;
6310	}	6310	}
6311		6311
6312	/* Swap pipes & planes for FBC on pre-965 */	6312	/* Swap pipes & planes for FBC on pre-965 */
6313	intel_crtc->pipe = pipe;	6313	intel_crtc->pipe = pipe;
6314	intel_crtc->plane = pipe;	6314	intel_crtc->plane = pipe;
6315	if (IS_MOBILE(dev) && IS_GEN3(dev)) {	6315	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6316	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");	6316	DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6317	intel_crtc->plane = !pipe;	6317	intel_crtc->plane = !pipe;
6318	}	6318	}
6319		6319
6320	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|	6320	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) \|\|
6321	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);	6321	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6322	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;	6322	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6323	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;	6323	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6324		6324
6325	intel_crtc_reset(&intel_crtc->base);	6325	intel_crtc_reset(&intel_crtc->base);
6326	intel_crtc->active = true; /* force the pipe off on setup_init_config */	6326	intel_crtc->active = true; /* force the pipe off on setup_init_config */
6327		6327
6328	if (HAS_PCH_SPLIT(dev)) {	6328	if (HAS_PCH_SPLIT(dev)) {
6329	intel_helper_funcs.prepare = ironlake_crtc_prepare;	6329	intel_helper_funcs.prepare = ironlake_crtc_prepare;
6330	intel_helper_funcs.commit = ironlake_crtc_commit;	6330	intel_helper_funcs.commit = ironlake_crtc_commit;
6331	} else {	6331	} else {
6332	intel_helper_funcs.prepare = i9xx_crtc_prepare;	6332	intel_helper_funcs.prepare = i9xx_crtc_prepare;
6333	intel_helper_funcs.commit = i9xx_crtc_commit;	6333	intel_helper_funcs.commit = i9xx_crtc_commit;
6334	}	6334	}
6335		6335
6336	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);	6336	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6337		6337
6338	intel_crtc->busy = false;	6338	intel_crtc->busy = false;
6339		6339
6340	setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,	6340	setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6341	(unsigned long)intel_crtc);	6341	(unsigned long)intel_crtc);
6342	}	6342	}
6343		6343
6344	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,	6344	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
6345	struct drm_file *file)	6345	struct drm_file *file)
6346	{	6346	{
6347	drm_i915_private_t *dev_priv = dev->dev_private;	6347	drm_i915_private_t *dev_priv = dev->dev_private;
6348	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;	6348	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6349	struct drm_mode_object *drmmode_obj;	6349	struct drm_mode_object *drmmode_obj;
6350	struct intel_crtc *crtc;	6350	struct intel_crtc *crtc;
6351		6351
6352	if (!dev_priv) {	6352	if (!dev_priv) {
6353	DRM_ERROR("called with no initialization\n");	6353	DRM_ERROR("called with no initialization\n");
6354	return -EINVAL;	6354	return -EINVAL;
6355	}	6355	}
6356		6356
6357	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,	6357	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6358	DRM_MODE_OBJECT_CRTC);	6358	DRM_MODE_OBJECT_CRTC);
6359		6359
6360	if (!drmmode_obj) {	6360	if (!drmmode_obj) {
6361	DRM_ERROR("no such CRTC id\n");	6361	DRM_ERROR("no such CRTC id\n");
6362	return -EINVAL;	6362	return -EINVAL;
6363	}	6363	}
6364		6364
6365	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));	6365	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6366	pipe_from_crtc_id->pipe = crtc->pipe;	6366	pipe_from_crtc_id->pipe = crtc->pipe;
6367		6367
6368	return 0;	6368	return 0;
6369	}	6369	}
6370		6370
6371	static int intel_encoder_clones(struct drm_device *dev, int type_mask)	6371	static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6372	{	6372	{
6373	struct intel_encoder *encoder;	6373	struct intel_encoder *encoder;
6374	int index_mask = 0;	6374	int index_mask = 0;
6375	int entry = 0;	6375	int entry = 0;
6376		6376
6377	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {	6377	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6378	if (type_mask & encoder->clone_mask)	6378	if (type_mask & encoder->clone_mask)
6379	index_mask \|= (1 << entry);	6379	index_mask \|= (1 << entry);
6380	entry++;	6380	entry++;
6381	}	6381	}
6382		6382
6383	return index_mask;	6383	return index_mask;
6384	}	6384	}
6385		6385
6386	static bool has_edp_a(struct drm_device *dev)	6386	static bool has_edp_a(struct drm_device *dev)
6387	{	6387	{
6388	struct drm_i915_private *dev_priv = dev->dev_private;	6388	struct drm_i915_private *dev_priv = dev->dev_private;
6389		6389
6390	if (!IS_MOBILE(dev))	6390	if (!IS_MOBILE(dev))
6391	return false;	6391	return false;
6392		6392
6393	if ((I915_READ(DP_A) & DP_DETECTED) == 0)	6393	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6394	return false;	6394	return false;
6395		6395
6396	if (IS_GEN5(dev) &&	6396	if (IS_GEN5(dev) &&
6397	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))	6397	(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6398	return false;	6398	return false;
6399		6399
6400	return true;	6400	return true;
6401	}	6401	}
6402		6402
6403	static void intel_setup_outputs(struct drm_device *dev)	6403	static void intel_setup_outputs(struct drm_device *dev)
6404	{	6404	{
6405	struct drm_i915_private *dev_priv = dev->dev_private;	6405	struct drm_i915_private *dev_priv = dev->dev_private;
6406	struct intel_encoder *encoder;	6406	struct intel_encoder *encoder;
6407	bool dpd_is_edp = false;	6407	bool dpd_is_edp = false;
6408	bool has_lvds = false;	6408	bool has_lvds = false;
6409		6409
6410	if (IS_MOBILE(dev) && !IS_I830(dev))	6410	if (IS_MOBILE(dev) && !IS_I830(dev))
6411	has_lvds = intel_lvds_init(dev);	6411	has_lvds = intel_lvds_init(dev);
6412	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {	6412	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6413	/* disable the panel fitter on everything but LVDS */	6413	/* disable the panel fitter on everything but LVDS */
6414	I915_WRITE(PFIT_CONTROL, 0);	6414	I915_WRITE(PFIT_CONTROL, 0);
6415	}	6415	}
6416		6416
6417	if (HAS_PCH_SPLIT(dev)) {	6417	if (HAS_PCH_SPLIT(dev)) {
6418	dpd_is_edp = intel_dpd_is_edp(dev);	6418	dpd_is_edp = intel_dpd_is_edp(dev);
6419		6419
6420	if (has_edp_a(dev))	6420	if (has_edp_a(dev))
6421	intel_dp_init(dev, DP_A);	6421	intel_dp_init(dev, DP_A);
6422		6422
6423	if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))	6423	if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6424	intel_dp_init(dev, PCH_DP_D);	6424	intel_dp_init(dev, PCH_DP_D);
6425	}	6425	}
6426		6426
6427	intel_crt_init(dev);	6427	intel_crt_init(dev);
6428		6428
6429	if (HAS_PCH_SPLIT(dev)) {	6429	if (HAS_PCH_SPLIT(dev)) {
6430	int found;	6430	int found;
6431		6431
6432	if (I915_READ(HDMIB) & PORT_DETECTED) {	6432	if (I915_READ(HDMIB) & PORT_DETECTED) {
6433	/* PCH SDVOB multiplex with HDMIB */	6433	/* PCH SDVOB multiplex with HDMIB */
6434	found = intel_sdvo_init(dev, PCH_SDVOB);	6434	found = intel_sdvo_init(dev, PCH_SDVOB);
6435	if (!found)	6435	if (!found)
6436	intel_hdmi_init(dev, HDMIB);	6436	intel_hdmi_init(dev, HDMIB);
6437	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))	6437	if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6438	intel_dp_init(dev, PCH_DP_B);	6438	intel_dp_init(dev, PCH_DP_B);
6439	}	6439	}
6440		6440
6441	if (I915_READ(HDMIC) & PORT_DETECTED)	6441	if (I915_READ(HDMIC) & PORT_DETECTED)
6442	intel_hdmi_init(dev, HDMIC);	6442	intel_hdmi_init(dev, HDMIC);
6443		6443
6444	if (I915_READ(HDMID) & PORT_DETECTED)	6444	if (I915_READ(HDMID) & PORT_DETECTED)
6445	intel_hdmi_init(dev, HDMID);	6445	intel_hdmi_init(dev, HDMID);
6446		6446
6447	if (I915_READ(PCH_DP_C) & DP_DETECTED)	6447	if (I915_READ(PCH_DP_C) & DP_DETECTED)
6448	intel_dp_init(dev, PCH_DP_C);	6448	intel_dp_init(dev, PCH_DP_C);
6449		6449
6450	if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))	6450	if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6451	intel_dp_init(dev, PCH_DP_D);	6451	intel_dp_init(dev, PCH_DP_D);
6452		6452
6453	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {	6453	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6454	bool found = false;	6454	bool found = false;
6455		6455
6456	if (I915_READ(SDVOB) & SDVO_DETECTED) {	6456	if (I915_READ(SDVOB) & SDVO_DETECTED) {
6457	DRM_DEBUG_KMS("probing SDVOB\n");	6457	DRM_DEBUG_KMS("probing SDVOB\n");
6458	found = intel_sdvo_init(dev, SDVOB);	6458	found = intel_sdvo_init(dev, SDVOB);
6459	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {	6459	if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6460	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");	6460	DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6461	intel_hdmi_init(dev, SDVOB);	6461	intel_hdmi_init(dev, SDVOB);
6462	}	6462	}
6463		6463
6464	if (!found && SUPPORTS_INTEGRATED_DP(dev)) {	6464	if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6465	DRM_DEBUG_KMS("probing DP_B\n");	6465	DRM_DEBUG_KMS("probing DP_B\n");
6466	intel_dp_init(dev, DP_B);	6466	intel_dp_init(dev, DP_B);
6467	}	6467	}
6468	}	6468	}
6469		6469
6470	/* Before G4X SDVOC doesn't have its own detect register */	6470	/* Before G4X SDVOC doesn't have its own detect register */
6471		6471
6472	if (I915_READ(SDVOB) & SDVO_DETECTED) {	6472	if (I915_READ(SDVOB) & SDVO_DETECTED) {
6473	DRM_DEBUG_KMS("probing SDVOC\n");	6473	DRM_DEBUG_KMS("probing SDVOC\n");
6474	found = intel_sdvo_init(dev, SDVOC);	6474	found = intel_sdvo_init(dev, SDVOC);
6475	}	6475	}
6476		6476
6477	if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {	6477	if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6478		6478
6479	if (SUPPORTS_INTEGRATED_HDMI(dev)) {	6479	if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6480	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");	6480	DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6481	intel_hdmi_init(dev, SDVOC);	6481	intel_hdmi_init(dev, SDVOC);
6482	}	6482	}
6483	if (SUPPORTS_INTEGRATED_DP(dev)) {	6483	if (SUPPORTS_INTEGRATED_DP(dev)) {
6484	DRM_DEBUG_KMS("probing DP_C\n");	6484	DRM_DEBUG_KMS("probing DP_C\n");
6485	intel_dp_init(dev, DP_C);	6485	intel_dp_init(dev, DP_C);
6486	}	6486	}
6487	}	6487	}
6488		6488
6489	if (SUPPORTS_INTEGRATED_DP(dev) &&	6489	if (SUPPORTS_INTEGRATED_DP(dev) &&
6490	(I915_READ(DP_D) & DP_DETECTED)) {	6490	(I915_READ(DP_D) & DP_DETECTED)) {
6491	DRM_DEBUG_KMS("probing DP_D\n");	6491	DRM_DEBUG_KMS("probing DP_D\n");
6492	intel_dp_init(dev, DP_D);	6492	intel_dp_init(dev, DP_D);
6493	}	6493	}
6494	} else if (IS_GEN2(dev))	6494	} else if (IS_GEN2(dev))
6495	intel_dvo_init(dev);	6495	intel_dvo_init(dev);
6496		6496
6497	if (SUPPORTS_TV(dev))	6497	if (SUPPORTS_TV(dev))
6498	intel_tv_init(dev);	6498	intel_tv_init(dev);
6499		6499
6500	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {	6500	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6501	encoder->base.possible_crtcs = encoder->crtc_mask;	6501	encoder->base.possible_crtcs = encoder->crtc_mask;
6502	encoder->base.possible_clones =	6502	encoder->base.possible_clones =
6503	intel_encoder_clones(dev, encoder->clone_mask);	6503	intel_encoder_clones(dev, encoder->clone_mask);
6504	}	6504	}
6505		6505
6506	intel_panel_setup_backlight(dev);	6506	intel_panel_setup_backlight(dev);
6507	}	6507	}
6508		6508
6509	static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)	6509	static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6510	{	6510	{
6511	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);	6511	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6512		6512
6513	drm_framebuffer_cleanup(fb);	6513	drm_framebuffer_cleanup(fb);
6514	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);	6514	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6515		6515
6516	kfree(intel_fb);	6516	kfree(intel_fb);
6517	}	6517	}
6518		6518
6519	static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,	6519	static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6520	struct drm_file *file,	6520	struct drm_file *file,
6521	unsigned int *handle)	6521	unsigned int *handle)
6522	{	6522	{
6523	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);	6523	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6524	struct drm_i915_gem_object *obj = intel_fb->obj;	6524	struct drm_i915_gem_object *obj = intel_fb->obj;
6525		6525
6526	return drm_gem_handle_create(file, &obj->base, handle);	6526	return drm_gem_handle_create(file, &obj->base, handle);
6527	}	6527	}
6528		6528
6529	static const struct drm_framebuffer_funcs intel_fb_funcs = {	6529	static const struct drm_framebuffer_funcs intel_fb_funcs = {
6530	.destroy = intel_user_framebuffer_destroy,	6530	.destroy = intel_user_framebuffer_destroy,
6531	.create_handle = intel_user_framebuffer_create_handle,	6531	.create_handle = intel_user_framebuffer_create_handle,
6532	};	6532	};
6533		6533
6534	int intel_framebuffer_init(struct drm_device *dev,	6534	int intel_framebuffer_init(struct drm_device *dev,
6535	struct intel_framebuffer *intel_fb,	6535	struct intel_framebuffer *intel_fb,
6536	struct drm_mode_fb_cmd *mode_cmd,	6536	struct drm_mode_fb_cmd *mode_cmd,
6537	struct drm_i915_gem_object *obj)	6537	struct drm_i915_gem_object *obj)
6538	{	6538	{
6539	int ret;	6539	int ret;
6540		6540
6541	if (obj->tiling_mode == I915_TILING_Y)	6541	if (obj->tiling_mode == I915_TILING_Y)
6542	return -EINVAL;	6542	return -EINVAL;
6543		6543
6544	if (mode_cmd->pitch & 63)	6544	if (mode_cmd->pitch & 63)
6545	return -EINVAL;	6545	return -EINVAL;
6546		6546
6547	switch (mode_cmd->bpp) {	6547	switch (mode_cmd->bpp) {
6548	case 8:	6548	case 8:
6549	case 16:	6549	case 16:
6550	case 24:	6550	case 24:
6551	case 32:	6551	case 32:
6552	break;	6552	break;
6553	default:	6553	default:
6554	return -EINVAL;	6554	return -EINVAL;
6555	}	6555	}
6556		6556
6557	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);	6557	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6558	if (ret) {	6558	if (ret) {
6559	DRM_ERROR("framebuffer init failed %d\n", ret);	6559	DRM_ERROR("framebuffer init failed %d\n", ret);
6560	return ret;	6560	return ret;
6561	}	6561	}
6562		6562
6563	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);	6563	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6564	intel_fb->obj = obj;	6564	intel_fb->obj = obj;
6565	return 0;	6565	return 0;
6566	}	6566	}
6567		6567
6568	static struct drm_framebuffer *	6568	static struct drm_framebuffer *
6569	intel_user_framebuffer_create(struct drm_device *dev,	6569	intel_user_framebuffer_create(struct drm_device *dev,
6570	struct drm_file *filp,	6570	struct drm_file *filp,
6571	struct drm_mode_fb_cmd *mode_cmd)	6571	struct drm_mode_fb_cmd *mode_cmd)
6572	{	6572	{
6573	struct drm_i915_gem_object *obj;	6573	struct drm_i915_gem_object *obj;
6574	struct intel_framebuffer *intel_fb;	6574	struct intel_framebuffer *intel_fb;
6575	int ret;	6575	int ret;
6576		6576
6577	obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));	6577	obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6578	if (&obj->base == NULL)	6578	if (&obj->base == NULL)
6579	return ERR_PTR(-ENOENT);	6579	return ERR_PTR(-ENOENT);
6580		6580
6581	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);	6581	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6582	if (!intel_fb)	6582	if (!intel_fb)
6583	return ERR_PTR(-ENOMEM);	6583	return ERR_PTR(-ENOMEM);
6584		6584
6585	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);	6585	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6586	if (ret) {	6586	if (ret) {
6587	drm_gem_object_unreference_unlocked(&obj->base);	6587	drm_gem_object_unreference_unlocked(&obj->base);
6588	kfree(intel_fb);	6588	kfree(intel_fb);
6589	return ERR_PTR(ret);	6589	return ERR_PTR(ret);
6590	}	6590	}
6591		6591
6592	return &intel_fb->base;	6592	return &intel_fb->base;
6593	}	6593	}
6594		6594
6595	static const struct drm_mode_config_funcs intel_mode_funcs = {	6595	static const struct drm_mode_config_funcs intel_mode_funcs = {
6596	.fb_create = intel_user_framebuffer_create,	6596	.fb_create = intel_user_framebuffer_create,
6597	.output_poll_changed = intel_fb_output_poll_changed,	6597	.output_poll_changed = intel_fb_output_poll_changed,
6598	};	6598	};
6599		6599
6600	static struct drm_i915_gem_object *	6600	static struct drm_i915_gem_object *
6601	intel_alloc_context_page(struct drm_device *dev)	6601	intel_alloc_context_page(struct drm_device *dev)
6602	{	6602	{
6603	struct drm_i915_gem_object *ctx;	6603	struct drm_i915_gem_object *ctx;
6604	int ret;	6604	int ret;
6605		6605
6606	ctx = i915_gem_alloc_object(dev, 4096);	6606	ctx = i915_gem_alloc_object(dev, 4096);
6607	if (!ctx) {	6607	if (!ctx) {
6608	DRM_DEBUG("failed to alloc power context, RC6 disabled\n");	6608	DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6609	return NULL;	6609	return NULL;
6610	}	6610	}
6611		6611
6612	mutex_lock(&dev->struct_mutex);	6612	mutex_lock(&dev->struct_mutex);
6613	ret = i915_gem_object_pin(ctx, 4096, true);	6613	ret = i915_gem_object_pin(ctx, 4096, true);
6614	if (ret) {	6614	if (ret) {
6615	DRM_ERROR("failed to pin power context: %d\n", ret);	6615	DRM_ERROR("failed to pin power context: %d\n", ret);
6616	goto err_unref;	6616	goto err_unref;
6617	}	6617	}
6618		6618
6619	ret = i915_gem_object_set_to_gtt_domain(ctx, 1);	6619	ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6620	if (ret) {	6620	if (ret) {
6621	DRM_ERROR("failed to set-domain on power context: %d\n", ret);	6621	DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6622	goto err_unpin;	6622	goto err_unpin;
6623	}	6623	}
6624	mutex_unlock(&dev->struct_mutex);	6624	mutex_unlock(&dev->struct_mutex);
6625		6625
6626	return ctx;	6626	return ctx;
6627		6627
6628	err_unpin:	6628	err_unpin:
6629	i915_gem_object_unpin(ctx);	6629	i915_gem_object_unpin(ctx);
6630	err_unref:	6630	err_unref:
6631	drm_gem_object_unreference(&ctx->base);	6631	drm_gem_object_unreference(&ctx->base);
6632	mutex_unlock(&dev->struct_mutex);	6632	mutex_unlock(&dev->struct_mutex);
6633	return NULL;	6633	return NULL;
6634	}	6634	}
6635		6635
6636	bool ironlake_set_drps(struct drm_device *dev, u8 val)	6636	bool ironlake_set_drps(struct drm_device *dev, u8 val)
6637	{	6637	{
6638	struct drm_i915_private *dev_priv = dev->dev_private;	6638	struct drm_i915_private *dev_priv = dev->dev_private;
6639	u16 rgvswctl;	6639	u16 rgvswctl;
6640		6640
6641	rgvswctl = I915_READ16(MEMSWCTL);	6641	rgvswctl = I915_READ16(MEMSWCTL);
6642	if (rgvswctl & MEMCTL_CMD_STS) {	6642	if (rgvswctl & MEMCTL_CMD_STS) {
6643	DRM_DEBUG("gpu busy, RCS change rejected\n");	6643	DRM_DEBUG("gpu busy, RCS change rejected\n");
6644	return false; /* still busy with another command */	6644	return false; /* still busy with another command */
6645	}	6645	}
6646		6646
6647	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) \|	6647	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) \|
6648	(val << MEMCTL_FREQ_SHIFT) \| MEMCTL_SFCAVM;	6648	(val << MEMCTL_FREQ_SHIFT) \| MEMCTL_SFCAVM;
6649	I915_WRITE16(MEMSWCTL, rgvswctl);	6649	I915_WRITE16(MEMSWCTL, rgvswctl);
6650	POSTING_READ16(MEMSWCTL);	6650	POSTING_READ16(MEMSWCTL);
6651		6651
6652	rgvswctl \|= MEMCTL_CMD_STS;	6652	rgvswctl \|= MEMCTL_CMD_STS;
6653	I915_WRITE16(MEMSWCTL, rgvswctl);	6653	I915_WRITE16(MEMSWCTL, rgvswctl);
6654		6654
6655	return true;	6655	return true;
6656	}	6656	}
6657		6657
6658	void ironlake_enable_drps(struct drm_device *dev)	6658	void ironlake_enable_drps(struct drm_device *dev)
6659	{	6659	{
6660	struct drm_i915_private *dev_priv = dev->dev_private;	6660	struct drm_i915_private *dev_priv = dev->dev_private;
6661	u32 rgvmodectl = I915_READ(MEMMODECTL);	6661	u32 rgvmodectl = I915_READ(MEMMODECTL);
6662	u8 fmax, fmin, fstart, vstart;	6662	u8 fmax, fmin, fstart, vstart;
6663		6663
6664	/* Enable temp reporting */	6664	/* Enable temp reporting */
6665	I915_WRITE16(PMMISC, I915_READ(PMMISC) \| MCPPCE_EN);	6665	I915_WRITE16(PMMISC, I915_READ(PMMISC) \| MCPPCE_EN);
6666	I915_WRITE16(TSC1, I915_READ(TSC1) \| TSE);	6666	I915_WRITE16(TSC1, I915_READ(TSC1) \| TSE);
6667		6667
6668	/* 100ms RC evaluation intervals */	6668	/* 100ms RC evaluation intervals */
6669	I915_WRITE(RCUPEI, 100000);	6669	I915_WRITE(RCUPEI, 100000);
6670	I915_WRITE(RCDNEI, 100000);	6670	I915_WRITE(RCDNEI, 100000);
6671		6671
6672	/* Set max/min thresholds to 90ms and 80ms respectively */	6672	/* Set max/min thresholds to 90ms and 80ms respectively */
6673	I915_WRITE(RCBMAXAVG, 90000);	6673	I915_WRITE(RCBMAXAVG, 90000);
6674	I915_WRITE(RCBMINAVG, 80000);	6674	I915_WRITE(RCBMINAVG, 80000);
6675		6675
6676	I915_WRITE(MEMIHYST, 1);	6676	I915_WRITE(MEMIHYST, 1);
6677		6677
6678	/* Set up min, max, and cur for interrupt handling */	6678	/* Set up min, max, and cur for interrupt handling */
6679	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;	6679	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6680	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);	6680	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6681	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>	6681	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6682	MEMMODE_FSTART_SHIFT;	6682	MEMMODE_FSTART_SHIFT;
6683		6683
6684	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>	6684	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6685	PXVFREQ_PX_SHIFT;	6685	PXVFREQ_PX_SHIFT;
6686		6686
6687	dev_priv->fmax = fmax; /* IPS callback will increase this */	6687	dev_priv->fmax = fmax; /* IPS callback will increase this */
6688	dev_priv->fstart = fstart;	6688	dev_priv->fstart = fstart;
6689		6689
6690	dev_priv->max_delay = fstart;	6690	dev_priv->max_delay = fstart;
6691	dev_priv->min_delay = fmin;	6691	dev_priv->min_delay = fmin;
6692	dev_priv->cur_delay = fstart;	6692	dev_priv->cur_delay = fstart;
6693		6693
6694	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",	6694	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6695	fmax, fmin, fstart);	6695	fmax, fmin, fstart);
6696		6696
6697	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN \| MEMINT_EVAL_CHG_EN);	6697	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN \| MEMINT_EVAL_CHG_EN);
6698		6698
6699	/*	6699	/*
6700	* Interrupts will be enabled in ironlake_irq_postinstall	6700	* Interrupts will be enabled in ironlake_irq_postinstall
6701	*/	6701	*/
6702		6702
6703	I915_WRITE(VIDSTART, vstart);	6703	I915_WRITE(VIDSTART, vstart);
6704	POSTING_READ(VIDSTART);	6704	POSTING_READ(VIDSTART);
6705		6705
6706	rgvmodectl \|= MEMMODE_SWMODE_EN;	6706	rgvmodectl \|= MEMMODE_SWMODE_EN;
6707	I915_WRITE(MEMMODECTL, rgvmodectl);	6707	I915_WRITE(MEMMODECTL, rgvmodectl);
6708		6708
6709	if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))	6709	if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6710	DRM_ERROR("stuck trying to change perf mode\n");	6710	DRM_ERROR("stuck trying to change perf mode\n");
6711	msleep(1);	6711	msleep(1);
6712		6712
6713	ironlake_set_drps(dev, fstart);	6713	ironlake_set_drps(dev, fstart);
6714		6714
6715	dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +	6715	dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6716	I915_READ(0x112e0);	6716	I915_READ(0x112e0);
6717	dev_priv->last_time1 = jiffies_to_msecs(jiffies);	6717	dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6718	dev_priv->last_count2 = I915_READ(0x112f4);	6718	dev_priv->last_count2 = I915_READ(0x112f4);
6719	getrawmonotonic(&dev_priv->last_time2);	6719	getrawmonotonic(&dev_priv->last_time2);
6720	}	6720	}
6721		6721
6722	void ironlake_disable_drps(struct drm_device *dev)	6722	void ironlake_disable_drps(struct drm_device *dev)
6723	{	6723	{
6724	struct drm_i915_private *dev_priv = dev->dev_private;	6724	struct drm_i915_private *dev_priv = dev->dev_private;
6725	u16 rgvswctl = I915_READ16(MEMSWCTL);	6725	u16 rgvswctl = I915_READ16(MEMSWCTL);
6726		6726
6727	/* Ack interrupts, disable EFC interrupt */	6727	/* Ack interrupts, disable EFC interrupt */
6728	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);	6728	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6729	I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);	6729	I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6730	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);	6730	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6731	I915_WRITE(DEIIR, DE_PCU_EVENT);	6731	I915_WRITE(DEIIR, DE_PCU_EVENT);
6732	I915_WRITE(DEIMR, I915_READ(DEIMR) \| DE_PCU_EVENT);	6732	I915_WRITE(DEIMR, I915_READ(DEIMR) \| DE_PCU_EVENT);
6733		6733
6734	/* Go back to the starting frequency */	6734	/* Go back to the starting frequency */
6735	ironlake_set_drps(dev, dev_priv->fstart);	6735	ironlake_set_drps(dev, dev_priv->fstart);
6736	msleep(1);	6736	msleep(1);
6737	rgvswctl \|= MEMCTL_CMD_STS;	6737	rgvswctl \|= MEMCTL_CMD_STS;
6738	I915_WRITE(MEMSWCTL, rgvswctl);	6738	I915_WRITE(MEMSWCTL, rgvswctl);
6739	msleep(1);	6739	msleep(1);
6740		6740
6741	}	6741	}
6742		6742
6743	void gen6_set_rps(struct drm_device *dev, u8 val)	6743	void gen6_set_rps(struct drm_device *dev, u8 val)
6744	{	6744	{
6745	struct drm_i915_private *dev_priv = dev->dev_private;	6745	struct drm_i915_private *dev_priv = dev->dev_private;
6746	u32 swreq;	6746	u32 swreq;
6747		6747
6748	swreq = (val & 0x3ff) << 25;	6748	swreq = (val & 0x3ff) << 25;
6749	I915_WRITE(GEN6_RPNSWREQ, swreq);	6749	I915_WRITE(GEN6_RPNSWREQ, swreq);
6750	}	6750	}
6751		6751
6752	void gen6_disable_rps(struct drm_device *dev)	6752	void gen6_disable_rps(struct drm_device *dev)
6753	{	6753	{
6754	struct drm_i915_private *dev_priv = dev->dev_private;	6754	struct drm_i915_private *dev_priv = dev->dev_private;
6755		6755
6756	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);	6756	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6757	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);	6757	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6758	I915_WRITE(GEN6_PMIER, 0);	6758	I915_WRITE(GEN6_PMIER, 0);
6759	I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));	6759	I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6760	}	6760	}
6761		6761
6762	static unsigned long intel_pxfreq(u32 vidfreq)	6762	static unsigned long intel_pxfreq(u32 vidfreq)
6763	{	6763	{
6764	unsigned long freq;	6764	unsigned long freq;
6765	int div = (vidfreq & 0x3f0000) >> 16;	6765	int div = (vidfreq & 0x3f0000) >> 16;
6766	int post = (vidfreq & 0x3000) >> 12;	6766	int post = (vidfreq & 0x3000) >> 12;
6767	int pre = (vidfreq & 0x7);	6767	int pre = (vidfreq & 0x7);
6768		6768
6769	if (!pre)	6769	if (!pre)
6770	return 0;	6770	return 0;
6771		6771
6772	freq = ((div * 133333) / ((1<<post) * pre));	6772	freq = ((div * 133333) / ((1<<post) * pre));
6773		6773
6774	return freq;	6774	return freq;
6775	}	6775	}
6776		6776
6777	void intel_init_emon(struct drm_device *dev)	6777	void intel_init_emon(struct drm_device *dev)
6778	{	6778	{
6779	struct drm_i915_private *dev_priv = dev->dev_private;	6779	struct drm_i915_private *dev_priv = dev->dev_private;
6780	u32 lcfuse;	6780	u32 lcfuse;
6781	u8 pxw[16];	6781	u8 pxw[16];
6782	int i;	6782	int i;
6783		6783
6784	/* Disable to program */	6784	/* Disable to program */
6785	I915_WRITE(ECR, 0);	6785	I915_WRITE(ECR, 0);
6786	POSTING_READ(ECR);	6786	POSTING_READ(ECR);
6787		6787
6788	/* Program energy weights for various events */	6788	/* Program energy weights for various events */
6789	I915_WRITE(SDEW, 0x15040d00);	6789	I915_WRITE(SDEW, 0x15040d00);
6790	I915_WRITE(CSIEW0, 0x007f0000);	6790	I915_WRITE(CSIEW0, 0x007f0000);
6791	I915_WRITE(CSIEW1, 0x1e220004);	6791	I915_WRITE(CSIEW1, 0x1e220004);
6792	I915_WRITE(CSIEW2, 0x04000004);	6792	I915_WRITE(CSIEW2, 0x04000004);
6793		6793
6794	for (i = 0; i < 5; i++)	6794	for (i = 0; i < 5; i++)
6795	I915_WRITE(PEW + (i * 4), 0);	6795	I915_WRITE(PEW + (i * 4), 0);
6796	for (i = 0; i < 3; i++)	6796	for (i = 0; i < 3; i++)
6797	I915_WRITE(DEW + (i * 4), 0);	6797	I915_WRITE(DEW + (i * 4), 0);
6798		6798
6799	/* Program P-state weights to account for frequency power adjustment */	6799	/* Program P-state weights to account for frequency power adjustment */
6800	for (i = 0; i < 16; i++) {	6800	for (i = 0; i < 16; i++) {
6801	u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));	6801	u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6802	unsigned long freq = intel_pxfreq(pxvidfreq);	6802	unsigned long freq = intel_pxfreq(pxvidfreq);
6803	unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>	6803	unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6804	PXVFREQ_PX_SHIFT;	6804	PXVFREQ_PX_SHIFT;
6805	unsigned long val;	6805	unsigned long val;
6806		6806
6807	val = vid * vid;	6807	val = vid * vid;
6808	val *= (freq / 1000);	6808	val *= (freq / 1000);
6809	val *= 255;	6809	val *= 255;
6810	val /= (127127900);	6810	val /= (127127900);
6811	if (val > 0xff)	6811	if (val > 0xff)
6812	DRM_ERROR("bad pxval: %ld\n", val);	6812	DRM_ERROR("bad pxval: %ld\n", val);
6813	pxw[i] = val;	6813	pxw[i] = val;
6814	}	6814	}
6815	/* Render standby states get 0 weight */	6815	/* Render standby states get 0 weight */
6816	pxw[14] = 0;	6816	pxw[14] = 0;
6817	pxw[15] = 0;	6817	pxw[15] = 0;
6818		6818
6819	for (i = 0; i < 4; i++) {	6819	for (i = 0; i < 4; i++) {
6820	u32 val = (pxw[i4] << 24) \| (pxw[(i4)+1] << 16) \|	6820	u32 val = (pxw[i4] << 24) \| (pxw[(i4)+1] << 16) \|
6821	(pxw[(i4)+2] << 8) \| (pxw[(i4)+3]);	6821	(pxw[(i4)+2] << 8) \| (pxw[(i4)+3]);
6822	I915_WRITE(PXW + (i * 4), val);	6822	I915_WRITE(PXW + (i * 4), val);
6823	}	6823	}
6824		6824
6825	/* Adjust magic regs to magic values (more experimental results) */	6825	/* Adjust magic regs to magic values (more experimental results) */
6826	I915_WRITE(OGW0, 0);	6826	I915_WRITE(OGW0, 0);
6827	I915_WRITE(OGW1, 0);	6827	I915_WRITE(OGW1, 0);
6828	I915_WRITE(EG0, 0x00007f00);	6828	I915_WRITE(EG0, 0x00007f00);
6829	I915_WRITE(EG1, 0x0000000e);	6829	I915_WRITE(EG1, 0x0000000e);
6830	I915_WRITE(EG2, 0x000e0000);	6830	I915_WRITE(EG2, 0x000e0000);
6831	I915_WRITE(EG3, 0x68000300);	6831	I915_WRITE(EG3, 0x68000300);
6832	I915_WRITE(EG4, 0x42000000);	6832	I915_WRITE(EG4, 0x42000000);
6833	I915_WRITE(EG5, 0x00140031);	6833	I915_WRITE(EG5, 0x00140031);
6834	I915_WRITE(EG6, 0);	6834	I915_WRITE(EG6, 0);
6835	I915_WRITE(EG7, 0);	6835	I915_WRITE(EG7, 0);
6836		6836
6837	for (i = 0; i < 8; i++)	6837	for (i = 0; i < 8; i++)
6838	I915_WRITE(PXWL + (i * 4), 0);	6838	I915_WRITE(PXWL + (i * 4), 0);
6839		6839
6840	/* Enable PMON + select events */	6840	/* Enable PMON + select events */
6841	I915_WRITE(ECR, 0x80000019);	6841	I915_WRITE(ECR, 0x80000019);
6842		6842
6843	lcfuse = I915_READ(LCFUSE02);	6843	lcfuse = I915_READ(LCFUSE02);
6844		6844
6845	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);	6845	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6846	}	6846	}
6847		6847
6848	void gen6_enable_rps(struct drm_i915_private *dev_priv)	6848	void gen6_enable_rps(struct drm_i915_private *dev_priv)
6849	{	6849	{
6850	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);	6850	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6851	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);	6851	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6852	u32 pcu_mbox;	6852	u32 pcu_mbox;
6853	int cur_freq, min_freq, max_freq;	6853	int cur_freq, min_freq, max_freq;
6854	int i;	6854	int i;
6855		6855
6856	/* Here begins a magic sequence of register writes to enable	6856	/* Here begins a magic sequence of register writes to enable
6857	* auto-downclocking.	6857	* auto-downclocking.
6858	*	6858	*
6859	* Perhaps there might be some value in exposing these to	6859	* Perhaps there might be some value in exposing these to
6860	* userspace...	6860	* userspace...
6861	*/	6861	*/
6862	I915_WRITE(GEN6_RC_STATE, 0);	6862	I915_WRITE(GEN6_RC_STATE, 0);
6863	__gen6_gt_force_wake_get(dev_priv);	6863	__gen6_gt_force_wake_get(dev_priv);
6864		6864
6865	/* disable the counters and set deterministic thresholds */	6865	/* disable the counters and set deterministic thresholds */
6866	I915_WRITE(GEN6_RC_CONTROL, 0);	6866	I915_WRITE(GEN6_RC_CONTROL, 0);
6867		6867
6868	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);	6868	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6869	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 \| 30);	6869	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 \| 30);
6870	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);	6870	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6871	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);	6871	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6872	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);	6872	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6873		6873
6874	for (i = 0; i < I915_NUM_RINGS; i++)	6874	for (i = 0; i < I915_NUM_RINGS; i++)
6875	I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);	6875	I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6876		6876
6877	I915_WRITE(GEN6_RC_SLEEP, 0);	6877	I915_WRITE(GEN6_RC_SLEEP, 0);
6878	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);	6878	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6879	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);	6879	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6880	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);	6880	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6881	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */	6881	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6882		6882
6883	I915_WRITE(GEN6_RC_CONTROL,	6883	I915_WRITE(GEN6_RC_CONTROL,
6884	GEN6_RC_CTL_RC6p_ENABLE \|	6884	GEN6_RC_CTL_RC6p_ENABLE \|
6885	GEN6_RC_CTL_RC6_ENABLE \|	6885	GEN6_RC_CTL_RC6_ENABLE \|
6886	GEN6_RC_CTL_EI_MODE(1) \|	6886	GEN6_RC_CTL_EI_MODE(1) \|
6887	GEN6_RC_CTL_HW_ENABLE);	6887	GEN6_RC_CTL_HW_ENABLE);
6888		6888
6889	I915_WRITE(GEN6_RPNSWREQ,	6889	I915_WRITE(GEN6_RPNSWREQ,
6890	GEN6_FREQUENCY(10) \|	6890	GEN6_FREQUENCY(10) \|
6891	GEN6_OFFSET(0) \|	6891	GEN6_OFFSET(0) \|
6892	GEN6_AGGRESSIVE_TURBO);	6892	GEN6_AGGRESSIVE_TURBO);
6893	I915_WRITE(GEN6_RC_VIDEO_FREQ,	6893	I915_WRITE(GEN6_RC_VIDEO_FREQ,
6894	GEN6_FREQUENCY(12));	6894	GEN6_FREQUENCY(12));
6895		6895
6896	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);	6896	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6897	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,	6897	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6898	18 << 24 \|	6898	18 << 24 \|
6899	6 << 16);	6899	6 << 16);
6900	I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);	6900	I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6901	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);	6901	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
6902	I915_WRITE(GEN6_RP_UP_EI, 100000);	6902	I915_WRITE(GEN6_RP_UP_EI, 100000);
6903	I915_WRITE(GEN6_RP_DOWN_EI, 5000000);	6903	I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
6904	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);	6904	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6905	I915_WRITE(GEN6_RP_CONTROL,	6905	I915_WRITE(GEN6_RP_CONTROL,
6906	GEN6_RP_MEDIA_TURBO \|	6906	GEN6_RP_MEDIA_TURBO \|
6907	GEN6_RP_USE_NORMAL_FREQ \|	6907	GEN6_RP_USE_NORMAL_FREQ \|
6908	GEN6_RP_MEDIA_IS_GFX \|	6908	GEN6_RP_MEDIA_IS_GFX \|
6909	GEN6_RP_ENABLE \|	6909	GEN6_RP_ENABLE \|
6910	GEN6_RP_UP_BUSY_AVG \|	6910	GEN6_RP_UP_BUSY_AVG \|
6911	GEN6_RP_DOWN_IDLE_CONT);	6911	GEN6_RP_DOWN_IDLE_CONT);
6912		6912
6913	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,	6913	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6914	500))	6914	500))
6915	DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");	6915	DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6916		6916
6917	I915_WRITE(GEN6_PCODE_DATA, 0);	6917	I915_WRITE(GEN6_PCODE_DATA, 0);
6918	I915_WRITE(GEN6_PCODE_MAILBOX,	6918	I915_WRITE(GEN6_PCODE_MAILBOX,
6919	GEN6_PCODE_READY \|	6919	GEN6_PCODE_READY \|
6920	GEN6_PCODE_WRITE_MIN_FREQ_TABLE);	6920	GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6921	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,	6921	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6922	500))	6922	500))
6923	DRM_ERROR("timeout waiting for pcode mailbox to finish\n");	6923	DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6924		6924
6925	min_freq = (rp_state_cap & 0xff0000) >> 16;	6925	min_freq = (rp_state_cap & 0xff0000) >> 16;
6926	max_freq = rp_state_cap & 0xff;	6926	max_freq = rp_state_cap & 0xff;
6927	cur_freq = (gt_perf_status & 0xff00) >> 8;	6927	cur_freq = (gt_perf_status & 0xff00) >> 8;
6928		6928
6929	/* Check for overclock support */	6929	/* Check for overclock support */
6930	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,	6930	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6931	500))	6931	500))
6932	DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");	6932	DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6933	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);	6933	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6934	pcu_mbox = I915_READ(GEN6_PCODE_DATA);	6934	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6935	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,	6935	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6936	500))	6936	500))
6937	DRM_ERROR("timeout waiting for pcode mailbox to finish\n");	6937	DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6938	if (pcu_mbox & (1<<31)) { /* OC supported */	6938	if (pcu_mbox & (1<<31)) { /* OC supported */
6939	max_freq = pcu_mbox & 0xff;	6939	max_freq = pcu_mbox & 0xff;
6940	DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);	6940	DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
6941	}	6941	}
6942		6942
6943	/* In units of 100MHz */	6943	/* In units of 100MHz */
6944	dev_priv->max_delay = max_freq;	6944	dev_priv->max_delay = max_freq;
6945	dev_priv->min_delay = min_freq;	6945	dev_priv->min_delay = min_freq;
6946	dev_priv->cur_delay = cur_freq;	6946	dev_priv->cur_delay = cur_freq;
6947		6947
6948	/* requires MSI enabled */	6948	/* requires MSI enabled */
6949	I915_WRITE(GEN6_PMIER,	6949	I915_WRITE(GEN6_PMIER,
6950	GEN6_PM_MBOX_EVENT \|	6950	GEN6_PM_MBOX_EVENT \|
6951	GEN6_PM_THERMAL_EVENT \|	6951	GEN6_PM_THERMAL_EVENT \|
6952	GEN6_PM_RP_DOWN_TIMEOUT \|	6952	GEN6_PM_RP_DOWN_TIMEOUT \|
6953	GEN6_PM_RP_UP_THRESHOLD \|	6953	GEN6_PM_RP_UP_THRESHOLD \|
6954	GEN6_PM_RP_DOWN_THRESHOLD \|	6954	GEN6_PM_RP_DOWN_THRESHOLD \|
6955	GEN6_PM_RP_UP_EI_EXPIRED \|	6955	GEN6_PM_RP_UP_EI_EXPIRED \|
6956	GEN6_PM_RP_DOWN_EI_EXPIRED);	6956	GEN6_PM_RP_DOWN_EI_EXPIRED);
6957	I915_WRITE(GEN6_PMIMR, 0);	6957	I915_WRITE(GEN6_PMIMR, 0);
6958	/* enable all PM interrupts */	6958	/* enable all PM interrupts */
6959	I915_WRITE(GEN6_PMINTRMSK, 0);	6959	I915_WRITE(GEN6_PMINTRMSK, 0);
6960		6960
6961	__gen6_gt_force_wake_put(dev_priv);	6961	__gen6_gt_force_wake_put(dev_priv);
6962	}	6962	}
6963		6963
6964	void intel_enable_clock_gating(struct drm_device *dev)	6964	void intel_enable_clock_gating(struct drm_device *dev)
6965	{	6965	{
6966	struct drm_i915_private *dev_priv = dev->dev_private;	6966	struct drm_i915_private *dev_priv = dev->dev_private;
6967	int pipe;	6967	int pipe;
6968		6968
6969	/*	6969	/*
6970	* Disable clock gating reported to work incorrectly according to the	6970	* Disable clock gating reported to work incorrectly according to the
6971	* specs, but enable as much else as we can.	6971	* specs, but enable as much else as we can.
6972	*/	6972	*/
6973	if (HAS_PCH_SPLIT(dev)) {	6973	if (HAS_PCH_SPLIT(dev)) {
6974	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;	6974	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6975		6975
6976	if (IS_GEN5(dev)) {	6976	if (IS_GEN5(dev)) {
6977	/* Required for FBC */	6977	/* Required for FBC */
6978	dspclk_gate \|= DPFCUNIT_CLOCK_GATE_DISABLE \|	6978	dspclk_gate \|= DPFCUNIT_CLOCK_GATE_DISABLE \|
6979	DPFCRUNIT_CLOCK_GATE_DISABLE \|	6979	DPFCRUNIT_CLOCK_GATE_DISABLE \|
6980	DPFDUNIT_CLOCK_GATE_DISABLE;	6980	DPFDUNIT_CLOCK_GATE_DISABLE;
6981	/* Required for CxSR */	6981	/* Required for CxSR */
6982	dspclk_gate \|= DPARBUNIT_CLOCK_GATE_DISABLE;	6982	dspclk_gate \|= DPARBUNIT_CLOCK_GATE_DISABLE;
6983		6983
6984	I915_WRITE(PCH_3DCGDIS0,	6984	I915_WRITE(PCH_3DCGDIS0,
6985	MARIUNIT_CLOCK_GATE_DISABLE \|	6985	MARIUNIT_CLOCK_GATE_DISABLE \|
6986	SVSMUNIT_CLOCK_GATE_DISABLE);	6986	SVSMUNIT_CLOCK_GATE_DISABLE);
6987	I915_WRITE(PCH_3DCGDIS1,	6987	I915_WRITE(PCH_3DCGDIS1,
6988	VFMUNIT_CLOCK_GATE_DISABLE);	6988	VFMUNIT_CLOCK_GATE_DISABLE);
6989	}	6989	}
6990		6990
6991	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);	6991	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6992		6992
6993	/*	6993	/*
6994	* On Ibex Peak and Cougar Point, we need to disable clock	6994	* On Ibex Peak and Cougar Point, we need to disable clock
6995	* gating for the panel power sequencer or it will fail to	6995	* gating for the panel power sequencer or it will fail to
6996	* start up when no ports are active.	6996	* start up when no ports are active.
6997	*/	6997	*/
6998	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);	6998	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6999		6999
7000	/*	7000	/*
7001	* According to the spec the following bits should be set in	7001	* According to the spec the following bits should be set in
7002	* order to enable memory self-refresh	7002	* order to enable memory self-refresh
7003	* The bit 22/21 of 0x42004	7003	* The bit 22/21 of 0x42004
7004	* The bit 5 of 0x42020	7004	* The bit 5 of 0x42020
7005	* The bit 15 of 0x45000	7005	* The bit 15 of 0x45000
7006	*/	7006	*/
7007	if (IS_GEN5(dev)) {	7007	if (IS_GEN5(dev)) {
7008	I915_WRITE(ILK_DISPLAY_CHICKEN2,	7008	I915_WRITE(ILK_DISPLAY_CHICKEN2,
7009	(I915_READ(ILK_DISPLAY_CHICKEN2) \|	7009	(I915_READ(ILK_DISPLAY_CHICKEN2) \|
7010	ILK_DPARB_GATE \| ILK_VSDPFD_FULL));	7010	ILK_DPARB_GATE \| ILK_VSDPFD_FULL));
7011	I915_WRITE(ILK_DSPCLK_GATE,	7011	I915_WRITE(ILK_DSPCLK_GATE,
7012	(I915_READ(ILK_DSPCLK_GATE) \|	7012	(I915_READ(ILK_DSPCLK_GATE) \|
7013	ILK_DPARB_CLK_GATE));	7013	ILK_DPARB_CLK_GATE));
7014	I915_WRITE(DISP_ARB_CTL,	7014	I915_WRITE(DISP_ARB_CTL,
7015	(I915_READ(DISP_ARB_CTL) \|	7015	(I915_READ(DISP_ARB_CTL) \|
7016	DISP_FBC_WM_DIS));	7016	DISP_FBC_WM_DIS));
7017	I915_WRITE(WM3_LP_ILK, 0);	7017	I915_WRITE(WM3_LP_ILK, 0);
7018	I915_WRITE(WM2_LP_ILK, 0);	7018	I915_WRITE(WM2_LP_ILK, 0);
7019	I915_WRITE(WM1_LP_ILK, 0);	7019	I915_WRITE(WM1_LP_ILK, 0);
7020	}	7020	}
7021	/*	7021	/*
7022	* Based on the document from hardware guys the following bits	7022	* Based on the document from hardware guys the following bits
7023	* should be set unconditionally in order to enable FBC.	7023	* should be set unconditionally in order to enable FBC.
7024	* The bit 22 of 0x42000	7024	* The bit 22 of 0x42000
7025	* The bit 22 of 0x42004	7025	* The bit 22 of 0x42004
7026	* The bit 7,8,9 of 0x42020.	7026	* The bit 7,8,9 of 0x42020.
7027	*/	7027	*/
7028	if (IS_IRONLAKE_M(dev)) {	7028	if (IS_IRONLAKE_M(dev)) {
7029	I915_WRITE(ILK_DISPLAY_CHICKEN1,	7029	I915_WRITE(ILK_DISPLAY_CHICKEN1,
7030	I915_READ(ILK_DISPLAY_CHICKEN1) \|	7030	I915_READ(ILK_DISPLAY_CHICKEN1) \|
7031	ILK_FBCQ_DIS);	7031	ILK_FBCQ_DIS);
7032	I915_WRITE(ILK_DISPLAY_CHICKEN2,	7032	I915_WRITE(ILK_DISPLAY_CHICKEN2,
7033	I915_READ(ILK_DISPLAY_CHICKEN2) \|	7033	I915_READ(ILK_DISPLAY_CHICKEN2) \|
7034	ILK_DPARB_GATE);	7034	ILK_DPARB_GATE);
7035	I915_WRITE(ILK_DSPCLK_GATE,	7035	I915_WRITE(ILK_DSPCLK_GATE,
7036	I915_READ(ILK_DSPCLK_GATE) \|	7036	I915_READ(ILK_DSPCLK_GATE) \|
7037	ILK_DPFC_DIS1 \|	7037	ILK_DPFC_DIS1 \|
7038	ILK_DPFC_DIS2 \|	7038	ILK_DPFC_DIS2 \|
7039	ILK_CLK_FBC);	7039	ILK_CLK_FBC);
7040	}	7040	}
7041		7041
7042	I915_WRITE(ILK_DISPLAY_CHICKEN2,	7042	I915_WRITE(ILK_DISPLAY_CHICKEN2,
7043	I915_READ(ILK_DISPLAY_CHICKEN2) \|	7043	I915_READ(ILK_DISPLAY_CHICKEN2) \|
7044	ILK_ELPIN_409_SELECT);	7044	ILK_ELPIN_409_SELECT);
7045		7045
7046	if (IS_GEN5(dev)) {	7046	if (IS_GEN5(dev)) {
7047	I915_WRITE(_3D_CHICKEN2,	7047	I915_WRITE(_3D_CHICKEN2,
7048	_3D_CHICKEN2_WM_READ_PIPELINED << 16 \|	7048	_3D_CHICKEN2_WM_READ_PIPELINED << 16 \|
7049	_3D_CHICKEN2_WM_READ_PIPELINED);	7049	_3D_CHICKEN2_WM_READ_PIPELINED);
7050	}	7050	}
7051		7051
7052	if (IS_GEN6(dev)) {	7052	if (IS_GEN6(dev)) {
7053	I915_WRITE(WM3_LP_ILK, 0);	7053	I915_WRITE(WM3_LP_ILK, 0);
7054	I915_WRITE(WM2_LP_ILK, 0);	7054	I915_WRITE(WM2_LP_ILK, 0);
7055	I915_WRITE(WM1_LP_ILK, 0);	7055	I915_WRITE(WM1_LP_ILK, 0);
7056		7056
7057	/*	7057	/*
7058	* According to the spec the following bits should be	7058	* According to the spec the following bits should be
7059	* set in order to enable memory self-refresh and fbc:	7059	* set in order to enable memory self-refresh and fbc:
7060	* The bit21 and bit22 of 0x42000	7060	* The bit21 and bit22 of 0x42000
7061	* The bit21 and bit22 of 0x42004	7061	* The bit21 and bit22 of 0x42004
7062	* The bit5 and bit7 of 0x42020	7062	* The bit5 and bit7 of 0x42020
7063	* The bit14 of 0x70180	7063	* The bit14 of 0x70180
7064	* The bit14 of 0x71180	7064	* The bit14 of 0x71180
7065	*/	7065	*/
7066	I915_WRITE(ILK_DISPLAY_CHICKEN1,	7066	I915_WRITE(ILK_DISPLAY_CHICKEN1,
7067	I915_READ(ILK_DISPLAY_CHICKEN1) \|	7067	I915_READ(ILK_DISPLAY_CHICKEN1) \|
7068	ILK_FBCQ_DIS \| ILK_PABSTRETCH_DIS);	7068	ILK_FBCQ_DIS \| ILK_PABSTRETCH_DIS);
7069	I915_WRITE(ILK_DISPLAY_CHICKEN2,	7069	I915_WRITE(ILK_DISPLAY_CHICKEN2,
7070	I915_READ(ILK_DISPLAY_CHICKEN2) \|	7070	I915_READ(ILK_DISPLAY_CHICKEN2) \|
7071	ILK_DPARB_GATE \| ILK_VSDPFD_FULL);	7071	ILK_DPARB_GATE \| ILK_VSDPFD_FULL);
7072	I915_WRITE(ILK_DSPCLK_GATE,	7072	I915_WRITE(ILK_DSPCLK_GATE,
7073	I915_READ(ILK_DSPCLK_GATE) \|	7073	I915_READ(ILK_DSPCLK_GATE) \|
7074	ILK_DPARB_CLK_GATE \|	7074	ILK_DPARB_CLK_GATE \|
7075	ILK_DPFD_CLK_GATE);	7075	ILK_DPFD_CLK_GATE);
7076		7076
7077	for_each_pipe(pipe)	7077	for_each_pipe(pipe)
7078	I915_WRITE(DSPCNTR(pipe),	7078	I915_WRITE(DSPCNTR(pipe),
7079	I915_READ(DSPCNTR(pipe)) \|	7079	I915_READ(DSPCNTR(pipe)) \|
7080	DISPPLANE_TRICKLE_FEED_DISABLE);	7080	DISPPLANE_TRICKLE_FEED_DISABLE);
7081	}	7081	}
7082	} else if (IS_G4X(dev)) {	7082	} else if (IS_G4X(dev)) {
7083	uint32_t dspclk_gate;	7083	uint32_t dspclk_gate;
7084	I915_WRITE(RENCLK_GATE_D1, 0);	7084	I915_WRITE(RENCLK_GATE_D1, 0);
7085	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE \|	7085	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE \|
7086	GS_UNIT_CLOCK_GATE_DISABLE \|	7086	GS_UNIT_CLOCK_GATE_DISABLE \|
7087	CL_UNIT_CLOCK_GATE_DISABLE);	7087	CL_UNIT_CLOCK_GATE_DISABLE);
7088	I915_WRITE(RAMCLK_GATE_D, 0);	7088	I915_WRITE(RAMCLK_GATE_D, 0);
7089	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE \|	7089	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE \|
7090	OVRUNIT_CLOCK_GATE_DISABLE \|	7090	OVRUNIT_CLOCK_GATE_DISABLE \|
7091	OVCUNIT_CLOCK_GATE_DISABLE;	7091	OVCUNIT_CLOCK_GATE_DISABLE;
7092	if (IS_GM45(dev))	7092	if (IS_GM45(dev))
7093	dspclk_gate \|= DSSUNIT_CLOCK_GATE_DISABLE;	7093	dspclk_gate \|= DSSUNIT_CLOCK_GATE_DISABLE;
7094	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);	7094	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7095	} else if (IS_CRESTLINE(dev)) {	7095	} else if (IS_CRESTLINE(dev)) {
7096	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);	7096	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7097	I915_WRITE(RENCLK_GATE_D2, 0);	7097	I915_WRITE(RENCLK_GATE_D2, 0);
7098	I915_WRITE(DSPCLK_GATE_D, 0);	7098	I915_WRITE(DSPCLK_GATE_D, 0);
7099	I915_WRITE(RAMCLK_GATE_D, 0);	7099	I915_WRITE(RAMCLK_GATE_D, 0);
7100	I915_WRITE16(DEUC, 0);	7100	I915_WRITE16(DEUC, 0);
7101	} else if (IS_BROADWATER(dev)) {	7101	} else if (IS_BROADWATER(dev)) {
7102	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE \|	7102	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE \|
7103	I965_RCC_CLOCK_GATE_DISABLE \|	7103	I965_RCC_CLOCK_GATE_DISABLE \|
7104	I965_RCPB_CLOCK_GATE_DISABLE \|	7104	I965_RCPB_CLOCK_GATE_DISABLE \|
7105	I965_ISC_CLOCK_GATE_DISABLE \|	7105	I965_ISC_CLOCK_GATE_DISABLE \|
7106	I965_FBC_CLOCK_GATE_DISABLE);	7106	I965_FBC_CLOCK_GATE_DISABLE);
7107	I915_WRITE(RENCLK_GATE_D2, 0);	7107	I915_WRITE(RENCLK_GATE_D2, 0);
7108	} else if (IS_GEN3(dev)) {	7108	} else if (IS_GEN3(dev)) {
7109	u32 dstate = I915_READ(D_STATE);	7109	u32 dstate = I915_READ(D_STATE);
7110		7110
7111	dstate \|= DSTATE_PLL_D3_OFF \| DSTATE_GFX_CLOCK_GATING \|	7111	dstate \|= DSTATE_PLL_D3_OFF \| DSTATE_GFX_CLOCK_GATING \|
7112	DSTATE_DOT_CLOCK_GATING;	7112	DSTATE_DOT_CLOCK_GATING;
7113	I915_WRITE(D_STATE, dstate);	7113	I915_WRITE(D_STATE, dstate);
7114	} else if (IS_I85X(dev) \|\| IS_I865G(dev)) {	7114	} else if (IS_I85X(dev) \|\| IS_I865G(dev)) {
7115	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);	7115	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7116	} else if (IS_I830(dev)) {	7116	} else if (IS_I830(dev)) {
7117	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);	7117	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7118	}	7118	}
7119	}	7119	}
7120		7120
7121	static void ironlake_teardown_rc6(struct drm_device *dev)	7121	static void ironlake_teardown_rc6(struct drm_device *dev)
7122	{	7122	{
7123	struct drm_i915_private *dev_priv = dev->dev_private;	7123	struct drm_i915_private *dev_priv = dev->dev_private;
7124		7124
7125	if (dev_priv->renderctx) {	7125	if (dev_priv->renderctx) {
7126	i915_gem_object_unpin(dev_priv->renderctx);	7126	i915_gem_object_unpin(dev_priv->renderctx);
7127	drm_gem_object_unreference(&dev_priv->renderctx->base);	7127	drm_gem_object_unreference(&dev_priv->renderctx->base);
7128	dev_priv->renderctx = NULL;	7128	dev_priv->renderctx = NULL;
7129	}	7129	}
7130		7130
7131	if (dev_priv->pwrctx) {	7131	if (dev_priv->pwrctx) {
7132	i915_gem_object_unpin(dev_priv->pwrctx);	7132	i915_gem_object_unpin(dev_priv->pwrctx);
7133	drm_gem_object_unreference(&dev_priv->pwrctx->base);	7133	drm_gem_object_unreference(&dev_priv->pwrctx->base);
7134	dev_priv->pwrctx = NULL;	7134	dev_priv->pwrctx = NULL;
7135	}	7135	}
7136	}	7136	}
7137		7137
7138	static void ironlake_disable_rc6(struct drm_device *dev)	7138	static void ironlake_disable_rc6(struct drm_device *dev)
7139	{	7139	{
7140	struct drm_i915_private *dev_priv = dev->dev_private;	7140	struct drm_i915_private *dev_priv = dev->dev_private;
7141		7141
7142	if (I915_READ(PWRCTXA)) {	7142	if (I915_READ(PWRCTXA)) {
7143	/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */	7143	/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7144	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) \| RCX_SW_EXIT);	7144	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) \| RCX_SW_EXIT);
7145	wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),	7145	wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7146	50);	7146	50);
7147		7147
7148	I915_WRITE(PWRCTXA, 0);	7148	I915_WRITE(PWRCTXA, 0);
7149	POSTING_READ(PWRCTXA);	7149	POSTING_READ(PWRCTXA);
7150		7150
7151	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);	7151	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7152	POSTING_READ(RSTDBYCTL);	7152	POSTING_READ(RSTDBYCTL);
7153	}	7153	}
7154		7154
7155	ironlake_teardown_rc6(dev);	7155	ironlake_teardown_rc6(dev);
7156	}	7156	}
7157		7157
7158	static int ironlake_setup_rc6(struct drm_device *dev)	7158	static int ironlake_setup_rc6(struct drm_device *dev)
7159	{	7159	{
7160	struct drm_i915_private *dev_priv = dev->dev_private;	7160	struct drm_i915_private *dev_priv = dev->dev_private;
7161		7161
7162	if (dev_priv->renderctx == NULL)	7162	if (dev_priv->renderctx == NULL)
7163	dev_priv->renderctx = intel_alloc_context_page(dev);	7163	dev_priv->renderctx = intel_alloc_context_page(dev);
7164	if (!dev_priv->renderctx)	7164	if (!dev_priv->renderctx)
7165	return -ENOMEM;	7165	return -ENOMEM;
7166		7166
7167	if (dev_priv->pwrctx == NULL)	7167	if (dev_priv->pwrctx == NULL)
7168	dev_priv->pwrctx = intel_alloc_context_page(dev);	7168	dev_priv->pwrctx = intel_alloc_context_page(dev);
7169	if (!dev_priv->pwrctx) {	7169	if (!dev_priv->pwrctx) {
7170	ironlake_teardown_rc6(dev);	7170	ironlake_teardown_rc6(dev);
7171	return -ENOMEM;	7171	return -ENOMEM;
7172	}	7172	}
7173		7173
7174	return 0;	7174	return 0;
7175	}	7175	}
7176		7176
7177	void ironlake_enable_rc6(struct drm_device *dev)	7177	void ironlake_enable_rc6(struct drm_device *dev)
7178	{	7178	{
7179	struct drm_i915_private *dev_priv = dev->dev_private;	7179	struct drm_i915_private *dev_priv = dev->dev_private;
7180	int ret;	7180	int ret;
7181		7181
7182	/* rc6 disabled by default due to repeated reports of hanging during	7182	/* rc6 disabled by default due to repeated reports of hanging during
7183	* boot and resume.	7183	* boot and resume.
7184	*/	7184	*/
7185	if (!i915_enable_rc6)	7185	if (!i915_enable_rc6)
7186	return;	7186	return;
7187		7187
7188	ret = ironlake_setup_rc6(dev);	7188	ret = ironlake_setup_rc6(dev);
7189	if (ret)	7189	if (ret)
7190	return;	7190	return;
7191		7191
7192	/*	7192	/*
7193	* GPU can automatically power down the render unit if given a page	7193	* GPU can automatically power down the render unit if given a page
7194	* to save state.	7194	* to save state.
7195	*/	7195	*/
7196	ret = BEGIN_LP_RING(6);	7196	ret = BEGIN_LP_RING(6);
7197	if (ret) {	7197	if (ret) {
7198	ironlake_teardown_rc6(dev);	7198	ironlake_teardown_rc6(dev);
7199	return;	7199	return;
7200	}	7200	}
7201		7201
7202	OUT_RING(MI_SUSPEND_FLUSH \| MI_SUSPEND_FLUSH_EN);	7202	OUT_RING(MI_SUSPEND_FLUSH \| MI_SUSPEND_FLUSH_EN);
7203	OUT_RING(MI_SET_CONTEXT);	7203	OUT_RING(MI_SET_CONTEXT);
7204	OUT_RING(dev_priv->renderctx->gtt_offset \|	7204	OUT_RING(dev_priv->renderctx->gtt_offset \|
7205	MI_MM_SPACE_GTT \|	7205	MI_MM_SPACE_GTT \|
7206	MI_SAVE_EXT_STATE_EN \|	7206	MI_SAVE_EXT_STATE_EN \|
7207	MI_RESTORE_EXT_STATE_EN \|	7207	MI_RESTORE_EXT_STATE_EN \|
7208	MI_RESTORE_INHIBIT);	7208	MI_RESTORE_INHIBIT);
7209	OUT_RING(MI_SUSPEND_FLUSH);	7209	OUT_RING(MI_SUSPEND_FLUSH);
7210	OUT_RING(MI_NOOP);	7210	OUT_RING(MI_NOOP);
7211	OUT_RING(MI_FLUSH);	7211	OUT_RING(MI_FLUSH);
7212	ADVANCE_LP_RING();	7212	ADVANCE_LP_RING();
7213		7213
7214	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset \| PWRCTX_EN);	7214	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset \| PWRCTX_EN);
7215	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);	7215	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7216	}	7216	}
7217		7217
7218		7218
7219	/* Set up chip specific display functions */	7219	/* Set up chip specific display functions */
7220	static void intel_init_display(struct drm_device *dev)	7220	static void intel_init_display(struct drm_device *dev)
7221	{	7221	{
7222	struct drm_i915_private *dev_priv = dev->dev_private;	7222	struct drm_i915_private *dev_priv = dev->dev_private;
7223		7223
7224	/* We always want a DPMS function */	7224	/* We always want a DPMS function */
7225	if (HAS_PCH_SPLIT(dev))	7225	if (HAS_PCH_SPLIT(dev))
7226	dev_priv->display.dpms = ironlake_crtc_dpms;	7226	dev_priv->display.dpms = ironlake_crtc_dpms;
7227	else	7227	else
7228	dev_priv->display.dpms = i9xx_crtc_dpms;	7228	dev_priv->display.dpms = i9xx_crtc_dpms;
7229		7229
7230	if (I915_HAS_FBC(dev)) {	7230	if (I915_HAS_FBC(dev)) {
7231	if (HAS_PCH_SPLIT(dev)) {	7231	if (HAS_PCH_SPLIT(dev)) {
7232	dev_priv->display.fbc_enabled = ironlake_fbc_enabled;	7232	dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7233	dev_priv->display.enable_fbc = ironlake_enable_fbc;	7233	dev_priv->display.enable_fbc = ironlake_enable_fbc;
7234	dev_priv->display.disable_fbc = ironlake_disable_fbc;	7234	dev_priv->display.disable_fbc = ironlake_disable_fbc;
7235	} else if (IS_GM45(dev)) {	7235	} else if (IS_GM45(dev)) {
7236	dev_priv->display.fbc_enabled = g4x_fbc_enabled;	7236	dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7237	dev_priv->display.enable_fbc = g4x_enable_fbc;	7237	dev_priv->display.enable_fbc = g4x_enable_fbc;
7238	dev_priv->display.disable_fbc = g4x_disable_fbc;	7238	dev_priv->display.disable_fbc = g4x_disable_fbc;
7239	} else if (IS_CRESTLINE(dev)) {	7239	} else if (IS_CRESTLINE(dev)) {
7240	dev_priv->display.fbc_enabled = i8xx_fbc_enabled;	7240	dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7241	dev_priv->display.enable_fbc = i8xx_enable_fbc;	7241	dev_priv->display.enable_fbc = i8xx_enable_fbc;
7242	dev_priv->display.disable_fbc = i8xx_disable_fbc;	7242	dev_priv->display.disable_fbc = i8xx_disable_fbc;
7243	}	7243	}
7244	/* 855GM needs testing */	7244	/* 855GM needs testing */
7245	}	7245	}
7246		7246
7247	/* Returns the core display clock speed */	7247	/* Returns the core display clock speed */
7248	if (IS_I945G(dev) \|\| (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))	7248	if (IS_I945G(dev) \|\| (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7249	dev_priv->display.get_display_clock_speed =	7249	dev_priv->display.get_display_clock_speed =
7250	i945_get_display_clock_speed;	7250	i945_get_display_clock_speed;
7251	else if (IS_I915G(dev))	7251	else if (IS_I915G(dev))
7252	dev_priv->display.get_display_clock_speed =	7252	dev_priv->display.get_display_clock_speed =
7253	i915_get_display_clock_speed;	7253	i915_get_display_clock_speed;
7254	else if (IS_I945GM(dev) \|\| IS_845G(dev) \|\| IS_PINEVIEW_M(dev))	7254	else if (IS_I945GM(dev) \|\| IS_845G(dev) \|\| IS_PINEVIEW_M(dev))
7255	dev_priv->display.get_display_clock_speed =	7255	dev_priv->display.get_display_clock_speed =
7256	i9xx_misc_get_display_clock_speed;	7256	i9xx_misc_get_display_clock_speed;
7257	else if (IS_I915GM(dev))	7257	else if (IS_I915GM(dev))
7258	dev_priv->display.get_display_clock_speed =	7258	dev_priv->display.get_display_clock_speed =
7259	i915gm_get_display_clock_speed;	7259	i915gm_get_display_clock_speed;
7260	else if (IS_I865G(dev))	7260	else if (IS_I865G(dev))
7261	dev_priv->display.get_display_clock_speed =	7261	dev_priv->display.get_display_clock_speed =
7262	i865_get_display_clock_speed;	7262	i865_get_display_clock_speed;
7263	else if (IS_I85X(dev))	7263	else if (IS_I85X(dev))
7264	dev_priv->display.get_display_clock_speed =	7264	dev_priv->display.get_display_clock_speed =
7265	i855_get_display_clock_speed;	7265	i855_get_display_clock_speed;
7266	else /* 852, 830 */	7266	else /* 852, 830 */
7267	dev_priv->display.get_display_clock_speed =	7267	dev_priv->display.get_display_clock_speed =
7268	i830_get_display_clock_speed;	7268	i830_get_display_clock_speed;
7269		7269
7270	/* For FIFO watermark updates */	7270	/* For FIFO watermark updates */
7271	if (HAS_PCH_SPLIT(dev)) {	7271	if (HAS_PCH_SPLIT(dev)) {
7272	if (IS_GEN5(dev)) {	7272	if (IS_GEN5(dev)) {
7273	if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)	7273	if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7274	dev_priv->display.update_wm = ironlake_update_wm;	7274	dev_priv->display.update_wm = ironlake_update_wm;
7275	else {	7275	else {
7276	DRM_DEBUG_KMS("Failed to get proper latency. "	7276	DRM_DEBUG_KMS("Failed to get proper latency. "
7277	"Disable CxSR\n");	7277	"Disable CxSR\n");
7278	dev_priv->display.update_wm = NULL;	7278	dev_priv->display.update_wm = NULL;
7279	}	7279	}
7280	} else if (IS_GEN6(dev)) {	7280	} else if (IS_GEN6(dev)) {
7281	if (SNB_READ_WM0_LATENCY()) {	7281	if (SNB_READ_WM0_LATENCY()) {
7282	dev_priv->display.update_wm = sandybridge_update_wm;	7282	dev_priv->display.update_wm = sandybridge_update_wm;
7283	} else {	7283	} else {
7284	DRM_DEBUG_KMS("Failed to read display plane latency. "	7284	DRM_DEBUG_KMS("Failed to read display plane latency. "
7285	"Disable CxSR\n");	7285	"Disable CxSR\n");
7286	dev_priv->display.update_wm = NULL;	7286	dev_priv->display.update_wm = NULL;
7287	}	7287	}
7288	} else	7288	} else
7289	dev_priv->display.update_wm = NULL;	7289	dev_priv->display.update_wm = NULL;
7290	} else if (IS_PINEVIEW(dev)) {	7290	} else if (IS_PINEVIEW(dev)) {
7291	if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),	7291	if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7292	dev_priv->is_ddr3,	7292	dev_priv->is_ddr3,
7293	dev_priv->fsb_freq,	7293	dev_priv->fsb_freq,
7294	dev_priv->mem_freq)) {	7294	dev_priv->mem_freq)) {
7295	DRM_INFO("failed to find known CxSR latency "	7295	DRM_INFO("failed to find known CxSR latency "
7296	"(found ddr%s fsb freq %d, mem freq %d), "	7296	"(found ddr%s fsb freq %d, mem freq %d), "
7297	"disabling CxSR\n",	7297	"disabling CxSR\n",
7298	(dev_priv->is_ddr3 == 1) ? "3": "2",	7298	(dev_priv->is_ddr3 == 1) ? "3": "2",
7299	dev_priv->fsb_freq, dev_priv->mem_freq);	7299	dev_priv->fsb_freq, dev_priv->mem_freq);
7300	/* Disable CxSR and never update its watermark again */	7300	/* Disable CxSR and never update its watermark again */
7301	pineview_disable_cxsr(dev);	7301	pineview_disable_cxsr(dev);
7302	dev_priv->display.update_wm = NULL;	7302	dev_priv->display.update_wm = NULL;
7303	} else	7303	} else
7304	dev_priv->display.update_wm = pineview_update_wm;	7304	dev_priv->display.update_wm = pineview_update_wm;
7305	} else if (IS_G4X(dev))	7305	} else if (IS_G4X(dev))
7306	dev_priv->display.update_wm = g4x_update_wm;	7306	dev_priv->display.update_wm = g4x_update_wm;
7307	else if (IS_GEN4(dev))	7307	else if (IS_GEN4(dev))
7308	dev_priv->display.update_wm = i965_update_wm;	7308	dev_priv->display.update_wm = i965_update_wm;
7309	else if (IS_GEN3(dev)) {	7309	else if (IS_GEN3(dev)) {
7310	dev_priv->display.update_wm = i9xx_update_wm;	7310	dev_priv->display.update_wm = i9xx_update_wm;
7311	dev_priv->display.get_fifo_size = i9xx_get_fifo_size;	7311	dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7312	} else if (IS_I85X(dev)) {	7312	} else if (IS_I85X(dev)) {
7313	dev_priv->display.update_wm = i9xx_update_wm;	7313	dev_priv->display.update_wm = i9xx_update_wm;
7314	dev_priv->display.get_fifo_size = i85x_get_fifo_size;	7314	dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7315	} else {	7315	} else {
7316	dev_priv->display.update_wm = i830_update_wm;	7316	dev_priv->display.update_wm = i830_update_wm;
7317	if (IS_845G(dev))	7317	if (IS_845G(dev))
7318	dev_priv->display.get_fifo_size = i845_get_fifo_size;	7318	dev_priv->display.get_fifo_size = i845_get_fifo_size;
7319	else	7319	else
7320	dev_priv->display.get_fifo_size = i830_get_fifo_size;	7320	dev_priv->display.get_fifo_size = i830_get_fifo_size;
7321	}	7321	}
7322	}	7322	}
7323		7323
7324	/*	7324	/*
7325	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,	7325	* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7326	* resume, or other times. This quirk makes sure that's the case for	7326	* resume, or other times. This quirk makes sure that's the case for
7327	* affected systems.	7327	* affected systems.
7328	*/	7328	*/
7329	static void quirk_pipea_force (struct drm_device *dev)	7329	static void quirk_pipea_force (struct drm_device *dev)
7330	{	7330	{
7331	struct drm_i915_private *dev_priv = dev->dev_private;	7331	struct drm_i915_private *dev_priv = dev->dev_private;
7332		7332
7333	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;	7333	dev_priv->quirks \|= QUIRK_PIPEA_FORCE;
7334	DRM_DEBUG_DRIVER("applying pipe a force quirk\n");	7334	DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7335	}	7335	}
7336		7336
7337	struct intel_quirk {	7337	struct intel_quirk {
7338	int device;	7338	int device;
7339	int subsystem_vendor;	7339	int subsystem_vendor;
7340	int subsystem_device;	7340	int subsystem_device;
7341	void (hook)(struct drm_device dev);	7341	void (hook)(struct drm_device dev);
7342	};	7342	};
7343		7343
7344	struct intel_quirk intel_quirks[] = {	7344	struct intel_quirk intel_quirks[] = {
7345	/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */	7345	/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7346	{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },	7346	{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7347	/* HP Mini needs pipe A force quirk (LP: #322104) */	7347	/* HP Mini needs pipe A force quirk (LP: #322104) */
7348	{ 0x27ae,0x103c, 0x361a, quirk_pipea_force },	7348	{ 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7349		7349
7350	/* Thinkpad R31 needs pipe A force quirk */	7350	/* Thinkpad R31 needs pipe A force quirk */
7351	{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },	7351	{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7352	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */	7352	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7353	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },	7353	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7354		7354
7355	/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */	7355	/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7356	{ 0x3577, 0x1014, 0x0513, quirk_pipea_force },	7356	{ 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7357	/* ThinkPad X40 needs pipe A force quirk */	7357	/* ThinkPad X40 needs pipe A force quirk */
7358		7358
7359	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */	7359	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7360	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },	7360	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7361		7361
7362	/* 855 & before need to leave pipe A & dpll A up */	7362	/* 855 & before need to leave pipe A & dpll A up */
7363	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },	7363	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7364	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },	7364	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7365	};	7365	};
7366		7366
7367	static void intel_init_quirks(struct drm_device *dev)	7367	static void intel_init_quirks(struct drm_device *dev)
7368	{	7368	{
7369	struct pci_dev *d = dev->pdev;	7369	struct pci_dev *d = dev->pdev;
7370	int i;	7370	int i;
7371		7371
7372	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {	7372	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7373	struct intel_quirk *q = &intel_quirks[i];	7373	struct intel_quirk *q = &intel_quirks[i];
7374		7374
7375	if (d->device == q->device &&	7375	if (d->device == q->device &&
7376	(d->subsystem_vendor == q->subsystem_vendor \|\|	7376	(d->subsystem_vendor == q->subsystem_vendor \|\|
7377	q->subsystem_vendor == PCI_ANY_ID) &&	7377	q->subsystem_vendor == PCI_ANY_ID) &&
7378	(d->subsystem_device == q->subsystem_device \|\|	7378	(d->subsystem_device == q->subsystem_device \|\|
7379	q->subsystem_device == PCI_ANY_ID))	7379	q->subsystem_device == PCI_ANY_ID))
7380	q->hook(dev);	7380	q->hook(dev);
7381	}	7381	}
7382	}	7382	}
7383		7383
7384	/* Disable the VGA plane that we never use */	7384	/* Disable the VGA plane that we never use */
7385	static void i915_disable_vga(struct drm_device *dev)	7385	static void i915_disable_vga(struct drm_device *dev)
7386	{	7386	{
7387	struct drm_i915_private *dev_priv = dev->dev_private;	7387	struct drm_i915_private *dev_priv = dev->dev_private;
7388	u8 sr1;	7388	u8 sr1;
7389	u32 vga_reg;	7389	u32 vga_reg;
7390		7390
7391	if (HAS_PCH_SPLIT(dev))	7391	if (HAS_PCH_SPLIT(dev))
7392	vga_reg = CPU_VGACNTRL;	7392	vga_reg = CPU_VGACNTRL;
7393	else	7393	else
7394	vga_reg = VGACNTRL;	7394	vga_reg = VGACNTRL;
7395		7395
7396	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);	7396	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7397	outb(1, VGA_SR_INDEX);	7397	outb(1, VGA_SR_INDEX);
7398	sr1 = inb(VGA_SR_DATA);	7398	sr1 = inb(VGA_SR_DATA);
7399	outb(sr1 \| 1<<5, VGA_SR_DATA);	7399	outb(sr1 \| 1<<5, VGA_SR_DATA);
7400	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);	7400	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7401	udelay(300);	7401	udelay(300);
7402		7402
7403	I915_WRITE(vga_reg, VGA_DISP_DISABLE);	7403	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7404	POSTING_READ(vga_reg);	7404	POSTING_READ(vga_reg);
7405	}	7405	}
7406		7406
7407	void intel_modeset_init(struct drm_device *dev)	7407	void intel_modeset_init(struct drm_device *dev)
7408	{	7408	{
7409	struct drm_i915_private *dev_priv = dev->dev_private;	7409	struct drm_i915_private *dev_priv = dev->dev_private;
7410	int i;	7410	int i;
7411		7411
7412	drm_mode_config_init(dev);	7412	drm_mode_config_init(dev);
7413		7413
7414	dev->mode_config.min_width = 0;	7414	dev->mode_config.min_width = 0;
7415	dev->mode_config.min_height = 0;	7415	dev->mode_config.min_height = 0;
7416		7416
7417	dev->mode_config.funcs = (void *)&intel_mode_funcs;	7417	dev->mode_config.funcs = (void *)&intel_mode_funcs;
7418		7418
7419	intel_init_quirks(dev);	7419	intel_init_quirks(dev);
7420		7420
7421	intel_init_display(dev);	7421	intel_init_display(dev);
7422		7422
7423	if (IS_GEN2(dev)) {	7423	if (IS_GEN2(dev)) {
7424	dev->mode_config.max_width = 2048;	7424	dev->mode_config.max_width = 2048;
7425	dev->mode_config.max_height = 2048;	7425	dev->mode_config.max_height = 2048;
7426	} else if (IS_GEN3(dev)) {	7426	} else if (IS_GEN3(dev)) {
7427	dev->mode_config.max_width = 4096;	7427	dev->mode_config.max_width = 4096;
7428	dev->mode_config.max_height = 4096;	7428	dev->mode_config.max_height = 4096;
7429	} else {	7429	} else {
7430	dev->mode_config.max_width = 8192;	7430	dev->mode_config.max_width = 8192;
7431	dev->mode_config.max_height = 8192;	7431	dev->mode_config.max_height = 8192;
7432	}	7432	}
7433	dev->mode_config.fb_base = dev->agp->base;	7433	dev->mode_config.fb_base = dev->agp->base;
7434		7434
7435	DRM_DEBUG_KMS("%d display pipe%s available.\n",	7435	DRM_DEBUG_KMS("%d display pipe%s available.\n",
7436	dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");	7436	dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7437		7437
7438	for (i = 0; i < dev_priv->num_pipe; i++) {	7438	for (i = 0; i < dev_priv->num_pipe; i++) {
7439	intel_crtc_init(dev, i);	7439	intel_crtc_init(dev, i);
7440	}	7440	}
7441		7441
7442	intel_setup_outputs(dev);	7442	intel_setup_outputs(dev);
7443		7443
7444	intel_enable_clock_gating(dev);	7444	intel_enable_clock_gating(dev);
7445		7445
7446	/* Just disable it once at startup */	7446	/* Just disable it once at startup */
7447	i915_disable_vga(dev);	7447	i915_disable_vga(dev);
7448		7448
7449	if (IS_IRONLAKE_M(dev)) {	7449	if (IS_IRONLAKE_M(dev)) {
7450	ironlake_enable_drps(dev);	7450	ironlake_enable_drps(dev);
7451	intel_init_emon(dev);	7451	intel_init_emon(dev);
7452	}	7452	}
7453		7453
7454	if (IS_GEN6(dev))	7454	if (IS_GEN6(dev))
7455	gen6_enable_rps(dev_priv);	7455	gen6_enable_rps(dev_priv);
7456		7456
7457	if (IS_IRONLAKE_M(dev))	7457	if (IS_IRONLAKE_M(dev))
7458	ironlake_enable_rc6(dev);	7458	ironlake_enable_rc6(dev);
7459		7459
7460	INIT_WORK(&dev_priv->idle_work, intel_idle_update);	7460	INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7461	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,	7461	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7462	(unsigned long)dev);	7462	(unsigned long)dev);
7463		7463
7464	intel_setup_overlay(dev);	7464	intel_setup_overlay(dev);
7465	}	7465	}
7466		7466
7467	void intel_modeset_cleanup(struct drm_device *dev)	7467	void intel_modeset_cleanup(struct drm_device *dev)
7468	{	7468	{
7469	struct drm_i915_private *dev_priv = dev->dev_private;	7469	struct drm_i915_private *dev_priv = dev->dev_private;
7470	struct drm_crtc *crtc;	7470	struct drm_crtc *crtc;
7471	struct intel_crtc *intel_crtc;	7471	struct intel_crtc *intel_crtc;
7472		7472
7473	drm_kms_helper_poll_fini(dev);	7473	drm_kms_helper_poll_fini(dev);
7474	mutex_lock(&dev->struct_mutex);	7474	mutex_lock(&dev->struct_mutex);
7475		7475
7476	intel_unregister_dsm_handler();	7476	intel_unregister_dsm_handler();
7477		7477
7478		7478
7479	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {	7479	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7480	/* Skip inactive CRTCs */	7480	/* Skip inactive CRTCs */
7481	if (!crtc->fb)	7481	if (!crtc->fb)
7482	continue;	7482	continue;
7483		7483
7484	intel_crtc = to_intel_crtc(crtc);	7484	intel_crtc = to_intel_crtc(crtc);
7485	intel_increase_pllclock(crtc);	7485	intel_increase_pllclock(crtc);
7486	}	7486	}
7487		7487
7488	if (dev_priv->display.disable_fbc)	7488	if (dev_priv->display.disable_fbc)
7489	dev_priv->display.disable_fbc(dev);	7489	dev_priv->display.disable_fbc(dev);
7490		7490
7491	if (IS_IRONLAKE_M(dev))	7491	if (IS_IRONLAKE_M(dev))
7492	ironlake_disable_drps(dev);	7492	ironlake_disable_drps(dev);
7493	if (IS_GEN6(dev))	7493	if (IS_GEN6(dev))
7494	gen6_disable_rps(dev);	7494	gen6_disable_rps(dev);
7495		7495
7496	if (IS_IRONLAKE_M(dev))	7496	if (IS_IRONLAKE_M(dev))
7497	ironlake_disable_rc6(dev);	7497	ironlake_disable_rc6(dev);
7498		7498
7499	mutex_unlock(&dev->struct_mutex);	7499	mutex_unlock(&dev->struct_mutex);
7500		7500
7501	/* Disable the irq before mode object teardown, for the irq might	7501	/* Disable the irq before mode object teardown, for the irq might
7502	* enqueue unpin/hotplug work. */	7502	* enqueue unpin/hotplug work. */
7503	drm_irq_uninstall(dev);	7503	drm_irq_uninstall(dev);
7504	cancel_work_sync(&dev_priv->hotplug_work);	7504	cancel_work_sync(&dev_priv->hotplug_work);
7505		7505
7506	/* Shut off idle work before the crtcs get freed. */	7506	/* Shut off idle work before the crtcs get freed. */
7507	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {	7507	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7508	intel_crtc = to_intel_crtc(crtc);	7508	intel_crtc = to_intel_crtc(crtc);
7509	del_timer_sync(&intel_crtc->idle_timer);	7509	del_timer_sync(&intel_crtc->idle_timer);
7510	}	7510	}
7511	del_timer_sync(&dev_priv->idle_timer);	7511	del_timer_sync(&dev_priv->idle_timer);
7512	cancel_work_sync(&dev_priv->idle_work);	7512	cancel_work_sync(&dev_priv->idle_work);
7513		7513
7514	drm_mode_config_cleanup(dev);	7514	drm_mode_config_cleanup(dev);
7515	}	7515	}
7516		7516
7517	/*	7517	/*
7518	* Return which encoder is currently attached for connector.	7518	* Return which encoder is currently attached for connector.
7519	*/	7519	*/
7520	struct drm_encoder intel_best_encoder(struct drm_connector connector)	7520	struct drm_encoder intel_best_encoder(struct drm_connector connector)
7521	{	7521	{
7522	return &intel_attached_encoder(connector)->base;	7522	return &intel_attached_encoder(connector)->base;
7523	}	7523	}
7524		7524
7525	void intel_connector_attach_encoder(struct intel_connector *connector,	7525	void intel_connector_attach_encoder(struct intel_connector *connector,
7526	struct intel_encoder *encoder)	7526	struct intel_encoder *encoder)
7527	{	7527	{
7528	connector->encoder = encoder;	7528	connector->encoder = encoder;
7529	drm_mode_connector_attach_encoder(&connector->base,	7529	drm_mode_connector_attach_encoder(&connector->base,
7530	&encoder->base);	7530	&encoder->base);
7531	}	7531	}
7532		7532
7533	/*	7533	/*
7534	* set vga decode state - true == enable VGA decode	7534	* set vga decode state - true == enable VGA decode
7535	*/	7535	*/
7536	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)	7536	int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7537	{	7537	{
7538	struct drm_i915_private *dev_priv = dev->dev_private;	7538	struct drm_i915_private *dev_priv = dev->dev_private;
7539	u16 gmch_ctrl;	7539	u16 gmch_ctrl;
7540		7540
7541	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);	7541	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7542	if (state)	7542	if (state)
7543	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;	7543	gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7544	else	7544	else
7545	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;	7545	gmch_ctrl \|= INTEL_GMCH_VGA_DISABLE;
7546	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);	7546	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7547	return 0;	7547	return 0;
7548	}	7548	}
7549		7549
7550	#ifdef CONFIG_DEBUG_FS	7550	#ifdef CONFIG_DEBUG_FS
7551	#include <linux/seq_file.h>	7551	#include <linux/seq_file.h>
7552		7552
7553	struct intel_display_error_state {	7553	struct intel_display_error_state {
7554	struct intel_cursor_error_state {	7554	struct intel_cursor_error_state {
7555	u32 control;	7555	u32 control;
7556	u32 position;	7556	u32 position;
7557	u32 base;	7557	u32 base;
7558	u32 size;	7558	u32 size;
7559	} cursor[2];	7559	} cursor[2];
7560		7560
7561	struct intel_pipe_error_state {	7561	struct intel_pipe_error_state {
7562	u32 conf;	7562	u32 conf;
7563	u32 source;	7563	u32 source;
7564		7564
7565	u32 htotal;	7565	u32 htotal;
7566	u32 hblank;	7566	u32 hblank;
7567	u32 hsync;	7567	u32 hsync;
7568	u32 vtotal;	7568	u32 vtotal;
7569	u32 vblank;	7569	u32 vblank;
7570	u32 vsync;	7570	u32 vsync;
7571	} pipe[2];	7571	} pipe[2];
7572		7572
7573	struct intel_plane_error_state {	7573	struct intel_plane_error_state {
7574	u32 control;	7574	u32 control;
7575	u32 stride;	7575	u32 stride;
7576	u32 size;	7576	u32 size;
7577	u32 pos;	7577	u32 pos;
7578	u32 addr;	7578	u32 addr;
7579	u32 surface;	7579	u32 surface;
7580	u32 tile_offset;	7580	u32 tile_offset;
7581	} plane[2];	7581	} plane[2];
7582	};	7582	};
7583		7583
7584	struct intel_display_error_state *	7584	struct intel_display_error_state *
7585	intel_display_capture_error_state(struct drm_device *dev)	7585	intel_display_capture_error_state(struct drm_device *dev)
7586	{	7586	{
7587	drm_i915_private_t *dev_priv = dev->dev_private;	7587	drm_i915_private_t *dev_priv = dev->dev_private;
7588	struct intel_display_error_state *error;	7588	struct intel_display_error_state *error;
7589	int i;	7589	int i;
7590		7590
7591	error = kmalloc(sizeof(*error), GFP_ATOMIC);	7591	error = kmalloc(sizeof(*error), GFP_ATOMIC);
7592	if (error == NULL)	7592	if (error == NULL)
7593	return NULL;	7593	return NULL;
7594		7594
7595	for (i = 0; i < 2; i++) {	7595	for (i = 0; i < 2; i++) {
7596	error->cursor[i].control = I915_READ(CURCNTR(i));	7596	error->cursor[i].control = I915_READ(CURCNTR(i));
7597	error->cursor[i].position = I915_READ(CURPOS(i));	7597	error->cursor[i].position = I915_READ(CURPOS(i));
7598	error->cursor[i].base = I915_READ(CURBASE(i));	7598	error->cursor[i].base = I915_READ(CURBASE(i));
7599		7599
7600	error->plane[i].control = I915_READ(DSPCNTR(i));	7600	error->plane[i].control = I915_READ(DSPCNTR(i));
7601	error->plane[i].stride = I915_READ(DSPSTRIDE(i));	7601	error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7602	error->plane[i].size = I915_READ(DSPSIZE(i));	7602	error->plane[i].size = I915_READ(DSPSIZE(i));
7603	error->plane[i].pos= I915_READ(DSPPOS(i));	7603	error->plane[i].pos= I915_READ(DSPPOS(i));
7604	error->plane[i].addr = I915_READ(DSPADDR(i));	7604	error->plane[i].addr = I915_READ(DSPADDR(i));
7605	if (INTEL_INFO(dev)->gen >= 4) {	7605	if (INTEL_INFO(dev)->gen >= 4) {
7606	error->plane[i].surface = I915_READ(DSPSURF(i));	7606	error->plane[i].surface = I915_READ(DSPSURF(i));
7607	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));	7607	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7608	}	7608	}
7609		7609
7610	error->pipe[i].conf = I915_READ(PIPECONF(i));	7610	error->pipe[i].conf = I915_READ(PIPECONF(i));
7611	error->pipe[i].source = I915_READ(PIPESRC(i));	7611	error->pipe[i].source = I915_READ(PIPESRC(i));
7612	error->pipe[i].htotal = I915_READ(HTOTAL(i));	7612	error->pipe[i].htotal = I915_READ(HTOTAL(i));
7613	error->pipe[i].hblank = I915_READ(HBLANK(i));	7613	error->pipe[i].hblank = I915_READ(HBLANK(i));
7614	error->pipe[i].hsync = I915_READ(HSYNC(i));	7614	error->pipe[i].hsync = I915_READ(HSYNC(i));
7615	error->pipe[i].vtotal = I915_READ(VTOTAL(i));	7615	error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7616	error->pipe[i].vblank = I915_READ(VBLANK(i));	7616	error->pipe[i].vblank = I915_READ(VBLANK(i));
7617	error->pipe[i].vsync = I915_READ(VSYNC(i));	7617	error->pipe[i].vsync = I915_READ(VSYNC(i));
7618	}	7618	}
7619		7619
7620	return error;	7620	return error;
7621	}	7621	}
7622		7622
7623	void	7623	void
7624	intel_display_print_error_state(struct seq_file *m,	7624	intel_display_print_error_state(struct seq_file *m,
7625	struct drm_device *dev,	7625	struct drm_device *dev,
7626	struct intel_display_error_state *error)	7626	struct intel_display_error_state *error)
7627	{	7627	{
7628	int i;	7628	int i;
7629		7629
7630	for (i = 0; i < 2; i++) {	7630	for (i = 0; i < 2; i++) {
7631	seq_printf(m, "Pipe [%d]:\n", i);	7631	seq_printf(m, "Pipe [%d]:\n", i);
7632	seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);	7632	seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7633	seq_printf(m, " SRC: %08x\n", error->pipe[i].source);	7633	seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7634	seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);	7634	seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7635	seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);	7635	seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7636	seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);	7636	seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7637	seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);	7637	seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7638	seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);	7638	seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7639	seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);	7639	seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7640		7640
7641	seq_printf(m, "Plane [%d]:\n", i);	7641	seq_printf(m, "Plane [%d]:\n", i);
7642	seq_printf(m, " CNTR: %08x\n", error->plane[i].control);	7642	seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7643	seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);	7643	seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7644	seq_printf(m, " SIZE: %08x\n", error->plane[i].size);	7644	seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7645	seq_printf(m, " POS: %08x\n", error->plane[i].pos);	7645	seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7646	seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);	7646	seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7647	if (INTEL_INFO(dev)->gen >= 4) {	7647	if (INTEL_INFO(dev)->gen >= 4) {
7648	seq_printf(m, " SURF: %08x\n", error->plane[i].surface);	7648	seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7649	seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);	7649	seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7650	}	7650	}
7651		7651
7652	seq_printf(m, "Cursor [%d]:\n", i);	7652	seq_printf(m, "Cursor [%d]:\n", i);
7653	seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);	7653	seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7654	seq_printf(m, " POS: %08x\n", error->cursor[i].position);	7654	seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7655	seq_printf(m, " BASE: %08x\n", error->cursor[i].base);	7655	seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7656	}	7656	}
7657	}	7657	}
7658	#endif	7658	#endif
7659		7659

drivers/gpu/drm/radeon/radeon_display.c

Diff comments View file @ bbb0aef

 /*
  * Copyright 2007-8 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Dave Airlie
  *          Alex Deucher
  */
 #include "drmP.h"
 #include "radeon_drm.h"
 #include "radeon.h"
 #include "atom.h"
 #include <asm/div64.h>
 #include "drm_crtc_helper.h"
 #include "drm_edid.h"
 static int radeon_ddc_dump(struct drm_connector *connector);
 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int i;
 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
 	WREG32(AVIVO_DC_LUT_RW_MODE, 0);
 	WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
 	WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
 	for (i = 0; i < 256; i++) {
 		WREG32(AVIVO_DC_LUT_30_COLOR,
 			     (radeon_crtc->lut_r[i] << 20) |
 			     (radeon_crtc->lut_g[i] << 10) |
 			     (radeon_crtc->lut_b[i] << 0));
 	}
 	WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
 }
 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int i;
 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 	for (i = 0; i < 256; i++) {
 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 		       (radeon_crtc->lut_r[i] << 20) |
 		       (radeon_crtc->lut_g[i] << 10) |
 		       (radeon_crtc->lut_b[i] << 0));
 	}
 }
 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int i;
 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 		NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 	       NI_GRPH_PRESCALE_BYPASS);
 	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 	       NI_OVL_PRESCALE_BYPASS);
 	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 		NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 	for (i = 0; i < 256; i++) {
 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 		       (radeon_crtc->lut_r[i] << 20) |
 		       (radeon_crtc->lut_g[i] << 10) |
 		       (radeon_crtc->lut_b[i] << 0));
 	}
 	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 		NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 		NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 		NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 		NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 		NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 	       (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 		NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
 	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 }
 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int i;
 	uint32_t dac2_cntl;
 	dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 	if (radeon_crtc->crtc_id == 0)
 		dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 	else
 		dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 	WREG8(RADEON_PALETTE_INDEX, 0);
 	for (i = 0; i < 256; i++) {
 		WREG32(RADEON_PALETTE_30_DATA,
 			     (radeon_crtc->lut_r[i] << 20) |
 			     (radeon_crtc->lut_g[i] << 10) |
 			     (radeon_crtc->lut_b[i] << 0));
 	}
 }
 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	if (!crtc->enabled)
 		return;
 	if (ASIC_IS_DCE5(rdev))
 		dce5_crtc_load_lut(crtc);
 	else if (ASIC_IS_DCE4(rdev))
 		dce4_crtc_load_lut(crtc);
 	else if (ASIC_IS_AVIVO(rdev))
 		avivo_crtc_load_lut(crtc);
 	else
 		legacy_crtc_load_lut(crtc);
 }
 /** Sets the color ramps on behalf of fbcon */
 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 			      u16 blue, int regno)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	radeon_crtc->lut_r[regno] = red >> 6;
 	radeon_crtc->lut_g[regno] = green >> 6;
 	radeon_crtc->lut_b[regno] = blue >> 6;
 }
 /** Gets the color ramps on behalf of fbcon */
 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 			      u16 *blue, int regno)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	*red = radeon_crtc->lut_r[regno] << 6;
 	*green = radeon_crtc->lut_g[regno] << 6;
 	*blue = radeon_crtc->lut_b[regno] << 6;
 }
 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 				  u16 *blue, uint32_t start, uint32_t size)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	int end = (start + size > 256) ? 256 : start + size, i;
 	/* userspace palettes are always correct as is */
 	for (i = start; i < end; i++) {
 		radeon_crtc->lut_r[i] = red[i] >> 6;
 		radeon_crtc->lut_g[i] = green[i] >> 6;
 		radeon_crtc->lut_b[i] = blue[i] >> 6;
 	}
 	radeon_crtc_load_lut(crtc);
 }
 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	drm_crtc_cleanup(crtc);
 	kfree(radeon_crtc);
 }
 /*
  * Handle unpin events outside the interrupt handler proper.
  */
 static void radeon_unpin_work_func(struct work_struct *__work)
 {
 	struct radeon_unpin_work *work =
 		container_of(__work, struct radeon_unpin_work, work);
 	int r;
 	/* unpin of the old buffer */
 	r = radeon_bo_reserve(work->old_rbo, false);
 	if (likely(r == 0)) {
 		r = radeon_bo_unpin(work->old_rbo);
 		if (unlikely(r != 0)) {
 			DRM_ERROR("failed to unpin buffer after flip\n");
 		}
 		radeon_bo_unreserve(work->old_rbo);
 	} else
 		DRM_ERROR("failed to reserve buffer after flip\n");
 	kfree(work);
 }
 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 {
 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 	struct radeon_unpin_work *work;
 	struct drm_pending_vblank_event *e;
 	struct timeval now;
 	unsigned long flags;
 	u32 update_pending;
 	int vpos, hpos;
 	spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 	work = radeon_crtc->unpin_work;
 	if (work == NULL ||
 	    !radeon_fence_signaled(work->fence)) {
 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 		return;
 	}
 	/* New pageflip, or just completion of a previous one? */
 	if (!radeon_crtc->deferred_flip_completion) {
 		/* do the flip (mmio) */
 		update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 	} else {
 		/* This is just a completion of a flip queued in crtc
 		 * at last invocation. Make sure we go directly to
 		 * completion routine.
 		 */
 		update_pending = 0;
 		radeon_crtc->deferred_flip_completion = 0;
 	}
 	/* Has the pageflip already completed in crtc, or is it certain
 	 * to complete in this vblank?
 	 */
 	if (update_pending &&
 	    (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 							       &vpos, &hpos)) &&
 	    (vpos >=0) &&
 	    (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
 		/* crtc didn't flip in this target vblank interval,
 		 * but flip is pending in crtc. It will complete it
 		 * in next vblank interval, so complete the flip at
 		 * next vblank irq.
 		 */
 		radeon_crtc->deferred_flip_completion = 1;
 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 		return;
 	}
 	/* Pageflip (will be) certainly completed in this vblank. Clean up. */
 	radeon_crtc->unpin_work = NULL;
 	/* wakeup userspace */
 	if (work->event) {
 		e = work->event;
 		e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
 		e->event.tv_sec = now.tv_sec;
 		e->event.tv_usec = now.tv_usec;
 		list_add_tail(&e->base.link, &e->base.file_priv->event_list);
 		wake_up_interruptible(&e->base.file_priv->event_wait);
 	}
 	spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 	drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 	radeon_fence_unref(&work->fence);
 	radeon_post_page_flip(work->rdev, work->crtc_id);
 	schedule_work(&work->work);
 }
 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
 				 struct drm_pending_vblank_event *event)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct radeon_framebuffer *old_radeon_fb;
 	struct radeon_framebuffer *new_radeon_fb;
 	struct drm_gem_object *obj;
 	struct radeon_bo *rbo;
 	struct radeon_fence *fence;
 	struct radeon_unpin_work *work;
 	unsigned long flags;
 	u32 tiling_flags, pitch_pixels;
 	u64 base;
 	int r;
 	work = kzalloc(sizeof *work, GFP_KERNEL);
 	if (work == NULL)
 		return -ENOMEM;
 	r = radeon_fence_create(rdev, &fence);
 	if (unlikely(r != 0)) {
 		kfree(work);
 		DRM_ERROR("flip queue: failed to create fence.\n");
 		return -ENOMEM;
 	}
 	work->event = event;
 	work->rdev = rdev;
 	work->crtc_id = radeon_crtc->crtc_id;
 	work->fence = radeon_fence_ref(fence);
 	old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 	new_radeon_fb = to_radeon_framebuffer(fb);
 	/* schedule unpin of the old buffer */
 	obj = old_radeon_fb->obj;
 	rbo = gem_to_radeon_bo(obj);
 	work->old_rbo = rbo;
 	INIT_WORK(&work->work, radeon_unpin_work_func);
 	/* We borrow the event spin lock for protecting unpin_work */
 	spin_lock_irqsave(&dev->event_lock, flags);
 	if (radeon_crtc->unpin_work) {
 		spin_unlock_irqrestore(&dev->event_lock, flags);
 		kfree(work);
 		radeon_fence_unref(&fence);
 		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 		return -EBUSY;
 	}
 	radeon_crtc->unpin_work = work;
 	radeon_crtc->deferred_flip_completion = 0;
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	/* pin the new buffer */
 	obj = new_radeon_fb->obj;
 	rbo = gem_to_radeon_bo(obj);
 	DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 			 work->old_rbo, rbo);
 	r = radeon_bo_reserve(rbo, false);
 	if (unlikely(r != 0)) {
 		DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 		goto pflip_cleanup;
 	}
 	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 	if (unlikely(r != 0)) {
 		radeon_bo_unreserve(rbo);
 		r = -EINVAL;
 		DRM_ERROR("failed to pin new rbo buffer before flip\n");
 		goto pflip_cleanup;
 	}
 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 	radeon_bo_unreserve(rbo);
 	if (!ASIC_IS_AVIVO(rdev)) {
 		/* crtc offset is from display base addr not FB location */
 		base -= radeon_crtc->legacy_display_base_addr;
 		pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8);
 		if (tiling_flags & RADEON_TILING_MACRO) {
 			if (ASIC_IS_R300(rdev)) {
 				base &= ~0x7ff;
 			} else {
 				int byteshift = fb->bits_per_pixel >> 4;
 				int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 				base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 			}
 		} else {
 			int offset = crtc->y * pitch_pixels + crtc->x;
 			switch (fb->bits_per_pixel) {
 			case 8:
 			default:
 				offset *= 1;
 				break;
 			case 15:
 			case 16:
 				offset *= 2;
 				break;
 			case 24:
 				offset *= 3;
 				break;
 			case 32:
 				offset *= 4;
 				break;
 			}
 			base += offset;
 		}
 		base &= ~7;
 	}
 	spin_lock_irqsave(&dev->event_lock, flags);
 	work->new_crtc_base = base;
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	/* update crtc fb */
 	crtc->fb = fb;
 	r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 	if (r) {
 		DRM_ERROR("failed to get vblank before flip\n");
 		goto pflip_cleanup1;
 	}
 	/* 32 ought to cover us */
 	r = radeon_ring_lock(rdev, 32);
 	if (r) {
 		DRM_ERROR("failed to lock the ring before flip\n");
 		goto pflip_cleanup2;
 	}
 	/* emit the fence */
 	radeon_fence_emit(rdev, fence);
 	/* set the proper interrupt */
 	radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 	/* fire the ring */
 	radeon_ring_unlock_commit(rdev);
 	return 0;
 pflip_cleanup2:
 	drm_vblank_put(dev, radeon_crtc->crtc_id);
 pflip_cleanup1:
 	r = radeon_bo_reserve(rbo, false);
 	if (unlikely(r != 0)) {
 		DRM_ERROR("failed to reserve new rbo in error path\n");
 		goto pflip_cleanup;
 	}
 	r = radeon_bo_unpin(rbo);
 	if (unlikely(r != 0)) {
 		radeon_bo_unreserve(rbo);
 		r = -EINVAL;
 		DRM_ERROR("failed to unpin new rbo in error path\n");
 		goto pflip_cleanup;
 	}
 	radeon_bo_unreserve(rbo);
 pflip_cleanup:
 	spin_lock_irqsave(&dev->event_lock, flags);
 	radeon_crtc->unpin_work = NULL;
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	radeon_fence_unref(&fence);
 	kfree(work);
 	return r;
 }
 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 	.cursor_set = radeon_crtc_cursor_set,
 	.cursor_move = radeon_crtc_cursor_move,
 	.gamma_set = radeon_crtc_gamma_set,
 	.set_config = drm_crtc_helper_set_config,
 	.destroy = radeon_crtc_destroy,
 	.page_flip = radeon_crtc_page_flip,
 };
 static void radeon_crtc_init(struct drm_device *dev, int index)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc;
 	int i;
 	radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 	if (radeon_crtc == NULL)
 		return;
 	drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 	drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 	radeon_crtc->crtc_id = index;
 	rdev->mode_info.crtcs[index] = radeon_crtc;
 #if 0
 	radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 	radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 	radeon_crtc->mode_set.num_connectors = 0;
 #endif
 	for (i = 0; i < 256; i++) {
 		radeon_crtc->lut_r[i] = i << 2;
 		radeon_crtc->lut_g[i] = i << 2;
 		radeon_crtc->lut_b[i] = i << 2;
 	}
 	if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 		radeon_atombios_init_crtc(dev, radeon_crtc);
 	else
 		radeon_legacy_init_crtc(dev, radeon_crtc);
 }
 static const char *encoder_names[36] = {
 	"NONE",
 	"INTERNAL_LVDS",
 	"INTERNAL_TMDS1",
 	"INTERNAL_TMDS2",
 	"INTERNAL_DAC1",
 	"INTERNAL_DAC2",
 	"INTERNAL_SDVOA",
 	"INTERNAL_SDVOB",
 	"SI170B",
 	"CH7303",
 	"CH7301",
 	"INTERNAL_DVO1",
 	"EXTERNAL_SDVOA",
 	"EXTERNAL_SDVOB",
 	"TITFP513",
 	"INTERNAL_LVTM1",
 	"VT1623",
 	"HDMI_SI1930",
 	"HDMI_INTERNAL",
 	"INTERNAL_KLDSCP_TMDS1",
 	"INTERNAL_KLDSCP_DVO1",
 	"INTERNAL_KLDSCP_DAC1",
 	"INTERNAL_KLDSCP_DAC2",
 	"SI178",
 	"MVPU_FPGA",
 	"INTERNAL_DDI",
 	"VT1625",
 	"HDMI_SI1932",
 	"DP_AN9801",
 	"DP_DP501",
 	"INTERNAL_UNIPHY",
 	"INTERNAL_KLDSCP_LVTMA",
 	"INTERNAL_UNIPHY1",
 	"INTERNAL_UNIPHY2",
 	"NUTMEG",
 	"TRAVIS",
 };
 static const char *connector_names[15] = {
 	"Unknown",
 	"VGA",
 	"DVI-I",
 	"DVI-D",
 	"DVI-A",
 	"Composite",
 	"S-video",
 	"LVDS",
 	"Component",
 	"DIN",
 	"DisplayPort",
 	"HDMI-A",
 	"HDMI-B",
 	"TV",
 	"eDP",
 };
 static const char *hpd_names[6] = {
 	"HPD1",
 	"HPD2",
 	"HPD3",
 	"HPD4",
 	"HPD5",
 	"HPD6",
 };
 static void radeon_print_display_setup(struct drm_device *dev)
 {
 	struct drm_connector *connector;
 	struct radeon_connector *radeon_connector;
 	struct drm_encoder *encoder;
 	struct radeon_encoder *radeon_encoder;
 	uint32_t devices;
 	int i = 0;
 	DRM_INFO("Radeon Display Connectors\n");
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		radeon_connector = to_radeon_connector(connector);
 		DRM_INFO("Connector %d:\n", i);
 		DRM_INFO("  %s\n", connector_names[connector->connector_type]);
 		if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 			DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 		if (radeon_connector->ddc_bus) {
 			DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 				 radeon_connector->ddc_bus->rec.mask_clk_reg,
 				 radeon_connector->ddc_bus->rec.mask_data_reg,
 				 radeon_connector->ddc_bus->rec.a_clk_reg,
 				 radeon_connector->ddc_bus->rec.a_data_reg,
 				 radeon_connector->ddc_bus->rec.en_clk_reg,
 				 radeon_connector->ddc_bus->rec.en_data_reg,
 				 radeon_connector->ddc_bus->rec.y_clk_reg,
 				 radeon_connector->ddc_bus->rec.y_data_reg);
 			if (radeon_connector->router.ddc_valid)
 				DRM_INFO("  DDC Router 0x%x/0x%x\n",
 					 radeon_connector->router.ddc_mux_control_pin,
 					 radeon_connector->router.ddc_mux_state);
 			if (radeon_connector->router.cd_valid)
 				DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 					 radeon_connector->router.cd_mux_control_pin,
 					 radeon_connector->router.cd_mux_state);
 		} else {
 			if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 				DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 		}
 		DRM_INFO("  Encoders:\n");
 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 			radeon_encoder = to_radeon_encoder(encoder);
 			devices = radeon_encoder->devices & radeon_connector->devices;
 			if (devices) {
 				if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 					DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 					DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 					DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 					DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 					DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 					DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 					DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 					DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 					DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_TV1_SUPPORT)
 					DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 				if (devices & ATOM_DEVICE_CV_SUPPORT)
 					DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 			}
 		}
 		i++;
 	}
 }
 static bool radeon_setup_enc_conn(struct drm_device *dev)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	struct drm_connector *drm_connector;
 	bool ret = false;
 	if (rdev->bios) {
 		if (rdev->is_atom_bios) {
 			ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 			if (ret == false)
 				ret = radeon_get_atom_connector_info_from_object_table(dev);
 		} else {
 			ret = radeon_get_legacy_connector_info_from_bios(dev);
 			if (ret == false)
 				ret = radeon_get_legacy_connector_info_from_table(dev);
 		}
 	} else {
 		if (!ASIC_IS_AVIVO(rdev))
 			ret = radeon_get_legacy_connector_info_from_table(dev);
 	}
 	if (ret) {
 		radeon_setup_encoder_clones(dev);
 		radeon_print_display_setup(dev);
 		list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
 			radeon_ddc_dump(drm_connector);
 	}
 	return ret;
 }
 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 {
 	struct drm_device *dev = radeon_connector->base.dev;
 	struct radeon_device *rdev = dev->dev_private;
 	int ret = 0;
 	/* on hw with routers, select right port */
 	if (radeon_connector->router.ddc_valid)
 		radeon_router_select_ddc_port(radeon_connector);
 	if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 	    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 		struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 		if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 		     dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 			radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
 	}
 	if (!radeon_connector->ddc_bus)
 		return -1;
 	if (!radeon_connector->edid) {
 		radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
 	}
 	if (!radeon_connector->edid) {
 		if (rdev->is_atom_bios) {
 			/* some laptops provide a hardcoded edid in rom for LCDs */
 			if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 			     (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 				radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 		} else
 			/* some servers provide a hardcoded edid in rom for KVMs */
 			radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 	}
 	if (radeon_connector->edid) {
 		drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 		ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 		return ret;
 	}
 	drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 	return 0;
 }
 static int radeon_ddc_dump(struct drm_connector *connector)
 {
 	struct edid *edid;
 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 	int ret = 0;
 	/* on hw with routers, select right port */
 	if (radeon_connector->router.ddc_valid)
 		radeon_router_select_ddc_port(radeon_connector);
 	if (!radeon_connector->ddc_bus)
 		return -1;
 	edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
 	if (edid) {
 		kfree(edid);
 	}
 	return ret;
 }
 /* avivo */
 static void avivo_get_fb_div(struct radeon_pll *pll,
 			     u32 target_clock,
 			     u32 post_div,
 			     u32 ref_div,
 			     u32 *fb_div,
 			     u32 *frac_fb_div)
 {
 	u32 tmp = post_div * ref_div;
 	tmp *= target_clock;
 	*fb_div = tmp / pll->reference_freq;
 	*frac_fb_div = tmp % pll->reference_freq;
         if (*fb_div > pll->max_feedback_div)
 		*fb_div = pll->max_feedback_div;
         else if (*fb_div < pll->min_feedback_div)
                 *fb_div = pll->min_feedback_div;
 }
 static u32 avivo_get_post_div(struct radeon_pll *pll,
 			      u32 target_clock)
 {
 	u32 vco, post_div, tmp;
 	if (pll->flags & RADEON_PLL_USE_POST_DIV)
 		return pll->post_div;
 	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 		if (pll->flags & RADEON_PLL_IS_LCD)
 			vco = pll->lcd_pll_out_min;
 		else
 			vco = pll->pll_out_min;
 	} else {
 		if (pll->flags & RADEON_PLL_IS_LCD)
 			vco = pll->lcd_pll_out_max;
 		else
 			vco = pll->pll_out_max;
 	}
 	post_div = vco / target_clock;
 	tmp = vco % target_clock;
 	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 		if (tmp)
 			post_div++;
 	} else {
 		if (!tmp)
 			post_div--;
 	}
 	if (post_div > pll->max_post_div)
 		post_div = pll->max_post_div;
 	else if (post_div < pll->min_post_div)
 		post_div = pll->min_post_div;
 	return post_div;
 }
 #define MAX_TOLERANCE 10
 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 			      u32 freq,
 			      u32 *dot_clock_p,
 			      u32 *fb_div_p,
 			      u32 *frac_fb_div_p,
 			      u32 *ref_div_p,
 			      u32 *post_div_p)
 {
 	u32 target_clock = freq / 10;
 	u32 post_div = avivo_get_post_div(pll, target_clock);
 	u32 ref_div = pll->min_ref_div;
 	u32 fb_div = 0, frac_fb_div = 0, tmp;
 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
 		ref_div = pll->reference_div;
 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 		avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 		frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 		if (frac_fb_div >= 5) {
 			frac_fb_div -= 5;
 			frac_fb_div = frac_fb_div / 10;
 			frac_fb_div++;
 		}
 		if (frac_fb_div >= 10) {
 			fb_div++;
 			frac_fb_div = 0;
 		}
 	} else {
 		while (ref_div <= pll->max_ref_div) {
 			avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 					 &fb_div, &frac_fb_div);
 			if (frac_fb_div >= (pll->reference_freq / 2))
 				fb_div++;
 			frac_fb_div = 0;
 			tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 			tmp = (tmp * 10000) / target_clock;
 			if (tmp > (10000 + MAX_TOLERANCE))
 				ref_div++;
 			else if (tmp >= (10000 - MAX_TOLERANCE))
 				break;
 			else
 				ref_div++;
 		}
 	}
 	*dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 		(ref_div * post_div * 10);
 	*fb_div_p = fb_div;
 	*frac_fb_div_p = frac_fb_div;
 	*ref_div_p = ref_div;
 	*post_div_p = post_div;
 	DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 		      *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 }
 /* pre-avivo */
 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 {
 	uint64_t mod;
 	n += d / 2;
 	mod = do_div(n, d);
 	return n;
 }
 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 			       uint64_t freq,
 			       uint32_t *dot_clock_p,
 			       uint32_t *fb_div_p,
 			       uint32_t *frac_fb_div_p,
 			       uint32_t *ref_div_p,
 			       uint32_t *post_div_p)
 {
 	uint32_t min_ref_div = pll->min_ref_div;
 	uint32_t max_ref_div = pll->max_ref_div;
 	uint32_t min_post_div = pll->min_post_div;
 	uint32_t max_post_div = pll->max_post_div;
 	uint32_t min_fractional_feed_div = 0;
 	uint32_t max_fractional_feed_div = 0;
 	uint32_t best_vco = pll->best_vco;
 	uint32_t best_post_div = 1;
 	uint32_t best_ref_div = 1;
 	uint32_t best_feedback_div = 1;
 	uint32_t best_frac_feedback_div = 0;
 	uint32_t best_freq = -1;
 	uint32_t best_error = 0xffffffff;
 	uint32_t best_vco_diff = 1;
 	uint32_t post_div;
 	u32 pll_out_min, pll_out_max;
 	DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 	freq = freq * 1000;
 	if (pll->flags & RADEON_PLL_IS_LCD) {
 		pll_out_min = pll->lcd_pll_out_min;
 		pll_out_max = pll->lcd_pll_out_max;
 	} else {
 		pll_out_min = pll->pll_out_min;
 		pll_out_max = pll->pll_out_max;
 	}
 	if (pll_out_min > 64800)
 		pll_out_min = 64800;
 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
 		min_ref_div = max_ref_div = pll->reference_div;
 	else {
 		while (min_ref_div < max_ref_div-1) {
 			uint32_t mid = (min_ref_div + max_ref_div) / 2;
 			uint32_t pll_in = pll->reference_freq / mid;
 			if (pll_in < pll->pll_in_min)
 				max_ref_div = mid;
 			else if (pll_in > pll->pll_in_max)
 				min_ref_div = mid;
 			else
 				break;
 		}
 	}
 	if (pll->flags & RADEON_PLL_USE_POST_DIV)
 		min_post_div = max_post_div = pll->post_div;
 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 		min_fractional_feed_div = pll->min_frac_feedback_div;
 		max_fractional_feed_div = pll->max_frac_feedback_div;
 	}
 	for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 		uint32_t ref_div;
 		if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 			continue;
 		/* legacy radeons only have a few post_divs */
 		if (pll->flags & RADEON_PLL_LEGACY) {
 			if ((post_div == 5) ||
 			    (post_div == 7) ||
 			    (post_div == 9) ||
 			    (post_div == 10) ||
 			    (post_div == 11) ||
 			    (post_div == 13) ||
 			    (post_div == 14) ||
 			    (post_div == 15))
 				continue;
 		}
 		for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 			uint32_t feedback_div, current_freq = 0, error, vco_diff;
 			uint32_t pll_in = pll->reference_freq / ref_div;
 			uint32_t min_feed_div = pll->min_feedback_div;
 			uint32_t max_feed_div = pll->max_feedback_div + 1;
 			if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 				continue;
 			while (min_feed_div < max_feed_div) {
 				uint32_t vco;
 				uint32_t min_frac_feed_div = min_fractional_feed_div;
 				uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 				uint32_t frac_feedback_div;
 				uint64_t tmp;
 				feedback_div = (min_feed_div + max_feed_div) / 2;
 				tmp = (uint64_t)pll->reference_freq * feedback_div;
 				vco = radeon_div(tmp, ref_div);
 				if (vco < pll_out_min) {
 					min_feed_div = feedback_div + 1;
 					continue;
 				} else if (vco > pll_out_max) {
 					max_feed_div = feedback_div;
 					continue;
 				}
 				while (min_frac_feed_div < max_frac_feed_div) {
 					frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 					tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 					tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 					current_freq = radeon_div(tmp, ref_div * post_div);
 					if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 						if (freq < current_freq)
 							error = 0xffffffff;
 						else
 							error = freq - current_freq;
 					} else
 						error = abs(current_freq - freq);
 					vco_diff = abs(vco - best_vco);
 					if ((best_vco == 0 && error < best_error) ||
 					    (best_vco != 0 &&
 					     ((best_error > 100 && error < best_error - 100) ||
 					      (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 						best_post_div = post_div;
 						best_ref_div = ref_div;
 						best_feedback_div = feedback_div;
 						best_frac_feedback_div = frac_feedback_div;
 						best_freq = current_freq;
 						best_error = error;
 						best_vco_diff = vco_diff;
 					} else if (current_freq == freq) {
 						if (best_freq == -1) {
 							best_post_div = post_div;
 							best_ref_div = ref_div;
 							best_feedback_div = feedback_div;
 							best_frac_feedback_div = frac_feedback_div;
 							best_freq = current_freq;
 							best_error = error;
 							best_vco_diff = vco_diff;
 						} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 							best_post_div = post_div;
 							best_ref_div = ref_div;
 							best_feedback_div = feedback_div;
 							best_frac_feedback_div = frac_feedback_div;
 							best_freq = current_freq;
 							best_error = error;
 							best_vco_diff = vco_diff;
 						}
 					}
 					if (current_freq < freq)
 						min_frac_feed_div = frac_feedback_div + 1;
 					else
 						max_frac_feed_div = frac_feedback_div;
 				}
 				if (current_freq < freq)
 					min_feed_div = feedback_div + 1;
 				else
 					max_feed_div = feedback_div;
 			}
 		}
 	}
 	*dot_clock_p = best_freq / 10000;
 	*fb_div_p = best_feedback_div;
 	*frac_fb_div_p = best_frac_feedback_div;
 	*ref_div_p = best_ref_div;
 	*post_div_p = best_post_div;
-	DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
+	DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
-		      freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
+		      (long long)freq,
+		      best_freq / 1000, best_feedback_div, best_frac_feedback_div,
 		      best_ref_div, best_post_div);
 }
 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 {
 	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 	if (radeon_fb->obj) {
 		drm_gem_object_unreference_unlocked(radeon_fb->obj);
 	}
 	drm_framebuffer_cleanup(fb);
 	kfree(radeon_fb);
 }
 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 						  struct drm_file *file_priv,
 						  unsigned int *handle)
 {
 	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 	return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
 }
 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 	.destroy = radeon_user_framebuffer_destroy,
 	.create_handle = radeon_user_framebuffer_create_handle,
 };
 void
 radeon_framebuffer_init(struct drm_device *dev,
 			struct radeon_framebuffer *rfb,
 			struct drm_mode_fb_cmd *mode_cmd,
 			struct drm_gem_object *obj)
 {
 	rfb->obj = obj;
 	drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
 	drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 }
 static struct drm_framebuffer *
 radeon_user_framebuffer_create(struct drm_device *dev,
 			       struct drm_file *file_priv,
 			       struct drm_mode_fb_cmd *mode_cmd)
 {
 	struct drm_gem_object *obj;
 	struct radeon_framebuffer *radeon_fb;
 	obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
 	if (obj ==  NULL) {
 		dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 			"can't create framebuffer\n", mode_cmd->handle);
 		return ERR_PTR(-ENOENT);
 	}
 	radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
 	if (radeon_fb == NULL)
 		return ERR_PTR(-ENOMEM);
 	radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
 	return &radeon_fb->base;
 }
 static void radeon_output_poll_changed(struct drm_device *dev)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	radeon_fb_output_poll_changed(rdev);
 }
 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 	.fb_create = radeon_user_framebuffer_create,
 	.output_poll_changed = radeon_output_poll_changed
 };
 struct drm_prop_enum_list {
 	int type;
 	char *name;
 };
 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
 {	{ 0, "driver" },
 	{ 1, "bios" },
 };
 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
 {	{ TV_STD_NTSC, "ntsc" },
 	{ TV_STD_PAL, "pal" },
 	{ TV_STD_PAL_M, "pal-m" },
 	{ TV_STD_PAL_60, "pal-60" },
 	{ TV_STD_NTSC_J, "ntsc-j" },
 	{ TV_STD_SCART_PAL, "scart-pal" },
 	{ TV_STD_PAL_CN, "pal-cn" },
 	{ TV_STD_SECAM, "secam" },
 };
 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
 {	{ UNDERSCAN_OFF, "off" },
 	{ UNDERSCAN_ON, "on" },
 	{ UNDERSCAN_AUTO, "auto" },
 };
 static int radeon_modeset_create_props(struct radeon_device *rdev)
 {
 	int i, sz;
 	if (rdev->is_atom_bios) {
 		rdev->mode_info.coherent_mode_property =
 			drm_property_create(rdev->ddev,
 					    DRM_MODE_PROP_RANGE,
 					    "coherent", 2);
 		if (!rdev->mode_info.coherent_mode_property)
 			return -ENOMEM;
 		rdev->mode_info.coherent_mode_property->values[0] = 0;
 		rdev->mode_info.coherent_mode_property->values[1] = 1;
 	}
 	if (!ASIC_IS_AVIVO(rdev)) {
 		sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
 		rdev->mode_info.tmds_pll_property =
 			drm_property_create(rdev->ddev,
 					    DRM_MODE_PROP_ENUM,
 					    "tmds_pll", sz);
 		for (i = 0; i < sz; i++) {
 			drm_property_add_enum(rdev->mode_info.tmds_pll_property,
 					      i,
 					      radeon_tmds_pll_enum_list[i].type,
 					      radeon_tmds_pll_enum_list[i].name);
 		}
 	}
 	rdev->mode_info.load_detect_property =
 		drm_property_create(rdev->ddev,
 				    DRM_MODE_PROP_RANGE,
 				    "load detection", 2);
 	if (!rdev->mode_info.load_detect_property)
 		return -ENOMEM;
 	rdev->mode_info.load_detect_property->values[0] = 0;
 	rdev->mode_info.load_detect_property->values[1] = 1;
 	drm_mode_create_scaling_mode_property(rdev->ddev);
 	sz = ARRAY_SIZE(radeon_tv_std_enum_list);
 	rdev->mode_info.tv_std_property =
 		drm_property_create(rdev->ddev,
 				    DRM_MODE_PROP_ENUM,
 				    "tv standard", sz);
 	for (i = 0; i < sz; i++) {
 		drm_property_add_enum(rdev->mode_info.tv_std_property,
 				      i,
 				      radeon_tv_std_enum_list[i].type,
 				      radeon_tv_std_enum_list[i].name);
 	}
 	sz = ARRAY_SIZE(radeon_underscan_enum_list);
 	rdev->mode_info.underscan_property =
 		drm_property_create(rdev->ddev,
 				    DRM_MODE_PROP_ENUM,
 				    "underscan", sz);
 	for (i = 0; i < sz; i++) {
 		drm_property_add_enum(rdev->mode_info.underscan_property,
 				      i,
 				      radeon_underscan_enum_list[i].type,
 				      radeon_underscan_enum_list[i].name);
 	}
 	rdev->mode_info.underscan_hborder_property =
 		drm_property_create(rdev->ddev,
 					DRM_MODE_PROP_RANGE,
 					"underscan hborder", 2);
 	if (!rdev->mode_info.underscan_hborder_property)
 		return -ENOMEM;
 	rdev->mode_info.underscan_hborder_property->values[0] = 0;
 	rdev->mode_info.underscan_hborder_property->values[1] = 128;
 	rdev->mode_info.underscan_vborder_property =
 		drm_property_create(rdev->ddev,
 					DRM_MODE_PROP_RANGE,
 					"underscan vborder", 2);
 	if (!rdev->mode_info.underscan_vborder_property)
 		return -ENOMEM;
 	rdev->mode_info.underscan_vborder_property->values[0] = 0;
 	rdev->mode_info.underscan_vborder_property->values[1] = 128;
 	return 0;
 }
 void radeon_update_display_priority(struct radeon_device *rdev)
 {
 	/* adjustment options for the display watermarks */
 	if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
 		/* set display priority to high for r3xx, rv515 chips
 		 * this avoids flickering due to underflow to the
 		 * display controllers during heavy acceleration.
 		 * Don't force high on rs4xx igp chips as it seems to
 		 * affect the sound card.  See kernel bug 15982.
 		 */
 		if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
 		    !(rdev->flags & RADEON_IS_IGP))
 			rdev->disp_priority = 2;
 		else
 			rdev->disp_priority = 0;
 	} else
 		rdev->disp_priority = radeon_disp_priority;
 }
 int radeon_modeset_init(struct radeon_device *rdev)
 {
 	int i;
 	int ret;
 	drm_mode_config_init(rdev->ddev);
 	rdev->mode_info.mode_config_initialized = true;
 	rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
 	if (ASIC_IS_DCE5(rdev)) {
 		rdev->ddev->mode_config.max_width = 16384;
 		rdev->ddev->mode_config.max_height = 16384;
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		rdev->ddev->mode_config.max_width = 8192;
 		rdev->ddev->mode_config.max_height = 8192;
 	} else {
 		rdev->ddev->mode_config.max_width = 4096;
 		rdev->ddev->mode_config.max_height = 4096;
 	}
 	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
 	ret = radeon_modeset_create_props(rdev);
 	if (ret) {
 		return ret;
 	}
 	/* init i2c buses */
 	radeon_i2c_init(rdev);
 	/* check combios for a valid hardcoded EDID - Sun servers */
 	if (!rdev->is_atom_bios) {
 		/* check for hardcoded EDID in BIOS */
 		radeon_combios_check_hardcoded_edid(rdev);
 	}
 	/* allocate crtcs */
 	for (i = 0; i < rdev->num_crtc; i++) {
 		radeon_crtc_init(rdev->ddev, i);
 	}
 	/* okay we should have all the bios connectors */
 	ret = radeon_setup_enc_conn(rdev->ddev);
 	if (!ret) {
 		return ret;
 	}
 	/* initialize hpd */
 	radeon_hpd_init(rdev);
 	/* Initialize power management */
 	radeon_pm_init(rdev);
 	radeon_fbdev_init(rdev);
 	drm_kms_helper_poll_init(rdev->ddev);
 	return 0;
 }
 void radeon_modeset_fini(struct radeon_device *rdev)
 {
 	radeon_fbdev_fini(rdev);
 	kfree(rdev->mode_info.bios_hardcoded_edid);
 	radeon_pm_fini(rdev);
 	if (rdev->mode_info.mode_config_initialized) {
 		drm_kms_helper_poll_fini(rdev->ddev);
 		radeon_hpd_fini(rdev);
 		drm_mode_config_cleanup(rdev->ddev);
 		rdev->mode_info.mode_config_initialized = false;
 	}
 	/* free i2c buses */
 	radeon_i2c_fini(rdev);
 }
 static bool is_hdtv_mode(struct drm_display_mode *mode)
 {
 	/* try and guess if this is a tv or a monitor */
 	if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
 	    (mode->vdisplay == 576) || /* 576p */
 	    (mode->vdisplay == 720) || /* 720p */
 	    (mode->vdisplay == 1080)) /* 1080p */
 		return true;
 	else
 		return false;
 }
 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 				struct drm_display_mode *mode,
 				struct drm_display_mode *adjusted_mode)
 {
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct drm_encoder *encoder;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	struct radeon_encoder *radeon_encoder;
 	struct drm_connector *connector;
 	struct radeon_connector *radeon_connector;
 	bool first = true;
 	u32 src_v = 1, dst_v = 1;
 	u32 src_h = 1, dst_h = 1;
 	radeon_crtc->h_border = 0;
 	radeon_crtc->v_border = 0;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc != crtc)
 			continue;
 		radeon_encoder = to_radeon_encoder(encoder);
 		connector = radeon_get_connector_for_encoder(encoder);
 		radeon_connector = to_radeon_connector(connector);
 		if (first) {
 			/* set scaling */
 			if (radeon_encoder->rmx_type == RMX_OFF)
 				radeon_crtc->rmx_type = RMX_OFF;
 			else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
 				 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
 				radeon_crtc->rmx_type = radeon_encoder->rmx_type;
 			else
 				radeon_crtc->rmx_type = RMX_OFF;
 			/* copy native mode */
 			memcpy(&radeon_crtc->native_mode,
 			       &radeon_encoder->native_mode,
 				sizeof(struct drm_display_mode));
 			src_v = crtc->mode.vdisplay;
 			dst_v = radeon_crtc->native_mode.vdisplay;
 			src_h = crtc->mode.hdisplay;
 			dst_h = radeon_crtc->native_mode.hdisplay;
 			/* fix up for overscan on hdmi */
 			if (ASIC_IS_AVIVO(rdev) &&
 			    (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
 			    ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
 			     ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
 			      drm_detect_hdmi_monitor(radeon_connector->edid) &&
 			      is_hdtv_mode(mode)))) {
 				if (radeon_encoder->underscan_hborder != 0)
 					radeon_crtc->h_border = radeon_encoder->underscan_hborder;
 				else
 					radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
 				if (radeon_encoder->underscan_vborder != 0)
 					radeon_crtc->v_border = radeon_encoder->underscan_vborder;
 				else
 					radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
 				radeon_crtc->rmx_type = RMX_FULL;
 				src_v = crtc->mode.vdisplay;
 				dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
 				src_h = crtc->mode.hdisplay;
 				dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
 			}
 			first = false;
 		} else {
 			if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
 				/* WARNING: Right now this can't happen but
 				 * in the future we need to check that scaling
 				 * are consistent across different encoder
 				 * (ie all encoder can work with the same
 				 *  scaling).
 				 */
 				DRM_ERROR("Scaling not consistent across encoder.\n");
 				return false;
 			}
 		}
 	}
 	if (radeon_crtc->rmx_type != RMX_OFF) {
 		fixed20_12 a, b;
 		a.full = dfixed_const(src_v);
 		b.full = dfixed_const(dst_v);
 		radeon_crtc->vsc.full = dfixed_div(a, b);
 		a.full = dfixed_const(src_h);
 		b.full = dfixed_const(dst_h);
 		radeon_crtc->hsc.full = dfixed_div(a, b);
 	} else {
 		radeon_crtc->vsc.full = dfixed_const(1);
 		radeon_crtc->hsc.full = dfixed_const(1);
 	}
 	return true;
 }
 /*
  * Retrieve current video scanout position of crtc on a given gpu.
  *
  * \param dev Device to query.
  * \param crtc Crtc to query.
  * \param *vpos Location where vertical scanout position should be stored.
  * \param *hpos Location where horizontal scanout position should go.
  *
  * Returns vpos as a positive number while in active scanout area.
  * Returns vpos as a negative number inside vblank, counting the number
  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
  * until start of active scanout / end of vblank."
  *
  * \return Flags, or'ed together as follows:
  *
  * DRM_SCANOUTPOS_VALID = Query successful.
  * DRM_SCANOUTPOS_INVBL = Inside vblank.
  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
  * this flag means that returned position may be offset by a constant but
  * unknown small number of scanlines wrt. real scanout position.
  *
  */
 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
 {
 	u32 stat_crtc = 0, vbl = 0, position = 0;
 	int vbl_start, vbl_end, vtotal, ret = 0;
 	bool in_vbl = true;
 	struct radeon_device *rdev = dev->dev_private;
 	if (ASIC_IS_DCE4(rdev)) {
 		if (crtc == 0) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC0_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC0_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 1) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC1_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC1_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 2) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC2_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC2_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 3) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC3_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC3_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 4) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC4_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC4_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 5) {
 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 				     EVERGREEN_CRTC5_REGISTER_OFFSET);
 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 					  EVERGREEN_CRTC5_REGISTER_OFFSET);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 	} else if (ASIC_IS_AVIVO(rdev)) {
 		if (crtc == 0) {
 			vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
 			position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 1) {
 			vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
 			position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 	} else {
 		/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
 		if (crtc == 0) {
 			/* Assume vbl_end == 0, get vbl_start from
 			 * upper 16 bits.
 			 */
 			vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
 				RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
 			/* Only retrieve vpos from upper 16 bits, set hpos == 0. */
 			position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 			stat_crtc = RREG32(RADEON_CRTC_STATUS);
 			if (!(stat_crtc & 1))
 				in_vbl = false;
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 		if (crtc == 1) {
 			vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
 				RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
 			position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 			stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 			if (!(stat_crtc & 1))
 				in_vbl = false;
 			ret |= DRM_SCANOUTPOS_VALID;
 		}
 	}
 	/* Decode into vertical and horizontal scanout position. */
 	*vpos = position & 0x1fff;
 	*hpos = (position >> 16) & 0x1fff;
 	/* Valid vblank area boundaries from gpu retrieved? */
 	if (vbl > 0) {
 		/* Yes: Decode. */
 		ret |= DRM_SCANOUTPOS_ACCURATE;
 		vbl_start = vbl & 0x1fff;
 		vbl_end = (vbl >> 16) & 0x1fff;
 	}
 	else {
 		/* No: Fake something reasonable which gives at least ok results. */
 		vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
 		vbl_end = 0;
 	}
 	/* Test scanout position against vblank region. */
 	if ((*vpos < vbl_start) && (*vpos >= vbl_end))
 		in_vbl = false;
 	/* Check if inside vblank area and apply corrective offsets:
 	 * vpos will then be >=0 in video scanout area, but negative
 	 * within vblank area, counting down the number of lines until
 	 * start of scanout.
 	 */
 	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
 	if (in_vbl && (*vpos >= vbl_start)) {
 		vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
 		*vpos = *vpos - vtotal;
 	}
 	/* Correct for shifted end of vbl at vbl_end. */
 	*vpos = *vpos - vbl_end;
 	/* In vblank? */
 	if (in_vbl)
 		ret |= DRM_SCANOUTPOS_INVBL;
 	return ret;
 }

include/drm/drmP.h

Diff comments View file @ bbb0aef

 /**
  * \file drmP.h
  * Private header for Direct Rendering Manager
  *
  * \author Rickard E. (Rik) Faith <faith@valinux.com>
  * \author Gareth Hughes <gareth@valinux.com>
  */
 /*
  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * Copyright (c) 2009-2010, Code Aurora Forum.
  * All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 #ifndef _DRM_P_H_
 #define _DRM_P_H_
 #ifdef __KERNEL__
 #ifdef __alpha__
 /* add include of current.h so that "current" is defined
  * before static inline funcs in wait.h. Doing this so we
  * can build the DRM (part of PI DRI). 4/21/2000 S + B */
 #include <asm/current.h>
 #endif				/* __alpha__ */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/miscdevice.h>
 #include <linux/fs.h>
 #include <linux/proc_fs.h>
 #include <linux/init.h>
 #include <linux/file.h>
 #include <linux/platform_device.h>
 #include <linux/pci.h>
 #include <linux/jiffies.h>
 #include <linux/dma-mapping.h>
 #include <linux/mm.h>
 #include <linux/cdev.h>
 #include <linux/mutex.h>
 #include <linux/slab.h>
 #if defined(__alpha__) || defined(__powerpc__)
 #include <asm/pgtable.h>	/* For pte_wrprotect */
 #endif
 #include <asm/io.h>
 #include <asm/mman.h>
 #include <asm/uaccess.h>
 #ifdef CONFIG_MTRR
 #include <asm/mtrr.h>
 #endif
 #if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
 #include <linux/types.h>
 #include <linux/agp_backend.h>
 #endif
 #include <linux/workqueue.h>
 #include <linux/poll.h>
 #include <asm/pgalloc.h>
 #include "drm.h"
 #include <linux/idr.h>
 #define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
 #define __OS_HAS_MTRR (defined(CONFIG_MTRR))
 struct drm_file;
 struct drm_device;
 #include "drm_os_linux.h"
 #include "drm_hashtab.h"
 #include "drm_mm.h"
 #define DRM_UT_CORE 		0x01
 #define DRM_UT_DRIVER		0x02
 #define DRM_UT_KMS		0x04
 /*
  * Three debug levels are defined.
  * drm_core, drm_driver, drm_kms
  * drm_core level can be used in the generic drm code. For example:
  * 	drm_ioctl, drm_mm, drm_memory
  * The macro definition of DRM_DEBUG is used.
  * 	DRM_DEBUG(fmt, args...)
  * 	The debug info by using the DRM_DEBUG can be obtained by adding
  * 	the boot option of "drm.debug=1".
  *
  * drm_driver level can be used in the specific drm driver. It is used
  * to add the debug info related with the drm driver. For example:
  * i915_drv, i915_dma, i915_gem, radeon_drv,
  * 	The macro definition of DRM_DEBUG_DRIVER can be used.
  * 	DRM_DEBUG_DRIVER(fmt, args...)
  * 	The debug info by using the DRM_DEBUG_DRIVER can be obtained by
  * 	adding the boot option of "drm.debug=0x02"
  *
  * drm_kms level can be used in the KMS code related with specific drm driver.
  * It is used to add the debug info related with KMS mode. For example:
  * the connector/crtc ,
  * 	The macro definition of DRM_DEBUG_KMS can be used.
  * 	DRM_DEBUG_KMS(fmt, args...)
  * 	The debug info by using the DRM_DEBUG_KMS can be obtained by
  * 	adding the boot option of "drm.debug=0x04"
  *
  * If we add the boot option of "drm.debug=0x06", we can get the debug info by
  * using the DRM_DEBUG_KMS and DRM_DEBUG_DRIVER.
  * If we add the boot option of "drm.debug=0x05", we can get the debug info by
  * using the DRM_DEBUG_KMS and DRM_DEBUG.
  */
-extern void drm_ut_debug_printk(unsigned int request_level,
+extern __attribute__((format (printf, 4, 5)))
+void drm_ut_debug_printk(unsigned int request_level,
 				const char *prefix,
 				const char *function_name,
 				const char *format, ...);
 extern __attribute__((format (printf, 2, 3)))
 int drm_err(const char *func, const char *format, ...);
 /***********************************************************************/
 /** \name DRM template customization defaults */
 /*@{*/
 /* driver capabilities and requirements mask */
 #define DRIVER_USE_AGP     0x1
 #define DRIVER_REQUIRE_AGP 0x2
 #define DRIVER_USE_MTRR    0x4
 #define DRIVER_PCI_DMA     0x8
 #define DRIVER_SG          0x10
 #define DRIVER_HAVE_DMA    0x20
 #define DRIVER_HAVE_IRQ    0x40
 #define DRIVER_IRQ_SHARED  0x80
 #define DRIVER_IRQ_VBL     0x100
 #define DRIVER_DMA_QUEUE   0x200
 #define DRIVER_FB_DMA      0x400
 #define DRIVER_IRQ_VBL2    0x800
 #define DRIVER_GEM         0x1000
 #define DRIVER_MODESET     0x2000
 #define DRIVER_BUS_PCI 0x1
 #define DRIVER_BUS_PLATFORM 0x2
 #define DRIVER_BUS_USB 0x3
 /***********************************************************************/
 /** \name Begin the DRM... */
 /*@{*/
 #define DRM_DEBUG_CODE 2	  /**< Include debugging code if > 1, then
 				     also include looping detection. */
 #define DRM_MAGIC_HASH_ORDER  4  /**< Size of key hash table. Must be power of 2. */
 #define DRM_KERNEL_CONTEXT    0	 /**< Change drm_resctx if changed */
 #define DRM_RESERVED_CONTEXTS 1	 /**< Change drm_resctx if changed */
 #define DRM_LOOPING_LIMIT     5000000
 #define DRM_TIME_SLICE	      (HZ/20)  /**< Time slice for GLXContexts */
 #define DRM_LOCK_SLICE	      1	/**< Time slice for lock, in jiffies */
 #define DRM_FLAG_DEBUG	  0x01
 #define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8)
 #define DRM_MAP_HASH_OFFSET 0x10000000
 /*@}*/
 /***********************************************************************/
 /** \name Macros to make printk easier */
 /*@{*/
 /**
  * Error output.
  *
  * \param fmt printf() like format string.
  * \param arg arguments
  */
 #define DRM_ERROR(fmt, ...)				\
 	drm_err(__func__, fmt, ##__VA_ARGS__)
 #define DRM_INFO(fmt, ...)				\
 	printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__)
 /**
  * Debug output.
  *
  * \param fmt printf() like format string.
  * \param arg arguments
  */
 #if DRM_DEBUG_CODE
 #define DRM_DEBUG(fmt, args...)						\
 	do {								\
 		drm_ut_debug_printk(DRM_UT_CORE, DRM_NAME, 		\
 					__func__, fmt, ##args);		\
 	} while (0)
 #define DRM_DEBUG_DRIVER(fmt, args...)					\
 	do {								\
 		drm_ut_debug_printk(DRM_UT_DRIVER, DRM_NAME,		\
 					__func__, fmt, ##args);		\
 	} while (0)
 #define DRM_DEBUG_KMS(fmt, args...)				\
 	do {								\
 		drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, 		\
 					 __func__, fmt, ##args);	\
 	} while (0)
 #define DRM_LOG(fmt, args...)						\
 	do {								\
 		drm_ut_debug_printk(DRM_UT_CORE, NULL,			\
 					NULL, fmt, ##args);		\
 	} while (0)
 #define DRM_LOG_KMS(fmt, args...)					\
 	do {								\
 		drm_ut_debug_printk(DRM_UT_KMS, NULL,			\
 					NULL, fmt, ##args);		\
 	} while (0)
 #define DRM_LOG_MODE(fmt, args...)					\
 	do {								\
 		drm_ut_debug_printk(DRM_UT_MODE, NULL,			\
 					NULL, fmt, ##args);		\
 	} while (0)
 #define DRM_LOG_DRIVER(fmt, args...)					\
 	do {								\
 		drm_ut_debug_printk(DRM_UT_DRIVER, NULL,		\
 					NULL, fmt, ##args);		\
 	} while (0)
 #else
 #define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0)
 #define DRM_DEBUG_KMS(fmt, args...)	do { } while (0)
 #define DRM_DEBUG(fmt, arg...)		 do { } while (0)
 #define DRM_LOG(fmt, arg...)		do { } while (0)
 #define DRM_LOG_KMS(fmt, args...) do { } while (0)
 #define DRM_LOG_MODE(fmt, arg...) do { } while (0)
 #define DRM_LOG_DRIVER(fmt, arg...) do { } while (0)
 #endif
 /*@}*/
 /***********************************************************************/
 /** \name Internal types and structures */
 /*@{*/
 #define DRM_ARRAY_SIZE(x) ARRAY_SIZE(x)
 #define DRM_LEFTCOUNT(x) (((x)->rp + (x)->count - (x)->wp) % ((x)->count + 1))
 #define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x))
 #define DRM_IF_VERSION(maj, min) (maj << 16 | min)
 /**
  * Test that the hardware lock is held by the caller, returning otherwise.
  *
  * \param dev DRM device.
  * \param filp file pointer of the caller.
  */
 #define LOCK_TEST_WITH_RETURN( dev, _file_priv )				\
 do {										\
 	if (!_DRM_LOCK_IS_HELD(_file_priv->master->lock.hw_lock->lock) ||	\
 	    _file_priv->master->lock.file_priv != _file_priv)	{		\
 		DRM_ERROR( "%s called without lock held, held  %d owner %p %p\n",\
 			   __func__, _DRM_LOCK_IS_HELD(_file_priv->master->lock.hw_lock->lock),\
 			   _file_priv->master->lock.file_priv, _file_priv);	\
 		return -EINVAL;							\
 	}									\
 } while (0)
 /**
  * Ioctl function type.
  *
  * \param inode device inode.
  * \param file_priv DRM file private pointer.
  * \param cmd command.
  * \param arg argument.
  */
 typedef int drm_ioctl_t(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd,
 			       unsigned long arg);
 #define DRM_IOCTL_NR(n)                _IOC_NR(n)
 #define DRM_MAJOR       226
 #define DRM_AUTH	0x1
 #define	DRM_MASTER	0x2
 #define DRM_ROOT_ONLY	0x4
 #define DRM_CONTROL_ALLOW 0x8
 #define DRM_UNLOCKED	0x10
 struct drm_ioctl_desc {
 	unsigned int cmd;
 	int flags;
 	drm_ioctl_t *func;
 	unsigned int cmd_drv;
 };
 /**
  * Creates a driver or general drm_ioctl_desc array entry for the given
  * ioctl, for use by drm_ioctl().
  */
 #define DRM_IOCTL_DEF_DRV(ioctl, _func, _flags)			\
 	[DRM_IOCTL_NR(DRM_##ioctl)] = {.cmd = DRM_##ioctl, .func = _func, .flags = _flags, .cmd_drv = DRM_IOCTL_##ioctl}
 struct drm_magic_entry {
 	struct list_head head;
 	struct drm_hash_item hash_item;
 	struct drm_file *priv;
 };
 struct drm_vma_entry {
 	struct list_head head;
 	struct vm_area_struct *vma;
 	pid_t pid;
 };
 /**
  * DMA buffer.
  */
 struct drm_buf {
 	int idx;		       /**< Index into master buflist */
 	int total;		       /**< Buffer size */
 	int order;		       /**< log-base-2(total) */
 	int used;		       /**< Amount of buffer in use (for DMA) */
 	unsigned long offset;	       /**< Byte offset (used internally) */
 	void *address;		       /**< Address of buffer */
 	unsigned long bus_address;     /**< Bus address of buffer */
 	struct drm_buf *next;	       /**< Kernel-only: used for free list */
 	__volatile__ int waiting;      /**< On kernel DMA queue */
 	__volatile__ int pending;      /**< On hardware DMA queue */
 	wait_queue_head_t dma_wait;    /**< Processes waiting */
 	struct drm_file *file_priv;    /**< Private of holding file descr */
 	int context;		       /**< Kernel queue for this buffer */
 	int while_locked;	       /**< Dispatch this buffer while locked */
 	enum {
 		DRM_LIST_NONE = 0,
 		DRM_LIST_FREE = 1,
 		DRM_LIST_WAIT = 2,
 		DRM_LIST_PEND = 3,
 		DRM_LIST_PRIO = 4,
 		DRM_LIST_RECLAIM = 5
 	} list;			       /**< Which list we're on */
 	int dev_priv_size;		 /**< Size of buffer private storage */
 	void *dev_private;		 /**< Per-buffer private storage */
 };
 /** bufs is one longer than it has to be */
 struct drm_waitlist {
 	int count;			/**< Number of possible buffers */
 	struct drm_buf **bufs;		/**< List of pointers to buffers */
 	struct drm_buf **rp;			/**< Read pointer */
 	struct drm_buf **wp;			/**< Write pointer */
 	struct drm_buf **end;		/**< End pointer */
 	spinlock_t read_lock;
 	spinlock_t write_lock;
 };
 struct drm_freelist {
 	int initialized;	       /**< Freelist in use */
 	atomic_t count;		       /**< Number of free buffers */
 	struct drm_buf *next;	       /**< End pointer */
 	wait_queue_head_t waiting;     /**< Processes waiting on free bufs */
 	int low_mark;		       /**< Low water mark */
 	int high_mark;		       /**< High water mark */
 	atomic_t wfh;		       /**< If waiting for high mark */
 	spinlock_t lock;
 };
 typedef struct drm_dma_handle {
 	dma_addr_t busaddr;
 	void *vaddr;
 	size_t size;
 } drm_dma_handle_t;
 /**
  * Buffer entry.  There is one of this for each buffer size order.
  */
 struct drm_buf_entry {
 	int buf_size;			/**< size */
 	int buf_count;			/**< number of buffers */
 	struct drm_buf *buflist;		/**< buffer list */
 	int seg_count;
 	int page_order;
 	struct drm_dma_handle **seglist;
 	struct drm_freelist freelist;
 };
 /* Event queued up for userspace to read */
 struct drm_pending_event {
 	struct drm_event *event;
 	struct list_head link;
 	struct drm_file *file_priv;
 	pid_t pid; /* pid of requester, no guarantee it's valid by the time
 		      we deliver the event, for tracing only */
 	void (*destroy)(struct drm_pending_event *event);
 };
 /** File private data */
 struct drm_file {
 	int authenticated;
 	pid_t pid;
 	uid_t uid;
 	drm_magic_t magic;
 	unsigned long ioctl_count;
 	struct list_head lhead;
 	struct drm_minor *minor;
 	unsigned long lock_count;
 	/** Mapping of mm object handles to object pointers. */
 	struct idr object_idr;
 	/** Lock for synchronization of access to object_idr. */
 	spinlock_t table_lock;
 	struct file *filp;
 	void *driver_priv;
 	int is_master; /* this file private is a master for a minor */
 	struct drm_master *master; /* master this node is currently associated with
 				      N.B. not always minor->master */
 	struct list_head fbs;
 	wait_queue_head_t event_wait;
 	struct list_head event_list;
 	int event_space;
 };
 /** Wait queue */
 struct drm_queue {
 	atomic_t use_count;		/**< Outstanding uses (+1) */
 	atomic_t finalization;		/**< Finalization in progress */
 	atomic_t block_count;		/**< Count of processes waiting */
 	atomic_t block_read;		/**< Queue blocked for reads */
 	wait_queue_head_t read_queue;	/**< Processes waiting on block_read */
 	atomic_t block_write;		/**< Queue blocked for writes */
 	wait_queue_head_t write_queue;	/**< Processes waiting on block_write */
 	atomic_t total_queued;		/**< Total queued statistic */
 	atomic_t total_flushed;		/**< Total flushes statistic */
 	atomic_t total_locks;		/**< Total locks statistics */
 	enum drm_ctx_flags flags;	/**< Context preserving and 2D-only */
 	struct drm_waitlist waitlist;	/**< Pending buffers */
 	wait_queue_head_t flush_queue;	/**< Processes waiting until flush */
 };
 /**
  * Lock data.
  */
 struct drm_lock_data {
 	struct drm_hw_lock *hw_lock;	/**< Hardware lock */
 	/** Private of lock holder's file (NULL=kernel) */
 	struct drm_file *file_priv;
 	wait_queue_head_t lock_queue;	/**< Queue of blocked processes */
 	unsigned long lock_time;	/**< Time of last lock in jiffies */
 	spinlock_t spinlock;
 	uint32_t kernel_waiters;
 	uint32_t user_waiters;
 	int idle_has_lock;
 };
 /**
  * DMA data.
  */
 struct drm_device_dma {
 	struct drm_buf_entry bufs[DRM_MAX_ORDER + 1];	/**< buffers, grouped by their size order */
 	int buf_count;			/**< total number of buffers */
 	struct drm_buf **buflist;		/**< Vector of pointers into drm_device_dma::bufs */
 	int seg_count;
 	int page_count;			/**< number of pages */
 	unsigned long *pagelist;	/**< page list */
 	unsigned long byte_count;
 	enum {
 		_DRM_DMA_USE_AGP = 0x01,
 		_DRM_DMA_USE_SG = 0x02,
 		_DRM_DMA_USE_FB = 0x04,
 		_DRM_DMA_USE_PCI_RO = 0x08
 	} flags;
 };
 /**
  * AGP memory entry.  Stored as a doubly linked list.
  */
 struct drm_agp_mem {
 	unsigned long handle;		/**< handle */
 	DRM_AGP_MEM *memory;
 	unsigned long bound;		/**< address */
 	int pages;
 	struct list_head head;
 };
 /**
  * AGP data.
  *
  * \sa drm_agp_init() and drm_device::agp.
  */
 struct drm_agp_head {
 	DRM_AGP_KERN agp_info;		/**< AGP device information */
 	struct list_head memory;
 	unsigned long mode;		/**< AGP mode */
 	struct agp_bridge_data *bridge;
 	int enabled;			/**< whether the AGP bus as been enabled */
 	int acquired;			/**< whether the AGP device has been acquired */
 	unsigned long base;
 	int agp_mtrr;
 	int cant_use_aperture;
 	unsigned long page_mask;
 };
 /**
  * Scatter-gather memory.
  */
 struct drm_sg_mem {
 	unsigned long handle;
 	void *virtual;
 	int pages;
 	struct page **pagelist;
 	dma_addr_t *busaddr;
 };
 struct drm_sigdata {
 	int context;
 	struct drm_hw_lock *lock;
 };
 /**
  * Kernel side of a mapping
  */
 struct drm_local_map {
 	resource_size_t offset;	 /**< Requested physical address (0 for SAREA)*/
 	unsigned long size;	 /**< Requested physical size (bytes) */
 	enum drm_map_type type;	 /**< Type of memory to map */
 	enum drm_map_flags flags;	 /**< Flags */
 	void *handle;		 /**< User-space: "Handle" to pass to mmap() */
 				 /**< Kernel-space: kernel-virtual address */
 	int mtrr;		 /**< MTRR slot used */
 };
 typedef struct drm_local_map drm_local_map_t;
 /**
  * Mappings list
  */
 struct drm_map_list {
 	struct list_head head;		/**< list head */
 	struct drm_hash_item hash;
 	struct drm_local_map *map;	/**< mapping */
 	uint64_t user_token;
 	struct drm_master *master;
 	struct drm_mm_node *file_offset_node;	/**< fake offset */
 };
 /**
  * Context handle list
  */
 struct drm_ctx_list {
 	struct list_head head;		/**< list head */
 	drm_context_t handle;		/**< context handle */
 	struct drm_file *tag;		/**< associated fd private data */
 };
 /* location of GART table */
 #define DRM_ATI_GART_MAIN 1
 #define DRM_ATI_GART_FB   2
 #define DRM_ATI_GART_PCI 1
 #define DRM_ATI_GART_PCIE 2
 #define DRM_ATI_GART_IGP 3
 struct drm_ati_pcigart_info {
 	int gart_table_location;
 	int gart_reg_if;
 	void *addr;
 	dma_addr_t bus_addr;
 	dma_addr_t table_mask;
 	struct drm_dma_handle *table_handle;
 	struct drm_local_map mapping;
 	int table_size;
 };
 /**
  * GEM specific mm private for tracking GEM objects
  */
 struct drm_gem_mm {
 	struct drm_mm offset_manager;	/**< Offset mgmt for buffer objects */
 	struct drm_open_hash offset_hash; /**< User token hash table for maps */
 };
 /**
  * This structure defines the drm_mm memory object, which will be used by the
  * DRM for its buffer objects.
  */
 struct drm_gem_object {
 	/** Reference count of this object */
 	struct kref refcount;
 	/** Handle count of this object. Each handle also holds a reference */
 	atomic_t handle_count; /* number of handles on this object */
 	/** Related drm device */
 	struct drm_device *dev;
 	/** File representing the shmem storage */
 	struct file *filp;
 	/* Mapping info for this object */
 	struct drm_map_list map_list;
 	/**
 	 * Size of the object, in bytes.  Immutable over the object's
 	 * lifetime.
 	 */
 	size_t size;
 	/**
 	 * Global name for this object, starts at 1. 0 means unnamed.
 	 * Access is covered by the object_name_lock in the related drm_device
 	 */
 	int name;
 	/**
 	 * Memory domains. These monitor which caches contain read/write data
 	 * related to the object. When transitioning from one set of domains
 	 * to another, the driver is called to ensure that caches are suitably
 	 * flushed and invalidated
 	 */
 	uint32_t read_domains;
 	uint32_t write_domain;
 	/**
 	 * While validating an exec operation, the
 	 * new read/write domain values are computed here.
 	 * They will be transferred to the above values
 	 * at the point that any cache flushing occurs
 	 */
 	uint32_t pending_read_domains;
 	uint32_t pending_write_domain;
 	void *driver_private;
 };
 #include "drm_crtc.h"
 /* per-master structure */
 struct drm_master {
 	struct kref refcount; /* refcount for this master */
 	struct list_head head; /**< each minor contains a list of masters */
 	struct drm_minor *minor; /**< link back to minor we are a master for */
 	char *unique;			/**< Unique identifier: e.g., busid */
 	int unique_len;			/**< Length of unique field */
 	int unique_size;		/**< amount allocated */
 	int blocked;			/**< Blocked due to VC switch? */
 	/** \name Authentication */
 	/*@{ */
 	struct drm_open_hash magiclist;
 	struct list_head magicfree;
 	/*@} */
 	struct drm_lock_data lock;	/**< Information on hardware lock */
 	void *driver_priv; /**< Private structure for driver to use */
 };
 /* Size of ringbuffer for vblank timestamps. Just double-buffer
  * in initial implementation.
  */
 #define DRM_VBLANKTIME_RBSIZE 2
 /* Flags and return codes for get_vblank_timestamp() driver function. */
 #define DRM_CALLED_FROM_VBLIRQ 1
 #define DRM_VBLANKTIME_SCANOUTPOS_METHOD (1 << 0)
 #define DRM_VBLANKTIME_INVBL             (1 << 1)
 /* get_scanout_position() return flags */
 #define DRM_SCANOUTPOS_VALID        (1 << 0)
 #define DRM_SCANOUTPOS_INVBL        (1 << 1)
 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
 struct drm_bus {
 	int bus_type;
 	int (*get_irq)(struct drm_device *dev);
 	const char *(*get_name)(struct drm_device *dev);
 	int (*set_busid)(struct drm_device *dev, struct drm_master *master);
 	int (*set_unique)(struct drm_device *dev, struct drm_master *master,
 			  struct drm_unique *unique);
 	int (*irq_by_busid)(struct drm_device *dev, struct drm_irq_busid *p);
 	/* hooks that are for PCI */
 	int (*agp_init)(struct drm_device *dev);
 };
 /**
  * DRM driver structure. This structure represent the common code for
  * a family of cards. There will one drm_device for each card present
  * in this family
  */
 struct drm_driver {
 	int (*load) (struct drm_device *, unsigned long flags);
 	int (*firstopen) (struct drm_device *);
 	int (*open) (struct drm_device *, struct drm_file *);
 	void (*preclose) (struct drm_device *, struct drm_file *file_priv);
 	void (*postclose) (struct drm_device *, struct drm_file *);
 	void (*lastclose) (struct drm_device *);
 	int (*unload) (struct drm_device *);
 	int (*suspend) (struct drm_device *, pm_message_t state);
 	int (*resume) (struct drm_device *);
 	int (*dma_ioctl) (struct drm_device *dev, void *data, struct drm_file *file_priv);
 	int (*dma_quiescent) (struct drm_device *);
 	int (*context_dtor) (struct drm_device *dev, int context);
 	/**
 	 * get_vblank_counter - get raw hardware vblank counter
 	 * @dev: DRM device
 	 * @crtc: counter to fetch
 	 *
 	 * Driver callback for fetching a raw hardware vblank counter
 	 * for @crtc.  If a device doesn't have a hardware counter, the
 	 * driver can simply return the value of drm_vblank_count and
 	 * make the enable_vblank() and disable_vblank() hooks into no-ops,
 	 * leaving interrupts enabled at all times.
 	 *
 	 * Wraparound handling and loss of events due to modesetting is dealt
 	 * with in the DRM core code.
 	 *
 	 * RETURNS
 	 * Raw vblank counter value.
 	 */
 	u32 (*get_vblank_counter) (struct drm_device *dev, int crtc);
 	/**
 	 * enable_vblank - enable vblank interrupt events
 	 * @dev: DRM device
 	 * @crtc: which irq to enable
 	 *
 	 * Enable vblank interrupts for @crtc.  If the device doesn't have
 	 * a hardware vblank counter, this routine should be a no-op, since
 	 * interrupts will have to stay on to keep the count accurate.
 	 *
 	 * RETURNS
 	 * Zero on success, appropriate errno if the given @crtc's vblank
 	 * interrupt cannot be enabled.
 	 */
 	int (*enable_vblank) (struct drm_device *dev, int crtc);
 	/**
 	 * disable_vblank - disable vblank interrupt events
 	 * @dev: DRM device
 	 * @crtc: which irq to enable
 	 *
 	 * Disable vblank interrupts for @crtc.  If the device doesn't have
 	 * a hardware vblank counter, this routine should be a no-op, since
 	 * interrupts will have to stay on to keep the count accurate.
 	 */
 	void (*disable_vblank) (struct drm_device *dev, int crtc);
 	/**
 	 * Called by \c drm_device_is_agp.  Typically used to determine if a
 	 * card is really attached to AGP or not.
 	 *
 	 * \param dev  DRM device handle
 	 *
 	 * \returns
 	 * One of three values is returned depending on whether or not the
 	 * card is absolutely \b not AGP (return of 0), absolutely \b is AGP
 	 * (return of 1), or may or may not be AGP (return of 2).
 	 */
 	int (*device_is_agp) (struct drm_device *dev);
 	/**
 	 * Called by vblank timestamping code.
 	 *
 	 * Return the current display scanout position from a crtc.
 	 *
 	 * \param dev  DRM device.
 	 * \param crtc Id of the crtc to query.
 	 * \param *vpos Target location for current vertical scanout position.
 	 * \param *hpos Target location for current horizontal scanout position.
 	 *
 	 * Returns vpos as a positive number while in active scanout area.
 	 * Returns vpos as a negative number inside vblank, counting the number
 	 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
 	 * until start of active scanout / end of vblank."
 	 *
 	 * \return Flags, or'ed together as follows:
 	 *
 	 * DRM_SCANOUTPOS_VALID = Query successful.
 	 * DRM_SCANOUTPOS_INVBL = Inside vblank.
 	 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
 	 * this flag means that returned position may be offset by a constant
 	 * but unknown small number of scanlines wrt. real scanout position.
 	 *
 	 */
 	int (*get_scanout_position) (struct drm_device *dev, int crtc,
 				     int *vpos, int *hpos);
 	/**
 	 * Called by \c drm_get_last_vbltimestamp. Should return a precise
 	 * timestamp when the most recent VBLANK interval ended or will end.
 	 *
 	 * Specifically, the timestamp in @vblank_time should correspond as
 	 * closely as possible to the time when the first video scanline of
 	 * the video frame after the end of VBLANK will start scanning out,
 	 * the time immmediately after end of the VBLANK interval. If the
 	 * @crtc is currently inside VBLANK, this will be a time in the future.
 	 * If the @crtc is currently scanning out a frame, this will be the
 	 * past start time of the current scanout. This is meant to adhere
 	 * to the OpenML OML_sync_control extension specification.
 	 *
 	 * \param dev dev DRM device handle.
 	 * \param crtc crtc for which timestamp should be returned.
 	 * \param *max_error Maximum allowable timestamp error in nanoseconds.
 	 *                   Implementation should strive to provide timestamp
 	 *                   with an error of at most *max_error nanoseconds.
 	 *                   Returns true upper bound on error for timestamp.
 	 * \param *vblank_time Target location for returned vblank timestamp.
 	 * \param flags 0 = Defaults, no special treatment needed.
 	 * \param       DRM_CALLED_FROM_VBLIRQ = Function is called from vblank
 	 *	        irq handler. Some drivers need to apply some workarounds
 	 *              for gpu-specific vblank irq quirks if flag is set.
 	 *
 	 * \returns
 	 * Zero if timestamping isn't supported in current display mode or a
 	 * negative number on failure. A positive status code on success,
 	 * which describes how the vblank_time timestamp was computed.
 	 */
 	int (*get_vblank_timestamp) (struct drm_device *dev, int crtc,
 				     int *max_error,
 				     struct timeval *vblank_time,
 				     unsigned flags);
 	/* these have to be filled in */
 	irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
 	void (*irq_preinstall) (struct drm_device *dev);
 	int (*irq_postinstall) (struct drm_device *dev);
 	void (*irq_uninstall) (struct drm_device *dev);
 	void (*reclaim_buffers) (struct drm_device *dev,
 				 struct drm_file * file_priv);
 	void (*reclaim_buffers_locked) (struct drm_device *dev,
 					struct drm_file *file_priv);
 	void (*reclaim_buffers_idlelocked) (struct drm_device *dev,
 					    struct drm_file *file_priv);
 	void (*set_version) (struct drm_device *dev,
 			     struct drm_set_version *sv);
 	/* Master routines */
 	int (*master_create)(struct drm_device *dev, struct drm_master *master);
 	void (*master_destroy)(struct drm_device *dev, struct drm_master *master);
 	/**
 	 * master_set is called whenever the minor master is set.
 	 * master_drop is called whenever the minor master is dropped.
 	 */
 	int (*master_set)(struct drm_device *dev, struct drm_file *file_priv,
 			  bool from_open);
 	void (*master_drop)(struct drm_device *dev, struct drm_file *file_priv,
 			    bool from_release);
 	int (*debugfs_init)(struct drm_minor *minor);
 	void (*debugfs_cleanup)(struct drm_minor *minor);
 	/**
 	 * Driver-specific constructor for drm_gem_objects, to set up
 	 * obj->driver_private.
 	 *
 	 * Returns 0 on success.
 	 */
 	int (*gem_init_object) (struct drm_gem_object *obj);
 	void (*gem_free_object) (struct drm_gem_object *obj);
 	/* vga arb irq handler */
 	void (*vgaarb_irq)(struct drm_device *dev, bool state);
 	/* dumb alloc support */
 	int (*dumb_create)(struct drm_file *file_priv,
 			   struct drm_device *dev,
 			   struct drm_mode_create_dumb *args);
 	int (*dumb_map_offset)(struct drm_file *file_priv,
 			       struct drm_device *dev, uint32_t handle,
 			       uint64_t *offset);
 	int (*dumb_destroy)(struct drm_file *file_priv,
 			    struct drm_device *dev,
 			    uint32_t handle);
 	/* Driver private ops for this object */
 	struct vm_operations_struct *gem_vm_ops;
 	int major;
 	int minor;
 	int patchlevel;
 	char *name;
 	char *desc;
 	char *date;
 	u32 driver_features;
 	int dev_priv_size;
 	struct drm_ioctl_desc *ioctls;
 	int num_ioctls;
 	struct file_operations fops;
 	union {
 		struct pci_driver *pci;
 		struct platform_device *platform_device;
 		struct usb_driver *usb;
 	} kdriver;
 	struct drm_bus *bus;
 	/* List of devices hanging off this driver */
 	struct list_head device_list;
 };
 #define DRM_MINOR_UNASSIGNED 0
 #define DRM_MINOR_LEGACY 1
 #define DRM_MINOR_CONTROL 2
 #define DRM_MINOR_RENDER 3
 /**
  * debugfs node list. This structure represents a debugfs file to
  * be created by the drm core
  */
 struct drm_debugfs_list {
 	const char *name; /** file name */
 	int (*show)(struct seq_file*, void*); /** show callback */
 	u32 driver_features; /**< Required driver features for this entry */
 };
 /**
  * debugfs node structure. This structure represents a debugfs file.
  */
 struct drm_debugfs_node {
 	struct list_head list;
 	struct drm_minor *minor;
 	struct drm_debugfs_list *debugfs_ent;
 	struct dentry *dent;
 };
 /**
  * Info file list entry. This structure represents a debugfs or proc file to
  * be created by the drm core
  */
 struct drm_info_list {
 	const char *name; /** file name */
 	int (*show)(struct seq_file*, void*); /** show callback */
 	u32 driver_features; /**< Required driver features for this entry */
 	void *data;
 };
 /**
  * debugfs node structure. This structure represents a debugfs file.
  */
 struct drm_info_node {
 	struct list_head list;
 	struct drm_minor *minor;
 	struct drm_info_list *info_ent;
 	struct dentry *dent;
 };
 /**
  * DRM minor structure. This structure represents a drm minor number.
  */
 struct drm_minor {
 	int index;			/**< Minor device number */
 	int type;                       /**< Control or render */
 	dev_t device;			/**< Device number for mknod */
 	struct device kdev;		/**< Linux device */
 	struct drm_device *dev;
 	struct proc_dir_entry *proc_root;  /**< proc directory entry */
 	struct drm_info_node proc_nodes;
 	struct dentry *debugfs_root;
 	struct drm_info_node debugfs_nodes;
 	struct drm_master *master; /* currently active master for this node */
 	struct list_head master_list;
 	struct drm_mode_group mode_group;
 };
 struct drm_pending_vblank_event {
 	struct drm_pending_event base;
 	int pipe;
 	struct drm_event_vblank event;
 };
 /**
  * DRM device structure. This structure represent a complete card that
  * may contain multiple heads.
  */
 struct drm_device {
 	struct list_head driver_item;	/**< list of devices per driver */
 	char *devname;			/**< For /proc/interrupts */
 	int if_version;			/**< Highest interface version set */
 	/** \name Locks */
 	/*@{ */
 	spinlock_t count_lock;		/**< For inuse, drm_device::open_count, drm_device::buf_use */
 	struct mutex struct_mutex;	/**< For others */
 	/*@} */
 	/** \name Usage Counters */
 	/*@{ */
 	int open_count;			/**< Outstanding files open */
 	atomic_t ioctl_count;		/**< Outstanding IOCTLs pending */
 	atomic_t vma_count;		/**< Outstanding vma areas open */
 	int buf_use;			/**< Buffers in use -- cannot alloc */
 	atomic_t buf_alloc;		/**< Buffer allocation in progress */
 	/*@} */
 	/** \name Performance counters */
 	/*@{ */
 	unsigned long counters;
 	enum drm_stat_type types[15];
 	atomic_t counts[15];
 	/*@} */
 	struct list_head filelist;
 	/** \name Memory management */
 	/*@{ */
 	struct list_head maplist;	/**< Linked list of regions */
 	int map_count;			/**< Number of mappable regions */
 	struct drm_open_hash map_hash;	/**< User token hash table for maps */
 	/** \name Context handle management */
 	/*@{ */
 	struct list_head ctxlist;	/**< Linked list of context handles */
 	int ctx_count;			/**< Number of context handles */
 	struct mutex ctxlist_mutex;	/**< For ctxlist */
 	struct idr ctx_idr;
 	struct list_head vmalist;	/**< List of vmas (for debugging) */
 	/*@} */
 	/** \name DMA queues (contexts) */
 	/*@{ */
 	int queue_count;		/**< Number of active DMA queues */
 	int queue_reserved;		  /**< Number of reserved DMA queues */
 	int queue_slots;		/**< Actual length of queuelist */
 	struct drm_queue **queuelist;	/**< Vector of pointers to DMA queues */
 	struct drm_device_dma *dma;		/**< Optional pointer for DMA support */
 	/*@} */
 	/** \name Context support */
 	/*@{ */
 	int irq_enabled;		/**< True if irq handler is enabled */
 	__volatile__ long context_flag;	/**< Context swapping flag */
 	__volatile__ long interrupt_flag; /**< Interruption handler flag */
 	__volatile__ long dma_flag;	/**< DMA dispatch flag */
 	wait_queue_head_t context_wait;	/**< Processes waiting on ctx switch */
 	int last_checked;		/**< Last context checked for DMA */
 	int last_context;		/**< Last current context */
 	unsigned long last_switch;	/**< jiffies at last context switch */
 	/*@} */
 	struct work_struct work;
 	/** \name VBLANK IRQ support */
 	/*@{ */
 	/*
 	 * At load time, disabling the vblank interrupt won't be allowed since
 	 * old clients may not call the modeset ioctl and therefore misbehave.
 	 * Once the modeset ioctl *has* been called though, we can safely
 	 * disable them when unused.
 	 */
 	int vblank_disable_allowed;
 	wait_queue_head_t *vbl_queue;   /**< VBLANK wait queue */
 	atomic_t *_vblank_count;        /**< number of VBLANK interrupts (driver must alloc the right number of counters) */
 	struct timeval *_vblank_time;   /**< timestamp of current vblank_count (drivers must alloc right number of fields) */
 	spinlock_t vblank_time_lock;    /**< Protects vblank count and time updates during vblank enable/disable */
 	spinlock_t vbl_lock;
 	atomic_t *vblank_refcount;      /* number of users of vblank interruptsper crtc */
 	u32 *last_vblank;               /* protected by dev->vbl_lock, used */
 					/* for wraparound handling */
 	int *vblank_enabled;            /* so we don't call enable more than
 					   once per disable */
 	int *vblank_inmodeset;          /* Display driver is setting mode */
 	u32 *last_vblank_wait;		/* Last vblank seqno waited per CRTC */
 	struct timer_list vblank_disable_timer;
 	u32 max_vblank_count;           /**< size of vblank counter register */
 	/**
 	 * List of events
 	 */
 	struct list_head vblank_event_list;
 	spinlock_t event_lock;
 	/*@} */
 	cycles_t ctx_start;
 	cycles_t lck_start;
 	struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */
 	wait_queue_head_t buf_readers;	/**< Processes waiting to read */
 	wait_queue_head_t buf_writers;	/**< Processes waiting to ctx switch */
 	struct drm_agp_head *agp;	/**< AGP data */
 	struct device *dev;             /**< Device structure */
 	struct pci_dev *pdev;		/**< PCI device structure */
 	int pci_vendor;			/**< PCI vendor id */
 	int pci_device;			/**< PCI device id */
 #ifdef __alpha__
 	struct pci_controller *hose;
 #endif
 	struct platform_device *platformdev; /**< Platform device struture */
 	struct usb_device *usbdev;
 	struct drm_sg_mem *sg;	/**< Scatter gather memory */
 	unsigned int num_crtcs;                  /**< Number of CRTCs on this device */
 	void *dev_private;		/**< device private data */
 	void *mm_private;
 	struct address_space *dev_mapping;
 	struct drm_sigdata sigdata;	   /**< For block_all_signals */
 	sigset_t sigmask;
 	struct drm_driver *driver;
 	struct drm_local_map *agp_buffer_map;
 	unsigned int agp_buffer_token;
 	struct drm_minor *control;		/**< Control node for card */
 	struct drm_minor *primary;		/**< render type primary screen head */
         struct drm_mode_config mode_config;	/**< Current mode config */
 	/** \name GEM information */
 	/*@{ */
 	spinlock_t object_name_lock;
 	struct idr object_name_idr;
 	/*@} */
 	int switch_power_state;
 };
 #define DRM_SWITCH_POWER_ON 0
 #define DRM_SWITCH_POWER_OFF 1
 #define DRM_SWITCH_POWER_CHANGING 2
 static __inline__ int drm_core_check_feature(struct drm_device *dev,
 					     int feature)
 {
 	return ((dev->driver->driver_features & feature) ? 1 : 0);
 }
 static inline int drm_dev_to_irq(struct drm_device *dev)
 {
 	return dev->driver->bus->get_irq(dev);
 }
 #if __OS_HAS_AGP
 static inline int drm_core_has_AGP(struct drm_device *dev)
 {
 	return drm_core_check_feature(dev, DRIVER_USE_AGP);
 }
 #else
 #define drm_core_has_AGP(dev) (0)
 #endif
 #if __OS_HAS_MTRR
 static inline int drm_core_has_MTRR(struct drm_device *dev)
 {
 	return drm_core_check_feature(dev, DRIVER_USE_MTRR);
 }
 #define DRM_MTRR_WC		MTRR_TYPE_WRCOMB
 static inline int drm_mtrr_add(unsigned long offset, unsigned long size,
 			       unsigned int flags)
 {
 	return mtrr_add(offset, size, flags, 1);
 }
 static inline int drm_mtrr_del(int handle, unsigned long offset,
 			       unsigned long size, unsigned int flags)
 {
 	return mtrr_del(handle, offset, size);
 }
 #else
 #define drm_core_has_MTRR(dev) (0)
 #define DRM_MTRR_WC		0
 static inline int drm_mtrr_add(unsigned long offset, unsigned long size,
 			       unsigned int flags)
 {
 	return 0;
 }
 static inline int drm_mtrr_del(int handle, unsigned long offset,
 			       unsigned long size, unsigned int flags)
 {
 	return 0;
 }
 #endif
 /******************************************************************/
 /** \name Internal function definitions */
 /*@{*/
 				/* Driver support (drm_drv.h) */
 extern long drm_ioctl(struct file *filp,
 		      unsigned int cmd, unsigned long arg);
 extern long drm_compat_ioctl(struct file *filp,
 			     unsigned int cmd, unsigned long arg);
 extern int drm_lastclose(struct drm_device *dev);
 				/* Device support (drm_fops.h) */
 extern struct mutex drm_global_mutex;
 extern int drm_open(struct inode *inode, struct file *filp);
 extern int drm_stub_open(struct inode *inode, struct file *filp);
 extern int drm_fasync(int fd, struct file *filp, int on);
 extern ssize_t drm_read(struct file *filp, char __user *buffer,
 			size_t count, loff_t *offset);
 extern int drm_release(struct inode *inode, struct file *filp);
 				/* Mapping support (drm_vm.h) */
 extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
 extern int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma);
 extern void drm_vm_open_locked(struct vm_area_struct *vma);
 extern void drm_vm_close_locked(struct vm_area_struct *vma);
 extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
 				/* Memory management support (drm_memory.h) */
 #include "drm_memory.h"
 extern void drm_mem_init(void);
 extern int drm_mem_info(char *buf, char **start, off_t offset,
 			int request, int *eof, void *data);
 extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
 extern void drm_free_agp(DRM_AGP_MEM * handle, int pages);
 extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start);
 extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev,
 				       struct page **pages,
 				       unsigned long num_pages,
 				       uint32_t gtt_offset,
 				       uint32_t type);
 extern int drm_unbind_agp(DRM_AGP_MEM * handle);
 				/* Misc. IOCTL support (drm_ioctl.h) */
 extern int drm_irq_by_busid(struct drm_device *dev, void *data,
 			    struct drm_file *file_priv);
 extern int drm_getunique(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
 extern int drm_setunique(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
 extern int drm_getmap(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv);
 extern int drm_getclient(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
 extern int drm_getstats(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 extern int drm_getcap(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv);
 extern int drm_setversion(struct drm_device *dev, void *data,
 			  struct drm_file *file_priv);
 extern int drm_noop(struct drm_device *dev, void *data,
 		    struct drm_file *file_priv);
 				/* Context IOCTL support (drm_context.h) */
 extern int drm_resctx(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv);
 extern int drm_addctx(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv);
 extern int drm_modctx(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv);
 extern int drm_getctx(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv);
 extern int drm_switchctx(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
 extern int drm_newctx(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv);
 extern int drm_rmctx(struct drm_device *dev, void *data,
 		     struct drm_file *file_priv);
 extern int drm_ctxbitmap_init(struct drm_device *dev);
 extern void drm_ctxbitmap_cleanup(struct drm_device *dev);
 extern void drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle);
 extern int drm_setsareactx(struct drm_device *dev, void *data,
 			   struct drm_file *file_priv);
 extern int drm_getsareactx(struct drm_device *dev, void *data,
 			   struct drm_file *file_priv);
 				/* Authentication IOCTL support (drm_auth.h) */
 extern int drm_getmagic(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 extern int drm_authmagic(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
 /* Cache management (drm_cache.c) */
 void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
 				/* Locking IOCTL support (drm_lock.h) */
 extern int drm_lock(struct drm_device *dev, void *data,
 		    struct drm_file *file_priv);
 extern int drm_unlock(struct drm_device *dev, void *data,
 		      struct drm_file *file_priv);
 extern int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context);
 extern void drm_idlelock_take(struct drm_lock_data *lock_data);
 extern void drm_idlelock_release(struct drm_lock_data *lock_data);
 /*
  * These are exported to drivers so that they can implement fencing using
  * DMA quiscent + idle. DMA quiescent usually requires the hardware lock.
  */
 extern int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv);
 				/* Buffer management support (drm_bufs.h) */
 extern int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request);
 extern int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request);
 extern int drm_addmap(struct drm_device *dev, resource_size_t offset,
 		      unsigned int size, enum drm_map_type type,
 		      enum drm_map_flags flags, struct drm_local_map **map_ptr);
 extern int drm_addmap_ioctl(struct drm_device *dev, void *data,
 			    struct drm_file *file_priv);
 extern int drm_rmmap(struct drm_device *dev, struct drm_local_map *map);
 extern int drm_rmmap_locked(struct drm_device *dev, struct drm_local_map *map);
 extern int drm_rmmap_ioctl(struct drm_device *dev, void *data,
 			   struct drm_file *file_priv);
 extern int drm_addbufs(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv);
 extern int drm_infobufs(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 extern int drm_markbufs(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 extern int drm_freebufs(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 extern int drm_mapbufs(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv);
 extern int drm_order(unsigned long size);
 				/* DMA support (drm_dma.h) */
 extern int drm_dma_setup(struct drm_device *dev);
 extern void drm_dma_takedown(struct drm_device *dev);
 extern void drm_free_buffer(struct drm_device *dev, struct drm_buf * buf);
 extern void drm_core_reclaim_buffers(struct drm_device *dev,
 				     struct drm_file *filp);
 				/* IRQ support (drm_irq.h) */
 extern int drm_control(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv);
 extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS);
 extern int drm_irq_install(struct drm_device *dev);
 extern int drm_irq_uninstall(struct drm_device *dev);
 extern void drm_driver_irq_preinstall(struct drm_device *dev);
 extern void drm_driver_irq_postinstall(struct drm_device *dev);
 extern void drm_driver_irq_uninstall(struct drm_device *dev);
 extern int drm_vblank_init(struct drm_device *dev, int num_crtcs);
 extern int drm_wait_vblank(struct drm_device *dev, void *data,
 			   struct drm_file *filp);
 extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
 extern u32 drm_vblank_count(struct drm_device *dev, int crtc);
 extern u32 drm_vblank_count_and_time(struct drm_device *dev, int crtc,
 				     struct timeval *vblanktime);
 extern bool drm_handle_vblank(struct drm_device *dev, int crtc);
 extern int drm_vblank_get(struct drm_device *dev, int crtc);
 extern void drm_vblank_put(struct drm_device *dev, int crtc);
 extern void drm_vblank_off(struct drm_device *dev, int crtc);
 extern void drm_vblank_cleanup(struct drm_device *dev);
 extern u32 drm_get_last_vbltimestamp(struct drm_device *dev, int crtc,
 				     struct timeval *tvblank, unsigned flags);
 extern int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
 						 int crtc, int *max_error,
 						 struct timeval *vblank_time,
 						 unsigned flags,
 						 struct drm_crtc *refcrtc);
 extern void drm_calc_timestamping_constants(struct drm_crtc *crtc);
 /* Modesetting support */
 extern void drm_vblank_pre_modeset(struct drm_device *dev, int crtc);
 extern void drm_vblank_post_modeset(struct drm_device *dev, int crtc);
 extern int drm_modeset_ctl(struct drm_device *dev, void *data,
 			   struct drm_file *file_priv);
 				/* AGP/GART support (drm_agpsupport.h) */
 extern struct drm_agp_head *drm_agp_init(struct drm_device *dev);
 extern int drm_agp_acquire(struct drm_device *dev);
 extern int drm_agp_acquire_ioctl(struct drm_device *dev, void *data,
 				 struct drm_file *file_priv);
 extern int drm_agp_release(struct drm_device *dev);
 extern int drm_agp_release_ioctl(struct drm_device *dev, void *data,
 				 struct drm_file *file_priv);
 extern int drm_agp_enable(struct drm_device *dev, struct drm_agp_mode mode);
 extern int drm_agp_enable_ioctl(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 extern int drm_agp_info(struct drm_device *dev, struct drm_agp_info *info);
 extern int drm_agp_info_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 extern int drm_agp_alloc(struct drm_device *dev, struct drm_agp_buffer *request);
 extern int drm_agp_alloc_ioctl(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
 extern int drm_agp_free(struct drm_device *dev, struct drm_agp_buffer *request);
 extern int drm_agp_free_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 extern int drm_agp_unbind(struct drm_device *dev, struct drm_agp_binding *request);
 extern int drm_agp_unbind_ioctl(struct drm_device *dev, void *data,
 			  struct drm_file *file_priv);
 extern int drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request);
 extern int drm_agp_bind_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 				/* Stub support (drm_stub.h) */
 extern int drm_setmaster_ioctl(struct drm_device *dev, void *data,
 			       struct drm_file *file_priv);
 extern int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 struct drm_master *drm_master_create(struct drm_minor *minor);
 extern struct drm_master *drm_master_get(struct drm_master *master);
 extern void drm_master_put(struct drm_master **master);
 extern void drm_put_dev(struct drm_device *dev);
 extern int drm_put_minor(struct drm_minor **minor);
 extern unsigned int drm_debug;
 extern unsigned int drm_vblank_offdelay;
 extern unsigned int drm_timestamp_precision;
 extern struct class *drm_class;
 extern struct proc_dir_entry *drm_proc_root;
 extern struct dentry *drm_debugfs_root;
 extern struct idr drm_minors_idr;
 extern struct drm_local_map *drm_getsarea(struct drm_device *dev);
 				/* Proc support (drm_proc.h) */
 extern int drm_proc_init(struct drm_minor *minor, int minor_id,
 			 struct proc_dir_entry *root);
 extern int drm_proc_cleanup(struct drm_minor *minor, struct proc_dir_entry *root);
 				/* Debugfs support */
 #if defined(CONFIG_DEBUG_FS)
 extern int drm_debugfs_init(struct drm_minor *minor, int minor_id,
 			    struct dentry *root);
 extern int drm_debugfs_create_files(struct drm_info_list *files, int count,
 				    struct dentry *root, struct drm_minor *minor);
 extern int drm_debugfs_remove_files(struct drm_info_list *files, int count,
                                     struct drm_minor *minor);
 extern int drm_debugfs_cleanup(struct drm_minor *minor);
 #endif
 				/* Info file support */
 extern int drm_name_info(struct seq_file *m, void *data);
 extern int drm_vm_info(struct seq_file *m, void *data);
 extern int drm_queues_info(struct seq_file *m, void *data);
 extern int drm_bufs_info(struct seq_file *m, void *data);
 extern int drm_vblank_info(struct seq_file *m, void *data);
 extern int drm_clients_info(struct seq_file *m, void* data);
 extern int drm_gem_name_info(struct seq_file *m, void *data);
 #if DRM_DEBUG_CODE
 extern int drm_vma_info(struct seq_file *m, void *data);
 #endif
 				/* Scatter Gather Support (drm_scatter.h) */
 extern void drm_sg_cleanup(struct drm_sg_mem * entry);
 extern int drm_sg_alloc_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 extern int drm_sg_alloc(struct drm_device *dev, struct drm_scatter_gather * request);
 extern int drm_sg_free(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv);
 			       /* ATI PCIGART support (ati_pcigart.h) */
 extern int drm_ati_pcigart_init(struct drm_device *dev,
 				struct drm_ati_pcigart_info * gart_info);
 extern int drm_ati_pcigart_cleanup(struct drm_device *dev,
 				   struct drm_ati_pcigart_info * gart_info);
 extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
 				       size_t align);
 extern void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
 extern void drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
 			       /* sysfs support (drm_sysfs.c) */
 struct drm_sysfs_class;
 extern struct class *drm_sysfs_create(struct module *owner, char *name);
 extern void drm_sysfs_destroy(void);
 extern int drm_sysfs_device_add(struct drm_minor *minor);
 extern void drm_sysfs_hotplug_event(struct drm_device *dev);
 extern void drm_sysfs_device_remove(struct drm_minor *minor);
 extern char *drm_get_connector_status_name(enum drm_connector_status status);
 extern int drm_sysfs_connector_add(struct drm_connector *connector);
 extern void drm_sysfs_connector_remove(struct drm_connector *connector);
 /* Graphics Execution Manager library functions (drm_gem.c) */
 int drm_gem_init(struct drm_device *dev);
 void drm_gem_destroy(struct drm_device *dev);
 void drm_gem_object_release(struct drm_gem_object *obj);
 void drm_gem_object_free(struct kref *kref);
 struct drm_gem_object *drm_gem_object_alloc(struct drm_device *dev,
 					    size_t size);
 int drm_gem_object_init(struct drm_device *dev,
 			struct drm_gem_object *obj, size_t size);
 void drm_gem_object_handle_free(struct drm_gem_object *obj);
 void drm_gem_vm_open(struct vm_area_struct *vma);
 void drm_gem_vm_close(struct vm_area_struct *vma);
 int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
 #include "drm_global.h"
 static inline void
 drm_gem_object_reference(struct drm_gem_object *obj)
 {
 	kref_get(&obj->refcount);
 }
 static inline void
 drm_gem_object_unreference(struct drm_gem_object *obj)
 {
 	if (obj != NULL)
 		kref_put(&obj->refcount, drm_gem_object_free);
 }
 static inline void
 drm_gem_object_unreference_unlocked(struct drm_gem_object *obj)
 {
 	if (obj != NULL) {
 		struct drm_device *dev = obj->dev;
 		mutex_lock(&dev->struct_mutex);
 		kref_put(&obj->refcount, drm_gem_object_free);
 		mutex_unlock(&dev->struct_mutex);
 	}
 }
 int drm_gem_handle_create(struct drm_file *file_priv,
 			  struct drm_gem_object *obj,
 			  u32 *handlep);
 int drm_gem_handle_delete(struct drm_file *filp, u32 handle);
 static inline void
 drm_gem_object_handle_reference(struct drm_gem_object *obj)
 {
 	drm_gem_object_reference(obj);
 	atomic_inc(&obj->handle_count);
 }
 static inline void
 drm_gem_object_handle_unreference(struct drm_gem_object *obj)
 {
 	if (obj == NULL)
 		return;
 	if (atomic_read(&obj->handle_count) == 0)
 		return;
 	/*
 	 * Must bump handle count first as this may be the last
 	 * ref, in which case the object would disappear before we
 	 * checked for a name
 	 */
 	if (atomic_dec_and_test(&obj->handle_count))
 		drm_gem_object_handle_free(obj);
 	drm_gem_object_unreference(obj);
 }
 static inline void
 drm_gem_object_handle_unreference_unlocked(struct drm_gem_object *obj)
 {
 	if (obj == NULL)
 		return;
 	if (atomic_read(&obj->handle_count) == 0)
 		return;
 	/*
 	* Must bump handle count first as this may be the last
 	* ref, in which case the object would disappear before we
 	* checked for a name
 	*/
 	if (atomic_dec_and_test(&obj->handle_count))
 		drm_gem_object_handle_free(obj);
 	drm_gem_object_unreference_unlocked(obj);
 }
 struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
 					     struct drm_file *filp,
 					     u32 handle);
 int drm_gem_close_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 int drm_gem_flink_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 int drm_gem_open_ioctl(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv);
 void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
 void drm_gem_release(struct drm_device *dev, struct drm_file *file_private);
 extern void drm_core_ioremap(struct drm_local_map *map, struct drm_device *dev);
 extern void drm_core_ioremap_wc(struct drm_local_map *map, struct drm_device *dev);
 extern void drm_core_ioremapfree(struct drm_local_map *map, struct drm_device *dev);
 static __inline__ struct drm_local_map *drm_core_findmap(struct drm_device *dev,
 							 unsigned int token)
 {
 	struct drm_map_list *_entry;
 	list_for_each_entry(_entry, &dev->maplist, head)
 	    if (_entry->user_token == token)
 		return _entry->map;
 	return NULL;
 }
 static __inline__ void drm_core_dropmap(struct drm_local_map *map)
 {
 }
 #include "drm_mem_util.h"
 extern int drm_fill_in_dev(struct drm_device *dev,
 			   const struct pci_device_id *ent,
 			   struct drm_driver *driver);
 int drm_get_minor(struct drm_device *dev, struct drm_minor **minor, int type);
 /*@}*/
 /* PCI section */
 static __inline__ int drm_pci_device_is_agp(struct drm_device *dev)
 {
 	if (dev->driver->device_is_agp != NULL) {
 		int err = (*dev->driver->device_is_agp) (dev);
 		if (err != 2) {
 			return err;
 		}
 	}
 	return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP);
 }
 static __inline__ int drm_pci_device_is_pcie(struct drm_device *dev)
 {
 	return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
 }
 extern int drm_pci_init(struct drm_driver *driver, struct pci_driver *pdriver);
 extern void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver);
 extern int drm_get_pci_dev(struct pci_dev *pdev,
 			   const struct pci_device_id *ent,
 			   struct drm_driver *driver);
 /* platform section */
 extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device);
 extern void drm_platform_exit(struct drm_driver *driver, struct platform_device *platform_device);
 extern int drm_get_platform_dev(struct platform_device *pdev,
 				struct drm_driver *driver);
 #endif				/* __KERNEL__ */
 #endif