Eric Lee / smarc-fsl-linux-kernel

18 Oct, 2016

1 commit

  • d3397484b   clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init ... Browse Code »

    The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
    also reset controller. It worked fine that single sysctrl/mediactrl
    device node in DT can be used to initialize clock driver and populate
    platform device for reset controller. But it stops working after
    commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
    gets merged. The commit sets flag OF_POPULATED during clock
    initialization to skip the platform device populating for the same
    device node. On hi6220, it effectively makes hi6220-sysctrl reset
    driver not probe any more.

    The patch changes hi6220 sysctrl and mediactrl clock init macro from
    CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using
    the same hardware block can continue working.

    Signed-off-by: Shawn Guo
    Tested-by: John Stultz
    Signed-off-by: Stephen Boyd

    Shawn Guo
     

07 Jul, 2016

1 commit

  • c6e80ace8   clk: hi6220: Change syspll and media_syspll clk to 1.19GHz ... Browse Code »

    In the bootloader of HiKey/96boards, syspll and media_syspll clk
    was initialized to 1.19GHz. So, here changes it in kernel accordingly.

    1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise
    HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI
    (74.25MHz required by standards). Closer pixel clock means better
    compatibility to HDMI monitors.

    Signed-off-by: Guodong Xu
    Signed-off-by: Xinliang Liu
    Signed-off-by: Michael Turquette
    Link: lkml.kernel.org/r/1467189955-21694-1-git-send-email-guodong.xu@linaro.org

    Xinliang Liu
     

01 Jul, 2016

1 commit

  • 6fb924dc9   clk: hi6220: Add RTC clock for pl031 ... Browse Code »

    Adds clk support for the pl031 RTC on hi6220

    Cc: Michael Turquette
    Cc: Stephen Boyd
    Cc: Rob Herring
    Cc: Pawel Moll
    Cc: Wei Xu
    Cc: Guodong Xu
    Signed-off-by: Zhangfei Gao
    [jstultz: Forward ported, tweaked commit description]
    Signed-off-by: John Stultz
    Signed-off-by: Stephen Boyd

    Zhangfei Gao
     

03 Mar, 2016

1 commit

04 Jun, 2015

1 commit

  • 72ea48610   clk: hi6220: Clock driver support for Hisilicon hi6220 SoC ... Browse Code »

    Add clock drivers for hi6220 SoC, this driver controls the SoC
    registers to supply different clocks to different IPs in the SoC.

    We add one divider clock for hi6220 because the divider in hi6220
    also has a mask bit but it doesnot obey the rule defined by flag
    "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
    left shift fixed bits (e.g. 16 bits), so we add this divider clock
    to handle it.

    Signed-off-by: Jorge Ramirez-Ortiz
    Signed-off-by: Bintian Wang
    Acked-by: Haojian Zhuang
    Reviewed-by: Zhangfei Gao
    Tested-by: Will Deacon
    Tested-by: Tyler Baker
    Tested-by: Kevin Hilman
    Signed-off-by: Michael Turquette

    Bintian Wang