14 Mar, 2019
1 commit
-
Pull UBI and UBIFS updates from Richard Weinberger:
- A new interface for UBI to deal better with read disturb
- Reject unsupported ioctl flags in UBIFS (xfstests found it)
* tag 'upstream-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs:
ubi: wl: Silence uninitialized variable warning
ubifs: Reject unsupported ioctl flags explicitly
ubi: Expose the bitrot interface
ubi: Introduce in_pq()
06 Mar, 2019
1 commit
-
This condition needs to be fipped around because "err" is uninitialized
when "force" is set. The Smatch static analysis tool complains and
UBsan will also complain at runtime.Fixes: 663586c0a892 ("ubi: Expose the bitrot interface")
Signed-off-by: Dan Carpenter
Reviewed-by: Nathan Chancellor
Tested-by: Nathan Chancellor
Signed-off-by: Richard Weinberger
05 Mar, 2019
2 commits
-
Pull spi updates from Mark Brown:
"A fairly quiet release for SPI, the biggest thing is the conversion to
use GPIO descriptors which is now 90% done but still needs some
stragglers converting.Summary:
- Support for inter-word delays
- Conversion of the core and most drivers to use GPIO descriptors for
GPIO controlled chip selects- New drivers for NXP FlexSPI and QuadSPI, SiFive and Spreadtrum"
* tag 'spi-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (104 commits)
spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3
spi: sifive: Remove redundant dev_err call in sifive_spi_probe()
spi: sifive: Remove spi_master_put in sifive_spi_remove()
spi: spi-gpio: fix SPI_CS_HIGH capability
spi: pxa2xx: Setup maximum supported DMA transfer length
spi: sifive: Add driver for the SiFive SPI controller
spi: sifive: Add DT documentation for SiFive SPI controller
spi: sprd: Add a prefix for SPI DMA channel macros
spi: sprd: spi: sprd: Add DMA mode support
dt-bindings: spi: Add the DMA properties for the SPI dma mode
spi: sprd: Add the SPI irq function for the SPI DMA mode
dt-bindings: spi: imx: Add an entry for the i.MX8QM compatible
spi: use gpio[d]_set_value_cansleep for setting chipselect GPIO
spi: gpio: Advertise support for SPI_CS_HIGH
spi: sh-msiof: Replace spi_master by spi_controller
spi: sh-hspi: Replace spi_master by spi_controller
spi: rspi: Replace spi_master by spi_controller
spi: atmel-quadspi: add support for sam9x60 qspi controller
dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60
spi: atmel-quadspi: add support for named peripheral clock
... -
Pull MTD updates from Boris Brezillon:
"Core MTD changes:
- Use struct_size() where appropriate
- mtd_{read,write}() as wrappers around mtd_{read,write}_oob()
- Fix misuse of PTR_ERR() in docg3
- Coding style improvements in mtdcore.cSPI NOR changes:
Core changes:
- Add support of octal mode I/O transfer
- Add a bunch of SPI NOR entries to the flash_info tableSPI NOR controller driver changes:
- cadence-quadspi:
* Add support for Octal SPI controller
* write upto 8-bytes data in STIG mode
- mtk-quadspi:
* rename config to a common one
* add SNOR_HWCAPS_READ to spi_nor_hwcaps mask
- Add Tudor as SPI-NOR co-maintainerNAND changes:
NAND core changes:
- Fourth batch of fixes/cleanup to the raw NAND core impacting
various controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2).
- Check the return code of nand_reset() and nand_readid_op().
- Remove ->legacy.erase and single_erase().
- Simplify the locking.
- Several implicit fall through annotations.Raw NAND controllers drivers changes:
- Fix various possible object reference leaks (MTK, JZ4780, Atmel)
- ST:
* Add support for STM32 FMC2 NAND flash controller
- Meson:
* Add support for Amlogic NAND flash controller
- Denali:
* Several cleanup patches
- Sunxi:
* Several cleanup patches
- FSMC:
* Disable NAND on remove()
* Reset NAND timings on resume()SPI-NAND drivers changes:
- Toshiba:
* Add support for all Toshiba products.
- Macronix:
* Fix ECC status read.
- Gigadevice:
* Add support for GD5F1GQ4UExxG"* tag 'mtd/for-5.1' of git://git.infradead.org/linux-mtd: (64 commits)
mtd: spi-nor: Fix wrong abbreviation HWCPAS
mtd: spi-nor: cadence-quadspi: fix spelling mistake: "Couldnt't" -> "Couldn't"
mtd: spi-nor: Add support for en25qh64
mtd: spi-nor: Add support for MX25V8035F
mtd: spi-nor: Add support for EN25Q80A
mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC
mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1
mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode
mtd: spi-nor: Add support for mx25u3235f
mtd: rawnand: denali_dt: remove single anonymous clock support
mtd: rawnand: mtk: fix possible object reference leak
mtd: rawnand: jz4780: fix possible object reference leak
mtd: rawnand: atmel: fix possible object reference leak
mtd: rawnand: fsmc: Disable NAND on remove()
mtd: rawnand: fsmc: Reset NAND timings on resume()
mtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG
mtd: rawnand: denali: remove unused dma_addr field from denali_nand_info
mtd: rawnand: denali: remove unused function argument 'raw'
mtd: rawnand: denali: remove unneeded denali_reset_irq() call
...
04 Mar, 2019
1 commit
25 Feb, 2019
2 commits
-
NAND core changes:
- Fourth batch of fixes/cleanup to the raw NAND core impacting various
controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2).
- Checking the return code of nand_reset() and nand_readid_op().
- Removing ->legacy.erase and single_erase().
- Simplifying the locking.
- Several implicit fall through annotations.Raw NAND controllers drivers changes:
- Fixing various possible object reference leaks (MTK, JZ4780, Atmel).
- ST:
* Adding support for STM32 FMC2 NAND flash controller.
- Meson:
* Adding support for Amlogic NAND flash controller.
- Denali:
* Several cleanup patches.
- Sunxi:
* Several cleanup patches.
- FSMC:
* Disabling NAND on remove().
* Resetting NAND timings on resume().SPI-NAND drivers changes:
- Toshiba:
* Adding support for all Toshiba products.
- Macronix:
* Fixing ECC status read.
- Gigadevice:
* Adding support for GD5F1GQ4UExxG. -
SPI NOR Changes
Core changes:
- Add support of octal mode I/O transfer
- Add a bunch of SPI NOR entries to the flash_info tableSPI NOR controller driver changes:
- cadence-quadspi:
* Add support for Octal SPI controller
* write upto 8-bytes data in STIG mode
- mtk-quadspi:
* rename config to a common one
* add SNOR_HWCAPS_READ to spi_nor_hwcaps maskMAINTAINERS:
- Add Tudor as SPI-NOR co-maintainer
24 Feb, 2019
2 commits
-
Using UBI_IOCRPEB and UBI_IOCSPEB userspace can force
reading and scrubbing of PEBs.In case of bitflips UBI will automatically take action
and move data to a different PEB.
This interface allows a daemon to foster your NAND.Signed-off-by: Richard Weinberger
-
This function works like in_wl_tree() but checks whether an ubi_wl_entry
is currently in the protection queue.
We need this function to query the current state of an ubi_wl_entry.Signed-off-by: Richard Weinberger
21 Feb, 2019
4 commits
-
There is a spelling mistake in a dev_error message. Fix it.
Signed-off-by: Colin Ian King
Reviewed-by: Tudor Ambarus
Signed-off-by: Boris Brezillon -
The Eon EN25QH64 is a 64 Mbit SPI NOR flash memory chip found
on recent wireless routers. Its 32, 128 and 256 Mbit siblings
are already supported.Tested on a COMFAST CF-E120A v3 router board.
Signed-off-by: Roger Pueyo Centelles
Reviewed-by: Tudor Ambarus
Signed-off-by: Boris Brezillon -
This adds support for the Macronix MX25V8035F, a 8Mb SPI NOR chip.
It is used on i.MX6UL/ULL SoMs by Kontron Electronics GmbH (N631x).
It was only tested with a single data line connected, by writing and
reading random data with dd.Signed-off-by: Frieder Schrempf
Reviewed-by: Tudor Ambarus
Signed-off-by: Boris Brezillon -
This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip.
It is used on i.MX6 boards by Kontron Electronics GmbH
(N60xx, N61xx).
It was only tested with a single data line connected, by writing and
reading random data with dd.Signed-off-by: Frieder Schrempf
Reviewed-by: Tudor Ambarus
Signed-off-by: Boris Brezillon
13 Feb, 2019
4 commits
-
Cadence OSPI controller IP supports Octal IO (x8 IO lines),
It also has an integrated PHY. IP register layout is very
similar to existing QSPI IP except for additional bits to support Octal
and Octal DDR mode. Therefore, extend current driver to support Octal
mode. Only Octal SDR read (1-1-8)mode is supported for now.Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
Signed-off-by: Vignesh R
Reviewed-by: Tudor Ambarus
Signed-off-by: Boris Brezillon -
Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of
the s25fl128s qspi memory, the single "s25fl128s" device entry must be
split into two to match the correct JEDEC ID's for each version. Solves
paging related issues of S25FL128SAGBHI210 chips.Signed-off-by: Ahmet Celenk
Cc: Boris Brezillon
Cc: Marek Vasut
Reviewed-by: Tudor Ambarus
Signed-off-by: Boris Brezillon -
This change helps me to get multiple mtd device registered. Without this
I getsysfs: cannot create duplicate filename '/bus/nvmem/devices/flash0'
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.0.0-rc2-00557-g1ef20ef21f22 #13
Call Trace:
[c0000000b38e3220] [c000000000b58fe4] dump_stack+0xe8/0x164 (unreliable)
[c0000000b38e3270] [c0000000004cf074] sysfs_warn_dup+0x84/0xb0
[c0000000b38e32f0] [c0000000004cf6c4] sysfs_do_create_link_sd.isra.0+0x114/0x150
[c0000000b38e3340] [c000000000726a84] bus_add_device+0x94/0x1e0
[c0000000b38e33c0] [c0000000007218f0] device_add+0x4d0/0x830
[c0000000b38e3480] [c0000000009d54a8] nvmem_register.part.2+0x1c8/0xb30
[c0000000b38e3560] [c000000000834530] mtd_nvmem_add+0x90/0x120
[c0000000b38e3650] [c000000000835bc8] add_mtd_device+0x198/0x4e0
[c0000000b38e36f0] [c00000000083619c] mtd_device_parse_register+0x11c/0x280
[c0000000b38e3780] [c000000000840830] powernv_flash_probe+0x180/0x250
[c0000000b38e3820] [c00000000072c120] platform_drv_probe+0x60/0xf0
[c0000000b38e38a0] [c0000000007283c8] really_probe+0x138/0x4d0
[c0000000b38e3930] [c000000000728acc] driver_probe_device+0x13c/0x1b0
[c0000000b38e39b0] [c000000000728c7c] __driver_attach+0x13c/0x1c0
[c0000000b38e3a30] [c000000000725130] bus_for_each_dev+0xa0/0x120
[c0000000b38e3a90] [c000000000727b2c] driver_attach+0x2c/0x40
[c0000000b38e3ab0] [c0000000007270f8] bus_add_driver+0x228/0x360
[c0000000b38e3b40] [c00000000072a2e0] driver_register+0x90/0x1a0
[c0000000b38e3bb0] [c00000000072c020] __platform_driver_register+0x50/0x70
[c0000000b38e3bd0] [c00000000105c984] powernv_flash_driver_init+0x24/0x38
[c0000000b38e3bf0] [c000000000010904] do_one_initcall+0x84/0x464
[c0000000b38e3cd0] [c000000001004548] kernel_init_freeable+0x530/0x634
[c0000000b38e3db0] [c000000000011154] kernel_init+0x1c/0x168
[c0000000b38e3e20] [c00000000000bed4] ret_from_kernel_thread+0x5c/0x68
mtd mtd1: Failed to register NVMEM deviceWith the change we now have
root@(none):/sys/bus/nvmem/devices# ls -al
total 0
drwxr-xr-x 2 root root 0 Feb 6 20:49 .
drwxr-xr-x 4 root root 0 Feb 6 20:49 ..
lrwxrwxrwx 1 root root 0 Feb 6 20:49 flash@0 -> ../../../devices/platform/ibm,opal:flash@0/mtd/mtd0/flash@0
lrwxrwxrwx 1 root root 0 Feb 6 20:49 flash@1 -> ../../../devices/platform/ibm,opal:flash@1/mtd/mtd1/flash@1Fixes: 1cbb4a1c433a ("mtd: powernv: Add powernv flash MTD abstraction driver")
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Boris Brezillon -
With this patch, we use the mtd->name instead of concatenating the name
with '0'.Fixes: c4dfa25ab307 ("mtd: add support for reading MTD devices via the nvmem API")
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Boris Brezillon
10 Feb, 2019
2 commits
-
cadence-quadspi controller allows upto eight bytes of data to
be written in software Triggered Instruction generator (STIG) mode
of operation. Lower 4 bytes are written through writedatalower and
upper 4 bytes by writedataupper register.This patch allows all the 8 bytes to be written.
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Tudor Ambarus
Reviewed-by: Vignesh R
Signed-off-by: Boris Brezillon -
The mx25u3235f is found on the ZyXEL NBG6817 router, therefore
add driver support for it so that we can upstream board support.Minimal tested with u-boot tools fw_printenv/fw_setenv on GlobalScale
ESPRESSObin v5 board.Signed-off-by: André Valentin
[miyatsu@qq.com: Remove unnecessary white space.]
Signed-off-by: Ding Tao
Reviewed-by: Tudor Ambarus
Signed-off-by: Boris Brezillon
08 Feb, 2019
4 commits
-
Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based
on IP datasheet") introduced a more correct binding that requires
three named clocks.Now that all upstream DT files migrated over to it, remove the single
anonymous clock support.Signed-off-by: Masahiro Yamada
Tested-by: Dinh Nguyen
Acked-by: Dinh Nguyen
Signed-off-by: Miquel Raynal -
of_find_device_by_node() takes a reference to the struct device
when it finds a match via get_device, there is no need to call
get_device() twice.
We also should make sure to drop the reference to the device
taken by of_find_device_by_node() on driver unbind.Fixes: 1d6b1e464950 ("mtd: mediatek: driver for MTK Smart Device")
Signed-off-by: Wen Yang
Signed-off-by: Miquel Raynal -
of_find_device_by_node() takes a reference to the struct device
when it finds a match via get_device, there is no need to call
get_device() twice.
We also should make sure to drop the reference to the device
taken by of_find_device_by_node() on driver unbind.Fixes: ae02ab00aa3c ("mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs")
Signed-off-by: Wen Yang
Signed-off-by: Miquel Raynal -
of_find_device_by_node() takes a reference to the struct device
when it finds a match via get_device, there is no need to call
get_device() twice.
We also should make sure to drop the reference to the device
taken by of_find_device_by_node() on driver unbind.Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver")
Signed-off-by: Wen Yang
Suggested-by: Boris Brezillon
Reviewed-by: Boris Brezillon
Reviewed-by: Miquel Raynal
Acked-by: Miquel Raynal
Cc: Tudor Ambarus
Cc: Boris Brezillon
Cc: Miquel Raynal
Cc: Richard Weinberger
Cc: David Woodhouse
Cc: Brian Norris
Cc: Marek Vasut
Cc: Nicolas Ferre
Cc: Alexandre Belloni
Cc: Ludovic Desroches
Cc: linux-mtd@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Miquel Raynal
06 Feb, 2019
2 commits
-
Disable BCH soft reset according to MX23 erratum #2847 ("BCH soft
reset may cause bus master lock up") for MX28 too. It has the same
problem.Observed problem: once per 100,000+ MX28 reboots NAND read failed on
DMA timeout errors:
[ 1.770823] UBI: attaching mtd3 to ubi0
[ 2.768088] gpmi_nand: DMA timeout, last DMA :1
[ 3.958087] gpmi_nand: BCH timeout, last DMA :1
[ 4.156033] gpmi_nand: Error in ECC-based read: -110
[ 4.161136] UBI warning: ubi_io_read: error -110 while reading 64
bytes from PEB 0:0, read only 0 bytes, retry
[ 4.171283] step 1 error
[ 4.173846] gpmi_nand: Chip: 0, Error -1Without BCH soft reset we successfully executed 1,000,000 MX28 reboots.
I have a quote from NXP regarding this problem, from July 18th 2016:
"As the i.MX23 and i.MX28 are of the same generation, they share many
characteristics. Unfortunately, also the erratas may be shared.
In case of the documented erratas and the workarounds, you can also
apply the workaround solution of one device on the other one. This have
been reported, but I’m afraid that there are not an estimated date for
updating the Errata documents.
Please accept our apologies for any inconveniences this may cause."Fixes: 6f2a6a52560a ("mtd: nand: gpmi: reset BCH earlier, too, to avoid NAND startup problems")
Cc: stable@vger.kernel.org
Signed-off-by: Manfred Schlaegl
Signed-off-by: Martin Kepplinger
Reviewed-by: Miquel Raynal
Reviewed-by: Fabio Estevam
Acked-by: Han Xu
Signed-off-by: Boris Brezillon -
Commit 33f45c44d68b ("mtd: Do not allow MTD devices with inconsistent
erase properties") introduced a check to make sure ->erasesize and
->_erase values are consistent with the MTD_NO_ERASE flag.
This patch did not take the 0 bytes partition case into account which
can happen when the defined partition is outside the flash device memory
range. Fix that by setting the partition erasesize to the parent
erasesize.Fixes: 33f45c44d68b ("mtd: Do not allow MTD devices with inconsistent erase properties")
Reported-by: Geert Uytterhoeven
Cc:
Cc: Geert Uytterhoeven
Signed-off-by: Boris Brezillon
Tested-by: Geert Uytterhoeven
05 Feb, 2019
15 commits
-
This disables the NAND on remove() and the errorpath,
making sure the chipselect gets deasserted when the
NAND is not in use.Cc: Miquel Raynal
Signed-off-by: Linus Walleij
Signed-off-by: Miquel Raynal -
When we go through a suspend/resume cycle the NAND
timings and other settings may have been lost so reset
the chip to bring it up in a known working state.The FSMC only supports single CS chips so we only need
to call nand_reset(chip, 0).Cc: Miquel Raynal
Signed-off-by: Linus Walleij
Signed-off-by: Miquel Raynal -
Add support for GigaDevice GD5F1GQ4UExxG SPI NAND chip.
Signed-off-by: Stefan Roese
Cc: Chuanhong Guo
Cc: Frieder Schrempf
Cc: Miquel Raynal
Cc: Boris Brezillon
Reviewed-by: Boris Brezillon
Signed-off-by: Miquel Raynal -
This is a leftover of commit 997cde2a2220 ("mtd: nand: denali: skip
driver internal bounce buffer when possible").Signed-off-by: Masahiro Yamada
Signed-off-by: Miquel Raynal -
This argument is not used at all.
Signed-off-by: Masahiro Yamada
Signed-off-by: Miquel Raynal -
This code was added by commit 26d266e10e5e ("mtd: nand: denali: fix
raw and oob accessors for syndrome page layout"), but I do not see
sensible reason.The IRQ flags are correctly reset by denali_cmd_ctrl(), so this code
is unneeded.Signed-off-by: Masahiro Yamada
Signed-off-by: Miquel Raynal -
nand_scan_ident() iterates over maxchips to find as many homogeneous
chips as possible.Since commit 2d472aba15ff ("mtd: nand: document the NAND
controller/NAND chip DT representation"), new drivers should pass in
the exact number of CS lines instead of possible max, but old
platforms may still rely on nand_scan_ident() to detect the actual
number of connected CS lines.In that case, this loop bails out when manufacturer or device ID
unmatches. The reason of unmatch is most likely no chip is connected
to that CS line. If so, nand_reset() should already have failed,
and the following nand_readid_op() is pointless.Before ->exec_op hook was introduced, drivers had no way to tell
the failure of NAND_CMD_RESET to the framework because the legacy
->cmdfunc() has void return type. Now drivers implementing ->exec_op
hook can return the error code. You can save nand_readid_op() by
checking the return value of nand_reset(). The return value of
nand_readid_op() should be checked as well. If it fails, probably
id[0] and id[1] are undefined values.Just for consistency, it should be sensible to check the return
code in nand_do_write_oob() as well.Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
Signed-off-by: Miquel Raynal -
Now that the last user of this hook, denali.c, stopped using it,
we can remove the erase hook from nand_legacy.I squashed single_erase() because only the difference between
single_erase() and nand_erase_op() is the number of bit shifts.The status/ret conversion in nand_erase_nand() is unneeded since
commit eb94555e9e97 ("mtd: nand: use usual return values for the
->erase() hook"). Cleaned it up now.Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
Signed-off-by: Miquel Raynal -
Commit f9ebd1bb4103 ("mtd: rawnand: Deprecate ->erase()") discouraged
the use of this hook, so I am happy to follow the suggestion.Although the Denali IP provides a special MAP10 command for erasing,
using it would not buy us much. The Denali IP actually works with the
generic erasing by single_erase() + ->cmdfunc hook (nand_command_lp)
+ ->cmd_ctrl hook (denali_cmd_ctrl).This method is also deprecated, but denali_erase() can go away
irrespective of ->exec_op conversion.Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
Signed-off-by: Miquel Raynal -
There is a plan to build the kernel with -Wimplicit-fallthrough and
these places in the code produced warnings (W=1).This commit removes the following warnings:
drivers/mtd/nand/raw/nand_base.c:5556:6: warning: this statement may fall through [-Wimplicit-fallthrough=]
drivers/mtd/nand/raw/nand_base.c:5575:6: warning: this statement may fall through [-Wimplicit-fallthrough=]
drivers/mtd/nand/raw/nand_base.c:5613:13: warning: this statement may fall through [-Wimplicit-fallthrough=]Signed-off-by: Mathieu Malaterre
Signed-off-by: Miquel Raynal -
There is a plan to build the kernel with -Wimplicit-fallthrough and
these places in the code produced warnings (W=1).This commit removes the following warnings:
drivers/mtd/nand/raw/nand_legacy.c:332:6: warning: this statement may fall through [-Wimplicit-fallthrough=]
drivers/mtd/nand/raw/nand_legacy.c:483:3: warning: this statement may fall through [-Wimplicit-fallthrough=]Signed-off-by: Mathieu Malaterre
Signed-off-by: Miquel Raynal -
Add device table for Toshiba Memory products.
Also, generalize OOB layout structure and function names.Signed-off-by: Yoshio Furuyama
Reviewed-by: Frieder Schrempf
Signed-off-by: Miquel Raynal -
Add initial support for the Amlogic NAND flash controller which is
available on Meson SoCs.Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Signed-off-by: Miquel Raynal -
nand_get_device() was complex for apparently no good reason. Let's
replace this locking scheme with 2 mutexes: one attached to the
controller and another one attached to the chip.Every time the core calls nand_get_device(), it will first lock the
chip and if the chip is not suspended, will then lock the controller.
nand_release_device() will release both lock in the reverse order.nand_get_device() can sleep, just like the previous implementation,
which means you should never call that from an atomic context.We also get rid of
- the chip->state field, since all it was used for was flagging the
chip as suspended. We replace it by a field called chip->suspended
and directly set it from nand_suspend/resume()
- the controller->wq and controller->active fields which are no longer
needed since the new controller->lock (now a mutex) guarantees that
all operations are serialized at the controller level
- panic_nand_get_device() which would anyway be a no-op. Talking about
panic write, I keep thinking the rawnand implementation is unsafe
because there's not negotiation with the controller to know when it's
actually done with it's previous operation. I don't intend to fix
that here, but that's probably something we should look at, or maybe
we should consider dropping the ->_panic_write() implementationLast important change to mention: we now return -EBUSY when someone
tries to access a device that as been suspended, and propagate this
error to the upper layer.Signed-off-by: Boris Brezillon
Signed-off-by: Miquel Raynal -
We are about to simplify the locking in the rawnand framework, and part
of this simplication is about getting rid of chip->state, so let's
first patch drivers that check the state.All of them do that to get a timeout value based on the operation that
is being executed. Since a timeout is, by definition, something that
is here to prevent hanging on an event that might never happen,
picking the maximum timeout value no matter the operation should be
harmless.Signed-off-by: Boris Brezillon
Signed-off-by: Miquel Raynal
