Eric Lee / smarc-fsl-linux-kernel

10 Mar, 2019

1 commit

  • 2901752c1   Merge tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci ... Browse Code »

    Pull PCI updates from Bjorn Helgaas:

    - Use match_string() instead of reimplementing it (Andy Shevchenko)

    - Enable SERR# forwarding for all bridges (Bharat Kumar Gogada)

    - Use Latency Tolerance Reporting if already enabled by platform (Bjorn
    Helgaas)

    - Save/restore LTR info for suspend/resume (Bjorn Helgaas)

    - Fix DPC use of uninitialized data (Dongdong Liu)

    - Probe bridge window attributes only once at enumeration-time to fix
    device accesses during rescan (Bjorn Helgaas)

    - Return BAR size (not "size -1 ") from pci_size() to simplify code (Du
    Changbin)

    - Use config header type (not class code) identify bridges more
    reliably (Honghui Zhang)

    - Work around Intel Denverton incorrect Trace Hub BAR size reporting
    (Alexander Shishkin)

    - Reorder pciehp cached state/hardware state updates to avoid missed
    interrupts (Mika Westerberg)

    - Turn ibmphp semaphores into completions or mutexes (Arnd Bergmann)

    - Mark expected switch fall-through (Mathieu Malaterre)

    - Use of_node_name_eq() for node name comparisons (Rob Herring)

    - Add ACS and pciehp quirks for HXT SD4800 (Shunyong Yang)

    - Consolidate Rohm Vendor ID definitions (Andy Shevchenko)

    - Use u32 (not __u32) for things not exposed to userspace (Logan
    Gunthorpe)

    - Fix locking semantics of bus and slot reset interfaces (Alex
    Williamson)

    - Update PCIEPORTBUS Kconfig help text (Hou Zhiqiang)

    - Allow portdrv to claim subtractive decode Ports so PCIe services will
    work for them (Honghui Zhang)

    - Report PCIe links that become degraded at run-time (Alexandru
    Gagniuc)

    - Blacklist Gigabyte X299 Root Port power management to fix Thunderbolt
    hotplug (Mika Westerberg)

    - Revert runtime PM suspend/resume callbacks that broke PME on network
    cable plug (Mika Westerberg)

    - Disable Data Link State Changed interrupts to prevent wakeup
    immediately after suspend (Mika Westerberg)

    - Extend altera to support Stratix 10 (Ley Foon Tan)

    - Allow building altera driver on ARM64 (Ley Foon Tan)

    - Replace Douglas with Tom Joseph as Cadence PCI host/endpoint
    maintainer (Lorenzo Pieralisi)

    - Add DT support for R-Car RZ/G2E (R8A774C0) (Fabrizio Castro)

    - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay Abraham I)

    - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay
    Abraham I)

    - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I)

    - Simplify dwc (remove unnecessary header includes, name variables
    consistently, reduce inverted logic, etc) (Gustavo Pimentel)

    - Add i.MX8MQ support (Andrey Smirnov)

    - Add message to help debug dwc MSI-X mask bit errors (Gustavo
    Pimentel)

    - Work around imx7d PCIe PLL erratum (Trent Piepho)

    - Don't assert qcom reset GPIO during probe (Bjorn Andersson)

    - Skip dwc MSI init if MSIs have been disabled (Lucas Stach)

    - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI
    endpoint framework (Wen Yang)

    - Add interface to discover supported endpoint features to replace a
    bitfield that wasn't flexible enough (Kishon Vijay Abraham I)

    - Implement the new supported-feature interface for designware-plat,
    dra7xx, rockchip, cadence (Kishon Vijay Abraham I)

    - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I)

    - Add layerscape endpoint mode support (Xiaowei Bao)

    - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya
    Nakamura)

    - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of
    open-coded reimplementation (Maya Nakamura)

    - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura)

    - Fix mediatek MMIO size computation to enable full size of available
    MMIO space (Honghui Zhang)

    - Fix mediatek DMA window size computation to allow endpoint DMA access
    to full DRAM address range (Honghui Zhang)

    - Fix mvebu prefetchable BAR regression caused by common bridge
    emulation that assumed all bridges had prefetchable windows (Thomas
    Petazzoni)

    - Make advk_pci_bridge_emul_ops static (Wei Yongjun)

    - Configure MPS settings for VMD root ports (Jon Derrick)

    * tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (92 commits)
    PCI: Update PCIEPORTBUS Kconfig help text
    PCI: Fix "try" semantics of bus and slot reset
    PCI/LINK: Report degraded links via link bandwidth notification
    dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
    PCI: altera: Enable driver on ARM64
    PCI: altera: Add Stratix 10 PCIe support
    PCI/PME: Fix possible use-after-free on remove
    PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static
    PCI: dwc: skip MSI init if MSIs have been explicitly disabled
    PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset()
    PCI: hv: Replace hv_vp_set with hv_vpset
    PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt
    PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM
    PCI: mediatek: Fix memory mapped IO range size computation
    PCI: dwc: Remove superfluous shifting in definitions
    PCI: dwc: Make use of GENMASK/FIELD_PREP
    PCI: dwc: Make use of BIT() in constant definitions
    PCI: dwc: Share code for dw_pcie_rd/wr_other_conf()
    PCI: dwc: Make use of IS_ALIGNED()
    PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ
    ...

    Linus Torvalds
     

04 Mar, 2019

3 commits

22 Feb, 2019

3 commits

  • daad4d2a0   spi: sifive: Remove redundant dev_err call in sifive_spi_probe() ... Browse Code »

    There is a error message within devm_ioremap_resource
    already, so remove the dev_err call to avoid redundant
    error message.

    Signed-off-by: Wei Yongjun
    Signed-off-by: Mark Brown

    Wei Yongjun
     
  • 049e5feae   spi: sifive: Remove spi_master_put in sifive_spi_remove() ... Browse Code »

    The call to spi_master_put() in sifive_spi_remove() is redundant since
    the master is registered using devm_spi_register_master() and no
    reference hold by using spi_master_get() in sifive_spi_remove().

    This is detected by Coccinelle semantic patch.

    Fixes: 484a9a68d669 ("spi: sifive: Add driver for the SiFive SPI controller")
    Signed-off-by: Wei Yongjun
    Signed-off-by: Mark Brown

    Wei Yongjun
     
  • b89fefda7   spi: spi-gpio: fix SPI_CS_HIGH capability ... Browse Code »

    spi-gpio is capable of dealing with active-high chip-selects.
    Unfortunately, commit 4b859db2c606 ("spi: spi-gpio: add SPI_3WIRE
    support") broke this by setting master->mode_bits, which overrides
    the setting in the spi-bitbang code. Fix this.

    [Fixed a trivial conflict with SPI_3WIRE_HIZ support -- broonie]

    Fixes: 4b859db2c606 ("spi: spi-gpio: add SPI_3WIRE support")
    Signed-off-by: Russell King
    Signed-off-by: Mark Brown
    Cc: stable@vger.kernel.org

    Russell King
     

21 Feb, 2019

2 commits

19 Feb, 2019

1 commit

13 Feb, 2019

5 commits

08 Feb, 2019

3 commits

07 Feb, 2019

11 commits

02 Feb, 2019

1 commit

31 Jan, 2019

2 commits

  • 473a78a7b   spi-atmel: support inter-word delay ... Browse Code »

    If the SPI slave requires an inter-word delay, configure the DLYBCT
    register accordingly.

    Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
    board).

    Signed-off-by: Jonas Bonn
    Acked-by: Nicolas Ferre
    CC: Nicolas Ferre
    CC: Mark Brown
    CC: Alexandre Belloni
    CC: Ludovic Desroches
    CC: linux-spi@vger.kernel.org
    CC: linux-arm-kernel@lists.infradead.org
    Signed-off-by: Mark Brown

    Jonas Bonn
     
  • b7bb367af   spi: support inter-word delay requirement for devices ... Browse Code »

    Some devices are slow and cannot keep up with the SPI bus and therefore
    require a short delay between words of the SPI transfer.

    The example of this that I'm looking at is a SAMA5D2 with a minimum SPI
    clock of 400kHz talking to an AVR-based SPI slave. The AVR cannot put
    bytes on the bus fast enough to keep up with the SoC's SPI controller
    even at the lowest bus speed.

    This patch introduces the ability to specify a required inter-word
    delay for SPI devices. It is up to the controller driver to configure
    itself accordingly in order to introduce the requested delay.

    Note that, for spi_transfer, there is already a field word_delay that
    provides similar functionality. This field, however, is specified in
    clock cycles (and worse, SPI controller cycles, not SCK cycles); that
    makes this value dependent on the master clock instead of the device
    clock for which the delay is intended to provide some relief. This
    patch leaves this old word_delay in place and provides a time-based
    word_delay_us alongside it; the new field fits in the struct padding
    so struct size is constant. There is only one in-kernel user of the
    word_delay field and presumably that driver could be reworked to use
    the time-based value instead.

    The time-based delay is limited to 8 bits as these delays are intended
    to be short. The SAMA5D2 that I've tested this on limits delays to a
    maximum of ~100us, which is already many word-transfer periods even at
    the minimum transfer speed supported by the controller.

    Signed-off-by: Jonas Bonn
    CC: Mark Brown
    CC: Rob Herring
    CC: Mark Rutland
    CC: linux-spi@vger.kernel.org
    CC: devicetree@vger.kernel.org
    Signed-off-by: Mark Brown

    Jonas Bonn
     

29 Jan, 2019

6 commits

28 Jan, 2019

2 commits

  • b32817944   spi: nxp-fspi: add octal mode flag bit for octal support ... Browse Code »

    Add octal mode flags for octal I/O data transfer support.
    NXP FlexSPI controller supports 8 lines Rx/Tx data transfer.

    Signed-off-by: Yogesh Narayan Gaur
    Signed-off-by: Mark Brown

    Yogesh Narayan Gaur
     
  • a5356aef6   spi: spi-mem: Add driver for NXP FlexSPI controller ... Browse Code »

    - Add driver for NXP FlexSPI host controller

    (0) What is the FlexSPI controller?
    FlexSPI is a flexsible SPI host controller which supports two SPI
    channels and up to 4 external devices. Each channel supports
    Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
    data lines) i.e. FlexSPI acts as an interface to external devices,
    maximum 4, each with up to 8 bidirectional data lines.

    It uses new SPI memory interface of the SPI framework to issue
    flash memory operations to up to four connected flash
    devices (2 buses with 2 CS each).

    (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility
    on NXP LX2160ARDB and LX2160AQDS targets.
    LX2160ARDB is having two NOR slave device connected on single bus A
    i.e. A0 and A1 (CS0 and CS1).
    LX2160AQDS is having two NOR slave device connected on separate buses
    one flash on A0 and second on B1 i.e. (CS0 and CS3).
    Verified this driver on following SPI NOR flashes:
    Micron, mt35xu512ab, [Read - 1 bit mode]
    Cypress, s25fl512s, [Read - 1/2/4 bit mode]

    Signed-off-by: Yogesh Narayan Gaur
    Reviewed-by: Frieder Schrempf
    Reviewed-by: Boris Brezillon
    Tested-by: Ashish Kumar
    Signed-off-by: Mark Brown

    Yogesh Narayan Gaur