09 Oct, 2008

4 commits


08 Oct, 2008

1 commit

  • The register definitions have been changed for the mpc5200 PSC ports
    to cover some of the changes in the mpc5200b. One change is that the
    ccr register is now a u32 instead of a u16. However, for the purposes
    of this driver we want to continue to use 16 bit access to avoid
    changing the existing (working) behaviour.

    This patch allows the driver to continue to do 16 bit accesses without
    the compiler complaining about it.

    Signed-off-by: Grant Likely

    Grant Likely
     

07 Oct, 2008

11 commits

  • When manipulating 64-bit PCI addresses, the code would lose the
    top 32-bit in a couple of places when shifting a pfn due to missing
    type casting from the 32-bit pfn to a 64-bit resource before the
    shift.

    This breaks using newer X servers for example on 440 machines
    with the PCI bus above 32-bit.

    Signed-off-by: Benjamin Herrenschmidt

    Benjamin Herrenschmidt
     
  • rtas_log_read() doesn't check file flags for O_NONBLOCK and blocks
    non-blocking readers of /proc/ppc64/rtas/error_log when there is
    no data available. This fixes it.

    Also rtas_log_read() returns now with ENODATA to prevent suspending of
    process in wait_event_interruptible() when logging facility was
    switched off and log is already empty.

    Signed-off-by: Vitaly Mayatskikh
    Acked-by: David Howells
    Signed-off-by: Benjamin Herrenschmidt

    Vitaly Mayatskikh
     
  • Fix various defconfigs for Freescale chip based boards to remove
    CONFIG_PPC_PMAC or CONFIG_PPC_CHRP which crept in due to those
    being default y

    Signed-off-by: Timur Tabi
    Signed-off-by: Benjamin Herrenschmidt

    Timur Tabi
     
  • powerpc uses CONFIG_FORCE_MAX_ZONEORDER, and some things depend on it
    being at least 10 when 64k pages are not configured (notably the dart
    iommu code with CONFIG_PM). The defaults are fine, but when going from a
    64K pages config to one without 64K pages, MAX_ORDER stays at 9 which is
    too low for 4K pages.

    This patch makes the Kconfig enforce at least the defaults.

    Signed-off-by: Johannes Berg
    Acked-by: Timur Tabi
    Signed-off-by: Benjamin Herrenschmidt

    Johannes Berg
     
  • A bug in my initial 64-bit hibernation code breaks it when using
    page sizes that aren't 4K.

    Signed-off-by: Johannes Berg
    Signed-off-by: Benjamin Herrenschmidt

    Johannes Berg
     
  • The variable statindex in send_request is never read, so remove it.

    Signed-off-by: Johann Felix Soden
    Signed-off-by: Benjamin Herrenschmidt

    Johann Felix Soden
     
  • Documentation/powerpc/smp.txt is so outdated that it makes sense to just
    remove it.

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Benjamin Herrenschmidt

    Geert Uytterhoeven
     
  • commit 14cf11af6cf608eb8c23e989ddb17a715ddce109 ("powerpc: Merge enough to
    start building in arch/powerpc.") unwired /proc/ppc_htab, and commit
    917f0af9e5a9ceecf9e72537fabb501254ba321d ("powerpc: Remove arch/ppc and
    include/asm-ppc") removed the rest of the /proc/ppc_htab support, but there are
    still a few references left. Kill them for good.

    Signed-off-by: Geert Uytterhoeven
    Signed-off-by: Benjamin Herrenschmidt

    Geert Uytterhoeven
     
  • Commit 8b150478 ("ppc: make phys_mem_access_prot() work with pfns
    instead of addresses") fixed page_is_ram() in arch/ppc to avoid overflow
    for addresses above 4G on 32-bit kernels. However arch/powerpc's
    page_is_ram() is missing the same fix -- it computes a physical address
    by doing pfn << PAGE_SHIFT, which overflows if pfn corresponds to a page
    above 4G.

    In particular this causes pages above 4G to be mapped with the wrong
    caching attribute; for example many ppc440-based SoCs have PCI space
    above 4G, and mmap()ing MMIO space may end up with a mapping that has
    caching enabled.

    Fix this by working with the pfn and avoiding the conversion to
    physical address that causes the overflow. This patch compares the
    pfn to max_pfn, which is a semantic change from the old code -- that
    code compared the physical address to high_memory, which corresponds
    to max_low_pfn. However, I think that was is another bug, since
    highmem pages are still RAM.

    Reported-by: vb
    Signed-off-by: Roland Dreier
    Acked-by: Benjamin Herrenschmidt
    Signed-off-by: Benjamin Herrenschmidt

    Roland Dreier
     
  • Add a .gitignore in arch/powerpc/kernel to ignore the generated
    vmlinux.lds.

    Signed-off-by: Sebastien Dugue
    Signed-off-by: Benjamin Herrenschmidt

    Sebastien Dugue
     
  • Benjamin Herrenschmidt
     

03 Oct, 2008

4 commits


02 Oct, 2008

3 commits


01 Oct, 2008

1 commit

  • The math emulation code is centered around a set of generic macros that
    provide the core of the emulation that are shared by the various
    architectures and other projects (like glibc). Each arch implements its
    own sfp-machine.h to specific various arch specific details.

    For historic reasons that are now lost the powerpc math-emu code had
    its own version of the common headers. This moves us to using the
    kernel generic version and thus getting fixes when those are updated.

    Also cleaned up exception/error reporting from the FP emulation functions.

    Signed-off-by: Kumar Gala

    Kumar Gala
     

30 Sep, 2008

3 commits

  • The PowerPC 405EZ SoC has some differences in the interrupt layout and
    handling for the MAL. The SERR, TXDE, and RXDE interrupts are OR'd into
    a single interrupt. Also, due to the possibility for interrupt coalescing,
    the TXEOB and RXEOB interrupts require an interrupt bit to be cleared in
    the ICINTSTAT SDR.

    This sets the proper MAL feature bits for 405EZ boards, and adds a common
    shared handler for SERR, TXDE, and RXDE. The defines for the ICINTSTAT DCR
    are added to the proper header file as well.

    This has been adapted from code originally written by Stefan Roese.

    Signed-off-by: Josh Boyer
    Acked-by: Benjamin Herrenschmidt
    Acked-by: Jeff Garzik
    Signed-off-by: Josh Boyer

    Josh Boyer
     
  • There are some PowerPC SoCs that do odd things with the MAL handling. In
    order to accommodate them, we need to introduce a feature mechanism that is
    similar to the existing emac_has_feature function.

    This adds a feature variable to the mal_instance structure, and adds a
    mal_has_feature function. Two features are defined and are guarded
    by Kconfig options that are selected by the affected platforms.

    MAL_FTR_CLEAR_ICINSTAT is used for platforms that need to clear the
    interrupt bits in the ICINTSTAT SDR for txeob/rxeob. This is common
    on MAL implementations that have interrupt coalescing.

    MAL_FTR_COMMON_ERR_INT is used for platforms that have SERR, TXDE,
    and RXDE OR'd into a single interrupt bit.

    Signed-off-by: Josh Boyer
    Acked-by: Benjamin Herrenschmidt
    Acked-by: Jeff Garzik
    Signed-off-by: Josh Boyer

    Josh Boyer
     
  • Some PowerPC 40x chips have errata that force us not to use the integrated
    flow control. We have the feature defined, but it currently can't be used
    because it is never added to EMAC_FTRS_POSSIBLE.

    This adds a Kconfig option for affected platforms to select and puts the
    feature in the EMAC_FTRS_POSSIBLE list. This is set for PowerPC 405EZ
    platforms as well.

    Signed-off-by: Josh Boyer
    Acked-by: Benjamin Herrenschmidt
    Acked-by: Jeff Garzik
    Signed-off-by: Josh Boyer

    Josh Boyer
     

29 Sep, 2008

3 commits


25 Sep, 2008

10 commits

  • Now that arch/ppc is gone we don't need CONFIG_PPC_MERGE anymore
    remove the dead code associated with !CONFIG_PPC_MERGE.

    Signed-off-by: Kumar Gala

    Kumar Gala
     
  • This rearranges a bit of code, and adds support for
    36-bit physical addressing for configs that use a
    hashed page table. The 36b physical support is not
    enabled by default on any config - it must be
    explicitly enabled via the config system.

    This patch *only* expands the page table code to accomodate
    large physical addresses on 32-bit systems and enables the
    PHYS_64BIT config option for 86xx. It does *not*
    allow you to boot a board with more than about 3.5GB of
    RAM - for that, SWIOTLB support is also required (and
    coming soon).

    Signed-off-by: Becky Bruce
    Signed-off-by: Kumar Gala

    Becky Bruce
     
  • Implement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will
    be used by the fast get_user_pages() to differenciate PTEs that correspond
    to a valid struct page from special mappings that don't such as IO mappings
    obtained via io_remap_pfn_ranges().

    We currently only implement this on sub-arch that support SMP or will so
    in the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).

    Signed-off-by: Kumar Gala
    Acked-by: Benjamin Herrenschmidt

    Kumar Gala
     
  • There are some minor issues with support 64-bit PTEs on a 32-bit processor
    when dealing with SMP.

    * We need to order the stores in set_pte_at to make sure the flag word
    is set second.
    * Change pte_clear to use pte_update so only the flag word is cleared
    * Added a WARN_ON to set_pte_at to ensure the pte isn't present for
    the 64-bit pte/SMP case (to ensure our assumption of this fact).

    Signed-off-by: Kumar Gala
    Acked-by: Becky Bruce

    Kumar Gala
     
  • Introduced a new set of low level tlb invalidate functions that do not
    broadcast invalidates on the bus:

    _tlbil_all - invalidate all
    _tlbil_pid - invalidate based on process id (or mm context)
    _tlbil_va - invalidate based on virtual address (ea + pid)

    On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and
    _tlbil_va should be functionally equivalent to _tlbie.

    The intent of this change is to handle SMP based invalidates via IPIs instead
    of broadcasts as the mechanism scales better for larger number of cores.

    On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls
    and tlbsx/tlbwe for invalidate virtual address.

    Signed-off-by: Kumar Gala

    Kumar Gala
     
  • Signed-off-by: Becky Bruce
    Signed-off-by: Kumar Gala

    Becky Bruce
     
  • We essentially adopt the 64-bit dma code, with some changes to support
    32-bit systems, including HIGHMEM. dma functions on 32-bit are now
    invoked via accessor functions which call the correct op for a device based
    on archdata dma_ops. If there is no archdata dma_ops, this defaults
    to dma_direct_ops.

    In addition, the dma_map/unmap_page functions are added to dma_ops
    because we can't just fall back on map/unmap_single when HIGHMEM is
    enabled. In the case of dma_direct_*, we stop using map/unmap_single
    and just use the page version - this saves a lot of ugly
    ifdeffing. We leave map/unmap_single in the dma_ops definition,
    though, because they are needed by the iommu code, which does not
    implement map/unmap_page. Ideally, going forward, we will completely
    eliminate map/unmap_single and just have map/unmap_page, if it's
    workable for 64-bit.

    Signed-off-by: Becky Bruce
    Signed-off-by: Kumar Gala

    Becky Bruce
     
  • Use the struct device's numa_node instead; use accessor functions
    to get/set numa_node.

    Signed-off-by: Becky Bruce
    Signed-off-by: Kumar Gala

    Becky Bruce
     
  • 32-bit platforms are about to start using dma.c; move the iommu
    dma ops into their own file to make this a bit cleaner.

    Signed-off-by: Becky Bruce
    Signed-off-by: Kumar Gala

    Becky Bruce
     
  • This is in preparation for the merge of the 32 and 64-bit
    dma code in arch/powerpc.

    Signed-off-by: Becky Bruce
    Signed-off-by: Kumar Gala

    Becky Bruce