09 May, 2016
1 commit
-
arm-ccn driver uses irq_set_affinity, which is not exported and
hence cannot be built as a module, eventhough we have all the
bits ready. This patch makes use of the exported helper
irq_set_affinity_hint() instead. Also, the __free_irq expects
the affinity_hint to be NULL when we free the irq. So set the
affinity_hint to NULL at clean up.Now that we can build it as a module, update the Kconfig to
reflect the change.Cc: Will Deacon
Cc: Mark Rutland
Cc: Paul Gortmaker
Acked-by: Pawel Moll
Signed-off-by: Suzuki K Poulose
Signed-off-by: Arnd Bergmann
26 Apr, 2016
1 commit
-
Merge "Broadcom ARM-based SoCs drivers changes" from Florian Fainelli:
- Justin adds a soc_dev driver to properly report to user-space the Broadcom
STB SoC family, product and revision- Florian reworks how the brcmstb_gisb driver dependency is done to enable it
on Broadcom STB MIPS-based SoCs and remove a select in
arch/arm/mach-bcm/Kconfig* tag 'arm-soc/for-4.7/drivers' of http://github.com/Broadcom/stblinux:
bus: brcmstb_gisb: Rework dependencies
soc: brcmstb: add SoC driver to brcmstb
19 Apr, 2016
1 commit
-
Do not have the machine Kconfig entry point need to select
BRCMSTB_GISB_ARB, instead, just let it be default ARCH_BRCMSTB which is
a better way to deal with this. While at it, also make it default
BMIPS_GENERIC so the legacy MIPS-based STB platforms can benefit from
the same thing.Signed-off-by: Florian Fainelli
28 Mar, 2016
1 commit
-
Make use of ARCH_RENESAS in place of ARCH_SHMOBILE.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.Acked-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
22 Mar, 2016
1 commit
-
Pull arm[64] perf updates from Will Deacon:
"I have another mixed bag of ARM-related perf patches here.It's about 25% CPU and 75% interconnect, but with drivers/bus/
languishing without an obvious maintainer or tree, Olof and I agreed
to keep all of these PMU patches together. I suspect a whole load of
code from drivers/bus/arm-* can be moved under drivers/perf/, so
that's on the radar for the future.Summary:
- Initial support for ARMv8.1 CPU PMUs
- Support for the CPU PMU in Cavium ThunderX
- CPU PMU support for systems running 32-bit Linux in secure mode
- Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect)"
* tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (26 commits)
drivers/perf: arm_pmu: avoid NULL dereference when not using devicetree
arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC
arm-cci: remove unused variable
arm-cci: don't return value from void function
arm-cci: make private functions static
arm-cci: CoreLink CCI-550 PMU driver
arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU
arm-cci: CCI-500: Work around PMU counter writes
arm-cci: Provide hook for writing to PMU counters
arm-cci: Add helper to enable PMU without synchornising counters
arm-cci: Add routines to save/restore all counters
arm-cci: Get the status of a counter
arm-cci: write_counter: Remove redundant check
arm-cci: Delay PMU counter writes to pmu::pmu_enable
arm-cci: Refactor CCI PMU enable/disable methods
arm-cci: Group writes to counter
arm-cci: fix handling cpumask_any_but return value
arm-cci: simplify sysfs attr handling
drivers/perf: arm_pmu: implement CPU_PM notifier
arm64: dts: Add Cavium ThunderX specific PMU
...
01 Mar, 2016
2 commits
-
Add ARM CoreLink CCI-550 cache coherent interconnect PMU
driver support. The CCI-550 PMU shares all the attributes of CCI-500
PMU, except for an additional master interface (MI-6 - 0xe).
CCI-550 requires the same work around as for CCI-500 to
write to the PMU counter.Acked-by: Olof Johansson
Acked-by: Punit Agrawal
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
Signed-off-by: Will Deacon -
CCI-550 PMU shares most of the CCI-500 PMU attributes including the
event format, PMU event codes. The only difference is an additional
master interface (MI6 - 0xe). Hence we share the driver code for both,
except for a model specific event validate method.
This patch renames the common CCI500 symbols to CCI5xx, including the
Kconfig symbol.No functional changes to the PMU driver.
Acked-by: Olof Johansson
Acked-by: Punit Agrawal
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
Signed-off-by: Will Deacon
02 Feb, 2016
1 commit
-
At first, commit 4b7f48d395a7 ("bus: uniphier-system-bus: add UniPhier
System Bus driver") introduced this driver as a tristate one.Then, commit 326ea45aa827 ("bus: uniphier: allow only built-in
driver") temporarily made it boolean in order to fix a link error
in case it is compiled as a module.The root cause was fixed by commit b80443c2211c ("of/platform: export
of_default_bus_match_table").Now this driver can really be a module.
Signed-off-by: Masahiro Yamada
Signed-off-by: Olof Johansson
01 Jan, 2016
1 commit
-
Building the newly added uniphier system bus driver as a module
causes a link error, so let's only allow it to be built-in for
now, to fix allmodconfig:ERROR: "of_default_bus_match_table" [drivers/bus/uniphier-system-bus.ko] undefined!
Signed-off-by: Arnd Bergmann
23 Dec, 2015
1 commit
-
The UniPhier System Bus is an external bus that connects on-board
devices to the UniPhier SoC. Each bank (chip select) is dynamically
mapped to the CPU-viewed address base via the bus controller. The
bus controller must be configured before any access to the bus.This driver parses the "ranges" property of the System Bus node and
initialized the bus controller. After the bus becomes ready, devices
below it are populated.Note:
Each bank can be mapped anywhere in the supported address space;
there is nothing preventing us from assigning bank 0 on 0x42000000,
0x43000000, or anywhere as long as such region is not used by others.
So, the "ranges" is just one possible software configuration, which
does not seem to fit in device tree because device tree is a hardware
description language. However, of_translate_address() requires
"ranges" in every bus node between CPUs and device mapped on the CPU
address space. In other words, "ranges" properties must be statically
defined in device tree. After some discussion, I decided the dynamic
address reassignment by the driver is too bothersome. Instead, the
device tree should provide a reasonable translation setup that the OS
can rely on.Signed-off-by: Masahiro Yamada
Acked-by: Rob Herring
Acked-by: Arnd Bergmann
Signed-off-by: Olof Johansson
11 Nov, 2015
1 commit
-
Pull ARM SoC driver updates from Olof Johansson:
"As we've enabled multiplatform kernels on ARM, and greatly done away
with the contents under arch/arm/mach-*, there's still need for
SoC-related drivers to go somewhere.Many of them go in through other driver trees, but we still have
drivers/soc to hold some of the "doesn't fit anywhere" lowlevel code
that might be shared between ARM and ARM64 (or just in general makes
sense to not have under the architecture directory).This branch contains mostly such code:
- Drivers for qualcomm SoCs for SMEM, SMD and SMD-RPM, used to
communicate with power management blocks on these SoCs for use by
clock, regulator and bus frequency drivers.- Allwinner Reduced Serial Bus driver, again used to communicate with
PMICs.- Drivers for ARM's SCPI (System Control Processor). Not to be
confused with PSCI (Power State Coordination Interface). SCPI is
used to communicate with the assistant embedded cores doing power
management, and we have yet to see how many of them will implement
this for their hardware vs abstracting in other ways (or not at all
like in the past).- To make confusion between SCPI and PSCI more likely, this release
also includes an update of PSCI to interface version 1.0.- Rockchip support for power domains.
- A driver to talk to the firmware on Raspberry Pi"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (57 commits)
soc: qcom: smd-rpm: Correct size of outgoing message
bus: sunxi-rsb: Add driver for Allwinner Reduced Serial Bus
bus: sunxi-rsb: Add Allwinner Reduced Serial Bus (RSB) controller bindings
ARM: bcm2835: add mutual inclusion protection
drivers: psci: make PSCI 1.0 functions initialization version dependent
dt-bindings: Correct paths in Rockchip power domains binding document
soc: rockchip: power-domain: don't try to print the clock name in error case
soc: qcom/smem: add HWSPINLOCK dependency
clk: berlin: add cpuclk
ARM: berlin: dts: add CLKID_CPU for BG2Q
ARM: bcm2835: Add the Raspberry Pi firmware driver
soc: qcom: smem: Move RPM message ram out of smem DT node
soc: qcom: smd-rpm: Correct the active vs sleep state flagging
soc: qcom: smd: delete unneeded of_node_put
firmware: qcom-scm: build for correct architecture level
soc: qcom: smd: Correct SMEM items for upper channels
qcom-scm: add missing prototype for qcom_scm_is_available()
qcom-scm: fix endianess issue in __qcom_scm_is_call_available
soc: qcom: smd: Reject send of too big packets
soc: qcom: smd: Handle big endian CPUs
...
26 Oct, 2015
1 commit
-
Reduced Serial Bus (RSB) is an Allwinner proprietery interface
used to communicate with PMICs and other peripheral ICs.RSB is a two-wire push-pull serial bus that supports 1 master
device and up to 15 active slave devices.Signed-off-by: Chen-Yu Tsai
Reviewed-by: Mark Brown
Acked-by: Arnd Bergmann
Signed-off-by: Maxime Ripard
Signed-off-by: Olof Johansson
29 Sep, 2015
1 commit
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Disable building CCI-500 PMU driver by default.
Reported-by: Russell King
Cc: Punit Agrawal
Cc: Mark Rutland
Cc: arm@kernel.org
Signed-off-by: Suzuki K. Poulose
Signed-off-by: Olof Johansson
29 May, 2015
3 commits
-
CCI-500 provides 8 event counters which can count any of the
supported events independently. The PMU event id is a 9-bit
value made of two parts.
bits [8:5] - Source port
0x0-0x6 Slave Ports
0x8-0xD Master Ports
0xf Global Events to CCI
0x7,0xe Reserved
bits [0:4] - Event code (specific to each type of port)The generic CCI-500 controlling interface remains the same with CCI-400.
However there are some differences in the PMU event counters.
- No cycle counter
- Upto 8 counters(4 in CCI-400)
- Each counter area is 64K(4K in CCI400)
- The counter0 starts at offset 0x10000 from the base of CCICc: Punit Agrawal
Cc: Mark Rutland
Cc: Will Deacon
Cc: devicetree@vger.kernel.org
Signed-off-by: Suzuki K. Poulose
Acked-by: Punit Agrawal
Signed-off-by: Arnd Bergmann -
Rename CCI400 specific defintions from CCI_xxx to CCI400_xxx.
Introduce generic ARM_CCI_PMU to cover common code for handling
the CCI PMU.Cc: Mark Rutland
Cc: Will Deacon
Cc: Punit Agrawal
Signed-off-by: Suzuki K. Poulose
Acked-by: Punit Agrawal
Signed-off-by: Arnd Bergmann -
Do not enable CCI-400 PMU by default and fix the dependency on PERF_EVENTS
than HW_PERF_EVENTS.Reported-by: Russell King
Cc: Will Deacon
Cc: arm@kernel.org
Cc: Russell King
Signed-off-by: Suzuki K. Poulose
Signed-off-by: Arnd Bergmann
23 Apr, 2015
1 commit
-
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for v4.1. Some of these are for drivers/soc, where we
find more and more SoC-specific drivers these days. Some are for
other driver subsystems where we have received acks from the
appropriate maintainers.The larger parts of this branch are:
- MediaTek support for their PMIC wrapper interface, a high-level
interface for talking to the system PMIC over a dedicated I2C
interface.- Qualcomm SCM driver has been moved to drivers/firmware. It's used
for CPU up/down and needs to be in a shared location for arm/arm64
common code.- cleanup of ARM-CCI PMU code.
- another set of cleanusp to the OMAP GPMC code"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
soc/mediatek: Remove unused variables
clocksource: atmel-st: select MFD_SYSCON
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs
arm-cci: Fix CCI PMU event validation
arm-cci: Split the code for PMU vs driver support
arm-cci: Get rid of secure transactions for PMU driver
arm-cci: Abstract the CCI400 PMU specific definitions
arm-cci: Rearrange code for splitting PMU vs driver code
drivers: cci: reject groups spanning multiple HW PMUs
ARM: at91: remove useless include
clocksource: atmel-st: remove mach/hardware dependency
clocksource: atmel-st: use syscon/regmap
ARM: at91: time: move the system timer driver to drivers/clocksource
ARM: at91: properly initialize timer
ARM: at91: at91rm9200: remove deprecated arm_pm_restart
watchdog: at91rm9200: implement restart handler
watchdog: at91rm9200: use the system timer syscon
mfd: syscon: Add atmel system timer registers definition
ARM: at91/dt: declare atmel,at91rm9200-st as a syscon
soc: qcom: gsbi: Add support for ADM CRCI muxing
...
04 Apr, 2015
1 commit
-
…inux into next/drivers
Merge "arm-cci PMU updates for 4.1" from Will Deacon:
CCI-400 PMU updates
This series reworks some of the CCI-400 PMU code so that it can be used
on both ARM and ARM64-based systems, without the need to boot in secure
mode on the latter. This paves the way for CCI-500 support in future.* tag 'arm-perf-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux:
arm-cci: Fix CCI PMU event validation
arm-cci: Split the code for PMU vs driver support
arm-cci: Get rid of secure transactions for PMU driver
arm-cci: Abstract the CCI400 PMU specific definitions
arm-cci: Rearrange code for splitting PMU vs driver code
drivers: cci: reject groups spanning multiple HW PMUs
+ Linux 4.0-rc4Signed-off-by: Olof Johansson <olof@lixom.net>
31 Mar, 2015
1 commit
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Add MIPS Common Device Memory Map (CDMM) support in the form of a bus in
the standard Linux device model. Each device attached via CDMM is
discoverable via an 8-bit type identifier and may contain a number of
blocks of memory mapped registers in the CDMM region. IRQs are expected
to be handled separately.Due to the per-cpu (per-VPE for MT cores) nature of the CDMM devices,
all the driver callbacks take place from workqueues which are run on the
right CPU for the device in question, so that the driver doesn't need to
be as concerned about which CPU it is running on. Callbacks also exist
for when CPUs are taken offline, so that any per-CPU resources used by
the driver can be disabled so they don't get forcefully migrated. CDMM
devices are created as children of the CPU device they are attached to.Any existing CDMM configuration by the bootloader will be inherited,
however platforms wishing to enable CDMM should implement the weak
mips_cdmm_phys_base() function (see asm/cdmm.h) so that the bus driver
knows where it should put the CDMM region in the physical address space
if the bootloader hasn't already enabled it.A mips_cdmm_early_probe() function is also provided to allow early boot
or particularly low level code to set up the CDMM region and probe for a
specific device type, for example early console or KGDB IO drivers for
the EJTAG Fast Debug Channel (FDC) CDMM device.Signed-off-by: James Hogan
Cc: Greg Kroah-Hartman
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9599/
Signed-off-by: Ralf Baechle
27 Mar, 2015
1 commit
-
This patch separates the PMU driver code from the low level
CCI driver code and enables the PMU driver for ARM64.Introduces config options for both.
ARM_CCI400_PORT_CTRL - controls the low level driver code for
CCI400 ports.
ARM_CCI400_PMU - controls the PMU driver code
ARM_CCI400_COMMON - Common defintions for CCI400This patch also changes:
ARM_CCI - common code for probing the CCI devices. This can be
used for adding support for newer CCI versions(e.g, CCI-500).Cc: Bartlomiej Zolnierkiewicz
Cc: Kukjin Kim
Cc: Abhilash Kesavan
Cc: Liviu Dudau
Cc: Lorenzo Pieralisi
Cc: Sudeep Holla
Cc: Nicolas Pitre
Cc: Punit Agrawal
Acked-by: Sudeep Holla
Acked-by: Nicolas Pitre
Acked-by: Punit Agrawal
Signed-off-by: Suzuki K. Poulose
Signed-off-by: Will Deacon
24 Feb, 2015
2 commits
-
Add a driver for transparent busses that don't need a real driver, but
where the bus controller is part of a PM domain, or under the control of
a functional clock. Typically, the bus controller's PM domain and/or
clock must be enabled for child devices connected to the bus (either
on-SoC or externally) to function.Hence the sole purpose of this driver is to enable its clock and PM
domain (if exist(s)), which are specified in the DT and managed from
platform and PM domain code, and to probe for child devices.Due to the child-parent relationship with devices connected to the bus,
PM domain and clock state transitions are handled in the correct order.Signed-off-by: Geert Uytterhoeven
Tested-by: Ulrich Hecht
Reviewed-by: Kevin Hilman
Signed-off-by: Simon Horman -
Signed-off-by: Geert Uytterhoeven
Tested-by: Ulrich Hecht
Reviewed-by: Kevin Hilman
Signed-off-by: Simon Horman
29 Nov, 2014
1 commit
-
BCM7xxx ARM and MIPS platforms share a similar hardware block for
reporting GISB errors, so they both benefit from the use of this driver.
Conditionally compile the ARM-specific bus error handler so that the
GISB error IRQ handler works on other architectures.Signed-off-by: Kevin Cernekee
Signed-off-by: Florian Fainelli
24 Jul, 2014
2 commits
-
The CCN driver makes no sense without PERF_EVENTS, and trying to
build it when that option is disabled results in compile errors,
so it's best to just add a strong Kconfig dependency.Signed-off-by: Arnd Bergmann
-
Driver providing perf backend for ARM Cache Coherent Network
interconnect. Supports counting all hardware events and crosspoint
watchpoints.Currently works with CCN-504 only, although there should be
no changes required for CCN-508 (just impossible to test it now).Signed-off-by: Pawel Moll
Signed-off-by: Arnd Bergmann
17 Jun, 2014
1 commit
-
The arm-cci code uses device tree helpers for initialization
that don't work on kernels built without CONFIG_OF. Further,
it contains an inline assembly in cci_enable_port_for_self()
that uses ARMv7 instructions and fails to build when targetting
other ARM instruction set versions.This works around both issues by limiting the scope of the
Kconfig symbol to platforms that can actually build this driver
cleanly.Signed-off-by: Arnd Bergmann
Acked-by: Lorenzo Pieralisi
Cc: Shawn Guo
03 Jun, 2014
1 commit
-
Pull ARM SoC driver changes from Olof Johansson:
"SoC-near driver changes that we're merging through our tree. Mostly
because they depend on other changes we have staged, but in some cases
because the driver maintainers preferred that we did it this way.This contains a largeish cleanup series of the omap_l3_noc bus driver,
cpuidle rework for Exynos, some reset driver conversions and a long
branch of TI EDMA fixes and cleanups, with more to come next release.The TI EDMA cleanups is a shared branch with the dmaengine tree, with
a handful of Davinci-specific fixes on top.After discussion at last year's KS (and some more on the mailing
lists), we are here adding a drivers/soc directory. The purpose of
this is to keep per-vendor shared code that's needed by different
drivers but that doesn't fit into the MFD (nor drivers/platform)
model. We expect to keep merging contents for this hierarchy through
arm-soc so we can keep an eye on what the vendors keep adding here and
not making it a free-for-all to shove in crazy stuff"* tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
tty: serial: msm: Remove direct access to GSBI
power: reset: keystone-reset: introduce keystone reset driver
Documentation: dt: add bindings for keystone pll control controller
Documentation: dt: add bindings for keystone reset driver
soc: qcom: fix of_device_id table
ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
ARM: EXYNOS: Move the driver to drivers/cpuidle directory
ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
ARM: EXYNOS: Pass the AFTR callback to the platform_data
ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
ARM: EXYNOS: Move the AFTR state function into pm.c
ARM: EXYNOS: Encapsulate the AFTR code into a function
ARM: EXYNOS: Disable cpuidle for exynos5440
ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
ARM: EXYNOS: Remove ifdef for scu_enable in pm
ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
ARM: EXYNOS: Use the cpu_pm notifier for pm
...
27 May, 2014
1 commit
-
The versatile express changes for 3.16 introduced a number of
build regressions for randconfig kernels by not tracking dependencies
between the components right.This patch tries to rectify that:
* the mach-vexpress code cannot link without the syscfg driver,
which in turn needs MFD_VEXPRESS_SYSREG
* various drivers call devm_regmap_init_vexpress_config(), which
has to be exported so it can be used by loadable modules
* the configuration bus uses OF DT helper functions that are not
available to platforms disable CONFIG_OF
* The sysreg driver exports GPIOs through gpiolib, which can
be disabled on some platforms.
* The clocksource code cannot be built on platforms that don't
use modern timekeeping but rely on gettimeoffset.Signed-off-by: Arnd Bergmann
24 May, 2014
1 commit
-
This patch adds support for the Broadcom GISB arbiter bus timeout/error
handler. GISB is a proprietary bus used by Broadcom Set Top Box
System-on-a-chip devices (BCM7xxx) which allows multiple masters and
clients to be interfaced with each other.The bus arbiter offers support for generating two interrupts towards the
host CPU, thus allowing us to "catch" clock gated masters, or masters
being volontarily blocked for powersaving purposes, or do general system
troubleshooting.We also register a hook with the ARM fault exception handling to allow
printing a more informative message than "imprecise external abort at
0x00000000" for instance.Signed-off-by: Florian Fainelli
Signed-off-by: Arnd Bergmann
16 May, 2014
1 commit
-
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driverSigned-off-by: Pawel Moll
Acked-by: Mark Brown
Acked-by: Lee Jones
Acked-by: Guenter Roeck
Acked-by: Mike Turquette
16 Aug, 2013
1 commit
-
This patch adds WEIM support for all i.MX CPUs supported by the kernel.
Signed-off-by: Alexander Shiyan
Signed-off-by: Shawn Guo
03 Jul, 2013
1 commit
-
Pull ARM SoC device tree changes from Arnd Bergmann:
"These changes from 30 individual branches for the most part update
device tree files, but there are also a few source code changes that
have crept in this time, usually in order to atomically move over a
driver from using hardcoded data to DT probing.A number of platforms change their DT files to use the C preprocessor,
which is causing a bit of churn, but that is hopefully only this once"* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits)
ARM: at91: dt: rm9200ek: add spi support
ARM: at91: dt: rm9200: add spi support
ARM: at91/DT: at91sam9n12: add SPI DMA client infos
ARM: at91/DT: sama5d3: add SPI DMA client infos
ARM: at91/DT: fix SPI compatibility string
ARM: Kirkwood: Fix the internal register ranges translation
ARM: dts: bcm281xx: change comment to C89 style
ARM: mmc: bcm281xx SDHCI driver (dt mods)
ARM: nomadik: add the new clocks to the device tree
clk: nomadik: implement the Nomadik clocks properly
ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
ARM: dts: omap4-panda: Fix DVI EDID reads
ARM: dts: omap4-panda: Add USB Host support
arm: mvebu: enable mini-PCIe connectors on Armada 370 RD
ARM: shmobile: irqpin: add a DT property to enable masking on parent
ARM: dts: AM43x EPOS EVM support
ARM: dts: OMAP5: Add bandgap DT entry
ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
...
17 Jun, 2013
1 commit
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The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
This patch also adds the devicetree binding document.
The driver only works when the devicetree is enabled.Signed-off-by: Huang Shijie
Acked-by: Sascha Hauer
Signed-off-by: Shawn Guo
30 May, 2013
1 commit
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On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.Documentation describing the CCI DT bindings is provided with the patch.
Signed-off-by: Lorenzo Pieralisi
Signed-off-by: Nicolas Pitre
29 Mar, 2013
1 commit
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The Marvell EBU SoCs have a configurable physical address space
layout: the physical ranges of memory used to address PCI(e)
interfaces, NOR flashes, SRAM and various other types of memory are
configurable by software, through a mechanism of so-called 'address
decoding windows'.This new driver mvebu-mbus consolidates the existing code to address
the configuration of these memory ranges, which is spread into
mach-mvebu, mach-orion5x, mach-mv78xx0, mach-dove and mach-kirkwood.Following patches convert each Marvell EBU SoC family to use this
driver, therefore removing the old code that was configuring the
address decoding windows.It is worth mentioning that the MVEBU_MBUS Kconfig option is
intentionally added as a blind option. The new driver implements and
exports the mv_mbus_dram_info() function, which is used by various
Marvell drivers throughout the tree to get access to window
configuration parameters that they require. This function is also
implemented in arch/arm/plat-orion/addr-map.c, which ultimately gets
removed at the end of this patch series. So, in order to preserve
bisectability, we want to ensure that *either* this new driver, *or*
the legacy code in plat-orion/addr-map.c gets compiled in.By making MVEBU_MBUS a blind option, we are sure that only a platform
that does 'select MVEBU_MBUS' will get this new driver compiled
in. Therefore, throughout the next patches that convert the Marvell
sub-architectures one after the other to this new driver, we add the
'select MVEBU_MBUS' and also ensure to remove plat-orion/addr-map.c
from the build for this specific sub-architecture. This ensures that
bisectability is preserved.Ealier versions of this driver had a DT binding, but since those were
not yet agreed upon, they were removed. The driver still uses
of_device_id to find the SoC specific details according to the string
passed to mvebu_mbus_init(). The plan is to re-introduce a proper DT
binding as a followup set of patches.Signed-off-by: Thomas Petazzoni
Acked-by: Arnd Bergmann
Signed-off-by: Jason Cooper
17 Dec, 2012
1 commit
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These devices are not available on other architectures, so
let's limit them to omap.If the driver subsystem maintainers want to build test
system wide changes without building for each target,
it's easy to carry a test patch that just strips out the
depends entries from Kconfig files.Signed-off-by: Tony Lindgren
Signed-off-by: Linus Torvalds
19 Sep, 2012
1 commit
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OMAP interconnect drivers are used for the interconnect error handling.
Since they are bus driver, lets move it to newly created drivers/bus.Tested-by: Lokesh Vutla
Signed-off-by: Santosh Shilimkar
Acked-by: Tony Lindgren
Signed-off-by: Arnd Bergmann
22 Aug, 2012
1 commit
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Adds a new driver *omap-ocp2scp*. This driver takes the responsibility of
creating all the devices that is connected to OCP2SCP. In the case of OMAP4,
USB2PHY is connected to ocp2scp.This also includes device tree support for ocp2scp driver and
the documentation with device tree binding information is updated.Acked-by: Felipe Balbi
Acked-by: Arnd Bergmann
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Arnd Bergmann
