15 Jan, 2016
40 commits
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For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SPDIF needs to save
all the values of registers before the system suspend and restore them after
the system resume.The SRPC register should be volatile, LOCK bit is set by the hardware.
Signed-off-by: Zidan Wang
Acked-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit f9f4fa61aab9417e40898cf6706fffa94005dc44) -
ETDR and TX0~5 registers are writable and not readable. So they are non
volatile. Remove them from volatile list, and add default register value for
them.Signed-off-by: Zidan Wang
Acked-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 9528f0b1e8b7249460700b4df53b9f6b61da8c60) -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, ESAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.Signed-off-by: Zidan Wang
Acked-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit c64c60763b4e3c72a3520c8d51be858cd67bacb5) -
FSL_SAI_TDR register is writable and not readable. According to
regmap_volatile() function, if FSL_SAI_TDR want to be volatile,
it should be readable. So we should remove FSL_SAI_TDR from volatile
register list.If the flat cache don't have default register map, when do regcache_sync
operation, the non volatile and writable registers will be synchronised
to 0. FSL_SAI_TDR reigster will be written a 0 and cause channel swap.
So add default register map for flat cache, and such register will not
be written.Signed-off-by: Zidan Wang
Acked-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit b9b21722ff2e431c85d33bcc950327093cf9a991) -
Correct wdog->timeout after set_timeout(), otherwise, the WDIOC_GETTIMEOUT
will return the default value '60s' always, correct it and also for the new
wdog->pretimeout.Signed-off-by: Robin Gong
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The pre-timeout interrupt will be triggered before watchdog timeout happen.
So add interface in imx2_wdt driver.Signed-off-by: Robin Gong
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Since the watchdog common framework centrialize the IOCTL interfaces of device
driver now, the SETPRETIMEOUT and GETPRETIMEOUT need to be added in common codeSigned-off-by: Robin Gong
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Add set_pretimeout since our watchdog driver has those interfaces and
obviously, the new common watchdog framework didn't implement this interface.Signed-off-by: Robin Gong
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With a basic Linux userspace, the messages "Calling CRDA to update
world regulatory domain" appears 10 times after boot every second or
so, followed by a final "Exceeded CRDA call max attempts. Not calling
CRDA". For those of us not having the corresponding userspace parts,
having those messages repeatedly displayed at boot time is a bit
annoying, so this commit reduces their log level to pr_debug().Signed-off-by: Thomas Petazzoni
Signed-off-by: Johannes Berg
(cherry picked from commit 042ab5fc7a80b934032fcc673a125feb36645b33) -
In some i.MX6 board (i.MX6UL EVK), it will have a additional
GPIO controlled DC-DC regulator. we need to change this regulator's
voltage According the maximum frequency that CPU can run at.At present, we only need to set the voltage to minimum one, we need
to set the voltage to the maximum before suspend, resume back to the
minimum voltage after suspend.Signed-off-by: Bai Ping
(cherry picked from commit 31f0773ee7d6ba5715486a221857f2ceccb434b4) -
For the i.MX6UL EVK board, according to the latest schematic, use a GPIO pin along with
the 'PMIC_STBY_REQ' pin to control the DC-DC voltage output. the possible voltage output
as below:PMIC_STBY_REQ = 0, GPIO_DVFS = 0, output is 1.4V (1.375V + 25mV)
PMIC_STBY_REQ = 0, GPIO_DVFS = 1, output is 1.3V (1.275V + 25mV)
PMIC_STBY_REQ = 1, GPIO_DVFS = 0, output is 0.925V (0.9V + 25mV)In normal run mode, the voltage output should be changed using the 'GPIO_DVFS' pin,
so add gpio regulator to control it.Signed-off-by: Bai Ping
(cherry picked from commit 4517cf404b4e0cfb805a9d0c412b2f2839400d9b) -
Adding 'is_prepared' callback function for pllv3 type clk to make sure when
the system is bootup, the unused clk is in a known state to match the prepare
count info.Signed-off-by: Bai Ping
(cherry picked from commit badf477b5a728807c84656edeacf43499b956218) -
Same as i.MX6SX, need to disconnect vddhigh and vddsnvs
in DSM on i.MX6UL, they have same design.Signed-off-by: Anson Huang
(cherry picked from commit f0c63b894a60512318481cb8a7b0777cdb7c46ab) -
per design team's recommendation, in DSM mode,
need to disconnect vddhigh and vddsnvs, add it for i.MX6SX.i.MX6SX has different bit definition than i.MX6SL about this
bit in PMU_MISC0 register.Signed-off-by: Anson Huang
(cherry picked from commit ec42012c66961c357a1ed4c31d27f83a1db86611) -
Update max voltage of SW1A to 3.3V on PF3000, see below datasheet:
http://cache.freescale.com/files/analog/doc/data_sheet/PF3000.pdf?fsrch=1&sr=1&pageNum=1Signed-off-by: Robin Gong
(cherry picked from commit 5cd7d3c5933b052b899183a45fa4be8cdb2a0c69) -
Regards to the pfuze3000 doc update, regulator driver need to be updated too.
Otherwise the voltage information show wrongly.Signed-off-by: Robin Gong
(cherry picked from commit ac1992e3eab0d31195781bb7d1c4ff7ccea1c86a) -
Add the GPU configuration in the dtsi files for the above three SOCs.
date Oct 28, 2015
Signed-off-by: Shawn Xiao
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Currently 128M reserved for GPU in all the i.MX6 boards that is
requiring kernel to allocate CMA 320M. For the low end devices like 6SX
and 6SL, the 320M is huge. Sometimes customer board may have very less
RAM.With Kernel 4.1, there is a new feature CMA can be calculated at DTS
level based on the amount queried from different module drivers.So
moving the GPU memory to DTS is valid and can be configured for each
board.And at the same time, also keep the option for user to configure the
parameters "contiguousBase and contiguousSize" in u-boot.Signed-off-by: Shawn Xiao
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For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.Signed-off-by: Zidan Wang
Acked-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 1fde5e83a17acbcfcce27f68be46a6da4344efbd) -
On i.MX6QP SabreSD board, VDDCORE is from PFuze's SW2, this
is different from i.MX6QDL SabreSD board, which is from SW1A/B.Signed-off-by: Anson Huang
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Attempt to read volatile register when cache_only is set will return
EBUSY. After playback/record, wm8962_runtime_suspend function will set
cache_only flag, so the volitale register ALC2 can't be read from cache.Separate ALC Coefficients to four reigsters, the volatile register ALC2
will be read from hardware instead of cache.Signed-off-by: Zidan Wang
(cherry picked from commit 5ec8878be12530517b4c8ae307441a0ac16071a3) -
Sim card CVCC is determined by the gpio value from sim controller.
How the CVCC is controlled on both post card boards is decribed below.NCN8025:Vcc=ACTIVE_HIGH?5V:3V
TDA8035:Vcc=ACTIVE_HIGH?5V:1.8VDifferent sim cards have different CVCC range. To support all cards
with same dts, this patch set gpio active high.Signed-off-by: Gao Pan
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Change pad settings to improve signal quality.
Signed-off-by: Gao Pan
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sim_activate() process is contained in the cold reset.
Thus, it is redundant and should be removed.This patch also adds comments to cold reset process.
Signed-off-by: Gao Pan
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On 4.1 kernel, some eMMC on i.MX7D-SDB board can't pass HS400 tuning,
the same eMMC can pass HS400 tuning on 3.14 kernel. The difference
is that 4.1 kernel does not have 1ms delay for eMMC during the
tuning procedure. The root cause still not find, add back the
1ms delay first.Signed-off-by: Haibo Chen
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The default gpio flag is 0 which actually means ACTIVE_HIGH.
However, it should be ACTIVE_LOW.
Change it using correct macro directly.Signed-off-by: Dong Aisheng
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The TF card slot on uSDHC2 does not support CD function,
so add non-removable property.Signed-off-by: Dong Aisheng
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This will cause meaningless CPU overhead by polling the card at backgroud
if the CD is broken.
Most board does not intend to use this function, so remove it.
Platform driver could add it for test if needed.Signed-off-by: Dong Aisheng
Conflicts:
drivers/mmc/host/sdhci.c -
Fix default initialization of iomuxc mux and conf registers,
on parse group pad id relays on dafult init state to set the
corresponding pin_id value for a given pad, if default init
value is missing it can result in erroneous pinctrl configuration.Signed-off-by: Adrian Alonso
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When compiling a GPU module without CONFIG_MULTI_CACHE enabled, the
compiler prompt warning which says symbol v7_dma_map_area and
v7_dma_flush_area not exported. And when insmod GPU module, it also
warns the above two symbols not found, which cause insmod module failed.This patch export these dma access functions and fix these issues.
Signed-off-by: Shawn Xiao
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Align tx path with kernel 3.14, otherwise there have data loss.
Signed-off-by: Fugang Duan
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We don't need btsdio driver support and enable it will cause
Broadcom WiFi driver suspend/resume unwork due to it does not
implement suspend/resume callback.Signed-off-by: Dong Aisheng
(cherry picked from commit ebd90ea123d493935b559c05db0cd5b5db9d3c73) -
Add Broadcom bcmdhd driver support.
BTW, the in kernel upstream brcmfmac driver is removed to avoid confusion.
And Atheros driver is also removed which is not supported anymore.Signed-off-by: Dong Aisheng
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Fixing a lot of compiling issues due to kernel upgrade and then
make it work on 4.1 kernel.Signed-off-by: Dong Aisheng
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restore pin setting for i2c in suspend/resume
Signed-off-by: Gao Pan
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Some registers on pfuze3000 will lost after exit from LPSR, need restore them,
otherwise system may reboot with below command after system enter LPSR one time:root@imx7d_all:~# echo enabled > /sys/class/tty/ttymxc0/power/wakeup
root@imx7d_all:~# echo mem > /sys/power/statebecause LDOGCTL not recover as 1. Add 'fsl,lpsr-mode' property to this case,
please add this property if your board support LPSR mode as imx7d-12x12-lpddr3-arm2
board.Signed-off-by: Robin Gong
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As SNVS clk may be disabled in kernel to save power(~1mA),
but during suspend/resume, we have to access SNVS register
to do MMDC retention and power down SoC etc.., need to
make sure SNVS clk is enabled before accessing its register.Signed-off-by: Anson Huang
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fix the pin conflict between ECSPI with MIPI and EPDC on i.MX7D 12x12 lpddr3 ARM2 board.
Signed-off-by: Han Xu
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mipi pins conflict with ecspi1 on i.MX7D 12x12 lpddr3 ARM2 board, manage
the mipi pins in a individual group to solve the issue.Signed-off-by: Han Xu
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Add i2c IOMUX sleep state for imx7d-12x12-lpddr3-arm2.
Signed-off-by: Gao Pan
