Eric Lee / smarc-fsl-linux-kernel

05 Dec, 2016

1 commit

  • 9d4b82706   fsl/usb: Workarourd for USB erratum-A005697 ... Browse Code »

    The EHCI specification states the following in the SUSP bit description:
    In the Suspend state, the port is sensitive to resume detection.
    Note that the bit status does not change until the port is suspended and
    that there may be a delay in suspending a port if there is a transaction
    currently in progress on the USB.

    However, in NXP USBDR controller, the PORTSCx[SUSP] bit changes immediately
    when the application sets it and not when the port is actually suspended.

    So the application must wait for at least 10 milliseconds after a port
    indicates that it is suspended, to make sure this port has entered
    suspended state before initiating this port resume using the Force Port
    Resume bit. This bit is for NXP controller, not EHCI compatible.

    Signed-off-by: Changming Huang
    Signed-off-by: Ramneek Mehresh
    Acked-by: Alan Stern
    Signed-off-by: Greg Kroah-Hartman

    Changming Huang
     

15 Aug, 2015

1 commit

  • f8786a915   drivers: usb: fsl: Workaround for USB erratum-A005275 ... Browse Code »

    Incoming packets in high speed are randomly corrupted by h/w
    resulting in multiple errors. This workaround makes FS as
    default mode in all affected socs by disabling HS chirp
    signalling.This errata does not affect FS and LS mode.

    Forces all HS devices to connect in FS mode for all socs
    affected by this erratum:
    P3041 and P2041 rev 1.0 and 1.1
    P5020 and P5010 rev 1.0 and 2.0
    P5040, P1010 and T4240 rev 1.0

    Signed-off-by: Ramneek Mehresh
    Signed-off-by: Nikhil Badola
    Cc: stable
    Signed-off-by: Greg Kroah-Hartman

    Nikhil Badola
     

23 Jul, 2015

4 commits

31 May, 2015

1 commit

25 Sep, 2012

1 commit

  • 5ed338778   powerpc/usb: remove checking PHY_CLK_VALID for UTMI PHY ... Browse Code »

    PHY_CLK_VALID bit doesn't work properly with UTMI PHY.
    e.g. This bit is always zero on P5040, etc.
    There is no need to check this bit for UTMI PHY, just keep
    checking for ULPI PHY to prevent system hanging.

    This patch should be squashed into previous commit 3735ba8db8e6e
    "powerpc/usb: fix bug of CPU hang when missing USB PHY clock"

    Signed-off-by: Shengzhou Liu
    Signed-off-by: Greg Kroah-Hartman

    Shengzhou Liu
     

22 Sep, 2012

1 commit

06 Sep, 2012

1 commit

19 Apr, 2012

1 commit

  • 58c559e65   fsl/usb: Add controller version based ULPI and UTMI phy support ... Browse Code »

    Add support for ULPI and UTMI PHYs based on usb controller
    version info read from device-tree

    Example of USB Controller versioning info:
    Version 1.2 and below : MPC8536, MPC8315, etc
    Version 1.6 : P1020, P1010, P2020, P5020, etc
    Version 2.2 : PSC9131, PSC9132, P3060, etc

    No changes for non-DT users

    Signed-off-by: Ramneek Mehresh
    Acked-by: Li Yang
    Signed-off-by: Greg Kroah-Hartman

    Ramneek Mehresh
     

03 May, 2011

2 commits

23 Oct, 2010

2 commits

  • 69cb1ec4c   mxc_udc: add workaround for ENGcm09152 for i.MX35 ... Browse Code »

    this patch gives the possibility to workaround bug ENGcm09152
    on i.MX35 when the hardware workaround is also implemented on
    the board.
    It covers the workaround described on page 25 of the following Errata :
    http://cache.freescale.com/files/dsp/doc/errata/IMX35CE.pdf

    Signed-off-by: Eric Bénard
    Signed-off-by: Greg Kroah-Hartman

    Eric Bénard
     
  • 230f7ede6   USB: add USB EHCI support for MPC5121 SoC ... Browse Code »

    Extends FSL EHCI platform driver glue layer to support
    MPC5121 USB controllers. MPC5121 Rev 2.0 silicon EHCI
    registers are in big endian format. The appropriate flags
    are set using the information in the platform data structure.
    MPC83xx system interface registers are not available on
    MPC512x, so the access to these registers is isolated in
    MPC512x case. Furthermore the USB controller clocks
    must be enabled before 512x register accesses which is
    done by providing platform specific init callback.

    The MPC512x internal USB PHY doesn't provide supply voltage.
    For boards using different power switches allow specifying
    DRVVBUS and PWR_FAULT signal polarity of the MPC5121 internal
    PHY using "fsl,invert-drvvbus" and "fsl,invert-pwr-fault"
    properties in the device tree USB nodes. Adds documentation
    for this new device tree bindings.

    Signed-off-by: Anatolij Gustschin
    Cc: Grant Likely
    Signed-off-by: Greg Kroah-Hartman

    Anatolij Gustschin
     

24 Nov, 2009

1 commit

  • 7d6709a20   powerpc: Fix build of some FSL platforms ... Browse Code »

    Commit 87ec0e98cfdd8b68da6a7f9e70142ffc0e404fbb in kumar's next branch
    broke one of my test configs since it looks like Anton forgot about
    that mpc832x_rdb platform which still uses the old style probing for
    the SPI stuff.

    I'll let them do a cleaner fix that probably involves changing the
    probing method and getting rid of the platform device but for now
    this will do to fix it.

    Signed-off-by: Benjamin Herrenschmidt

    Benjamin Herrenschmidt
     

12 Nov, 2009

2 commits

19 Jun, 2009

1 commit

  • 739028429   mpc52xx_psc_spi: convert to cs_control callback ... Browse Code »

    mpc52xx_psc_spi driver is the last user of the legacy activate_cs and
    deactivate_cs callbacks, so convert the driver to the cs_control hook and
    remove the legacy callbacks from fsl_spi_platform_data struct.

    Signed-off-by: Anton Vorontsov
    Cc: Grant Likely
    Cc: David Brownell
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Anton Vorontsov
     

22 Apr, 2009

1 commit

16 Apr, 2009

1 commit

  • 412401029   powerpc/5200: Bring the legacy fsl_spi_platform_data hooks back ... Browse Code »

    In commit 364fdbc00fbdd409ade63500710123fe323aa164 ("spi_mpc83xx:
    rework chip selects handling"), I merged activate_cs and deactivate_cs
    hooks into cs_control, but I overlooked that mpc52xx_psc_spi driver
    is using these hooks too. And that resulted in the following build
    failure:

    CC drivers/spi/mpc52xx_psc_spi.o
    drivers/spi/mpc52xx_psc_spi.c: In function 'mpc52xx_psc_spi_do_probe':
    drivers/spi/mpc52xx_psc_spi.c:398: error: 'struct fsl_spi_platform_data'
    has no member named 'activate_cs'
    drivers/spi/mpc52xx_psc_spi.c:399: error: 'struct fsl_spi_platform_data'
    has no member named 'deactivate_cs'
    make[2]: *** [drivers/spi/mpc52xx_psc_spi.o] Error 1

    This patch simply adds the legacy hooks back for 2.6.30, and for
    2.6.31 we'll convert the driver to ->cs_control.

    Reported-by: Subrata Modak
    Signed-off-by: Anton Vorontsov
    Signed-off-by: Grant Likely

    Anton Vorontsov
     

08 Apr, 2009

1 commit

07 Apr, 2009

1 commit

01 Apr, 2009

2 commits

  • 35b4b3c0c   spi_mpc83xx: add OF platform driver bindings ... Browse Code »

    Implement full support for OF SPI bindings. Now the driver can manage its
    own chip selects without any help from the board files and/or fsl_soc
    constructors.

    The "legacy" code is well isolated and could be removed as time goes by.

    Signed-off-by: Anton Vorontsov
    Cc: David Brownell
    Cc: Benjamin Herrenschmidt
    Cc: Kumar Gala
    Cc: Grant Likely
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Anton Vorontsov
     
  • 364fdbc00   spi_mpc83xx: rework chip selects handling ... Browse Code »

    The main purpose of this patch is to pass 'struct spi_device' to the chip
    select handling routines. This is needed so that we could implement
    full-fledged OpenFirmware support for this driver.

    While at it, also:
    - Replace two {de,activate}_cs routines by single cs_contol().
    - Don't duplicate platform data callbacks in mpc83xx_spi struct.

    Signed-off-by: Anton Vorontsov
    Cc: David Brownell
    Cc: Benjamin Herrenschmidt
    Cc: Kumar Gala
    Cc: Grant Likely
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Anton Vorontsov
     

31 Mar, 2009

1 commit

17 Dec, 2008

1 commit

  • b31a1d8b4   gianfar: Convert gianfar to an of_platform_driver ... Browse Code »

    Does the same for the accompanying MDIO driver, and then modifies the TBI
    configuration method. The old way used fields in einfo, which no longer
    exists. The new way is to create an MDIO device-tree node for each instance
    of gianfar, and create a tbi-handle property to associate ethernet controllers
    with the TBI PHYs they are connected to.

    Signed-off-by: Andy Fleming
    Signed-off-by: David S. Miller

    Andy Fleming
     

31 Oct, 2008

1 commit

  • c132419e5   gianfar: Fix race in TBI/SerDes configuration ... Browse Code »

    The init_phy() function attaches to the PHY, then configures the
    SerDesTBI link (in SGMII mode). The TBI is on the MDIO bus with the PHY
    (sort of) and is accessed via the gianfar's MDIO registers, using the
    functions gfar_local_mdio_read/write(), which don't do any locking.

    The previously attached PHY will start a work-queue on a timer, and
    probably an irq handler as well, which will talk to the PHY and thus use
    the MDIO bus. This uses phy_read/write(), which have locking, but not
    against the gfar_local_mdio versions.

    The result is that PHY code will try to use the MDIO bus at the same time
    as the SerDes setup code, corrupting the transfers.

    Setting up the SerDes before attaching to the PHY will insure that there is
    no race between the SerDes code and *our* PHY, but doesn't fix everything.
    Typically the PHYs for all gianfar devices are on the same MDIO bus, which
    is associated with the first gianfar device. This means that the first
    gianfar's SerDes code could corrupt the MDIO transfers for a different
    gianfar's PHY.

    The lock used by phy_read/write() is contained in the mii_bus structure,
    which is pointed to by the PHY. This is difficult to access from the
    gianfar drivers, as there is no link between a gianfar device and the
    mii_bus which shares the same MDIO registers. As far as the device layer
    and drivers are concerned they are two unrelated devices (which happen to
    share registers).

    Generally all gianfar devices' PHYs will be on the bus associated with the
    first gianfar. But this might not be the case, so simply locking the
    gianfar's PHY's mii bus might not lock the mii bus that the SerDes setup
    code is going to use.

    We solve this by having the code that creates the gianfar platform device
    look in the device tree for an mdio device that shares the gianfar's
    registers. If one is found the ID of its platform device is saved in the
    gianfar's platform data.

    A new function in the gianfar mii code, gfar_get_miibus(), can use the bus
    ID to search through the platform devices for a gianfar_mdio device with
    the right ID. The platform device's driver data is the mii_bus structure,
    which the SerDes setup code can use to lock the current bus.

    Signed-off-by: Trent Piepho
    CC: Andy Fleming
    Signed-off-by: Jeff Garzik

    Trent Piepho
     

17 Jul, 2008

2 commits

30 Apr, 2008

1 commit

17 Apr, 2008

1 commit

  • 9d9326d3b   phy: Change mii_bus id field to a string ... Browse Code »

    Having the id field be an int was making more complex bus topologies
    excessively difficult. For now, just convert it to a string, and
    change all instances of "bus->id = val" to
    snprintf(id, MII_BUS_ID_LEN, "%x", val).

    Signed-off-by: Andy Fleming
    Signed-off-by: Jeff Garzik

    Andy Fleming
     

19 Jul, 2007

1 commit

  • 7132ab7f6   Fix RGMII-ID handling in gianfar ... Browse Code »

    The TSEC/eTSEC can detect the interface to the PHY automatically,
    but it isn't able to detect whether the RGMII connection needs internal
    delay. So we need to detect that change in the device tree, propagate
    it to the platform data, and then check it if we're in RGMII. This fixes
    a bug on the 8641D HPCN board where the Vitesse PHY doesn't use the delay
    for RGMII.

    Signed-off-by: Andy Fleming

    Andy Fleming
     

18 Jul, 2007

1 commit

10 Jul, 2007

1 commit

  • 80128ff79   [POWERPC] 8xx: mpc885ads pcmcia support ... Browse Code »

    Adds support for PowerQuicc on-chip PCMCIA. The driver is implemented as
    of_device, so only arch/powerpc stuff is capable to use it, which now implies
    only mpc885ads reference board.

    To cope with the code that should be hooked inside driver, but is really board
    specific (like set_voltage), global structure mpc8xx_pcmcia_ops holds
    necessary function pointers that are filled in the BSP code.

    [akpm@linux-foundation.org: whitespace diddles]
    Signed-off-by: Vitaly Bordug
    Acked-by: Arnd Bergmann
    Acked-by: Olof Johansson
    Cc: Dominik Brodowski
    Cc: Paul Mackerras
    Cc: Benjamin Herrenschmidt
    Signed-off-by: Andrew Morton
    Signed-off-by: Kumar Gala

    Vitaly Bordug
     

28 Apr, 2007

1 commit

  • 728de4c92   ucc_geth: migrate ucc_geth to phylib ... Browse Code »

    migrate ucc_geth to use the common phylib code.

    There are several side effects from doing this:

    o deprecate 'interface' property specification present
    in some old device tree source files in
    favour of a split 'max-speed' and 'interface-type'
    description to appropriately match definitions
    in include/linux/phy.h. Note that 'interface' property
    is still honoured if max-speed or interface-type
    are not present (backward compatible).
    o compile-time CONFIG_UGETH_HAS_GIGA is eliminated
    in favour of probe time speed derivation logic.
    o adjust_link streamlined to only operate on maccfg2
    and upsmr.r10m, instead of reapplying static initial
    values related to the interface-type.
    o Addition of UEC MDIO of_platform driver requires
    platform code add 'mdio' type to id list
    prior to calling of_platform_bus_probe (separate patch).
    o ucc_struct_init introduced to reduce ucc_geth_startup
    complexity.

    Signed-off-by: Li Yang
    Signed-off-by: Kim Phillips
    Signed-off-by: Jeff Garzik

    Kim Phillips
     

11 Dec, 2006

1 commit

04 Oct, 2006

1 commit

  • 986585385   [POWERPC] Add QUICC Engine (QE) infrastructure ... Browse Code »

    Add QUICC Engine (QE) configuration, header files, and
    QE management and library code that are used by QE devices
    drivers.

    Includes Leo's modifications up to, and including, the
    platform_device to of_device adaptation:

    "The series of patches add generic QE infrastructure called
    qe_lib, and MPC8360EMDS board support. Qe_lib is used by
    QE device drivers such as ucc_geth driver.

    This version updates QE interrupt controller to use new irq
    mapping mechanism, addresses all the comments received with
    last submission and includes some style fixes.

    v2: Change to use device tree for BCSR and MURAM;
    Remove I/O port interrupt handling code as it is not generic
    enough.

    v3: Address comments from Kumar; Update definition of several
    device tree nodes; Copyright style change."

    In addition, the following changes have been made:

    o removed typedefs
    o uint -> u32 conversions
    o removed following defines:
    QE_SIZEOF_BD, BD_BUFFER_ARG, BD_BUFFER_CLEAR, BD_BUFFER,
    BD_STATUS_AND_LENGTH_SET, BD_STATUS_AND_LENGTH, and BD_BUFFER_SET
    because they hid sizeof/in_be32/out_be32 operations from the reader.
    o fixed qe_snums_init() serial num assignment to use a const array
    o made CONFIG_UCC_FAST select UCC_SLOW
    o reduced NR_QE_IC_INTS from 128 to 64
    o remove _IO_BASE, etc. defines (not used)
    o removed irrelevant comments, added others to resemble removed BD_ defines
    o realigned struct definitions in headers
    o various other style fixes including things like pinMask -> pin_mask
    o fixed a ton of whitespace issues
    o marked ioregs as __be32/__be16
    o removed platform_device code and redundant get_qe_base()
    o removed redundant comments
    o added cpu_relax() to qe_reset
    o uncasted all get_property() assignments
    o eliminated unneeded casts
    o eliminated immrbar_phys_to_virt (not used)

    Signed-off-by: Li Yang
    Signed-off-by: Shlomi Gridish
    Signed-off-by: Kim Phillips
    Signed-off-by: Paul Mackerras

    Li Yang
     

22 May, 2006

1 commit

21 Mar, 2006

1 commit

  • 80cb9aee0   [PATCH] USB: EHCI for Freescale 83xx ... Browse Code »

    Adding a Host Mode USB driver for the Freescale 83xx.

    This driver supports both the Dual-Role (DR) controller and the
    Multi-Port-Host (MPH) controller present in the Freescale MPC8349. It has
    been tested with the MPC8349CDS reference system. This driver depends on
    platform support code for setting up the pins on the device package in a
    manner appropriate for the board in use. Note that this patch requires
    selecting the EHCI controller option under the USB Host menu.

    Signed-off-by: Randy Vinson
    Signed-off-by: Greg Kroah-Hartman

    Randy Vinson