23 Feb, 2017
40 commits
-
i.MX7d MAC1_ADDR fuse offset address is 0x640, i.MX6q/dl/sx/ul
MAC1_ADDR fuse offset address is 0x620. Correct it for i.MX7d,
otherwise read un-correct MAC address.Signed-off-by: Fugang Duan
(cherry picked from commit:74ee5313534dd9453601f4428c4916d46405669f) -
ov5647 mipi camera sensor is replaced by ov5640
on imx7D SDB RevB board.Signed-off-by: Sandor Yu
-
Q901 (IRLML6401) is p-channel MOSET, need set pin1 (LCD_nPWREN) to low
to let pin3 output be 3V3. Normally when pin1 is high, then pin3
output should be gated. It was working previously due to some leakage.
Correct the enable logic from the software viewpoint.Signed-off-by: Robby Cai
-
JTAG, DS-5 attachment causes exceptions
Added properties to device tree, in order to enable and disable
alarms. The following are the available alarms:
-JTAG active
-WatchDOG 2 reset
-Internal Boot
-External Tamper Detection pad -
Add pfuze100 on imx6sx-sabreauto board to align with v3.14, although
no driver use pfuze100 regulator now.Signed-off-by: Robin Gong
-
CMA region is a must to avoid the multile memory mapping
for the DMAed memory and also benifit the large continious
phisical memory allocation.The default value is depend on the target system design and
user cases definition. This is not suitable to put this into
the soc.dtsi, thus we put it into the board DTS.customer can override the value by changing cma size in DTS file.
Again, customer need set the CMA size correctly according to the
target system. The incorrectly CMA size can cause Linux kernel fail
to boot up.CMA disabled or CMA size set to zero is also not allowed.Signed-off-by: Jason Liu
-
The 'otm8018b' is the Source Driver IC which is used
by 'TFT3P5079E' panel. This patch is adding the build
support for the 'otm8018b' kernel driver.Signed-off-by: Fancy Fang
-
Create a new dts for the 'TFT3P5079E' mipi panel on
imx7d sabresd revb board.Signed-off-by: Fancy Fang
-
Adjust high frequence (528M) read/write additional latency settings
from target board initial configuration; Save/restore MMDC_MDMISC
from DCD settings.Remove hardcodded value to issue a ZQ calibration command.
Signed-off-by: Adrian Alonso
Signed-off-by: Ranjani Vaidyanathan
(Cherry picked from commit 1036293d72173ef9051ec23babfd4d7f13db4f58) -
Add support for saving initial boot mmdc timing settings,
restore timming settings when switching from low to high
lpddr2 ddr frequency.Signed-off-by: Adrian Alonso
Signed-off-by: Ranjani Vaidyanathan
(Cherry picked from commit 6787b0fea9eb1ba5cc21e2faf232c3e7d80ac028) -
add lpsr mode state for flexcan pins
Signed-off-by: Dong Aisheng
-
There have two same extended enet dts file to enable fec2 port, so
remove the redundant enet dts file.The issue is caused by the commit 370426c2a918 that was cherry picked
after commit b74c6b9c7fdc.Signed-off-by: Fugang Duan
-
MMC core pm_notify will re-detect card after system suspend/resume,
regardless of post-cd claim.
Since in current MMC implement, non-removeable card only detects once,
this will break post card detect which happens next.
e.g. when we suspend/resume system first, then load Broadcom wifi module,
we will get below dump:root@imx6qdlsolo:/mnt/nfs/vte_IMX6QP-Sabre-SD# modprobe bcmdhd firmware_path=/lib/firmware/bcm/ZP_BCM4339/fw_bcmdhd.bin nvram_path=/lib/firmware/bcm/ZP_BCM4339/bcmdhd.ZP.SDIO.cal
dhd_module_init in
Power-up adapter 'DHD generic adapter'
wifi_platform_bus_enumerate device present 1
failed to power up DHD generic adapter, 3 retry left
wifi_platform_bus_enumerate device present 0
-----------[ cut here ]-----------
Kernel BUG at 80513170 [verbose debug info unavailable]
Internal error: Oops - BUG: 0 1 PREEMPT SMP ARM
Modules linked in: bcmdhd ov5642_camera ov5640_camera_mipi_int ov5640_camera_int mxc_v4l2_capture mxc_dcic ipu_bg_overlay_sdc ipu_still v4l2_int_device ipu_prp_enc ipu_csi_enc ipu_fg_overlay_sdc
CPU: 1 PID: 1487 Comm: modprobe Not tainted 4.1.15-1.0.0+g54cf6a2 #1
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
task: a881e3c0 ti: a9152000 task.ti: a9152000
PC is at mmc_sdio_remove+0x7c/0x80
LR is at mmc_sdio_force_remove+0xc/0x34
pc : [] lr : [] psr: 60030013
sp : a9153d28 ip : 00000000 fp : 00000000
r10: 00000000 r9 : 00000000 r8 : 7f0f76e0
r7 : a9153d58 r6 : 00000000 r5 : 00000000 r4 : a83f1800
r3 : 00000000 r2 : 00000000 r1 : 809c02f4 r0 : a83f1800
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c53c7d Table: 38d7804a DAC: 00000015
Process modprobe (pid: 1487, stack limit = 0xa9152210)
Stack: (0xa9153d28 to 0xa9154000)
3d20: 00000000 7f0c569c a9ffe440 00000003 00000000 7f0c58f4
3d40: a81942c0 8032e33c a8195960 7f0fbf68 00020002 00000000 a9153d58 a9153d58
3d60: fffffdfb 80bc0db4 a81af810 7f0f9518 fffffdfb 00000008 00000000 5624ce5c
3d80: 00000124 80381140 80bc0db4 a81af810 7f0f9518 00000000 00000008 8037f9dc
3da0: a81af810 7f0f9518 a81af844 80b288b0 00000000 8037fbec 00000000 7f0f9518
3dc0: 8037fb60 8037e068 a8025c5c a818fa34 7f0f9518 a20ff280 00000000 8037f16c
3de0: 7f0f0330 a9ffe440 00000000 7f0f9518 a9ffe440 00000000 80bb18f4 803801ec
3e00: 7f0fbf68 a9ffe440 00000000 7f0c5fdc 80b01720 80b01720 a9ffe440 7f11f000
3e20: 00000000 00000001 5624ce5c 80009730 abc7b120 800e316c 000000c8 a9209a00
3e40: 8040003f 00000001 00010000 800b0dfc 000000c8 8040003f abc7dc60 80afc2b0
3e60: abc75880 80afc260 a8001f00 80afe6c0 00000124 800e4944 7f0f9718 00000001
3e80: 7f0f9718 00000001 a9ffeb00 7f0f9718 a9db31c0 8078e47c 7f0f9718 a9db31c0
3ea0: a9153f58 00000001 a9db31c8 80094094 7f0f9724 00007fff 800910d4 00000000
3ec0: 00000000 7f0f9760 00000000 7f0f9860 c0fce8f4 7f0f9724 00000000 8079aa0c
3ee0: c0f07000 000c7944 00b6817a 00000000 0000000e 00000000 00000000 00000000
3f00: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3f20: 00000000 00000000 00000000 00000000 00000640 00000000 00000003 01608348
3f40: 0000017b 8000f604 a9152000 00000000 01608270 800944f8 c0f07000 000c7944
3f60: c0fce28c c0f83439 c0f99248 0007aff8 0008f968 00000000 00000000 00000000
3f80: 00000029 0000002a 00000020 00000024 00000015 00000000 01608348 00000073
3fa0: 00000000 8000f480 01608348 00000073 00000003 01608348 00000000 00000000
3fc0: 01608348 00000073 00000000 0000017b 01608218 00000000 00000073 01608270
3fe0: 7e9ab8c0 7e9ab8b0 0001f2c0 76eac340 600d0010 00000003 00000000 00000000
[] (mmc_sdio_remove) from [] (dhd_wifi_platform_load+0x180/0x39c [bcmdhd])
[] (dhd_wifi_platform_load [bcmdhd]) from [] (platform_drv_probe+0x44/0xac)
[] (platform_drv_probe) from [] (driver_probe_device+0x174/0x2b4)
[] (driver_probe_device) from [] (__driver_attach+0x8c/0x90)
[] (__driver_attach) from [] (bus_for_each_dev+0x68/0x9c)
[] (bus_for_each_dev) from [] (bus_add_driver+0x148/0x1f0)
[] (bus_add_driver) from [] (driver_register+0x78/0xf8)
[] (driver_register) from [] (dhd_wifi_platform_register_drv+0x1bc/0x208 [bcmdhd])
[] (dhd_wifi_platform_register_drv [bcmdhd]) from [] (do_one_initcall+0x8c/0x1d4)
[] (do_one_initcall) from [] (do_init_module+0x5c/0x1a8)
[] (do_init_module) from [] (load_module+0x1ba8/0x1e50)
[] (load_module) from [] (SyS_finit_module+0x80/0x90)
[] (SyS_finit_module) from [] (ret_fast_syscall+0x0/0x3c)Signed-off-by: Dong Aisheng
(cherry picked from commit 2ce993c504798e7fad0910432bd2c6cbd332120d) -
The pwm1's pin belongs to lpsr iomux. So this should
be corrected.Signed-off-by: Fancy Fang
-
Add ADC support for imx7d-12x12-lpddr3-arm2 board.
Signed-off-by: Haibo Chen
(cherry picked from commit 8ed7b52849feced89e8ddcbea49ec7426fa4d8bf) -
Below are the differences between standard evk:
- Enable tpl
- Enable software control vbus for otg2 (hardware rework is needed)
- Disable TSC due to the pin conflict with above vbus regulatorSigned-off-by: Peter Chen
-
Add spi1 IOMUX sleep state in imx7d-12x12-lpddr3-arm2.dts.
Signed-off-by: Gao Pan
-
Add 100Mhz (HIGH_AUDIO_CLK) bus frequency support for imx6q lpddr2 targets
On HIGH_AUDIO_CLK busfreq request source dram mmdc clock root from
pll2_pfd2_div_2 to generate 100Mhz operation frequency.Signed-off-by: Adrian Alonso
Signed-off-by: Anson Huang
(cherry-picked from commit 5bc118112b36b72ed6b1e75a3760c371b486abec) -
Before entering LPSR mode, as GPC was set to STOP/DSM mode already,
the wfi loop after LPSR mode would cause system enter STOP/DSM mode
first, then SNVS will force PMIC_ON_REQ to low, as SNVS needs IPG
clock to be on before entering SNVS/LPSR mode, so we have to disable
STOP/DSM mode to make sure IPG clock is on before SNVS actually enters
LPSR mode.Signed-off-by: Anson Huang
-
In the lpddr3-arm2-m4 dts, the I2C1 is disabled, so PMIC is disabled,
the cpufreq is not support. As thermal driver is depended on cpufreq
driver, if cpufreq is not support, the tempmon device can be disabled.Signed-off-by: Bai Ping
-
Wait PU LDO ramp before GPU power on once system resume back on i.mx6qp,
otherwise, GPU resume may hang.Signed-off-by: Robin Gong
(cherry picked from commit 361af86190c160e0ea66e007c61b18a793149b74) -
Before changing the ARM_PODF, the pll1_bypass clock should be enabled and
bypassed to make sure the ARM_PODF can be changed.Signed-off-by: Bai Ping
-
PU can be dynamically turned off or on, so we need remove
"regulator-always-on" property.Signed-off-by: Robin Gong
(cherry picked from commit f3c0df15fbecce36cae531a4a919d544f9ea8e2a)
(cherry picked from commit ec113127f090c225dd731383b6fb950c02ae1f0b) -
Add cpudile driver support for i.MX6DL.
Signed-off-by: Bai Ping
(cherry picked from commit 72809d405ca73f85c0397fa277ba2481512fe521) -
On i.MX6UL, PGC_CPU_PUPSCR_SW's counter uses IPG/2048 as clock
source, as IPG is at 1.5MHz during low power idle, so the power
up time can be up to 1.3mS which is too long for idle.Since TO1.1, design team re-define the bit[5], if this bit is
set to 1, the clock will be IPG/32, ~22us, enable this function
for TO1.1, the latency value for low power idle needs to be
adjusted accordingly.Signed-off-by: Anson Huang
Signed-off-by: Robin Gong -
To avoid touch other bits of HW_ANADIG_SNVS_MISC_CTRL , use set/clear register
, and correct the bit29 setting:
--before: write 1 to toggle DDR power pin to high before enter DDR retention,
and write 1 again to pull pin to low when exit from DDR retention.
--now: write 1 to pull DDR power pin to high and write 0 to low.Signed-off-by: Robin Gong
-
The cause is EPDC works not stable if DISP mix is enabled.
Signed-off-by: Robby Cai
(cherry picked from commit db5b89bd35d259504da1c15d62f898f1291541e2) -
Add power-domains for display domain for imx6sl.
Signed-off-by: Fancy Fang
-
Add power-domains for display domain for imx6sx.
Signed-off-by: Fancy Fang
-
BCM WiFi driver needs to take care of card detect by itself.
Using cd-post property to tell MMC core not detect card automatically
during host driver probe and post it untill client driver tells it to
do it.Signed-off-by: Dong Aisheng
-
bcmdhd can't support removing host during suspend and
driver crash when detect card after resume due to no response
to CMD7.
It looks bcmdhd has a special requirement to enumerate card
by itself which is incompatible with current MMC core.
So implement post-cd feature to allow driver to detect card
as it wants, then we add back non-removable capability
to avoid MMC core to redetect card after resume.root@imx6qdlsolo:~# echo standby > /sys/power/state
PM: Syncing filesystems ... done.
PM: Preparing system for standby sleep
Freezing user space processes ... (elapsed 0.001 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
PM: Entering standby sleep
evbug: Event. Dev: input3, Type: 0, Code: 0, Value: 1
evbug: Event. Dev: input2, Type: 0, Code: 0, Value: 1
PM: suspend of devices complete after 652.363 msecs
PM: suspend devices took 0.660 seconds
PM: late suspend of devices complete after 1.148 msecs
PM: noirq suspend of devices complete after 1.043 msecs
Disabling non-boot CPUs ...
CPU1: shutdown
Enabling non-boot CPUs ...
CPU1 is up
PM: noirq resume of devices complete after 0.534 msecs
PM: early resume of devices complete after 0.553 msecs
evbug: Event. Dev: input2, Type: 1, Code: 116, Value: 1
evbug: Event. Dev: input2, Type: 0, Code: 0, Value: 0
evbug: Event. Dev: input2, Type: 1, Code: 116, Value: 0
evbug: Event. Dev: input2, Type: 0, Code: 0, Value: 0
mmc1: error -110 during resume (card was removed?)
PM: resume of devices complete after 605.525 msecs
PM: resume devices took 0.610 seconds
PM: Finishing wakeup.
Restarting tasks ... done.
WARNING: driver bcmsdh_sdmmc did not remove its interrupt handler!
root@imx6qdlsolo:~# Unable to handle kernel NULL pointer dereference at virtual address 0000022c
pgd = 80004000
[0000022c] *pgd=00000000
Internal error: Oops: 17 [#1] PREEMPT SMP ARM
Modules linked in: bcmdhd evbug ov5647_camera_mipi mxc_mipi_csi mx6s_capture
CPU: 1 PID: 780 Comm: kworker/u4:4 Not tainted 4.1.15-01434-g70f4b36 #1310
Hardware name: Freescale i.MX7 Dual (Device Tree)
Workqueue: kmmcd mmc_rescan
task: a974af80 ti: a846e000 task.ti: a846e000
PC is at _raw_spin_lock_irqsave+0x1c/0x5c
LR is at get_parent_ip+0x10/0x2c
pc : [] lr : [] psr: 60050093
sp : a846fc20 ip : 0001001f fp : a800b000
r10: 00000000 r9 : 00000001 r8 : 0000022c
r7 : 00000002 r6 : 0000022c r5 : a0050013 r4 : 0000022c
r3 : a974af80 r2 : 00000001 r1 : a846fc44 r0 : 00000000
Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: a951406a DAC: 00000015
Process kworker/u4:4 (pid: 780, stack limit = 0xa846e210)
Stack: (0xa846fc20 to 0xa8470000)
fc20: 00000000 a846fc50 a846fc44 80061808 00000000 000001dc 00000000 805037fc
fc40: 8d89d5ec 00000000 a974af80 80053e88 00000000 00000000 ab7293c0 00000000
fc60: 7f09c828 000000c9 7f09c828 a916a804 00000001 0001001f a800b000 7f0698a4
fc80: a974afc8 00000001 00000000 00000000 00012ebc a974af80 00000001 80ad46c0
fca0: a974af80 00000000 a8eeccc0 00000001 0001001f a846fd04 00000000 7f099440
fcc0: a800b000 7f0699c4 a846fcdf 00000000 00000001 7f068834 a937c900 0105c688
fce0: a846fd04 a8e20000 00000000 00000001 00000000 7f071f08 a846fd04 a80a0000
fd00: ffffffff 00000000 ffffffff a8e20000 a8e20000 00000000 7f099440 00000000
fd20: 00000000 7f099440 a800b000 7f072f4c a974af80 00000000 00000000 80778564
fd40: a846fd54 a9346550 80330028 00000001 a846e000 a8e20000 7f099440 00000000
fd60: 18005000 a8eeccc0 00000000 7f099440 a800b000 7f073744 a846fd8c 80052130
fd80: a9273898 00000000 a800b000 a8e20000 7f099440 00000001 a8eec200 a9270000
fda0: 00000000 7f099440 a800b000 7f07cd3c 80b81100 8040003f a800b000 00000000
fdc0: 00000000 a8e20000 7f099440 a9270000 a9273000 a9270000 00000000 7f099440
fde0: a800b000 7f02df4c 00000001 a8e20000 7f099440 a8eec200 00000000 a916e008
fe00: 00000000 a90bfb00 a800b000 7f074cbc a9270000 7f099440 a8e20000 00000000
fe20: a8f81610 7f0765ec 7f0765b0 a8eeccc0 a855df40 7f069310 a916a800 a8eec200
fe40: 7f09b414 7f06a950 7f06a908 a8f81608 a8f81600 8050e8b8 a8f81608 7f09b414
fe60: 80b22c70 80379744 a974af80 a8f8163c a8f81608 803797d4 00000005 a81ce930
fe80: a8f81608 8037923c a8f81608 a8f81608 80b93cf4 80376504 a846fea0 800e0e3c
fea0: 00000000 00000000 a8f81608 000000bd a833f000 00000000 00000000 8050ed04
fec0: 00000001 8050dd8c 400f8c0f a833f000 ffffff92 a833f000 a81ce600 8050de30
fee0: 8050ddbc a833f240 a833f1dc 80506048 a90bfb00 a833f240 a800b000 a81ce600
ff00: 00000000 800462f0 a81ce600 80043c94 00000000 a800b000 a90bfb18 a800b014
ff20: a846e000 00000088 80b39379 a90bfb00 a800b000 8004654c 80ad4100 a800b164
ff40: a90bfb00 00000000 a84856c0 a90bfb00 80046500 00000000 00000000 00000000
ff60: 00000000 8004b1e8 2df9acc7 00000000 b5f3ff89 a90bfb00 00000000 00000000
ff80: a846ff80 a846ff80 00000000 00000000 a846ff90 a846ff90 a846ffac a84856c0
ffa0: 8004b10c 00000000 00000000 8000f568 00000000 00000000 00000000 00000000
ffc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
ffe0: 00000000 00000000 00000000 00000000 00000013 00000000 ecd61557 f82769f5
[] (_raw_spin_lock_irqsave) from [] (add_wait_queue+0x20/0x48)
[] (add_wait_queue) from [] (__mmc_claim_host+0x58/0x1b0)
[] (__mmc_claim_host) from [] (sdioh_request_byte+0x1cc/0x2a4 [bcmdhd])
[] (sdioh_request_byte [bcmdhd]) from [] (sdioh_cfg_write+0x20/0x28 [bcmdhd])
[] (sdioh_cfg_write [bcmdhd]) from [] (bcmsdh_cfg_write+0x90/0xdc [bcmdhd])
[] (bcmsdh_cfg_write [bcmdhd]) from [] (dhdsdio_clk_kso_enab+0x38/0x168 [bcmdhd])
[] (dhdsdio_clk_kso_enab [bcmdhd]) from [] (dhdsdio_clk_devsleep_iovar+0xf4/0x5f4 [bcmdhd])
[] (dhdsdio_clk_devsleep_iovar [bcmdhd]) from [] (dhdsdio_bussleep+0x2f8/0x4dc [bcmdhd])
[] (dhdsdio_bussleep [bcmdhd]) from [] (dhd_bus_stop+0x2e8/0x3f0 [bcmdhd])
[] (dhd_bus_stop [bcmdhd]) from [] (dhd_detach+0x2a4/0x438 [bcmdhd])
[] (dhd_detach [bcmdhd]) from [] (dhdsdio_release+0x4c/0x1dc [bcmdhd])
[] (dhdsdio_release [bcmdhd]) from [] (dhdsdio_disconnect+0x3c/0xa0 [bcmdhd])
[] (dhdsdio_disconnect [bcmdhd]) from [] (bcmsdh_remove+0x3c/0x60 [bcmdhd])
[] (bcmsdh_remove [bcmdhd]) from [] (bcmsdh_sdmmc_remove+0x48/0x60 [bcmdhd])
[] (bcmsdh_sdmmc_remove [bcmdhd]) from [] (sdio_bus_remove+0x30/0xf8)
[] (sdio_bus_remove) from [] (__device_release_driver+0x70/0xe4)
[] (__device_release_driver) from [] (device_release_driver+0x1c/0x28)
[] (device_release_driver) from [] (bus_remove_device+0xd8/0x104)
[] (bus_remove_device) from [] (device_del+0x10c/0x210)
[] (device_del) from [] (sdio_remove_func+0x1c/0x28)
[] (sdio_remove_func) from [] (mmc_sdio_remove+0x40/0x70)
[] (mmc_sdio_remove) from [] (mmc_sdio_detect+0x74/0x100)
[] (mmc_sdio_detect) from [] (mmc_rescan+0xb8/0x314)
[] (mmc_rescan) from [] (process_one_work+0x120/0x330)
[] (process_one_work) from [] (worker_thread+0x4c/0x480)
[] (worker_thread) from [] (kthread+0xdc/0xf4)
[] (kthread) from [] (ret_from_fork+0x14/0x2c)
Code: f10c0080 e3a00001 ebe359b1 f594f000 (e1943f9f)Signed-off-by: Dong Aisheng
-
Fix build error if CONFIG_SMP is disabled:
arch/arm/mach-imx/busfreq_lpddr2.c: In function ‘update_lpddr2_freq_smp’:
arch/arm/mach-imx/busfreq_lpddr2.c:236:67: error: ‘me’ undeclared (first
use in this function)
printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me);Signed-off-by: Adrian Alonso
Signed-off-by: Frank Li -
Add imx6q lpddr2 busfreq support for single channel memory
types, perform ddr frequency scaling taking into account if
ddr uses single or dual channel mode by checking
MMDC0_MDMISC[LPDDR2_2CH] state.Signed-off-by: Adrian Alonso
Signed-off-by: Anson Huang -
Set usable memory to 2 channel fixed mode
MMDC0 0x80000000 512M
MMDC1 0x10000000 512M
MMDC 2 channel fixed mode is enabled by setting
BOOT_CFG3[5:4] = 01 for Fixed 2x32 mapSigned-off-by: Adrian Alonso
-
Add lpddr2 two channel suspend support
- save/restore mmdc io pads for channel 2
- Set mmdc channe 2 on self refresh and auto power saving mode
only if mmdc channel 2 is enabled
- Perform a reset fifo on resume_io when restoring mmdc io padsSigned-off-by: Adrian Alonso
Signed-off-by: Anson Huang
(cherry picked from commit 2e5982e82edc8fc7de0aebc8894a9f0a41e01965) -
Add busfreq support for imx6q lpddr2 pop target platform
DDR scaling support for low bus frequency and high bus
frequency mode (24Mhz/400Mhz)
Update Copyrigth year infoSigned-off-by: Adrian Alonso
Signed-off-by: Anson Huang
(cherry picked from commit 91cff834d4f5d065fe8e7e60c1c1799f00990654) -
Refactor wfe_ddr3_freq_change to wfe_smp_freq_change in order
to reuse enter/exit wfe standby low power mode.Signed-off-by: Adrian Alonso
Signed-off-by: Anson Huang
(cherry picked from commit 4d92e1f5bab3480cb145821dce27960887e7a3ea) -
Add busfreq device node label to allow override busfreq
properties on machine device tree descriptorSigned-off-by: Adrian Alonso
Signed-off-by: Anson Huang
(cherry picked from commit fd8faeb7a40fc2f9fb331d6ca6a60b64c95d7ee6) -
Add device tree for imx6q arm2 lpddr2 pop target platform
Enable common imx6q features, uart, usb, usdhc, fec.
Set DDR max frequency to 400Mhz which is the clock rate
for MT42L128M64D2-25Signed-off-by: Adrian Alonso
Signed-off-by: Anson Huang
(cherry picked from commit 06783aba18bda32f25107485891fc4bafc609abf) -
Add low power suspend mode support for imx6q lpddr2
Save/restore mmdc iomux pads relevant to dual channel
lpddr2 memory when enter/exit low power suspend mode.
Remove unused macros in suspend-imx6.Signed-off-by: Adrian Alonso
Signed-off-by: Anson Huang
(cherry picked from commit 5ebac6d425b859c51d570489d03684e0c976ef60)
