06 Apr, 2017
2 commits
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Implement the suspend/resume hooks to make sure the PWM device is
restored to a correct state after a suspend.Signed-off-by: Boris Brezillon
Signed-off-by: Thierry Reding -
Implement the ->apply() hook and drop the ->enable(), ->disable,
->set_polarity and ->config() ones.Signed-off-by: Boris Brezillon
Acked-by: Nicolas Ferre
Signed-off-by: Thierry Reding
04 Jan, 2017
1 commit
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All PWM devices have been marked as "might sleep" since v4.5, there is
no longer a need to differentiate on a per-chip basis.Signed-off-by: Thierry Reding
14 Jun, 2016
1 commit
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The PWM device exposed by the HLCDC IP is configured with an inverted
polarity by default. Registering the PWM chip with the normal polarity
was not a problem before commit 42e8992c58d4 ("pwm: Add core
infrastructure to allow atomic updates") because the ->set_polarity()
hook was called no matter the current polarity state, but this is no longer
the case.Signed-off-by: Boris Brezillon
Signed-off-by: Thierry Reding
06 Oct, 2015
1 commit
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Add sama5d2 hlcdc backlight PWM support. This chip doesn't have to deal with an
errata, so it's a simple addition of the mfd compatible string.Signed-off-by: Nicolas Ferre
Signed-off-by: Thierry Reding
21 Sep, 2015
1 commit
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This platform driver has a OF device ID table but the OF module alias
information is not created so module autoloading won't work.This patch adds the missing MODULE_DEVICE_TABLE() for OF to export that
information so modules have the correct aliases built-in and autoloading
works correctly.A longer explanation by Javier Canillas can be found here:
https://lkml.org/lkml/2015/7/30/519Signed-off-by: Luis de Bethencourt
Signed-off-by: Thierry Reding
09 Sep, 2015
1 commit
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The errata for HLCDC PWM of at91sam9n12 are the same as for at91sam9x5.
Signed-off-by: Josh Wu
Acked-by: Alexandre Belloni
Signed-off-by: Thierry Reding
11 Mar, 2015
1 commit
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sama5d4 SoC also has an errata on the HLCDC PWM. It is the same as the
sama5d3 that is forbidding the use of div1 prescaler.Signed-off-by: Nicolas Ferre
Acked-by: Boris Brezillon
Signed-off-by: Thierry Reding
30 Jan, 2015
1 commit
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The slow and system clock should never return a rate of zero, but this
might happen if the clocks property defined in the DT is referencing the
wrong clocks.Prevent any division by zero from happening by testing the clk_freq
value before calling do_div().Signed-off-by: Boris Brezillon
Signed-off-by: Thierry Reding
04 Dec, 2014
1 commit
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at91sam9x5 has an errata forbidding the use of slow clk as a clk source and
sama5d3 SoCs has another errata forbidding the use of div1 prescaler.Take both of these erratas into account.
Signed-off-by: Boris Brezillon
Acked-by: Nicolas Ferre
Signed-off-by: Thierry Reding
17 Nov, 2014
1 commit
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The HLCDC IP available in some Atmel SoCs (i.e. at91sam9x5, at91sam9n12
or sama5d3 families for instance) provides a PWM device.This driver add support for a PWM chip exposing a single PWM device (which
will most likely be used to drive a backlight device).Signed-off-by: Boris Brezillon
Tested-by: Anthony Harivel
Tested-by: Ludovic Desroches
Acked-by: Thierry Reding
Acked-by: Nicolas Ferre
Signed-off-by: Thierry Reding