24 Oct, 2015

3 commits

• 28f98a12f   fpga: zynq-fpga: Fix issue with drvdata being overwritten. ... Browse Code »

  Upon registering a FPGA Manager low level driver, FPGA Manager
  core overwrites the platform drvdata pointer. Prior to this commit
  zynq-fpga falsely relied on this pointer to still be valid at remove()
  time.

  Reported-by: Alan Tull
  Signed-off-by: Moritz Fischer
  Acked-by: Alan Tull
  Signed-off-by: Greg Kroah-Hartman

  Moritz Fischer

  2015-10-24 07:49:44 +0800  
• 4d10eaff5   fpga: zynq-fpga: Change fw format to handle bin instead of bit. ... Browse Code »

  This gets rid of the code to strip away the header and byteswap,
  as well as the check for the sync word.

  Signed-off-by: Moritz Fischer
  Reviewed-by: Josh Cartwright
  Acked-by: Michal Simek
  Signed-off-by: Greg Kroah-Hartman

  Moritz Fischer

  2015-10-24 07:49:12 +0800  
• 6376931ba   fpga: zynq-fpga: Fix unbalanced clock handling ... Browse Code »

  This commit fixes the unbalanced clock handling, where
  a failed probe would leave the clock with an enable count of -1.

  Reported-by: Josh Cartwright
  Signed-off-by: Moritz Fischer
  Signed-off-by: Greg Kroah-Hartman

  Moritz Fischer

  2015-10-24 07:49:12 +0800  

18 Oct, 2015

1 commit

• 37784706b   fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000 ... Browse Code »

  This commit adds FPGA Manager support for the Xilinx Zynq chip.
  The code borrows some from the xdevcfg driver in Xilinx'
  vendor tree.

  Signed-off-by: Moritz Fischer
  Signed-off-by: Greg Kroah-Hartman

  Moritz Fischer

  2015-10-18 12:57:16 +0800