01 Mar, 2010
16 commits
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radeon was always including the atpx code unnecessarily, also core
switcheroo was including acpi headers.Signed-off-by: Dave Airlie
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Type of iterator was promoted to unsigned long in 64bit systems.
*header is small structure so it is alwas safe to cast return value
of sizeof operator to int.Signed-off-by: Pauli Nieminen
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Signed-off-by: Dave Airlie
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* 'gpu-switcher' of /ssd/git//linux-2.6:
vga_switcheroo: initial implementation (v15)
fb: for framebuffer handover don't exit the loop early.Conflicts:
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/radeon/Makefile
drivers/gpu/drm/radeon/radeon.h -
Many new laptops now come with 2 gpus, one to be used for low power
modes and one for gaming/on-ac applications. These GPUs are typically
wired to the laptop panel and VGA ports via a multiplexer unit which
is controlled via ACPI methods.4 combinations of systems typically exist - with 2 ACPI methods.
Intel/ATI - Lenovo W500/T500 - use ATPX ACPI method
ATI/ATI - some ASUS - use ATPX ACPI Method
Intel/Nvidia - - use _DSM ACPI method
Nvidia/Nvidia - - use _DSM ACPI method.TODO:
This patch adds support for the ATPX method and initial bits
for the _DSM methods that need to written by someone with
access to the hardware.
Add a proper non-debugfs interface - need to get some proper
testing first.v2: add power up/down support for both devices
on W500 puts i915/radeon into D3 and cuts power to radeon.v3: redo probing methods, no DMI list, drm devices call to
register with switcheroo, it tries to find an ATPX method on
any device and once there is two devices + ATPX it inits the
switcher.v4: ATPX msg handling using buffers - should work on more machines
v5: rearchitect after more mjg59 discussion - move ATPX handling to
radeon driver.v6: add file headers + initial nouveau bits (to be filled out).
v7: merge delayed switcher code.
v8: avoid suspend/resume of gpu that is off
v9: rearchitect - mjg59 is always right. - move all ATPX code to
radeon, should allow simpler DSM also proper ATRM handlingv10: add ATRM support for radeon BIOS, add mutex to lock vgasr_priv
v11: fix bug in resuming Intel for 2nd time.
v12: start fixing up nvidia code blindly.
v13: blindly guess at finishing nvidia code
v14: remove radeon audio hacks - fix up intel resume more like upstream
v15: clean up printks + remove unnecessary igd/dis pointers
mount debugfs
/sys/kernel/debug/vgaswitcheroo/switch - should exist if ATPX detected
+ 2 cards.DIS - immediate change to discrete
IGD - immediate change to IGD
DDIS - delayed change to discrete
DIGD - delayed change to IGD
ON - turn on not in use
OFF - turn off not in useTested on W500 (Intel/ATI) and T500 (Intel/ATI)
Signed-off-by: Dave Airlie
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Signed-off-by: Rafał Miłecki
Signed-off-by: Dave Airlie -
This commit "disabled" audio on RV710 and RV740 only, leaving RV770 and RV730.
The order is: CHIP_RV770 < CHIP_RV730 < CHIP_RV710 < CHIP_RV740.It is not needed anway, as we do not even try to enable audio on RV770 and
newer. We call initializing function in r600.c only, not in rv770.c.If there is something causing green tinges, it's HDMI mode setting for encoder
and I will try to debug that.Signed-off-by: Rafał Miłecki
Signed-off-by: Dave Airlie -
Signed-off-by: Rafał Miłecki
Signed-off-by: Dave Airlie -
* 'drm-radeon-testing' of /ssd/git/drm-radeon-next:
drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond
drm/ttm: fix function prototype to match implementation
drm/radeon: use ALIGN instead of open coding it
drm/radeon/kms: initialize set_surface_reg reg for rs600 asic -
radeon's have a special ability to passthrough writes in their internal
memory space directly to PCI, this ability means that if some of the internal
surfaces like the depth buffer point at 0x0, any writes to these will
go directly to RAM at 0x0 via PCI busmastering.Now mesa used to always emit clears after emitting state, since the
radeon mesa driver was refactored a year or more ago, it was found it
could generate a clear request without ever sending any setup state to the
card. So the clear would attempt to clear the depth buffer at 0x0, which
would overwrite main memory at this point. fs corruption ensues.Also once one app did this correctly, it would never get set back to 0
making this messy to reproduce.The kernel should block this from happening as mesa runs without privs,
though it does require the user be connected to the current running X session.This patch implements a check to make sure the depth offset has been set
before a depth clear occurs and if it finds one it prints a warning and
ignores the depth clear request. There is also a mesa fix to avoid sending
the badness going into mesa.This only affects r100/r200 GPUs in user modesetting mode.
Signed-off-by: Dave Airlie
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Fix function prototype to match its actual usage and implementation.
drivers/gpu/drm/ttm/ttm_bo_util.c:341:10: error: symbol 'ttm_io_prot' redeclared with different type (originally declared at include/drm/ttm/ttm_bo_driver.h:911) - incompatible argument 1 (different signedness)
Signed-off-by: Randy Dunlap
Cc: David Airlie
Signed-off-by: Dave Airlie -
Cc: Jerome Glisse
Cc: Alex Deucher
Signed-off-by: Matt Turner
Reviewed-by: Corbin Simpson
Signed-off-by: Dave Airlie -
rs600 asic was missing set_surface_reg callback leading to
oops.Signed-off-by: Jerome Glisse
Signed-off-by: Dave Airlie -
* anholt/drm-intel-next: (103 commits)
drm/i915: Use a dmi quirk to skip a broken SDVO TV output.
drm/i915: enable/disable LVDS port at DPMS time
drm/i915: check for multiple write domains in pin_and_relocate
drm/i915: clean-up i915_gem_flush_gpu_write_domain
drm/i915: reuse i915_gpu_idle helper
drm/i915: ensure lru ordering of fence_list
drm/i915: extract fence stealing code
drm/i915: fixup active list locking in object_unbind
drm/i915: reuse i915_gem_object_put_fence_reg for fence stealing code
drm/i915: Add dependency on the intel agp module
drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge.
drm/i915: Correct the Sandybridge chipset info structs.
drm/i915: Disable the hangcheck reset on Sandybridge until we add support.
drm/i915: Add a new mobile Sandybridge PCI ID.
agp/intel: Add a new Sandybridge HB/IG PCI ID combo.
drm/i915, agp/intel: Fix stolen memory size on Sandybridge
drm/i915: Correct locking in the modesetting failure path, fixing a BUG_ON.
drm/i915: Disable the surface tile swizzling on Sandybridge.
agp/intel: Use a non-reserved value for the cache field of the PTEs.
drm/i915: Fix sandybridge status page setup.
... -
* nouveau/for-airlied: (25 commits)
drm/nouveau: use ALIGN instead of open coding it
drm/nouveau: report unknown connector state if lid closed
drm/nouveau: support version 0x20 displayport tables
drm/nouveau: Fix noaccel/nofbaccel option descriptions.
drm/nv50: Implement ctxprog/state generation.
drm/nouveau: use dcb connector types throughout the driver
drm/nv50: enable hpd on any connector we know the gpio line for
drm/nouveau: use dcb connector table for creating drm connectors
drm/nouveau: construct a connector table for cards that lack a real one
drm/nouveau: check for known dcb connector types
drm/nouveau: parse dcb gpio/connector tables after encoders
drm/nouveau: reorganise bios header, add dcb connector type enums
drm/nouveau: merge nvbios and nouveau_bios_info
drm/nouveau: merge parsed_dcb and bios_parsed_dcb into dcb_table
drm/nouveau: rename parsed_dcb_gpio to dcb_gpio_table
drm/nouveau: allow retrieval of vbios image from debugfs
drm/nouveau: fix missing spin_unlock in failure path
drm/nouveau: fix i2ctable bounds checking
drm/nouveau: fix nouveau_i2c_find bounds checking
drm/nouveau: fix pramdac_table range checking
...Conflicts:
drivers/gpu/drm/nouveau/nouveau_gem.c -
* korg/drm-core-next:
drm/ttm: handle OOM in ttm_tt_swapout
drm/radeon/kms/atom: fix shr/shl ops
drm/kms: fix spelling of "CLOCK"
drm/kms: fix fb_changed = true else statement
drivers/gpu/drm/drm_fb_helper.c: don't use private implementation of atoi()
drm: switch all GEM/KMS ioctls to unlocked ioctl status.
Use drm_gem_object_[handle_]unreference_unlocked where possible
drm: introduce drm_gem_object_[handle_]unreference_unlocked
27 Feb, 2010
23 commits
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This IBM system has a multi-function SDVO card that reports both VGA
and TV, but the system has no TV connector. The TV connector always
reported as connected, which would lead to poor modesetting choices.https://bugs.freedesktop.org/show_bug.cgi?id=25787
Signed-off-by: Zhao Yakui
Tested-by: Vance
Cc: stable@kernel.org
Signed-off-by: Eric Anholt -
It would be good to disable the LVDS port when we shut down the panel
to save power. We haven't done so until now because we had trouble
getting the right LVDS parameters from the BIOS. I think we're past
that now, so enabling and disabling the port should be safe, though it
would probably be made cleaner with some additional changes to the
display code, where we also bang on the LVDS reg to set the pairing
correctly etc.Seems to save a bit of power (up to 300mW in my basic wattsup
meter testing).Signed-off-by: Jesse Barnes
Signed-off-by: Eric Anholt -
The assumption that an object has only ever one write domain is deeply
threaded into gem (it's even encoded the the singular of the variable
name). Don't let userspace screw us over.Signed-off-by: Daniel Vetter
Signed-off-by: Eric Anholt -
Now that we have an exact gpu write domain tracking, we don't need
to move objects to the active list ourself. i915_add_request will
take care of that under all circumstances.Idea stolen from a patch by Chris Wilson .
Signed-off-by: Daniel Vetter
Signed-off-by: Chris Wilson
Signed-off-by: Eric Anholt -
We have it, so use it. This required moving the function to avoid
a forward declaration.Signed-off-by: Daniel Vetter
Signed-off-by: Eric Anholt -
The fence_list should be lru ordered for otherwise we might try
to steal a fence reg from an active object even though there are
fences from inactive objects available. lru ordering was obeyed
for gpu access everywhere save when moving dirty objects from
flushing_list to active_list.Fixing this cause the code to indent way to much, so I've extracted
the flushing_list processing logic into its on function.Signed-off-by: Daniel Vetter
Reviewed-by: Chris Wilson
Signed-off-by: Eric Anholt -
The spaghetti logic in there tripped up my brain's code parser for a
few secs. Prevent this from happening again by extracting the fence
stealing code into a seperate functions. IMHO this slightly clears up
the code flow.v2: Beautified according to ickle's comments.
v3: ickle forgot to flush his comment queue ... Now there's also a
we-are-paranoid BUG_ON in there.
v4: I've forgotten to switch on my brain when doing v3. Now the BUG_ON
actually checks something useful.
v5: Clean up a stale comment as noted by Eric Anholt.Signed-off-by: Daniel Vetter
Reviewed-by: Chris Wilson
Signed-off-by: Eric Anholt -
All other accesses take this spinlock, so do this here, too.
Signed-off-by: Daniel Vetter
Signed-off-by: Eric Anholt -
This has a few functional changes against the old code:
* a few more unnecessary loads and stores to the drm_i915_fence_reg
objects. Also an unnecessary store to the hw fence register.* zaps any userspace mappings before doing other flushes. Only changes
anything when userspace does racy stuff against itself.* also flush GTT domain. This is a noop, but still try to keep the
bookkeeping correct.Signed-off-by: Daniel Vetter
Signed-off-by: Eric Anholt -
See http://bugzilla.kernel.org/show_bug.cgi?id=15021
Make sure that the appropriate AGP module is loaded and probed before
trying to set up the DRM. The DRM already depends on the AGP core,
but in this case we know the specific AGP driver we need too, and can
help users avoid the trap of loading the AGP driver after the DRM
driver.Signed-off-by: Zhenyu Wang
Signed-off-by: Eric Anholt -
I think this is pretty much correct. Not really tested.
Signed-off-by: Eric Anholt
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Disables CXSR until it's done, and sets the mobile bit on mobile.
Signed-off-by: Eric Anholt
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Signed-off-by: Eric Anholt
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Signed-off-by: Eric Anholt
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Signed-off-by: Eric Anholt
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New memory control config reg at 0x50 should be used for stolen
memory size detection on Sandybridge.Signed-off-by: Zhenyu Wang
Signed-off-by: Eric Anholt -
Signed-off-by: Eric Anholt
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I can't explain this, except that it makes my display correct.
Signed-off-by: Eric Anholt
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I don't know if this is what we'll want to be using long term, we'll see.
Signed-off-by: Eric Anholt
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The register's moved to the same location as the one for the BCS, it seems.
Signed-off-by: Eric Anholt
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Signed-off-by: Eric Anholt
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Signed-off-by: Eric Anholt
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Signed-off-by: Eric Anholt
26 Feb, 2010
1 commit
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* korg/drm-radeon-testing: (62 commits)
drm/radeon/kms: update new pll algo
drm/radeon/kms: add support for square microtiles on r3xx-r5xx
drm/radeon/kms: force pinning buffer into visible VRAM
drm/radeon/kms/evergreen: fix typo in cursor code
drm/radeon/kms: implement reading active PCIE lanes on R600+
drm/radeon/kms: for downclocking non-mobility check PERFORMANCE state
drm/radeon/kms: simplify storing current and requested PM mode
drm/radeon: fixes for r6xx/r7xx gfx init
drm/radeon/rv740: fix backend setup
drm/radeon/kms: fix R3XX/R4XX memory controller initialization
[rfc] drm/radeon/kms: pm debugging check for vbl.
drm/radeon: Fix memory allocation failures in the preKMS command stream checking.
drm: Add generic multipart buffer.
drm/radeon/kms: simplify memory controller setup V2
drm/radeon: Add asic hook for dma copy to r200 cards.
drm/radeon/kms: Create asic structure for r300 pcie cards.
drm/radeon/kms: remove unused r600_gart_clear_page
drm/radeon/kms: remove HDP flushes from fence emit (v2)
drm/radeon/kms: add LVDS pll quirk for Dell Studio 15
drm/radeon/kms: simplify picking power state
...Conflicts:
drivers/gpu/drm/radeon/atom.c
drivers/gpu/drm/radeon/atombios.h
drivers/gpu/drm/radeon/atombios_dp.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600_audio.c
drivers/gpu/drm/radeon/r600_cp.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_connectors.c
drivers/gpu/drm/radeon/radeon_ring.c
drivers/gpu/drm/radeon/rv770.c