15 May, 2012

1 commit


14 May, 2012

1 commit


12 May, 2012

4 commits


11 May, 2012

2 commits


05 May, 2012

1 commit


03 May, 2012

4 commits

  • Add debug entries for:
    1. calculated registers per frequency
    2. last polled value of MR4(temperature level
    of LPDDR2 memory)

    Signed-off-by: Aneesh V
    Reviewed-by: Santosh Shilimkar
    Reviewed-by: Benoit Cousson
    [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
    Signed-off-by: Santosh Shilimkar
    Tested-by: Lokesh Vutla
    Signed-off-by: Greg Kroah-Hartman

    Aneesh V
     
  • Add settings that are not dependent on frequency
    or any other transient parameters. This includes
    - power managment control init
    - impedence calibration control
    - frequency independent phy configuration registers
    - initialization of temperature polling

    Signed-off-by: Aneesh V
    Reviewed-by: Santosh Shilimkar
    Reviewed-by: Benoit Cousson
    [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
    Signed-off-by: Santosh Shilimkar
    Tested-by: Lokesh Vutla
    Signed-off-by: Greg Kroah-Hartman

    Aneesh V
     
  • Add an ISR for EMIF that:
    1. reports details of access errors
    2. takes action on thermal events

    Also clear all interrupts on shut-down. Pending IRQs
    may casue problems during warm-reset.

    Temperature handling:
    EMIF can be configured to poll the temperature level
    of an LPDDR2 device from the MR4 mode register in the
    device. EMIF generates an interrupt whenever it identifies
    a temperature level change between two consecutive pollings.

    Some of the timing parameters need to be de-rated at high
    temperatures. The interrupt handler takes care of doing
    this and also takes care of going back to nominal settings
    when temperature falls back to nominal levels.

    Signed-off-by: Aneesh V
    Reviewed-by: Santosh Shilimkar
    Reviewed-by: Benoit Cousson
    [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
    Signed-off-by: Santosh Shilimkar
    Signed-off-by: Greg Kroah-Hartman

    Aneesh V
     
  • Change SDRAM timings and other settings as necessary
    on voltage and frequency changes. We calculate these
    register settings based on data from the device data
    sheet and inputs such a frequency, voltage state(stable
    or ramping), temperature level etc.

    TODO: frequency and voltage change handling needs to
    be integrated with clock framework and regulator
    framework respectively. This is not done today
    due to missing pieces in the kernel.

    Signed-off-by: Aneesh V
    Reviewed-by: Santosh Shilimkar
    Reviewed-by: Benoit Cousson
    [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
    Signed-off-by: Santosh Shilimkar
    Tested-by: Lokesh Vutla
    Signed-off-by: Greg Kroah-Hartman

    Aneesh V
     

02 May, 2012

2 commits

  • EMIF is an SDRAM controller used in various Texas Instruments
    SoCs. EMIF supports, based on its revision, one or more of
    LPDDR2/DDR2/DDR3 protocols.

    Add the basic infrastructure for EMIF driver that includes
    driver registration, probe, parsing of platform data etc.

    Signed-off-by: Aneesh V
    Reviewed-by: Santosh Shilimkar
    Reviewed-by: Benoit Cousson
    [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
    Signed-off-by: Santosh Shilimkar
    Tested-by: Lokesh Vutla
    Signed-off-by: Greg Kroah-Hartman

    Aneesh V
     
  • Add register offsets and bit field definitions
    for EMIF module in TI SoCs

    Signed-off-by: Aneesh V
    Reviewed-by: Santosh Shilimkar
    Reviewed-by: Benoit Cousson
    [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
    Signed-off-by: Santosh Shilimkar
    Tested-by: Lokesh Vutla
    Signed-off-by: Greg Kroah-Hartman

    Aneesh V