26 Jul, 2018

1 commit

• 633e79650   clk: tegra: Add sdmmc mux divider clock ... Browse Code »

  Add a clock type to model the sdmmc switch divider clocks which have paths
  to source clocks bypassing the divider (Low Jitter paths). These
  are handled by selecting the lj path when the divider is 1 (ie the
  rate is the parent rate), otherwise the normal path with divider
  will be selected. Otherwise this clock behaves as a normal peripheral
  clock.

  Signed-off-by: Peter De-Schrijver
  Signed-off-by: Aapo Vienamo
  Acked-by: Peter De Schrijver
  Acked-by: Jon Hunter
  Signed-off-by: Stephen Boyd

  Peter De-Schrijver

  2018-07-26 04:45:09 +0800