25 May, 2010
2 commits
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Signed-off-by: John Rigby
Signed-off-by: Anatolij Gustschin
Signed-off-by: Grant Likely -
This patch adds an SPI master driver for the Cirrus EP93xx SPI controller found
in EP93xx chips.Signed-off-by: Mika Westerberg
Signed-off-by: H Hartley Sweeten
Acked-by: H Hartley Sweeten
Signed-off-by: Grant Likely
21 Jan, 2010
3 commits
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Adds a memory-mapped I/O dw_spi platform device.
Signed-off-by: Jean-Hugues Deschenes
Signed-off-by: Grant Likely -
Add support for the QSPI controller found some on Freescale/Motorola
Coldfire MCUs.Full duplex, active high cs, spi modes 0-3 and word sizes 8-16 bits are
supported. The hardware drives the MISO, MOSI and SCLK lines, but the chip
selects are managed via GPIO and must be configured by the board code.The QSPI controller has an 80 byte buffer which allows us to transfer up to 16
words at a time. For transfers longer than 16 words, we split the buffer in
half so we can update in one half while the controller is operating on the
other half. Interrupt latencies then ultimately limits our sustained thru-put
to something less than half the maximum speed supported by the part.Signed-off-by: Steven King
Signed-off-by: Grant Likely -
This patch adds support for a SPI master driver for the
DaVinci series of SOCsSigned-off-by: Sandeep Paulraj
Signed-off-by: Mark A. Greer
Signed-off-by: Philby John
Signed-off-by: Sudhakar Rajashekhara
Signed-off-by: Kevin Hilman
Signed-off-by: Grant Likely
17 Dec, 2009
3 commits
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Each SPI controller has exactly one CS line and as such doesn't
provide for multi-cs. We implement a workaround to support
multi-cs by _not_ configuring the mux'ed CS pin for each SPI
controller. The CS mechanism is assumed to be fully machine
specific - the driver doesn't even assume some GPIO pin is used
to control the CS.The driver selects between DMA and POLLING mode depending upon
the xfer size - DMA mode for xfers bigger than FIFO size, POLLING
mode otherwise.The driver has been designed to be capable of running SoCs since
s3c64xx and till date, for that reason some of the register fields
have been passed via, SoC specific, platform data.Signed-off-by: Jassi Brar
Signed-off-by: Grant Likely -
Add pseudo-DMA by FIQ to the S3C24XX SPI driver. This allows the driver
to get DMA-like performance where there are either no free DMA channels or
when doing transfers that required both TX and RX data paths.Since this patch requires the addition of an assembly file to hold the FIQ
code, we rename the module (instead of adding a rename of the .c file to
this patch). We expect most users are loading this via udev and thus
there should be no change to the userland configuration.Signed-off-by: Ben Dooks
Signed-off-by: Simtec Linux Team
Cc: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Grant Likely -
Driver for the Designware SPI core, it supports multipul interfaces like
PCI/APB etc. User can use "dw_apb_ssi_db.pdf" from Synopsys as HW
datasheet.[randy.dunlap@oracle.com: fix build]
[akpm@linux-foundation.org: build fix]
Signed-off-by: Feng Tang
Cc: David Brownell
Signed-off-by: Randy Dunlap
Signed-off-by: Andrew Morton
Signed-off-by: Grant Likely
13 Dec, 2009
3 commits
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This change adds the OMAP SPI 100k driver created by
Fabrice Crohas . This SPI bus is found on
OMAP7xx-series smartphones, and for many, the touchscreen is
attached to this bus.The lion's share of the work was done by Fabrice on this driver --
I am merely porting it from the Linwizard project on his behalf.Signed-off-by: Cory Maccarrone
Signed-off-by: Grant Likely -
Signed-off-by: Wan ZongShun
Signed-off-by: Grant Likely -
This patch is V2 of SPI Master support for the SuperH MSIOF.
Full duplex, spi mode 0-3, active high cs, 3-wire and lsb
first should all be supported, but the driver has so far
only been tested with "mmc_spi".The MSIOF hardware comes with 32-bit FIFOs for receive and
transmit, and this driver simply breaks the SPI messages
into FIFO-sized chunks. The MSIOF hardware manages the pins
for clock, receive and transmit (sck/miso/mosi), but the chip
select pin is managed by software and must be configured as
a regular GPIO pin by the board code.Performance wise there is still room for improvement, but
on a Ecovec board with the built-in sh7724 MSIOF0 this driver
gets Mini-sd read speeds of about half a megabyte per second.Future work include better clock setup and merging of 8-bit
transfers into 32-bit words to reduce interrupt load and
improve throughput.Signed-off-by: Magnus Damm
Signed-off-by: Grant Likely
09 Dec, 2009
2 commits
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This patch adds in a platform device driver using the xilinx_spi common module.
Tested-by: John Linn
Signed-off-by: Richard Röjfors
Signed-off-by: Grant Likely -
This patch splits the xilinx_spi driver into a generic part and a
OF driver part.The reason for this is to later add in a platform driver as well.
Tested-by: John Linn
Signed-off-by: Richard Röjfors
Signed-off-by: Grant Likely
05 Nov, 2009
1 commit
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Adds support for the dedicated SPI device on the Freescale MPC5200(b)
SoC.Signed-off-by: Grant Likely
02 Oct, 2009
1 commit
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This makes the filename match the Kconfig symbol and the driver name.
Signed-off-by: Uwe Kleine-König
Cc: Sascha Hauer
Cc: David Brownell
Cc: Guennadi Liakhovetski
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
23 Sep, 2009
4 commits
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Add SPI driver for Freescale STMP 3xxx-based boards
[dbrownell@users.sourceforge.net: cleanup sequence, spi_unregister_master]
Signed-off-by: dmitry pervushin
Signed-off-by: David Brownell
Cc: Kumar Gala
Cc: Timur Tabi
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This driver has been tested on i.MX1/i.MX27/i.MX35 with an AT25 type
EEPROM and on i.MX27/i.MX31 with a Freescale MC13783 PMIC.Signed-off-by: Sascha Hauer
Tested-by: Guennadi Liakhovetski
Acked-by: David Brownell
Cc: Andrea Paterniani
Cc: Russell King
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This adds a SPI driver for the SPI controller found in the IBM/AMCC
4xx PowerPC's.Signed-off-by: Stefan Roese
Signed-off-by: Wolfgang Ocker
Acked-by: Josh Boyer
Signed-off-by: Steven A. Falco
Signed-off-by: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This driver is in a non working state at the moment and will be replaced
by a bitbang driver which can also handle the newer i.MX variantsSigned-off-by: Sascha Hauer
Cc: Guennadi Liakhovetski
Acked-by: David Brownell
Acked-by: Andrea Paterniani
Cc: Russell King
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
20 Jun, 2009
2 commits
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Since we renamed the file, we might want to rename the file internals too.
Though we don't bother with changing platform driver name and platform
module alias. The stuff is legacy and hopefully we'll remove it soon.Suggested-by: Kumar Gala
Signed-off-by: Anton Vorontsov
Cc: David Brownell
Cc: Benjamin Herrenschmidt
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
The driver handles MPC83xx, MPC85xx and MPC86xx SPI controllers, so rename
the file for clarity.Suggested-by: Kumar Gala
Signed-off-by: Anton Vorontsov
Cc: Kumar Gala
Cc: David Brownell
Cc: Benjamin Herrenschmidt
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
11 Jun, 2009
1 commit
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This adds a driver for the ARM PL022 PrimeCell SSP/SPI
driver found in the U300 platforms as well as in some
ARM reference hardware, and in a modified version on the
Nomadik board.Reviewed-by: Alessandro Rubini
Reviewed-by: Russell King
Reviewed-by: Baruch SiachSigned-off-by: Linus Walleij
Signed-off-by: Russell King
27 Jan, 2009
1 commit
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Signed-off-by: Wolfram Sang
Signed-off-by: Jean Delvare
07 Jan, 2009
1 commit
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Generalize the old at91rm9200 "bootstrap" bitbanging SPI master driver as
"spi_gpio", so it works with arbitrary GPIOs and can be configured through
platform_data. Such SPI masters support:- any number of bus instances (bus_num is the platform_device.id)
- any number of chipselects (one GPIO per spi_device)
- all four SPI_MODE values, and SPI_CS_HIGH
- i/o word sizes from 1 to 32 bits;
- devices configured as with any other spi_master controllerWhen configured using platform_data, this provides relatively low clock
rates. On platforms that support inlined GPIO calls, significantly
improved transfer speeds are also possible with a semi-custom driver.
(It's still painful when accessing flash memory, but less so.)Sanity checked by using this version to replace both native controllers on
a board with six different SPI slaves, relying on three different
SPI_MODE_* values and both SPI_CS_HIGH settings for correct operation.[akpm@linux-foundation.org: cleanups]
Signed-off-by: David Brownell
Acked-by: Magnus Damm
Tested-by: Magnus Damm
Cc: Torgil Svensson
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
06 Aug, 2008
1 commit
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This adds an SPI driver for the SPI controller found in various Marvell
Orion ARM SoCs. It currently supports only one slave, which must use SPI
mode 0.[dbrownell@users.sourceforge.net: cleanups, meet specs, pass "sparse"]
Signed-off-by: Shadi Ammouri
Signed-off-by: Saeed Bishara
Signed-off-by: Lennert Buytenhek
Signed-off-by: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
07 Feb, 2008
1 commit
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Add support for SPI over SCI pins. SCI is a very simple serial controller
block that can be found on older SuperH processors. In theory it is
possible to use the SCI hardware block in syncronous mode, but this version
of the driver simply hooks up the bit banging code on the SCI pins.Signed-off-by: Magnus Damm
Signed-off-by: David Brownell
Cc: Paul Mundt
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
18 Jul, 2007
5 commits
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This is a driver for SPI controller built into TXx9 MIPS SoCs.
This driver is derived from arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c.Signed-off-by: Atsushi Nemoto
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Add OMAP24XX McSPI (Multichannel SPI) controller driver. This driver is
tested very well under OMAP GIT tree with N800 - Nokia Internet Tablet, and
some other OMAP2 boards.Recent updates included bugfixes, cleanups, speedups, and better
conformance to the current SPI programming interface. This doesn't yet
understand the third controller instance on the OMAP 2430.[david-b@pacbell.net: more minor cleanups to the omap2_mcspi driver]
Signed-off-by: Juha Yrjölä
Signed-off-by: Trilok Soni
Signed-off-by: David Brownell
Cc: Tony Lindgren
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Simple SPI master driver for Xilinx SPI controller.
No support for multiple masters.
Not using level 1 drivers from EDK.[akpm@linux-foundation.org: uninlining]
Signed-off-by: Yuri Frolov
Signed-off-by: Andrei Konovalov
Cc: Kumar Gala
Cc: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Add support for the Infineon TLE62x0 series of low-side driver chips, such
as the TLE6220 or TLE6230. These can be viewed as output GPIOs specialized
for power switching applications. The driver provides a userspace
interface to those GPIOs, and to the switch status they provide.Signed-off-by: Ben Dooks
Signed-off-by: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This adds a driver for the LM70-LLP parport adapter, which is an eval board
for the LM70 temperature sensor. For those without that board, it may be a
simpler example of a parport-to-SPI adapter then spi_butterfly.Signed-off-by: Kaiwan N Billimoria
Doc, coding style, and interface updates; build fixes. Minor rename.
Signed-off-by: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
11 May, 2007
1 commit
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SPI master driver for MPC52xx using its Programmable Serial Controller.
Signed-off-by: David Brownell
Signed-off-by: Dragos Carp
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
09 May, 2007
2 commits
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Here is a driver for the Alchemy au1550 PSC (Programmable Serial
Controller) in SPI master mode.It supports dma transfers using the Alchemy descriptor based dma controller
for 4-8 bits per word SPI transfers. For 9-24 bits per word transfers, pio
irq based mode is used to avoid setup of dma channels from scratch on each
number of bits per word change.Tested with au1550; this may also work on other MIPS Alchemy cpus, like
au1200/au1210/au1250. Used extensively with SD card connected via SPI;
this handles 8.1MHz SPI clock transfers using dma without any problem (the
highest SPI clock freq possible with au1550 running on 324MHz).The driver supports sharing of SPI bus by multiple devices. All features
of Alchemy SPI mode are supported (all SPI modes, msb/lsb first, bits per
word in 4-24 range).As the SPI clock of the controller depends on main input clock that shall
be configured externally, platform data structure for au1550 SPI controller
driver contains mainclk_hz attribute to define the input clock rate. From
this value, dividers of the controller for SPI clock are set up for
required frequency.Signed-off-by: Jan Nikitenko
Whitespace and section fixups. Remove partial workaround for platform
setup bug in dma_mask setup; it couldn't work with multiple controllers.Signed-off-by: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Add a filesystem API for stack. The initial version of
this interface is purely synchronous.dbrownell@users.sourceforge.net:
Cleaned up, bugfixed; much simplified; added preliminary documentation.
Works with mdev given CONFIG_SYSFS_DEPRECATED; and presumably udev.
Updated SPI_IOC_MESSAGE ioctl to full spi_message semantics, supporting
groups of one or more transfers (each of which may be full duplex if
desired).This is marked as EXPERIMENTAL with an explicit disclaimer that the API
(notably the ioctls) is subject to change.Signed-off-by: Andrea Paterniani
Signed-off-by: David Brownell
Cc: Arnd Bergmann
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
08 May, 2007
1 commit
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This patch implements the driver necessary use the Analog Devices Blackfin
processor's SPI Port.Signed-off-by: Bryan Wu
Cc: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
15 Feb, 2007
1 commit
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Driver for the Atmel on-chip SPI master controller.
Tested primarily on AVR32/AT32AP7000/ATSTK1000 using mtd_dataflash and the
jffs2 filesystem. Should also work fine on various AT91 ARM-based chips
like AT91SAM926x and AT91RM9200.Hardware documentation can be found in the AT32AP7000 data sheet, or its
AT91 siblings, which can be downloaded fromhttp://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen
Signed-off-by: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
13 Feb, 2007
3 commits
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This is adds a simple SPI EEPROM driver, providing access to the EEPROM
through sysfs much like the I2C "eeprom" driver ... except this driver
supports write access, and multiple EEPROM sizes.From: "Tuppa, Walter"
Since I have EEPROMs on SPI with different address sizing, I made some
changes to your at25.c to support them. Works perfectly. (Also includes a
small bugfix for the "what size address" test.)Signed-off-by: David Brownell
Signed-off-by: Walter Tuppa
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Add the SPI controller driver for Freescale i.MX(S/L/1).
Main features summary:> Per chip setup via board specific code and/or protocol driver.
> Per transfer setup.
> PIO transfers.
> DMA transfers.
> Managing of NULL tx / rx buffer for rd only / wr only transfers.This patch replace patch-2.6.20-rc4-spi_imx with the following changes:
> Few cosmetic changes.
> Function map_dma_buffers now return 0 for success and -1 for failure.
> Solved a bug inside spi_imx_probe function (wrong error path).
> Solved a bug inside setup function (bad undo setup for max_speed_hz).
> For read-only transfers, always write zero bytes.This is almost the same as the 'BIS' version sent by Andrea, except for
updating the 'DUMMY' byte so that read-only transfers shift out zeroes.
That part of the API changed recently, since some half duplex peripheral
chips require that semantic.Signed-off-by: Andrea Paterniani
Signed-off-by: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
This adds a SPI driver for the Microwire controller on OMAP1 chips. This
driver has been used in the Linux-OMAP tree for some time now, including
with some of those displays using standardized 9-bit commands followed by
data with 8-bit words.Microwire only supports half duplex transfers, but that's all that most SPI
protocols need. When full duplex, or higher speeds, are needed there are
several other controllers that can be used on OMAP.[akpm@osdl.org: cleanups]
Signed-off-by: David Brownell
Signed-off-by: Imre Deak
Signed-off-by: Juha Yrjola
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
22 May, 2006
1 commit
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Hardware based SPI driver for Samsung S3C24XX SoC systems
Signed-off-by: Ben Dooks
Cc: David Brownell
Cc: Greg KH
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds