15 Nov, 2005
40 commits
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The logging for boot errors was turned off because it was broken
on some AMD systems. But give Intel EM64T systems a chance because they are
supposed to be correct there.The advantage is that there is a chance to actually log uncorrected
machine checks after the reset.Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
On x86_64 arches, there is no way to choose ACPI_NUMA without having to choose
K8_NUMA. CONFIG_K8_NUMA is not needed for Intel EM64T NUMA boxes. It also
looks odd if you have to select ACPI_NUMA from the power management menu.
This patch fixes those oddities. Patch does the following:1. Makes NUMA a config option like other arches
2. Makes topology detection options like K8_NUMA dependent on NUMA
3. Choosing ACPI NUMA detection can be done from the standard
"Processor type and features" menuAK: I fixed up the dependencies and changed the help texts a bit
on top of Kiran's patch.Signed-off-by: Ravikiran Thirumalai
Signed-off-by: Shai Fultheim
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Keeping this function does not makes sense because it's a copied (and
buggy) copy of sys_time. The only difference is that now.tv_sec (which is
a time_t, i.e. a 64-bit long) is copied (and truncated) into a int
(32-bit).The prototype is the same (they both take a long __user *), so let's drop
this and redirect it to sys_time (and make sure it exists by defining
__ARCH_WANT_SYS_TIME).Only disadvantage is that the sys_stime definition is also compiled (may be
fixed if needed by adding a separate __ARCH_WANT_SYS_STIME macro, and
defining it for all arch's defining __ARCH_WANT_SYS_TIME except x86_64).Acked-by: Andi Kleen
Signed-off-by: Paolo 'Blaisorblade' Giarrusso
Signed-off-by: Andrew Morton
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
The current value was correct before the introduction of Intel EM64T support -
but now L1_CACHE_SHIFT_MAX can be less than L1_CACHE_SHIFT, which _is_ funny!Between the few users of ____cacheline_maxaligned_in_smp, we also have (for
example) rcu_ctrlblk, and struct zone, with zone->{lru_,}lock. I.e. we have
a lot of excess cacheline bouncing on them.No correctness issues, obviously. So this could even be merged for 2.6.14
(I'm not a fan of this idea, though).CC: Andi Kleen
Signed-off-by: Paolo 'Blaisorblade' Giarrusso
Signed-off-by: Andrew Morton
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Not needed since x86-64 always uses the spinlock based rwsems.
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
B stepping were the first shipping Opterons. memcpy/memset/copy_page/
clear_page had special optimized version for them. These are really
old and in the minority now and the difference to the generic versions
(using rep microcode) is not that big anyways. So just remove them.TODO: figure out optimized versions for Intel Netburst based EM64T
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Old code could retry for 10 seconds worst time. Only try it
for one second now.Suggested by Yinghai Lu
Cc: Yinghai.Lu@amd.com
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Fix the Intel cache detection code assumption that number of threads
sharing the cache will either be equal to number of HT or core siblings.This also cleans up the code in general a bit.
Signed-off-by: Suresh Siddha
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Fields obtained through cpuid vector 0x1(ebx[16:23]) and
vector 0x4(eax[14:25], eax[26:31]) indicate the maximum values and might not
always be the same as what is available and what OS sees. So make sure
"siblings" and "cpu cores" values in /proc/cpuinfo reflect the values as seen
by OS instead of what cpuid instruction says. This will also fix the buggy BIOS
cases (for example where cpuid on a single core cpu says there are "2" siblings,
even when HT is disabled in the BIOS.
http://bugzilla.kernel.org/show_bug.cgi?id=4359)Signed-off-by: Suresh Siddha
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
When they were disabled before (e.g. after a panic) it's better
to keep them off, otherwise followon panics can happen from timer
interrupt handlers etc.Drawback is that pageup in the console won't work anymore though.
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
No functional changes.
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
They report 40bit, but only have 36bits of physical address space.
This caused problems with setting up the correct masks for MTRR.CPUID workaround for steppings 0F33h(supporting x86) and 0F34h(supporting x86
and EM64T). Detail info can be found at:
http://download.intel.com/design/Xeon/specupdt/30240216.pdf
http://download.intel.com/design/Pentium4/specupdt/30235221.pdfSigned-off-by: Shaohua Li
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Ugh!
Cc: davej@redhat.com
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
So far all new ones have worked and there isn't much variation because
the CPU does all the interesting bits.So enable try unsupported by default.
Can be still disabled with try_unsupported=0 (module) or
amd64.try_unsupported=0 (boot option)Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
(no name because I'm not sure of the correct name)
Cc: davej@redhat.com
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Compute the highest possible value for memnode_shift, in order to reduce
footprint of memnodemap[] to the minimum, thus making all users
(phys_to_nid(), kfree()), more cache friendly.Before the patch :
Node 0 MemBase 0000000000000000 Limit 00000001ffffffff
Node 1 MemBase 0000000200000000 Limit 00000003ffffffff
Using 23 for the hash shift. Max adder is 3ffffffffAfter the patch :
Node 0 MemBase 0000000000000000 Limit 00000001ffffffff
Node 1 MemBase 0000000200000000 Limit 00000003ffffffff
Using 33 for the hash shift.In this case, only 2 bytes of memnodemap[] are used, instead of 2048
Signed-off-by: Eric Dumazet
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
This allows to run 64bit signal handlers in 64bit processes that run small
code snippets in compat mode.Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
With a NR_CPUS==128 kernel with CPU hotplug enabled we would waste 4MB
on per CPU data of all possible CPUs. The reason was that HOTPLUG
always set up possible map to NR_CPUS cpus and then we need to allocate
that much (each per CPU data is roughly ~32k now)The underlying problem is that ACPI didn't tell us how many hotplug CPUs
the platform supports. So the old code just assumed all, which would
lead to this memory wastage.This implements some new heuristics:
- If the BIOS specified disabled CPUs in the ACPI/mptables assume they
can be enabled later (this is bending the ACPI specification a bit,
but seems like a obvious extension)
- The user can overwrite it with a new additionals_cpus=NUM option
- Otherwise use half of the available CPUs or 2, whatever is more.Cc: ashok.raj@intel.com
Cc: len.brown@intel.comSigned-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Pointed out by Eric Dumazet
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
I got some questions on this, so just fix up the documentation.
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Minor victory on the continuous quest against all stray extern.
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Minor cleanup - remove obsolete extern
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Adding __initdata_* to asm-generic/sections.h
Replaces a lot of open coded externs in arch/x86_64/*
I had to change __bss_end to __bss_stop to match the other architectures.Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
It is for physical addresses, not for PFNs.
Pointed out by Tejun Heo.
Cc: htejun@gmail.com
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
We should zap the low mappings, as soon as possible, so that we can catch
kernel bugs more effectively. Previously early boot had NULL mapped
and didn't trap on NULL references.This patch introduces boot_level4_pgt, which will always have low identity
addresses mapped. Druing boot, all the processors will use this as their
level4 pgt. On BP, we will switch to init_level4_pgt as soon as we enter C
code and zap the low mappings as soon as we are done with the usage of
identity low mapped addresses. On AP's we will zap the low mappings as
soon as we jump to C code.Signed-off-by: Suresh Siddha
Signed-off-by: Ashok Raj
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Not go from the CPU number to an mapping array.
Mode number is often used now in fast paths.This also adds a generic numa_node_id to all the topology includes
Suggested by Eric Dumazet
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Fix
arch/x86_64/kernel/aperture.c: In function #iommu_hole_init#:
arch/x86_64/kernel/aperture.c:199: warning: #aper_order# may be used uninitialized in this functionSigned-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
According to cpuid instruction in IA32 SDM-Vol2, when computing cpu model,
we need to consider extended model ID for family 0x6 also.AK: Also added fixes/simplifcation from Petr Vandrovec
Signed-off-by: Suresh Siddha
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Remove duplicate __cpuinit in smp.c. Already defined in init.h which is
already included.Signed-off-by: Ashok Raj
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Has been introduced for x86-64 at some point to save memory
in struct page, but has been obsolete for some time. Just
remove it.Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
pfn_to_page really requires pfn_valid to be true now, no question.
Some people stumbled over it, but it was misleading and wrong.Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Here's a patch that builds on Natalie Protasevich's IRQ compression
patch and tries to work for MPS boots as well as ACPI. It is meant for
a 4-node IBM x460 NUMA box, which was dying because it had interrupt
pins with GSI numbers > NR_IRQS and thus overflowed irq_desc.The problem is that this system has 270 GSIs (which are 1:1 mapped with
I/O APIC RTEs) and an 8-node box would have 540. This is much bigger
than NR_IRQS (224 for both i386 and x86_64). Also, there aren't enough
vectors to go around. There are about 190 usable vectors, not counting
the reserved ones and the unused vectors at 0x20 to 0x2F. So, my patch
attempts to compress the GSI range and share vectors by sharing IRQs.Cc: "Protasevich, Natalie"
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.
This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.
The user may interface through sysfs files in order to change the threshold configuration.bank%d/error_count - reads current error count, write to clear.
bank%d/interrupt_enable - set/clear interrupt enable.
bank%d/threshold_limit - read/write the threshold limit.APIC vector 0xF9 in hw_irq.h.
5 software defined bank ids in mce.h.
new apic.c function to setup threshold apic lvt.
defaults to interrupt off, count enabled, and threshold limit max.
sysfs interface created on /sys/devices/system/threshold.AK: added some ifdefs to make it compile on UP
Signed-off-by: Jacob Shin
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Signed-off-by: Jan Beulich
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
The VM needs to know about lost memory in zones to accurately
balance dirty pages. This patch accounts mem_map in there too,
which fixes a constant errror of a few percent. Also some
other misc mappings and the kernel text itself are accounted
too.Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds -
The code should deal with an additional empty zone, so fix up the
#error.Signed-off-by: Andi Kleen
Signed-off-by: Linus Torvalds
