Eric Lee / smarc-fsl-linux-kernel

27 Oct, 2015

5 commits

  • ef0eebc05   drivers/pinctrl: Add the concept of an "init" state ... Browse Code »

    For pinctrl the "default" state is applied to pins before the driver's
    probe function is called. This is normally a sensible thing to do,
    but in some cases can cause problems. That's because the pins will
    change state before the driver is given a chance to program how those
    pins should behave.

    As an example you might have a regulator that is controlled by a PWM
    (output high = high voltage, output low = low voltage). The firmware
    might leave this pin as driven high. If we allow the driver core to
    reconfigure this pin as a PWM pin before the PWM's probe function runs
    then you might end up running at too low of a voltage while we probe.

    Let's introudce a new "init" state. If this is defined we'll set
    pinctrl to this state before probe and then "default" after probe
    (unless the driver explicitly changed states already).

    An alternative idea that was thought of was to use the pre-existing
    "sleep" or "idle" states and add a boolean property that we should
    start in that mode. This was not done because the "init" state is
    needed for correctness and those other states are only present (and
    only transitioned in to and out of) when (optional) power management
    is enabled.

    Changes in v3:
    - Moved declarations to pinctrl/devinfo.h
    - Fixed author/SoB

    Changes in v2:
    - Added comment to pinctrl_init_done() as per Linus W.

    Signed-off-by: Douglas Anderson
    Acked-by: Greg Kroah-Hartman
    Tested-by: Caesar Wang
    Signed-off-by: Linus Walleij

    Douglas Anderson
     
  • bac7f4c1b   pinctrl: uniphier: set input-enable before pin-muxing ... Browse Code »

    While IECTRL is disabled, input signals are pulled-down internally.
    If pin-muxing is set up first, glitch signals (Low to High transition)
    might be input to hardware blocks.

    Bad case scenario:
    [1] The hardware block is already running before pinctrl is handled.
    (the reset is de-asserted by default or by a firmware, for example)
    [2] The pin-muxing is set up. The input signals to hardware block
    are pulled-down by the chip-internal biasing.
    [3] The pins are input-enabled. The signals from the board reach the
    hardware block.

    Actually, one invalid character is input to the UART blocks for such
    SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the
    power on reset.

    To avoid such problems, pins should be input-enabled before muxing.

    Fixes: 6e9088920258 ("pinctrl: UniPhier: add UniPhier pinctrl core support")
    Signed-off-by: Masahiro Yamada
    Reported-by: Dai Okamura
    Signed-off-by: Linus Walleij

    Masahiro Yamada
     
  • e0548004d   pinctrl: cygnus: Add new compatible string for gpio controller driver ... Browse Code »

    This new compatible string, "brcm,iproc-gpio", should be used for
    all new iproc-based future SoCs.

    Signed-off-by: Pramod Kumar
    Reviewed-by: Ray Jui
    Reviewed-by: Scott Branden
    Signed-off-by: Linus Walleij

    Pramod Kumar
     
  • ea92211c0   pinctrl: cygnus: Remove GPIO to Pinctrl pin mapping from driver ... Browse Code »

    Remove gpio to pinctrl pin mapping code from driver and
    address this through standard property "gpio-ranges".

    Signed-off-by: Pramod Kumar
    Reviewed-by: Ray Jui
    Reviewed-by: Scott Branden
    Signed-off-by: Linus Walleij

    Pramod Kumar
     
  • 03e09bc18   pinctrl: cygnus: Optional DT property to support pin mappings ... Browse Code »

    If GPIO controller's pins are muxed, pin-controller subsystem
    need to be intimated by defining mapping between gpio and
    pinmux controller. This patch adds required properties to
    define this mapping via DT.

    Signed-off-by: Pramod Kumar
    Reviewed-by: Ray Jui
    Reviewed-by: Scott Branden
    Acked-by: Rob Herring
    Signed-off-by: Linus Walleij

    Pramod Kumar
     

26 Oct, 2015

1 commit

23 Oct, 2015

2 commits

20 Oct, 2015

9 commits

17 Oct, 2015

4 commits

  • ec879f127   pinctrl: baytrail: Fix compilation warnings when !CONFIG_PM ... Browse Code »

    When CONFIG_PM is not set we get following compilation warnings:

    warning: ‘byt_gpio_runtime_suspend’ defined but not used [-Wunused-function]
    warning: ‘byt_gpio_runtime_resume’ defined but not used [-Wunused-function]

    Fix this by guarding byt_gpio_runtime_suspend()/byt_gpio_runtime_resume()
    with #ifdef CONFIG_PM.

    Signed-off-by: Mika Westerberg
    Signed-off-by: Linus Walleij

    Mika Westerberg
     
  • f487bbf30   pinctrl: intel: Fix compilation warning when !CONFIG_PM_SLEEP ... Browse Code »

    We get following warning when CONFIG_PM_SLEEP is not set

    warning: ‘intel_gpio_irq_init’ defined but not used [-Wunused-function]

    Since the function is only called from intel_pinctrl_resume() move it
    inside CONFIG_PM_SLEEP guard as well.

    Signed-off-by: Mika Westerberg
    Signed-off-by: Linus Walleij

    Mika Westerberg
     
  • 11091fb0a   pinctrl: qcom: ssbi: fix compilation with DEBUG_FS=n ... Browse Code »

    The DEBUG_FS=n #defines for the dbg_show functions were missed when
    renaming the driver from msm_ to pm8xxx_, causing it to break the build
    when DEBUG_FS isn't enabled:

    CC [M] drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o
    drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:597:14: error: ‘pm8xxx_gpio_dbg_show’ undeclared here (not in a function)
    .dbg_show = pm8xxx_gpio_dbg_show,

    Fix this by renaming them correctly.

    Fixes: b4c45fe974bc ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers")
    Signed-off-by: Jonas Gorski
    Reviewed-by: Bjorn Andersson
    Signed-off-by: Linus Walleij

    Jonas Gorski
     
  • 3fa508cd2   pinctrl: atlas7: support atlas7 step B changes ... Browse Code »

    The the pin groups and pin functions have been changed
    in atlas7 step B soc. We have to update the driver
    to support step B chip.

    Changes:
    1. add 5 jtag pins to IOC_TOP:
    "jtag_tdo", "jtag_tms","jtag_tck", "jtag_tdi", "jtag_trstn"
    these 5 pins can be mutiplex with other functions, so we
    have to conver these 5 pins in pinmux.
    2. add pin groups for audio digmic, audio spdif, can transceiver
    en, can transceiver stb, i2s0, i2s1 and jtag.
    3. serval pins can be located to more PADs:
    audio_uart0_urfs, audio_uart1_urfs, audio_uart2_urfs,
    audio_uart2_urxd, audio_uart2_usclk, audio_uart2_utfs,
    audio_uart2_utxd, can0_rxd, can0_txd, can1_rxd, can1_txd
    jtag_ntrst, jtag_swdiotms, jtag_tck, jtag_tdi, jtag_tdo,
    pw_cko0, pw_cko1, pw_i2s01, pw_pwm0, pw_pwm1, sd2_cdb,
    sd2_wpb, uart2_cts, uart2_rts, uart2_rxd, uart2_txd,
    uart3_cts, uart3_rts, uart3_rxd, uart3_txd, uart4_cts,
    uart4_rts, usb0_drvvbus, usb1_drvvbus.

    Because of Changes#3, some functions should have more than one
    pin groups. So we have to split the original pin group to serval
    pin groups.

    For example:
    audio_uart0 has 5 pins, on STEPA, each of these 5 pins only has
    one related PAD. But on STEPB, audio_uart0_urfs has 4 related
    PAD.
    So we place the 4 pins with one PAD into a single pin group:
    audio_uart0_basic_group.
    and place urfs pin wtih different PADs to 4 different pin groups:
    audio_uart0_urfs_group0, ..., audio_uart0_urfs_group3

    A full audio_uart0 pin group can be:
    pinctrl-0 = ;
    If audio_uart0 pin group encountered some confiction, we only have
    to change the urfs group:
    pinctrl-0 = ;

    Signed-off-by: Wei Chen
    Signed-off-by: Barry Song
    Signed-off-by: Linus Walleij

    Wei Chen
     

16 Oct, 2015

8 commits

03 Oct, 2015

8 commits

02 Oct, 2015

3 commits

  • ee1635180   pinctrl: freescale: imx: fix system crash if enable two pinctl instances ... Browse Code »

    Fix system chrash caused by groups whose number is smaller than the number
    of groups of the last pinctl instance which is not initialized.

    iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing
    the second instance (iomuxc) the chrash below occurs.

    Uncompressing Linux... done, booting the kernel.
    [ 0.000000] Booting Linux on physical CPU 0x0
    [ 0.000000] Linux version 4.2.0-next-20150901-00006-gebfa43c (aalonso@bluefly)
    [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7)
    [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin instruction cache
    [ 0.000000] Machine model: Freescale i.MX7 SabreSD Board
    [ 0.661012] [] (strcmp) from [] (imx_dt_node_to_map+0x58/0x208)
    [ 0.668879] [] (imx_dt_node_to_map) from [] (pinctrl_dt_to_map+0x174/0x2b0)
    [ 0.677654] [] (pinctrl_dt_to_map) from [] (pinctrl_get+0x100/0x424)
    [ 0.685878] [] (pinctrl_get) from [] (pinctrl_register+0x26c/0x480)
    [ 0.694104] [] (pinctrl_register) from [] (imx_pinctrl_probe+0x580/0x6e8)
    [ 0.702706] [] (imx_pinctrl_probe) from [] (platform_drv_probe+0x44/0xa4)
    [ 0.711455] [] (platform_drv_probe) from [] (driver_probe_device+0x174/0x2b4)
    [ 0.720405] [] (driver_probe_device) from [] (__driver_attach+0x8c/0x90)
    [ 0.728982] [] (__driver_attach) from [] (bus_for_each_dev+0x6c/0xa0)
    [ 0.737381] [] (bus_for_each_dev) from [] (bus_add_driver+0x148/0x1f0)
    [ 0.745804] [] (bus_add_driver) from [] (driver_register+0x78/0xf8)
    [ 0.753880] [] (driver_register) from [] (do_one_initcall+0x8c/0x1d4)
    [ 0.762282] [] (do_one_initcall) from [] (kernel_init_freeable+0x144/0x1e4)
    [ 0.771061] [] (kernel_init_freeable) from [] (kernel_init+0x8/0xe8)
    [ 0.779285] [] (kernel_init) from [] (ret_from_fork+0x14/0x2c)
    [ 0.786981] Code: e3520000 e5e32001 1afffffb e12fff1e (e4d03001)

    Signed-off-by: Robin Gong
    Signed-off-by: Adrian Alonso
    Acked-by: Shawn Guo
    Signed-off-by: Linus Walleij

    Robin Gong
     
  • de4e882f3   pinctrl: at91-pio4: add PM stuff ... Browse Code »

    Allow GPIOs to be configured as wakeup sources. When going to suspend,
    disable all GPIO irqs excepting the one configured as wakeup sources.

    Signed-off-by: Ludovic Desroches
    Signed-off-by: Linus Walleij

    Ludovic Desroches
     
  • 4730f33f0   pinctrl: sunxi: add allwinner A83T PIO controller support ... Browse Code »

    Allwinner A83T soc port controller has 8 ports.
    It has 3 IRQ banks namely PB, PG, PH.
    Pinmuxing are different for some pins as compared to
    sun8i A23 and A33.

    Signed-off-by: Vishnu Patekar
    Acked-by: Maxime Ripard
    Signed-off-by: Linus Walleij

    Vishnu Patekar