31 Mar, 2011
2 commits
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Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi
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…git/tip/linux-2.6-tip
* 'irq-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
avr32: Fix missing irq namespace conversion
powerpc: qe_ic: Rename get_irq_desc_data and get_irq_desc_chip
genirq: Remove the now obsolete config options and select statements
arm: versatile : Fix typo introduced in irq namespace cleanup
sound: Fixup the last user of the old irq functions
genirq: Remove obsolete comment
genirq: Remove now obsolete set_irq_wake()
sh: Fix irq cleanup fallout
x86: apb_timer: Fixup genirq fallout
genirq: Fix misnamed label in handle_edge_eoi_irqFix up crazy conflict in arch/powerpc/include/asm/qe_ic.h:
- commit eead4d5c63ff ("powerpc: qe_ic: Rename get_irq_desc_data and
get_irq_desc_chip") made the helper functions use
irq_desc_get_handler_data() instead of the legacy (and no longer
existing) get_irq_desc_data.- commit d4db35e8dc96 ("powerpc/qe_ic: Fix another breakage from the
irq_data conversion") used irq_desc_get_chip_data() instead.According to Thomas, the former is the correct direct conversion, but it
does look like both should work (arch/powerpc/sysdev/qe_lib/qe_ic.c
seems to initialize both to the same thing), and the chip data in some
ways is the more logical. Somebody should really decide on one of the
other.This merge picks irq_desc_get_handler_data() as the straightforward pure
conversion to new names, as per Thomas.
30 Mar, 2011
2 commits
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* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin:
Blackfin: bitops: fix include order after little endian inclusion
Blackfin: defconfigs: update after misc devices defaulted to N
Blackfin: use more standard pr_fmt in the module loader -
Signed-off-by: Thomas Gleixner
29 Mar, 2011
3 commits
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Signed-off-by: Thomas Gleixner
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Convert to the new function names. Scripted with coccinelle.
Signed-off-by: Thomas Gleixner
Cc: Mike Frysinger
Cc: uclinux-dist-devel@blackfin.uclinux.org -
Use the trigger type in irq_data and check level type instead of
looking at desc->handle_irq.Signed-off-by: Thomas Gleixner
Cc: Mike Frysinger
Cc: uclinux-dist-devel@blackfin.uclinux.org
26 Mar, 2011
3 commits
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The le.h header requires things like test_bit to be declared, so we need
to move its inclusion to after the point where that happens.Signed-off-by: Mike Frysinger
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The default value for misc devices was changed from Y to N which
causes problems for mini defconfigs that were relying on this
defaulting to Y. So update all of the defconfigs accordingly.Reported-by: Uwe Kleine-König
Signed-off-by: Mike Frysinger -
Changed pr_fmt(fmt) to make the format arguments match the format.
Changed an argument name in apply_relocate from me to mod so that
the pr_err is consistent with the other uses.
Added missing '\n' to a format.Signed-off-by: Joe Perches
Signed-off-by: Mike Frysinger
24 Mar, 2011
4 commits
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* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin:
Blackfin: bf54x: re-enable anomaly 05000353 for all revs
Blackfin: enable atomic64_t support
Blackfin: wire up new syncfs syscall
Blackfin: SMP: flush CoreB cache when shutting down -
minix bit operations are only used by minix filesystem and useless by
other modules. Because byte order of inode and block bitmaps is different
on each architecture like below:m68k:
big-endian 16bit indexed bitmapsh8300, microblaze, s390, sparc, m68knommu:
big-endian 32 or 64bit indexed bitmapsm32r, mips, sh, xtensa:
big-endian 32 or 64bit indexed bitmaps for big-endian mode
little-endian bitmaps for little-endian modeOthers:
little-endian bitmapsIn order to move minix bit operations from asm/bitops.h to architecture
independent code in minix filesystem, this provides two config options.CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED is only selected by m68k.
CONFIG_MINIX_FS_NATIVE_ENDIAN is selected by the architectures which use
native byte order bitmaps (h8300, microblaze, s390, sparc, m68knommu,
m32r, mips, sh, xtensa). The architectures which always use little-endian
bitmaps do not select these options.Finally, we can remove minix bit operations from asm/bitops.h for all
architectures.Signed-off-by: Akinobu Mita
Acked-by: Arnd Bergmann
Acked-by: Greg Ungerer
Cc: Geert Uytterhoeven
Cc: Roman Zippel
Cc: Andreas Schwab
Cc: Martin Schwidefsky
Cc: Heiko Carstens
Cc: Yoshinori Sato
Cc: Michal Simek
Cc: "David S. Miller"
Cc: Hirokazu Takata
Acked-by: Ralf Baechle
Acked-by: Paul Mundt
Cc: Chris Zankel
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
As the result of conversions, there are no users of ext2 non-atomic bit
operations except for ext2 filesystem itself. Now we can put them into
architecture independent code in ext2 filesystem, and remove from
asm/bitops.h for all architectures.Signed-off-by: Akinobu Mita
Cc: Jan Kara
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
Introduce little-endian bit operations to the big-endian architectures
which do not have native little-endian bit operations and the
little-endian architectures. (alpha, avr32, blackfin, cris, frv, h8300,
ia64, m32r, mips, mn10300, parisc, sh, sparc, tile, x86, xtensa)These architectures can just include generic implementation
(asm-generic/bitops/le.h).Signed-off-by: Akinobu Mita
Cc: Richard Henderson
Cc: Ivan Kokshaysky
Cc: Mikael Starvik
Cc: David Howells
Cc: Yoshinori Sato
Cc: "Luck, Tony"
Cc: Ralf Baechle
Cc: Kyle McMartin
Cc: Matthew Wilcox
Cc: Grant Grundler
Cc: Paul Mundt
Cc: Kazumoto Kojima
Cc: Hirokazu Takata
Cc: "David S. Miller"
Cc: Chris Zankel
Cc: Ingo Molnar
Cc: Thomas Gleixner
Acked-by: Hans-Christian Egtvedt
Acked-by: "H. Peter Anvin"
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
23 Mar, 2011
4 commits
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Even though the anomaly sheet says that the the bootrom is fixed, tests
have shown that the fix itself does not handle all cases. So until we
get a ROM update, assume the reset code is still broken and we need to
handle things ourselves.Signed-off-by: Mike Frysinger
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Signed-off-by: Mike Frysinger
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Signed-off-by: Mike Frysinger
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When CoreB wakes up, it needs to read variables that CoreA might have
modified, and might be in CoreB's cache. So kill CoreB's cache before
going to sleep so that when we wake up, we are in a coherent state.Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger
18 Mar, 2011
22 commits
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The previous commit that changed this code to the common GPIO layers
forgot to delete the local and now unused "i" variable.Signed-off-by: Mike Frysinger
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No code uses these, and the short define names are polluting the global
namespace where they collide with things like common irq files. So just
punt the damned things. If in the future we need HDMA support, we can
make a standalone header for these things.Signed-off-by: Mike Frysinger
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Hook up name_to_handle_at, open_by_handle_at, and clock_adjtime.
Signed-off-by: Mike Frysinger
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This patch fixes the Blackfin irqflags to make them I-pipe aware anew,
after the introduction of the hard_local_irq_*() API.Signed-off-by: Philippe Gerum
Signed-off-by: Mike Frysinger -
This patch makes sure to sync the pipeline for the root stage only
from the outer interrupt level, when resuming kernel code after an
interrupt.This fixes a bug causing EVT15 to be spuriously popped off upon nested
interrupts, which in turn would cause the preempted kernel code to
resume without supervisor privileges.Signed-off-by: Philippe Gerum
Signed-off-by: Mike Frysinger -
This patch introduces Blackfin-specific bits to support the current
tip of the interrupt pipeline development, mainly:- 2/3-level interrupt maps (sparse IRQs)
- generic virq handling
- sysinfo v2 format for ipipe_get_sysinfo()Signed-off-by: Philippe Gerum
Signed-off-by: Mike Frysinger -
No functional changes here.
Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
All chips converted.
Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Signed-off-by: Mike Frysinger
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Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Fixup the open coded access to irq_desc and use the proper wrappers.
Signed-off-by: Thomas Gleixner
Signed-off-by: Mike Frysinger -
Take advantage of more Blackfin-specific insns, and only initialize
registers required by the ABI.Signed-off-by: Mike Frysinger
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In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram. The trouble with multi-core systems is that all
L1 sram is visible only to the active core. So we can't just place the
functions into L1 and call it directly. We need to setup a jump table and
place the entry point in external memory. This will call the right func
based on the active core.In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.Signed-off-by: Sonic Zhang
Signed-off-by: Mike Frysinger -
Re-use some of the existing cpu hotplugging code in the process.
Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger -
We need to place icache flush funcs into L1 inst sram to work around a
hardware anomaly. But this currently breaks SMP support as the L1 inst
sram is per-core and cannot be called directly. So in preparation for
making that work, split the two options.Further, split out the SMP depend so that we can allow some for SMP.
Signed-off-by: Mike Frysinger
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The smp_processor_id() API requires that preempt be disabled when calling
it, so make sure it is when we go to send messages to other processors.Signed-off-by: Sonic Zhang
Signed-off-by: Mike Frysinger
