01 May, 2017

1 commit


22 Apr, 2017

1 commit


06 Mar, 2017

1 commit


30 Jun, 2016

2 commits

  • Change the hardware reset gpio to 'GPIO6_IO15' for mipi dsi to
    allow fec2 and mipi dsi can run at the same time. This needs
    some hardware rework as follows:
    "
    1. Replace R631 with 100K resistor;
    2. Remove D14, D24;
    3. Solder the Cathode of the diode to R471,
    you can use BAT54HT1(ONSEMI) or NSR0320MW2T1G(ONSEMI);
    4. Solder the wire to the Anode end of the diode;
    5. Scrape the solder mask(Green oil) of the MIPI Reset via,
    then solder the end of the wire to the via.
    "

    Signed-off-by: Fancy Fang
    (cherry picked from commit 0af28564e73f006f742a9af0db4bc5b8588e3490)

    Fancy Fang
     
  • The 32 bpp pixel format which is passed to pxp should be
    'PXP_PIX_FMT_RGB32' instead of 'PXP_PIX_FMT_RGB24', since
    only 'PXP_PIX_FMT_RGB32' can be recognized by lcdif.

    Signed-off-by: Fancy Fang
    (cherry picked from commit c98efc59e1bc6d1814b2179f1b7e9f22cb177f47)

    Fancy Fang
     

29 Jun, 2016

4 commits

  • with CONFIG_HZ=100, the precision of jiffies is 10ms, and the
    generic_cmd6_time of some card is also 10ms. then, may be current
    time is only 5ms, but already timed out caused by jiffies precision.

    Signed-off-by: Chaotian Jing
    Signed-off-by: Ulf Hansson
    (cherry picked from commit 8bcce64faaaf07165453e6600ae9ffb887e79b1a)
    Signed-off-by: Haibo Chen
    (cherry picked from commit 38f639884a2cfd65cbe29ac2fbfe4ab3fcb1f1af)

    Chaotian Jing
     
  • there is a time window between __mmc_send_status() and time_afer(),
    on some eMMC chip, the timeout_ms is only 10ms, if this thread was
    scheduled out during this period, then, even card has already changes
    to transfer state by the result of CMD13, this part of code also treat
    it to timeout error.
    So, need calculate timeout first, then call __mmc_send_status(), if
    already timeout and card still in programing state, then treat it to
    the real timeout error.

    Signed-off-by: Chaotian Jing
    Signed-off-by: Ulf Hansson
    (cherry picked from commit 3bbb0deea6d5c6d5ed38ae927a5bf9b0cd7c8639)
    Signed-off-by: Haibo Chen
    (cherry picked from commit b9b8249b98b9128d8931887eccb38cd45a0f8bf3)

    Chaotian Jing
     
  • Now, when call esdhc_set_timeout() to set the data timeout counter value,
    IPP_RST_N(bit 23) is wrongly affected. This patch add a mask to avoid this.

    Signed-off-by: Haibo Chen
    (cherry picked from commit 6713b713dda4382677bc31a16d6ff3ef23f2d1ac)

    Haibo Chen
     
  • Our Reference Manual has a mistake, for the register SYS_CTRL,the
    DTOCV(bit 19~16) means the data timeout counter value. When DTOCV
    is set to 0xF, it means SDCLK << 29, not SDCLK << 28.

    This patch correct this in our usdhc driver.

    Signed-off-by: Haibo Chen
    (cherry picked from commit df9598d6dd617ed87b2e41e29bfc794b69831e86)

    Haibo Chen
     

23 Jun, 2016

1 commit


22 Jun, 2016

1 commit

  • During suspend, as 24MHz will be disabled, but system counter
    needs to be running in order to maintain accurate clock source,
    so we need to switch system counter's clock from base clock(24MHz)
    to alternate clock(32K) before system enter STOP mode, otherwise,
    the suspend time will NOT be counted into system time when issue
    a "date" command.

    Signed-off-by: Anson Huang

    Anson Huang
     

16 Jun, 2016

1 commit

  • This reverts commit 312979d1fcbd068d4ba0f461e974e7cbcc889548.

    When busfreq is at low bus mode, which is 24MHz, it means DDR/AHB/AXI
    will drop to 24MHz. At the same time, when in low busfreq mode, cpuidle
    can be in low power idle, DRAM will be put into self-refresh and DRAM IO
    will in low power mode to save power, so DMA will NOT work.

    So all peripherals that needs DMA, need to request bus freq to high
    setpoint when it is active.

    Signed-off-by: Haibo Chen
    (cherry picked from commit 2c01452f4d7c0f65553b365adc27a1b7b6ba8644)

    Haibo Chen
     

14 Jun, 2016

7 commits


13 Jun, 2016

1 commit


03 Jun, 2016

1 commit


02 Jun, 2016

1 commit


31 May, 2016

6 commits


26 May, 2016

1 commit


24 May, 2016

11 commits