/* * Copyright 2012-2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ #include #include / { aliases { mxcfb0 = &mxcfb1; mxcfb1 = &mxcfb2; mxcfb2 = &mxcfb3; mxcfb3 = &mxcfb4; }; memory: memory { reg = <0x10000000 0x40000000>; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_usb_otg_vbus: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 29 0>; enable-active-high; }; reg_usb_h1_vbus: regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 26 0>; enable-active-high; }; snvs_reg: vsnvs { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; regulator-boot-on; regulator-always-on; }; reg_1p8v: 1p8v { compatible = "regulator-fixed"; regulator-name = "1P8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; reg_2p5v: 2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; reg_3p3v: 3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; sound-sgtl5000 { compatible = "fsl,imx6q-ventana-sgtl5000", "fsl,imx-audio-sgtl5000"; model = "sgtl5000-audio"; ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; mux-int-port = <1>; mux-ext-port = <3>; }; sound-spdif { compatible = "fsl,imx-audio-spdif"; model = "imx-spdif"; spdif-controller = <&spdif>; spdif-in; spdif-out; }; sound-hdmi { compatible = "fsl,imx6q-audio-hdmi", "fsl,imx-audio-hdmi"; model = "imx-audio-hdmi"; hdmi-controller = <&hdmi_audio>; }; watchdog: watchdog { compatible = "linux,wdt-gpio"; gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; hw_algo = "toggle"; hw_margin_ms = <3000>; always-running; }; mxcfb1: fb@0 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "ldb"; interface_pix_fmt = "RGB24"; default_bpp = <24>; int_clk = <0>; late_init = <0>; status = "disabled"; }; mxcfb2: fb@1 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "hdmi"; interface_pix_fmt = "RGB24"; mode_str ="1920x1080M@60"; default_bpp = <24>; int_clk = <0>; late_init = <0>; status = "disabled"; }; mxcfb3: fb@2 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "lcd"; interface_pix_fmt = "RGB24"; mode_str ="CLAA-WVGA"; default_bpp = <16>; int_clk = <0>; late_init = <0>; status = "disabled"; }; mxcfb4: fb@3 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "ldb"; interface_pix_fmt = "RGB24"; default_bpp = <24>; int_clk = <0>; late_init = <0>; status = "disabled"; }; lcd@0 { compatible = "fsl,lcd"; ipu_id = <0>; disp_id = <0>; default_ifmt = "RGB24"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu1>; status = "okay"; }; backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; status = "okay"; }; v4l2_cap_0 { compatible = "fsl,imx6q-v4l2-capture"; ipu_id = <0>; csi_id = <0>; mclk_source = <0>; status = "disabled"; }; v4l2_cap_1 { compatible = "fsl,imx6q-v4l2-capture"; ipu_id = <0>; csi_id = <1>; mclk_source = <0>; status = "disabled"; }; v4l2_out { compatible = "fsl,mxc_v4l2_output"; status = "disabled"; }; }; &audmux { status = "okay"; }; &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; }; &clks { }; &ecspi1 { fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>, <&gpio4 10 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; status = "okay"; spidev@0x00 { compatible = "spidev"; spi-max-frequency = <16000000>; reg = <0>; }; spidev@0x01 { compatible = "spidev"; spi-max-frequency = <16000000>; reg = <1>; }; }; &ecspi2 { fsl,spi-num-chipselects = <4>; cs-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>,<&gpio3 24 GPIO_ACTIVE_HIGH>,<&gpio3 25 GPIO_ACTIVE_HIGH>,<0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; status = "okay"; /*SPI NOR Flash is lock up by U-Boot. Turn on GPIO4_20 if user need to access from kernel.*/ /*flash: mx25u3235f@0 { #address-cells = <1>; #size-cells = <1>; compatible = "macronix,mx25u3235f"; spi-max-frequency = <16000000>; reg = <0>; partition@0 { label = "U-Boot"; reg = <0x0 0x100000>; }; partition@100000 { label = "U-Boot Environment"; reg = <0x100000 0x080000>; }; partition@180000 { label = "Flattened Device Tree"; reg = <0x180000 0x200000>; }; };*/ spidev@0x02 { #address-cells = <1>; #size-cells = <0>; compatible = "spidev"; reg = <2>; spi-max-frequency = <16000000>; }; spidev@0x03 { #address-cells = <1>; #size-cells = <0>; compatible = "spidev"; reg = <3>; spi-max-frequency = <16000000>; }; }; &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; interrupts = <&pinctrl_enet_irq>; fsl,magic-packet; status = "okay"; }; &gpc { fsl,ldo-bypass = <0>; }; &dcic1 { dcic_id = <0>; dcic_mux = "dcic-hdmi"; status = "okay"; }; &dcic2 { dcic_id = <1>; dcic_mux = "dcic-lvds1"; status = "okay"; }; &hdmi_audio { status = "okay"; }; &hdmi_cec { pinctrl-names = "default"; /*&pinctrl-0 = <&pinctrl_hdmi_cec>;*/ status = "okay"; }; &hdmi_core { ipu_id = <0>; disp_id = <1>; status = "okay"; }; &hdmi_video { fsl,phy_reg_vlev = <0x0294>; fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; baseboard_eeprom: baseboard_eeprom@50 { compatible = "at,24c256"; reg = <0x50>; }; codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks 201>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_1p8v>; }; s35390a: s35390a@30 { compatible = "s35390a"; reg = <0x30>; interrupt-parent = <&gpio3>; interrupts = <30 0>, <31 0>; }; cape_eeprom0: cape_eeprom@57 { compatible = "at,24c256"; reg = <0x57>; }; battery: bq24735@09 { compatible = "ti,bq24735"; reg = <0x09>; ti,charge-current = <128>; ti,input-current = <256>; ti,charge-voltage = <5000>; }; }; &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; hdmi_edid: edid@50 { compatible = "fsl,imx6-hdmi-i2c"; reg = <0x50>; }; }; &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; i2c-switch@70 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; i2c@0 { #address-cells = <1>; #size-cells = <0>; compatible = "nxp,pca954x-bus"; reg = <0>; /*eeprom@54 { compatible = "at,24c08"; reg = <0x54>; };*/ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; compatible = "nxp,pca954x-bus"; reg = <1>; /* Example to add new i2c device */ /*rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; };*/ eeprom@76 { compatible = "at,24c256"; reg = <0x76>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; compatible = "nxp,pca954x-bus"; reg = <2>; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; compatible = "nxp,pca954x-bus"; reg = <3>; }; }; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; imx6qdl-sabresd { pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 /*MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x410 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x410*/ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x80000000 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0 >; }; /*pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 >; };*/ pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 >; }; pinctrl_ecspi1_cs: ecspi1cs { fsl,pins = < MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 >; }; pinctrl_ecspi2_cs: ecspi2cs { fsl,pins = < MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 >; }; pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 >; }; pinctrl_enet_irq: enetirqgrp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x000b1 >; }; pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 >; }; pinctrl_hdmi_cec: hdmicecgrp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 >; }; pinctrl_hdmi_hdcp: hdmihdcpgrp { fsl,pins = < MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 >; }; pinctrl_ipu1: ipu1grp { fsl,pins = < MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xe1 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xe1 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xe1 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xe1 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xe1 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xe1 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xe1 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xe1 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xe1 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xe1 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xe1 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xe1 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xe1 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xe1 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xe1 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xe1 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xe1 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xe1 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xe1 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xe1 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xe1 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xe1 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xe1 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xe1 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xe1 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xe1 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xe1 >; }; pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ fsl,pins = < MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 >; }; pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 >; }; pinctrl_pcie_reg: pciereggrp { fsl,pins = < MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 >; }; pinctrl_sgtl5000: sgtl5000grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 >; }; pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 >; }; pinctrl_pwm2: pwm2grp { fsl,pins = < MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 >; }; pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 >; }; pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 >; }; pinctrl_uart5_1: uart5grp-1 { fsl,pins = < MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 >; }; pinctrl_uart5dte_1: uart5dtegrp-1 { fsl,pins = < MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 >; }; pinctrl_uart5_2: uart5grp-2 { fsl,pins = < MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 >; }; pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 >; }; pinctrl_usdhc4: usdhc4grp { fsl,pins = < MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 >; }; }; gpio_leds { pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 >; }; }; }; &mipi_csi { status = "disabled"; ipu_id = <0>; csi_id = <1>; v_channel = <0>; lanes = <4>; }; &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio1 20 0>; status = "okay"; }; &spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spdif>; status = "okay"; }; &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; &snvs_poweroff { status = "okay"; }; &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; status = "okay"; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5_2>; status = "okay"; }; &usbh1 { vbus-supply = <®_usb_h1_vbus>; gpios = <&gpio1 26 1>, <&gpio1 27 2>; status = "okay"; }; &usbotg { vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; gpios = <&gpio1 29 1>, <&gpio1 30 2>; disable-over-current; srp-disable; hnp-disable; adp-disable; status = "okay"; }; &usbphy1 { tx-d-cal = <0x5>; }; &usbphy2 { tx-d-cal = <0x5>; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; bus-width = <4>; cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; no-1-8-v; keep-power-in-suspend; enable-sdio-wakeup; status = "okay"; }; &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; bus-width = <4>; /*cd-gpios = <&gpio2 0 0>; wp-gpios = <&gpio2 1 0>; enable-sdio-wakeup;*/ no-1-8-v; keep-power-in-suspend; status = "disabled"; }; &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <8>; non-removable; no-1-8-v; keep-power-in-suspend; status = "okay"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; status = "okay"; }; &can2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,wdog_b; status = "okay"; }; &wdog2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,wdog_b; status = "disabled"; };