Blame view
common/board_f.c
25.1 KB
1938f4a5b
|
1 2 3 4 5 6 7 8 9 |
/* * Copyright (c) 2011 The Chromium OS Authors. * (C) Copyright 2002-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> * |
1a4596601
|
10 |
* SPDX-License-Identifier: GPL-2.0+ |
1938f4a5b
|
11 12 13 14 15 16 |
*/ #include <common.h> #include <linux/compiler.h> #include <version.h> #include <environment.h> |
ab7cd6279
|
17 |
#include <dm.h> |
1938f4a5b
|
18 |
#include <fdtdec.h> |
f828bf25f
|
19 |
#include <fs.h> |
e4fef6cfc
|
20 21 22 23 |
#if defined(CONFIG_CMD_IDE) #include <ide.h> #endif #include <i2c.h> |
1938f4a5b
|
24 25 |
#include <initcall.h> #include <logbuff.h> |
e4fef6cfc
|
26 27 28 29 30 31 32 33 34 35 36 |
/* TODO: Can we move these into arch/ headers? */ #ifdef CONFIG_8xx #include <mpc8xx.h> #endif #ifdef CONFIG_5xx #include <mpc5xx.h> #endif #ifdef CONFIG_MPC5xxx #include <mpc5xxx.h> #endif |
ec3b48201
|
37 |
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
a76df7090
|
38 39 |
#include <asm/mp.h> #endif |
e4fef6cfc
|
40 |
|
a733b06b6
|
41 |
#include <os.h> |
1938f4a5b
|
42 |
#include <post.h> |
e4fef6cfc
|
43 |
#include <spi.h> |
c5d4001a1
|
44 |
#include <status_led.h> |
71c52dba2
|
45 |
#include <trace.h> |
e4fef6cfc
|
46 |
#include <watchdog.h> |
a733b06b6
|
47 |
#include <asm/errno.h> |
1938f4a5b
|
48 49 |
#include <asm/io.h> #include <asm/sections.h> |
48a338067
|
50 51 52 53 |
#ifdef CONFIG_X86 #include <asm/init_helpers.h> #include <asm/relocate.h> #endif |
a733b06b6
|
54 55 56 |
#ifdef CONFIG_SANDBOX #include <asm/state.h> #endif |
ab7cd6279
|
57 |
#include <dm/root.h> |
1938f4a5b
|
58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 |
#include <linux/compiler.h> /* * Pointer to initial global data area * * Here we initialize it if needed. */ #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR #undef XTRN_DECLARE_GLOBAL_DATA_PTR #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); #else DECLARE_GLOBAL_DATA_PTR; #endif /* * sjg: IMO this code should be * refactored to a single function, something like: * * void led_set_state(enum led_colour_t colour, int on); */ /************************************************************************ * Coloured LED functionality ************************************************************************ * May be supplied by boards if desired */ |
c5d4001a1
|
84 85 86 87 88 89 90 91 92 |
__weak void coloured_LED_init(void) {} __weak void red_led_on(void) {} __weak void red_led_off(void) {} __weak void green_led_on(void) {} __weak void green_led_off(void) {} __weak void yellow_led_on(void) {} __weak void yellow_led_off(void) {} __weak void blue_led_on(void) {} __weak void blue_led_off(void) {} |
1938f4a5b
|
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 |
/* * Why is gd allocated a register? Prior to reloc it might be better to * just pass it around to each function in this file? * * After reloc one could argue that it is hardly used and doesn't need * to be in a register. Or if it is it should perhaps hold pointers to all * global data for all modules, so that post-reloc we can avoid the massive * literal pool we get on ARM. Or perhaps just encourage each module to use * a structure... */ /* * Could the CONFIG_SPL_BUILD infection become a flag in gd? */ |
d54d7eb96
|
108 |
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cfc
|
109 110 |
static int init_func_watchdog_init(void) { |
d54d7eb96
|
111 112 113 114 115 |
# if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \ defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ defined(CONFIG_SH)) hw_watchdog_init(); # endif |
e4fef6cfc
|
116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 |
puts(" Watchdog enabled "); WATCHDOG_RESET(); return 0; } int init_func_watchdog_reset(void) { WATCHDOG_RESET(); return 0; } #endif /* CONFIG_WATCHDOG */ void __board_add_ram_info(int use_default) { /* please define platform specific board_add_ram_info() */ } void board_add_ram_info(int) __attribute__ ((weak, alias("__board_add_ram_info"))); |
1938f4a5b
|
138 139 140 141 142 143 144 145 |
static int init_baud_rate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); return 0; } static int display_text_info(void) { |
a733b06b6
|
146 |
#ifndef CONFIG_SANDBOX |
1938f4a5b
|
147 |
ulong bss_start, bss_end; |
632efa744
|
148 149 |
bss_start = (ulong)&__bss_start; bss_end = (ulong)&__bss_end; |
b60eff31f
|
150 |
|
1938f4a5b
|
151 152 |
debug("U-Boot code: %08X -> %08lX BSS: -> %08lX ", |
d54d7eb96
|
153 |
#ifdef CONFIG_SYS_TEXT_BASE |
1938f4a5b
|
154 |
CONFIG_SYS_TEXT_BASE, bss_start, bss_end); |
d54d7eb96
|
155 156 157 |
#else CONFIG_SYS_MONITOR_BASE, bss_start, bss_end); #endif |
a733b06b6
|
158 |
#endif |
1938f4a5b
|
159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 |
#ifdef CONFIG_MODEM_SUPPORT debug("Modem Support enabled "); #endif #ifdef CONFIG_USE_IRQ debug("IRQ Stack: %08lx ", IRQ_STACK_START); debug("FIQ Stack: %08lx ", FIQ_STACK_START); #endif return 0; } static int announce_dram_init(void) { puts("DRAM: "); return 0; } |
3da7e5a50
|
179 |
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) |
e4fef6cfc
|
180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 |
static int init_func_ram(void) { #ifdef CONFIG_BOARD_TYPES int board_type = gd->board_type; #else int board_type = 0; /* use dummy arg */ #endif gd->ram_size = initdram(board_type); if (gd->ram_size > 0) return 0; puts("*** failed *** "); return 1; } #endif |
1938f4a5b
|
198 199 |
static int show_dram_config(void) { |
fa39ffe5d
|
200 |
unsigned long long size; |
1938f4a5b
|
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 |
#ifdef CONFIG_NR_DRAM_BANKS int i; debug(" RAM Configuration: "); for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { size += gd->bd->bi_dram[i].size; debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); #ifdef DEBUG print_size(gd->bd->bi_dram[i].size, " "); #endif } debug(" DRAM: "); #else size = gd->ram_size; #endif |
e4fef6cfc
|
221 222 223 224 |
print_size(size, ""); board_add_ram_info(0); putc(' '); |
1938f4a5b
|
225 226 227 228 229 230 231 232 233 234 235 236 237 238 |
return 0; } void __dram_init_banksize(void) { #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); #endif } void dram_init_banksize(void) __attribute__((weak, alias("__dram_init_banksize"))); |
ea818dbbc
|
239 |
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cfc
|
240 241 242 |
static int init_func_i2c(void) { puts("I2C: "); |
815a76f2e
|
243 244 245 |
#ifdef CONFIG_SYS_I2C i2c_init_all(); #else |
e4fef6cfc
|
246 |
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2e
|
247 |
#endif |
e4fef6cfc
|
248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 |
puts("ready "); return 0; } #endif #if defined(CONFIG_HARD_SPI) static int init_func_spi(void) { puts("SPI: "); spi_init(); puts("ready "); return 0; } #endif __maybe_unused |
1938f4a5b
|
266 267 268 269 270 271 272 273 274 |
static int zero_global_data(void) { memset((void *)gd, '\0', sizeof(gd_t)); return 0; } static int setup_mon_len(void) { |
b60eff31f
|
275 276 |
#ifdef __ARM__ gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
a733b06b6
|
277 278 |
#elif defined(CONFIG_SANDBOX) gd->mon_len = (ulong)&_end - (ulong)_init; |
5ff10aa7e
|
279 |
#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb96
|
280 |
gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
632efa744
|
281 |
#else |
e4fef6cfc
|
282 283 |
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; |
632efa744
|
284 |
#endif |
1938f4a5b
|
285 286 287 288 289 290 291 |
return 0; } __weak int arch_cpu_init(void) { return 0; } |
f828bf25f
|
292 |
#ifdef CONFIG_OF_HOSTFILE |
f828bf25f
|
293 294 295 |
static int read_fdt_from_file(void) { struct sandbox_state *state = state_get_current(); |
95fac6ab4
|
296 |
const char *fname = state->fdt_fname; |
f828bf25f
|
297 |
void *blob; |
95fac6ab4
|
298 |
ssize_t size; |
f828bf25f
|
299 |
int err; |
95fac6ab4
|
300 |
int fd; |
f828bf25f
|
301 302 303 |
blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0); if (!state->fdt_fname) { |
95fac6ab4
|
304 |
err = fdt_create_empty_tree(blob, 256); |
f828bf25f
|
305 306 |
if (!err) goto done; |
95fac6ab4
|
307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 |
printf("Unable to create empty FDT: %s ", fdt_strerror(err)); return -EINVAL; } size = os_get_filesize(fname); if (size < 0) { printf("Failed to file FDT file '%s' ", fname); return -ENOENT; } fd = os_open(fname, OS_O_RDONLY); if (fd < 0) { printf("Failed to open FDT file '%s' ", fname); return -EACCES; |
f828bf25f
|
323 |
} |
95fac6ab4
|
324 325 |
if (os_read(fd, blob, size) != size) { os_close(fd); |
f828bf25f
|
326 |
return -EIO; |
95fac6ab4
|
327 328 |
} os_close(fd); |
f828bf25f
|
329 330 331 332 333 334 335 |
done: gd->fdt_blob = blob; return 0; } #endif |
a733b06b6
|
336 337 338 |
#ifdef CONFIG_SANDBOX static int setup_ram_buf(void) { |
5c2859cdc
|
339 340 341 342 |
struct sandbox_state *state = state_get_current(); gd->arch.ram_buf = state->ram_buf; gd->ram_size = state->ram_size; |
a733b06b6
|
343 344 345 346 |
return 0; } #endif |
1938f4a5b
|
347 348 |
static int setup_fdt(void) { |
c970dffed
|
349 350 |
#ifdef CONFIG_OF_CONTROL # ifdef CONFIG_OF_EMBED |
1938f4a5b
|
351 |
/* Get a pointer to the FDT */ |
6ab6b2afa
|
352 |
gd->fdt_blob = __dtb_dt_begin; |
c970dffed
|
353 |
# elif defined CONFIG_OF_SEPARATE |
1938f4a5b
|
354 |
/* FDT is at end of image */ |
632efa744
|
355 |
gd->fdt_blob = (ulong *)&_end; |
c970dffed
|
356 |
# elif defined(CONFIG_OF_HOSTFILE) |
f828bf25f
|
357 358 359 360 361 |
if (read_fdt_from_file()) { puts("Failed to read control FDT "); return -1; } |
c970dffed
|
362 |
# endif |
1938f4a5b
|
363 364 365 |
/* Allow the early environment to override the fdt address */ gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, (uintptr_t)gd->fdt_blob); |
c970dffed
|
366 |
#endif |
1938f4a5b
|
367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 |
return 0; } /* Get the top of usable RAM */ __weak ulong board_get_usable_ram_top(ulong total_size) { return gd->ram_top; } static int setup_dest_addr(void) { debug("Monitor len: %08lX ", gd->mon_len); /* * Ram is setup, size stored in gd !! */ debug("Ram size: %08lX ", (ulong)gd->ram_size); #if defined(CONFIG_SYS_MEM_TOP_HIDE) /* * Subtract specified amount of memory to hide so that it won't * get "touched" at all by U-Boot. By fixing up gd->ram_size * the Linux kernel should now get passed the now "corrected" * memory size and won't touch it either. This should work * for arch/ppc and arch/powerpc. Only Linux board ports in * arch/powerpc with bootwrapper support, that recalculate the * memory size from the SDRAM controller setup will have to * get fixed. */ gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; #endif #ifdef CONFIG_SYS_SDRAM_BASE gd->ram_top = CONFIG_SYS_SDRAM_BASE; #endif |
e4fef6cfc
|
401 |
gd->ram_top += get_effective_memsize(); |
1938f4a5b
|
402 |
gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279ac
|
403 |
gd->relocaddr = gd->ram_top; |
1938f4a5b
|
404 405 |
debug("Ram top: %08lX ", (ulong)gd->ram_top); |
ec3b48201
|
406 |
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cfc
|
407 408 409 410 |
/* * We need to make sure the location we intend to put secondary core * boot code is reserved and not used by any part of u-boot */ |
a0ba279ac
|
411 412 413 414 |
if (gd->relocaddr > determine_mp_bootpg(NULL)) { gd->relocaddr = determine_mp_bootpg(NULL); debug("Reserving MP boot page to %08lx ", gd->relocaddr); |
e4fef6cfc
|
415 416 |
} #endif |
1938f4a5b
|
417 418 419 420 421 422 423 |
return 0; } #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) static int reserve_logbuffer(void) { /* reserve kernel log buffer */ |
a0ba279ac
|
424 |
gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5b
|
425 426 |
debug("Reserving %dk for kernel logbuffer at %08lx ", LOGBUFF_LEN, |
a0ba279ac
|
427 |
gd->relocaddr); |
1938f4a5b
|
428 429 430 431 432 433 434 435 436 437 438 |
return 0; } #endif #ifdef CONFIG_PRAM /* reserve protected RAM */ static int reserve_pram(void) { ulong reg; reg = getenv_ulong("pram", 10, CONFIG_PRAM); |
a0ba279ac
|
439 |
gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5b
|
440 441 |
debug("Reserving %ldk for protected RAM at %08lx ", reg, |
a0ba279ac
|
442 |
gd->relocaddr); |
1938f4a5b
|
443 444 445 446 447 448 449 |
return 0; } #endif /* CONFIG_PRAM */ /* Round memory pointer down to next 4 kB limit */ static int reserve_round_4k(void) { |
a0ba279ac
|
450 |
gd->relocaddr &= ~(4096 - 1); |
1938f4a5b
|
451 452 453 454 455 456 457 458 |
return 0; } #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ defined(CONFIG_ARM) static int reserve_mmu(void) { /* reserve TLB table */ |
cce6be7f0
|
459 |
gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279ac
|
460 |
gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5b
|
461 462 |
/* round down to next 64 kB limit */ |
a0ba279ac
|
463 |
gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5b
|
464 |
|
a0ba279ac
|
465 |
gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5b
|
466 467 468 469 470 471 472 473 474 475 476 477 478 479 |
debug("TLB table from %08lx to %08lx ", gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); return 0; } #endif #ifdef CONFIG_LCD static int reserve_lcd(void) { #ifdef CONFIG_FB_ADDR gd->fb_base = CONFIG_FB_ADDR; #else /* reserve memory for LCD display (always full pages) */ |
a0ba279ac
|
480 481 |
gd->relocaddr = lcd_setmem(gd->relocaddr); gd->fb_base = gd->relocaddr; |
1938f4a5b
|
482 483 484 485 |
#endif /* CONFIG_FB_ADDR */ return 0; } #endif /* CONFIG_LCD */ |
71c52dba2
|
486 487 488 489 490 491 492 493 494 495 496 497 |
static int reserve_trace(void) { #ifdef CONFIG_TRACE gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); debug("Reserving %dk for trace data at: %08lx ", CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); #endif return 0; } |
d54d7eb96
|
498 499 500 |
#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ !defined(CONFIG_BLACKFIN) |
e4fef6cfc
|
501 502 503 |
static int reserve_video(void) { /* reserve memory for video display (always full pages) */ |
a0ba279ac
|
504 505 |
gd->relocaddr = video_setmem(gd->relocaddr); gd->fb_base = gd->relocaddr; |
e4fef6cfc
|
506 507 508 509 |
return 0; } #endif |
1938f4a5b
|
510 511 512 513 514 515 |
static int reserve_uboot(void) { /* * reserve memory for U-Boot code, data & bss * round down to next 4 kB limit */ |
a0ba279ac
|
516 517 |
gd->relocaddr -= gd->mon_len; gd->relocaddr &= ~(4096 - 1); |
e4fef6cfc
|
518 519 |
#ifdef CONFIG_E500 /* round down to next 64 kB limit so that IVPR stays aligned */ |
a0ba279ac
|
520 |
gd->relocaddr &= ~(65536 - 1); |
e4fef6cfc
|
521 |
#endif |
1938f4a5b
|
522 523 524 |
debug("Reserving %ldk for U-Boot at: %08lx ", gd->mon_len >> 10, |
a0ba279ac
|
525 526 527 |
gd->relocaddr); gd->start_addr_sp = gd->relocaddr; |
1938f4a5b
|
528 529 |
return 0; } |
8cae8a68e
|
530 |
#ifndef CONFIG_SPL_BUILD |
1938f4a5b
|
531 532 533 |
/* reserve memory for malloc() area */ static int reserve_malloc(void) { |
a0ba279ac
|
534 |
gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5b
|
535 536 |
debug("Reserving %dk for malloc() at: %08lx ", |
a0ba279ac
|
537 |
TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5b
|
538 539 540 541 542 543 |
return 0; } /* (permanently) allocate a Board Info struct */ static int reserve_board(void) { |
d54d7eb96
|
544 545 546 547 548 549 550 551 |
if (!gd->bd) { gd->start_addr_sp -= sizeof(bd_t); gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); memset(gd->bd, '\0', sizeof(bd_t)); debug("Reserving %zu Bytes for Board Info at: %08lx ", sizeof(bd_t), gd->start_addr_sp); } |
1938f4a5b
|
552 553 |
return 0; } |
8cae8a68e
|
554 |
#endif |
1938f4a5b
|
555 556 557 558 559 560 561 562 563 564 565 |
static int setup_machine(void) { #ifdef CONFIG_MACH_TYPE gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ #endif return 0; } static int reserve_global_data(void) { |
a0ba279ac
|
566 567 |
gd->start_addr_sp -= sizeof(gd_t); gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); |
1938f4a5b
|
568 569 |
debug("Reserving %zu Bytes for Global Data at: %08lx ", |
a0ba279ac
|
570 |
sizeof(gd_t), gd->start_addr_sp); |
1938f4a5b
|
571 572 573 574 575 576 577 578 579 580 581 582 |
return 0; } static int reserve_fdt(void) { /* * If the device tree is sitting immediate above our image then we * must relocate it. If it is embedded in the data section, then it * will be relocated with other data. */ if (gd->fdt_blob) { gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); |
a0ba279ac
|
583 584 |
gd->start_addr_sp -= gd->fdt_size; gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); |
a733b06b6
|
585 586 |
debug("Reserving %lu Bytes for FDT at: %08lx ", |
a0ba279ac
|
587 |
gd->fdt_size, gd->start_addr_sp); |
1938f4a5b
|
588 589 590 591 592 593 594 |
} return 0; } static int reserve_stacks(void) { |
8cae8a68e
|
595 596 |
#ifdef CONFIG_SPL_BUILD # ifdef CONFIG_ARM |
a0ba279ac
|
597 598 |
gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ gd->irq_sp = gd->start_addr_sp; |
8cae8a68e
|
599 600 |
# endif #else |
e4fef6cfc
|
601 602 603 |
# ifdef CONFIG_PPC ulong *s; # endif |
8cae8a68e
|
604 |
|
1938f4a5b
|
605 |
/* setup stack pointer for exceptions */ |
a0ba279ac
|
606 607 608 |
gd->start_addr_sp -= 16; gd->start_addr_sp &= ~0xf; gd->irq_sp = gd->start_addr_sp; |
1938f4a5b
|
609 610 611 612 613 614 |
/* * Handle architecture-specific things here * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack() * to handle this and put in arch/xxx/lib/stack.c */ |
cce6be7f0
|
615 |
# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) |
1938f4a5b
|
616 |
# ifdef CONFIG_USE_IRQ |
a0ba279ac
|
617 |
gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); |
1938f4a5b
|
618 619 |
debug("Reserving %zu Bytes for IRQ stack at: %08lx ", |
a0ba279ac
|
620 |
CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp); |
1938f4a5b
|
621 622 |
/* 8-byte alignment for ARM ABI compliance */ |
a0ba279ac
|
623 |
gd->start_addr_sp &= ~0x07; |
1938f4a5b
|
624 625 |
# endif /* leave 3 words for abort-stack, plus 1 for alignment */ |
a0ba279ac
|
626 |
gd->start_addr_sp -= 16; |
e4fef6cfc
|
627 628 |
# elif defined(CONFIG_PPC) /* Clear initial stack frame */ |
a0ba279ac
|
629 |
s = (ulong *) gd->start_addr_sp; |
e4fef6cfc
|
630 631 |
*s = 0; /* Terminate back chain */ *++s = 0; /* NULL return address */ |
8cae8a68e
|
632 |
# endif /* Architecture specific code */ |
1938f4a5b
|
633 634 |
return 0; |
8cae8a68e
|
635 |
#endif |
1938f4a5b
|
636 637 638 639 |
} static int display_new_sp(void) { |
a0ba279ac
|
640 641 |
debug("New Stack Pointer is: %08lx ", gd->start_addr_sp); |
1938f4a5b
|
642 643 644 |
return 0; } |
e4fef6cfc
|
645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 |
#ifdef CONFIG_PPC static int setup_board_part1(void) { bd_t *bd = gd->bd; /* * Save local variables to board info struct */ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ bd->bi_memsize = gd->ram_size; /* size in bytes */ #ifdef CONFIG_SYS_SRAM_BASE bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif |
58dac3276
|
661 |
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ |
e4fef6cfc
|
662 663 664 665 666 667 668 669 670 |
defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ #endif #if defined(CONFIG_MPC83xx) bd->bi_immrbar = CONFIG_SYS_IMMR; #endif |
e4fef6cfc
|
671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 |
return 0; } static int setup_board_part2(void) { bd_t *bd = gd->bd; bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ #if defined(CONFIG_CPM2) bd->bi_cpmfreq = gd->arch.cpm_clk; bd->bi_brgfreq = gd->arch.brg_clk; bd->bi_sccfreq = gd->arch.scc_clk; bd->bi_vco = gd->arch.vco_out; #endif /* CONFIG_CPM2 */ #if defined(CONFIG_MPC512X) bd->bi_ipsfreq = gd->arch.ips_clk; #endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC5xxx) bd->bi_ipbfreq = gd->arch.ipb_clk; bd->bi_pcifreq = gd->pci_clk; #endif /* CONFIG_MPC5xxx */ return 0; } #endif #ifdef CONFIG_SYS_EXTBDINFO static int setup_board_extra(void) { bd_t *bd = gd->bd; strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, sizeof(bd->bi_r_version)); bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ bd->bi_plb_busfreq = gd->bus_clk; #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) bd->bi_pci_busfreq = get_PCI_freq(); bd->bi_opbfreq = get_OPB_freq(); #elif defined(CONFIG_XILINX_405) bd->bi_pci_busfreq = get_PCI_freq(); #endif return 0; } #endif |
1938f4a5b
|
722 723 724 725 726 727 728 729 730 |
#ifdef CONFIG_POST static int init_post(void) { post_bootmode_init(); post_run(NULL, POST_ROM | post_bootmode_get(0)); return 0; } #endif |
1938f4a5b
|
731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 |
static int setup_dram_config(void) { /* Ram is board specific, so move it to board code ... */ dram_init_banksize(); return 0; } static int reloc_fdt(void) { if (gd->new_fdt) { memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); gd->fdt_blob = gd->new_fdt; } return 0; } static int setup_reloc(void) { |
d54d7eb96
|
751 |
#ifdef CONFIG_SYS_TEXT_BASE |
a0ba279ac
|
752 |
gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
d54d7eb96
|
753 |
#endif |
1938f4a5b
|
754 755 756 757 |
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); debug("Relocation Offset is: %08lx ", gd->reloc_off); |
a733b06b6
|
758 759 |
debug("Relocating to %08lx, new gd at %08lx, sp at %08lx ", |
a0ba279ac
|
760 761 |
gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), gd->start_addr_sp); |
1938f4a5b
|
762 763 764 765 766 |
return 0; } /* ARM calls relocate_code from its crt0.S */ |
808434cdb
|
767 |
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5b
|
768 769 770 |
static int jump_to_copy(void) { |
48a338067
|
771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 |
/* * x86 is special, but in a nice way. It uses a trampoline which * enables the dcache if possible. * * For now, other archs use relocate_code(), which is implemented * similarly for all archs. When we do generic relocation, hopefully * we can make all archs enable the dcache prior to relocation. */ #ifdef CONFIG_X86 /* * SDRAM and console are now initialised. The final stack can now * be setup in SDRAM. Code execution will continue in Flash, but * with the stack in SDRAM and Global Data in temporary memory * (CPU cache) */ board_init_f_r_trampoline(gd->start_addr_sp); #else |
a0ba279ac
|
788 |
relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a338067
|
789 |
#endif |
1938f4a5b
|
790 791 792 793 794 795 796 797 798 799 800 801 |
return 0; } #endif /* Record the board_init_f() bootstage (after arch_cpu_init()) */ static int mark_bootstage(void) { bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); return 0; } |
d59476b64
|
802 803 804 805 806 807 808 809 810 811 |
static int initf_malloc(void) { #ifdef CONFIG_SYS_MALLOC_F_LEN assert(gd->malloc_base); /* Set up by crt0.S */ gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN; gd->malloc_ptr = 0; #endif return 0; } |
ab7cd6279
|
812 813 814 815 816 817 818 819 820 821 822 823 |
static int initf_dm(void) { #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) int ret; ret = dm_init_and_scan(true); if (ret) return ret; #endif return 0; } |
1938f4a5b
|
824 |
static init_fnc_t init_sequence_f[] = { |
a733b06b6
|
825 826 827 |
#ifdef CONFIG_SANDBOX setup_ram_buf, #endif |
1938f4a5b
|
828 |
setup_mon_len, |
71c52dba2
|
829 830 |
setup_fdt, trace_early_init, |
e4fef6cfc
|
831 832 833 834 |
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) /* TODO: can this go into arch_cpu_init()? */ probecpu, #endif |
1938f4a5b
|
835 |
arch_cpu_init, /* basic arch cpu dependent setup */ |
48a338067
|
836 837 838 839 840 841 |
#ifdef CONFIG_X86 cpu_init_f, /* TODO(sjg@chromium.org): remove */ # ifdef CONFIG_OF_CONTROL find_fdt, /* TODO(sjg@chromium.org): remove */ # endif #endif |
1938f4a5b
|
842 843 844 845 |
mark_bootstage, #ifdef CONFIG_OF_CONTROL fdtdec_check_fdt, #endif |
3ea0953d3
|
846 847 |
initf_malloc, initf_dm, |
1938f4a5b
|
848 849 850 |
#if defined(CONFIG_BOARD_EARLY_INIT_F) board_early_init_f, #endif |
e4fef6cfc
|
851 852 853 854 855 856 857 858 859 860 |
/* TODO: can any of this go into arch_cpu_init()? */ #if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) get_clocks, /* get CPU and bus clocks (etc.) */ #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ && !defined(CONFIG_TQM885D) adjust_sdram_tbs_8xx, #endif /* TODO: can we rename this to timer_init()? */ init_timebase, #endif |
d54d7eb96
|
861 |
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || defined(CONFIG_BLACKFIN) |
1938f4a5b
|
862 |
timer_init, /* initialize timer */ |
e4fef6cfc
|
863 |
#endif |
e4fef6cfc
|
864 865 866 867 868 869 870 871 |
#ifdef CONFIG_SYS_ALLOC_DPRAM #if !defined(CONFIG_CPM2) dpram_init, #endif #endif #if defined(CONFIG_BOARD_POSTCLK_INIT) board_postclk_init, #endif |
b8521b740
|
872 873 874 |
#ifdef CONFIG_FSL_ESDHC get_clocks, #endif |
1938f4a5b
|
875 |
env_init, /* initialize environment */ |
e4fef6cfc
|
876 877 878 879 880 881 882 |
#if defined(CONFIG_8xx_CPUCLK_DEFAULT) /* get CPU and bus clocks according to the environment variable */ get_clocks_866, /* adjust sdram refresh rate according to the new clock */ sdram_adjust_866, init_timebase, #endif |
1938f4a5b
|
883 884 885 |
init_baud_rate, /* initialze baudrate settings */ serial_init, /* serial communications setup */ console_init_f, /* stage 1 init of console */ |
a733b06b6
|
886 887 888 889 890 |
#ifdef CONFIG_SANDBOX sandbox_early_getopt_check, #endif #ifdef CONFIG_OF_CONTROL fdtdec_prepare_fdt, |
48a338067
|
891 |
#endif |
1938f4a5b
|
892 893 |
display_options, /* say that we are here */ display_text_info, /* show debugging info if required */ |
58dac3276
|
894 |
#if defined(CONFIG_MPC8260) |
e4fef6cfc
|
895 896 |
prt_8260_rsr, prt_8260_clks, |
58dac3276
|
897 |
#endif /* CONFIG_MPC8260 */ |
e4fef6cfc
|
898 899 900 901 902 903 |
#if defined(CONFIG_MPC83xx) prt_83xx_rsr, #endif #ifdef CONFIG_PPC checkcpu, #endif |
1938f4a5b
|
904 |
print_cpuinfo, /* display cpu info (and speed) */ |
e4fef6cfc
|
905 906 907 |
#if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ |
1938f4a5b
|
908 909 910 |
#if defined(CONFIG_DISPLAY_BOARDINFO) checkboard, /* display board info */ #endif |
e4fef6cfc
|
911 912 913 914 915 |
INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) misc_init_f, #endif INIT_FUNC_WATCHDOG_RESET |
ea818dbbc
|
916 |
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cfc
|
917 918 919 920 921 922 923 |
init_func_i2c, #endif #if defined(CONFIG_HARD_SPI) init_func_spi, #endif #ifdef CONFIG_X86 dram_init_f, /* configure available RAM banks */ |
8b42dfc3b
|
924 |
calculate_relocation_address, |
e4fef6cfc
|
925 |
#endif |
1938f4a5b
|
926 927 928 929 930 |
announce_dram_init, /* TODO: unify all these dram functions? */ #ifdef CONFIG_ARM dram_init, /* configure available RAM banks */ #endif |
3da7e5a50
|
931 |
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) |
e4fef6cfc
|
932 933 934 935 936 937 938 939 940 941 |
init_func_ram, #endif #ifdef CONFIG_POST post_init_f, #endif INIT_FUNC_WATCHDOG_RESET #if defined(CONFIG_SYS_DRAM_TEST) testdram, #endif /* CONFIG_SYS_DRAM_TEST */ INIT_FUNC_WATCHDOG_RESET |
1938f4a5b
|
942 943 944 |
#ifdef CONFIG_POST init_post, #endif |
e4fef6cfc
|
945 |
INIT_FUNC_WATCHDOG_RESET |
1938f4a5b
|
946 947 948 949 950 951 952 953 954 955 956 957 958 |
/* * Now that we have DRAM mapped and working, we can * relocate the code and continue running from DRAM. * * Reserve memory at end of RAM for (top down in that order): * - area that won't get touched by U-Boot and Linux (optional) * - kernel log buffer * - protected RAM * - LCD framebuffer * - monitor code * - board info struct */ setup_dest_addr, |
5ff10aa7e
|
959 |
#if defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb96
|
960 961 962 |
/* Blackfin u-boot monitor should be on top of the ram */ reserve_uboot, #endif |
1938f4a5b
|
963 964 965 966 967 968 969 970 971 972 973 974 975 976 |
#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) reserve_logbuffer, #endif #ifdef CONFIG_PRAM reserve_pram, #endif reserve_round_4k, #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ defined(CONFIG_ARM) reserve_mmu, #endif #ifdef CONFIG_LCD reserve_lcd, #endif |
71c52dba2
|
977 |
reserve_trace, |
e4fef6cfc
|
978 |
/* TODO: Why the dependency on CONFIG_8xx? */ |
d54d7eb96
|
979 980 981 |
#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ !defined(CONFIG_BLACKFIN) |
e4fef6cfc
|
982 983 |
reserve_video, #endif |
5ff10aa7e
|
984 |
#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) |
1938f4a5b
|
985 |
reserve_uboot, |
d54d7eb96
|
986 |
#endif |
8cae8a68e
|
987 |
#ifndef CONFIG_SPL_BUILD |
1938f4a5b
|
988 989 |
reserve_malloc, reserve_board, |
8cae8a68e
|
990 |
#endif |
1938f4a5b
|
991 992 993 994 995 996 |
setup_machine, reserve_global_data, reserve_fdt, reserve_stacks, setup_dram_config, show_dram_config, |
e4fef6cfc
|
997 998 999 1000 1001 |
#ifdef CONFIG_PPC setup_board_part1, INIT_FUNC_WATCHDOG_RESET setup_board_part2, #endif |
1938f4a5b
|
1002 |
display_new_sp, |
e4fef6cfc
|
1003 1004 1005 1006 |
#ifdef CONFIG_SYS_EXTBDINFO setup_board_extra, #endif INIT_FUNC_WATCHDOG_RESET |
1938f4a5b
|
1007 1008 |
reloc_fdt, setup_reloc, |
808434cdb
|
1009 |
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5b
|
1010 1011 1012 1013 1014 1015 1016 |
jump_to_copy, #endif NULL, }; void board_init_f(ulong boot_flags) { |
2a1680e30
|
1017 1018 1019 1020 1021 1022 1023 |
#ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA /* * For some archtectures, global data is initialized and used before * calling this function. The data should be preserved. For others, * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack * here to host global data until relocation. */ |
1938f4a5b
|
1024 1025 1026 |
gd_t data; gd = &data; |
cce6be7f0
|
1027 1028 1029 1030 1031 |
/* * Clear global data before it is accessed at debug print * in initcall_run_list. Otherwise the debug print probably * get the wrong vaule of gd->have_console. */ |
cce6be7f0
|
1032 1033 |
zero_global_data(); #endif |
1938f4a5b
|
1034 |
gd->flags = boot_flags; |
9aed5a277
|
1035 |
gd->have_console = 0; |
1938f4a5b
|
1036 1037 1038 |
if (initcall_run_list(init_sequence_f)) hang(); |
808434cdb
|
1039 |
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5b
|
1040 1041 1042 1043 |
/* NOTREACHED - jump_to_copy() does not return */ hang(); #endif } |
48a338067
|
1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 |
#ifdef CONFIG_X86 /* * For now this code is only used on x86. * * init_sequence_f_r is the list of init functions which are run when * U-Boot is executing from Flash with a semi-limited 'C' environment. * The following limitations must be considered when implementing an * '_f_r' function: * - 'static' variables are read-only * - Global Data (gd->xxx) is read/write * * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if * supported). It _should_, if possible, copy global data to RAM and * initialise the CPU caches (to speed up the relocation process) * * NOTE: At present only x86 uses this route, but it is intended that * all archs will move to this when generic relocation is implemented. */ static init_fnc_t init_sequence_f_r[] = { init_cache_f_r, copy_uboot_to_ram, clear_bss, do_elf_reloc_fixups, NULL, }; void board_init_f_r(void) { if (initcall_run_list(init_sequence_f_r)) hang(); /* * U-Boot has been copied into SDRAM, the BSS has been cleared etc. * Transfer execution from Flash to RAM by calculating the address * of the in-RAM copy of board_init_r() and calling it */ (board_init_r + gd->reloc_off)(gd, gd->relocaddr); /* NOTREACHED - board_init_r() does not return */ hang(); } #endif /* CONFIG_X86 */ |